1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * drivers/soc/tegra/pmc.c 4 * 5 * Copyright (c) 2010 Google, Inc 6 * Copyright (c) 2018-2024, NVIDIA CORPORATION. All rights reserved. 7 * 8 * Author: 9 * Colin Cross <ccross@google.com> 10 */ 11 12 #define pr_fmt(fmt) "tegra-pmc: " fmt 13 14 #include <linux/arm-smccc.h> 15 #include <linux/clk.h> 16 #include <linux/clk-provider.h> 17 #include <linux/clkdev.h> 18 #include <linux/clk/clk-conf.h> 19 #include <linux/clk/tegra.h> 20 #include <linux/debugfs.h> 21 #include <linux/delay.h> 22 #include <linux/device.h> 23 #include <linux/err.h> 24 #include <linux/export.h> 25 #include <linux/init.h> 26 #include <linux/interrupt.h> 27 #include <linux/io.h> 28 #include <linux/iopoll.h> 29 #include <linux/irqdomain.h> 30 #include <linux/irq.h> 31 #include <linux/kernel.h> 32 #include <linux/of_address.h> 33 #include <linux/of_clk.h> 34 #include <linux/of.h> 35 #include <linux/of_irq.h> 36 #include <linux/of_platform.h> 37 #include <linux/pinctrl/pinconf-generic.h> 38 #include <linux/pinctrl/pinconf.h> 39 #include <linux/pinctrl/pinctrl.h> 40 #include <linux/platform_device.h> 41 #include <linux/pm_domain.h> 42 #include <linux/pm_opp.h> 43 #include <linux/power_supply.h> 44 #include <linux/reboot.h> 45 #include <linux/regmap.h> 46 #include <linux/reset.h> 47 #include <linux/seq_file.h> 48 #include <linux/slab.h> 49 #include <linux/spinlock.h> 50 #include <linux/syscore_ops.h> 51 52 #include <soc/tegra/common.h> 53 #include <soc/tegra/fuse.h> 54 #include <soc/tegra/pmc.h> 55 56 #include <dt-bindings/interrupt-controller/arm-gic.h> 57 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 58 #include <dt-bindings/gpio/tegra186-gpio.h> 59 #include <dt-bindings/gpio/tegra194-gpio.h> 60 #include <dt-bindings/gpio/tegra234-gpio.h> 61 #include <dt-bindings/soc/tegra-pmc.h> 62 63 #define PMC_CNTRL 0x0 64 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */ 65 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */ 66 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */ 67 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */ 68 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ 69 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ 70 #define PMC_CNTRL_PWRREQ_POLARITY BIT(8) 71 #define PMC_CNTRL_BLINK_EN 7 72 #define PMC_CNTRL_MAIN_RST BIT(4) 73 74 #define PMC_WAKE_MASK 0x0c 75 #define PMC_WAKE_LEVEL 0x10 76 #define PMC_WAKE_STATUS 0x14 77 #define PMC_SW_WAKE_STATUS 0x18 78 #define PMC_DPD_PADS_ORIDE 0x1c 79 #define PMC_DPD_PADS_ORIDE_BLINK 20 80 81 #define DPD_SAMPLE 0x020 82 #define DPD_SAMPLE_ENABLE BIT(0) 83 #define DPD_SAMPLE_DISABLE (0 << 0) 84 85 #define PWRGATE_TOGGLE 0x30 86 #define PWRGATE_TOGGLE_START BIT(8) 87 88 #define REMOVE_CLAMPING 0x34 89 90 #define PWRGATE_STATUS 0x38 91 92 #define PMC_BLINK_TIMER 0x40 93 #define PMC_IMPL_E_33V_PWR 0x40 94 95 #define PMC_PWR_DET 0x48 96 97 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31) 98 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30) 99 #define PMC_SCRATCH0_MODE_RCM BIT(1) 100 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ 101 PMC_SCRATCH0_MODE_BOOTLOADER | \ 102 PMC_SCRATCH0_MODE_RCM) 103 104 #define PMC_CPUPWRGOOD_TIMER 0xc8 105 #define PMC_CPUPWROFF_TIMER 0xcc 106 #define PMC_COREPWRGOOD_TIMER 0x3c 107 #define PMC_COREPWROFF_TIMER 0xe0 108 109 #define PMC_PWR_DET_VALUE 0xe4 110 111 #define PMC_USB_DEBOUNCE_DEL 0xec 112 #define PMC_USB_AO 0xf0 113 114 #define PMC_SCRATCH37 0x130 115 #define PMC_SCRATCH41 0x140 116 117 #define PMC_WAKE2_MASK 0x160 118 #define PMC_WAKE2_LEVEL 0x164 119 #define PMC_WAKE2_STATUS 0x168 120 #define PMC_SW_WAKE2_STATUS 0x16c 121 122 #define PMC_CLK_OUT_CNTRL 0x1a8 123 #define PMC_CLK_OUT_MUX_MASK GENMASK(1, 0) 124 #define PMC_SENSOR_CTRL 0x1b0 125 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) 126 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) 127 128 #define PMC_RST_STATUS_POR 0 129 #define PMC_RST_STATUS_WATCHDOG 1 130 #define PMC_RST_STATUS_SENSOR 2 131 #define PMC_RST_STATUS_SW_MAIN 3 132 #define PMC_RST_STATUS_LP0 4 133 #define PMC_RST_STATUS_AOTAG 5 134 135 #define IO_DPD_REQ 0x1b8 136 #define IO_DPD_REQ_CODE_IDLE (0U << 30) 137 #define IO_DPD_REQ_CODE_OFF (1U << 30) 138 #define IO_DPD_REQ_CODE_ON (2U << 30) 139 #define IO_DPD_REQ_CODE_MASK (3U << 30) 140 141 #define IO_DPD_STATUS 0x1bc 142 #define IO_DPD2_REQ 0x1c0 143 #define IO_DPD2_STATUS 0x1c4 144 #define SEL_DPD_TIM 0x1c8 145 146 #define PMC_UTMIP_UHSIC_TRIGGERS 0x1ec 147 #define PMC_UTMIP_UHSIC_SAVED_STATE 0x1f0 148 149 #define PMC_UTMIP_TERM_PAD_CFG 0x1f8 150 #define PMC_UTMIP_UHSIC_SLEEP_CFG 0x1fc 151 #define PMC_UTMIP_UHSIC_FAKE 0x218 152 153 #define PMC_SCRATCH54 0x258 154 #define PMC_SCRATCH54_DATA_SHIFT 8 155 #define PMC_SCRATCH54_ADDR_SHIFT 0 156 157 #define PMC_SCRATCH55 0x25c 158 #define PMC_SCRATCH55_RESET_TEGRA BIT(31) 159 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27 160 #define PMC_SCRATCH55_PINMUX_SHIFT 24 161 #define PMC_SCRATCH55_16BITOP BIT(15) 162 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16 163 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0 164 165 #define PMC_UTMIP_UHSIC_LINE_WAKEUP 0x26c 166 167 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x270 168 #define PMC_UTMIP_MASTER_CONFIG 0x274 169 #define PMC_UTMIP_UHSIC2_TRIGGERS 0x27c 170 #define PMC_UTMIP_MASTER2_CONFIG 0x29c 171 172 #define GPU_RG_CNTRL 0x2d4 173 174 #define PMC_UTMIP_PAD_CFG0 0x4c0 175 #define PMC_UTMIP_UHSIC_SLEEP_CFG1 0x4d0 176 #define PMC_UTMIP_SLEEPWALK_P3 0x4e0 177 /* Tegra186 and later */ 178 #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2)) 179 #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3) 180 #define WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN (1 << 1) 181 #define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2)) 182 #define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2)) 183 #define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2)) 184 #define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2)) 185 #define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2)) 186 #define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2)) 187 #define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2)) 188 #define WAKE_AOWAKE_SW_STATUS_W_0 0x49c 189 #define WAKE_AOWAKE_SW_STATUS(x) (0x4a0 + ((x) << 2)) 190 #define WAKE_LATCH_SW 0x498 191 192 #define WAKE_AOWAKE_CTRL 0x4f4 193 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0) 194 195 #define SW_WAKE_ID 83 /* wake83 */ 196 197 /* for secure PMC */ 198 #define TEGRA_SMC_PMC 0xc2fffe00 199 #define TEGRA_SMC_PMC_READ 0xaa 200 #define TEGRA_SMC_PMC_WRITE 0xbb 201 202 struct pmc_clk { 203 struct clk_hw hw; 204 unsigned long offs; 205 u32 mux_shift; 206 u32 force_en_shift; 207 }; 208 209 #define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw) 210 211 struct pmc_clk_gate { 212 struct clk_hw hw; 213 unsigned long offs; 214 u32 shift; 215 }; 216 217 #define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw) 218 219 struct pmc_clk_init_data { 220 char *name; 221 const char *const *parents; 222 int num_parents; 223 int clk_id; 224 u8 mux_shift; 225 u8 force_en_shift; 226 }; 227 228 static const char * const clk_out1_parents[] = { "osc", "osc_div2", 229 "osc_div4", "extern1", 230 }; 231 232 static const char * const clk_out2_parents[] = { "osc", "osc_div2", 233 "osc_div4", "extern2", 234 }; 235 236 static const char * const clk_out3_parents[] = { "osc", "osc_div2", 237 "osc_div4", "extern3", 238 }; 239 240 static const struct pmc_clk_init_data tegra_pmc_clks_data[] = { 241 { 242 .name = "pmc_clk_out_1", 243 .parents = clk_out1_parents, 244 .num_parents = ARRAY_SIZE(clk_out1_parents), 245 .clk_id = TEGRA_PMC_CLK_OUT_1, 246 .mux_shift = 6, 247 .force_en_shift = 2, 248 }, 249 { 250 .name = "pmc_clk_out_2", 251 .parents = clk_out2_parents, 252 .num_parents = ARRAY_SIZE(clk_out2_parents), 253 .clk_id = TEGRA_PMC_CLK_OUT_2, 254 .mux_shift = 14, 255 .force_en_shift = 10, 256 }, 257 { 258 .name = "pmc_clk_out_3", 259 .parents = clk_out3_parents, 260 .num_parents = ARRAY_SIZE(clk_out3_parents), 261 .clk_id = TEGRA_PMC_CLK_OUT_3, 262 .mux_shift = 22, 263 .force_en_shift = 18, 264 }, 265 }; 266 267 struct tegra_powergate { 268 struct generic_pm_domain genpd; 269 struct tegra_pmc *pmc; 270 unsigned int id; 271 struct clk **clks; 272 unsigned int num_clks; 273 unsigned long *clk_rates; 274 struct reset_control *reset; 275 }; 276 277 struct tegra_io_pad_soc { 278 enum tegra_io_pad id; 279 unsigned int dpd; 280 unsigned int request; 281 unsigned int status; 282 unsigned int voltage; 283 const char *name; 284 }; 285 286 struct tegra_pmc_regs { 287 unsigned int scratch0; 288 unsigned int rst_status; 289 unsigned int rst_source_shift; 290 unsigned int rst_source_mask; 291 unsigned int rst_level_shift; 292 unsigned int rst_level_mask; 293 }; 294 295 struct tegra_wake_event { 296 const char *name; 297 unsigned int id; 298 unsigned int irq; 299 struct { 300 unsigned int instance; 301 unsigned int pin; 302 } gpio; 303 }; 304 305 #define TEGRA_WAKE_SIMPLE(_name, _id) \ 306 { \ 307 .name = _name, \ 308 .id = _id, \ 309 .irq = 0, \ 310 .gpio = { \ 311 .instance = UINT_MAX, \ 312 .pin = UINT_MAX, \ 313 }, \ 314 } 315 316 #define TEGRA_WAKE_IRQ(_name, _id, _irq) \ 317 { \ 318 .name = _name, \ 319 .id = _id, \ 320 .irq = _irq, \ 321 .gpio = { \ 322 .instance = UINT_MAX, \ 323 .pin = UINT_MAX, \ 324 }, \ 325 } 326 327 #define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \ 328 { \ 329 .name = _name, \ 330 .id = _id, \ 331 .irq = 0, \ 332 .gpio = { \ 333 .instance = _instance, \ 334 .pin = _pin, \ 335 }, \ 336 } 337 338 struct tegra_pmc_soc { 339 unsigned int num_powergates; 340 const char *const *powergates; 341 unsigned int num_cpu_powergates; 342 const u8 *cpu_powergates; 343 344 bool has_tsense_reset; 345 bool has_gpu_clamps; 346 bool needs_mbist_war; 347 bool has_impl_33v_pwr; 348 bool maybe_tz_only; 349 350 const struct tegra_io_pad_soc *io_pads; 351 unsigned int num_io_pads; 352 353 const struct pinctrl_pin_desc *pin_descs; 354 unsigned int num_pin_descs; 355 356 const struct tegra_pmc_regs *regs; 357 void (*init)(struct tegra_pmc *pmc); 358 void (*setup_irq_polarity)(struct tegra_pmc *pmc, 359 struct device_node *np, 360 bool invert); 361 void (*set_wake_filters)(struct tegra_pmc *pmc); 362 int (*irq_set_wake)(struct irq_data *data, unsigned int on); 363 int (*irq_set_type)(struct irq_data *data, unsigned int type); 364 int (*powergate_set)(struct tegra_pmc *pmc, unsigned int id, 365 bool new_state); 366 367 const char * const *reset_sources; 368 unsigned int num_reset_sources; 369 const char * const *reset_levels; 370 unsigned int num_reset_levels; 371 372 /* 373 * These describe events that can wake the system from sleep (i.e. 374 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2) 375 * are dealt with in the LIC. 376 */ 377 const struct tegra_wake_event *wake_events; 378 unsigned int num_wake_events; 379 unsigned int max_wake_events; 380 unsigned int max_wake_vectors; 381 382 const struct pmc_clk_init_data *pmc_clks_data; 383 unsigned int num_pmc_clks; 384 bool has_blink_output; 385 bool has_usb_sleepwalk; 386 bool supports_core_domain; 387 bool has_single_mmio_aperture; 388 }; 389 390 /** 391 * struct tegra_pmc - NVIDIA Tegra PMC 392 * @dev: pointer to PMC device structure 393 * @base: pointer to I/O remapped register region 394 * @wake: pointer to I/O remapped region for WAKE registers 395 * @aotag: pointer to I/O remapped region for AOTAG registers 396 * @scratch: pointer to I/O remapped region for scratch registers 397 * @clk: pointer to pclk clock 398 * @soc: pointer to SoC data structure 399 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone 400 * @rate: currently configured rate of pclk 401 * @suspend_mode: lowest suspend mode available 402 * @cpu_good_time: CPU power good time (in microseconds) 403 * @cpu_off_time: CPU power off time (in microsecends) 404 * @core_osc_time: core power good OSC time (in microseconds) 405 * @core_pmu_time: core power good PMU time (in microseconds) 406 * @core_off_time: core power off time (in microseconds) 407 * @corereq_high: core power request is active-high 408 * @sysclkreq_high: system clock request is active-high 409 * @combined_req: combined power request for CPU & core 410 * @cpu_pwr_good_en: CPU power good signal is enabled 411 * @lp0_vec_phys: physical base address of the LP0 warm boot code 412 * @lp0_vec_size: size of the LP0 warm boot code 413 * @powergates_available: Bitmap of available power gates 414 * @powergates_lock: mutex for power gate register access 415 * @pctl_dev: pin controller exposed by the PMC 416 * @domain: IRQ domain provided by the PMC 417 * @irq: chip implementation for the IRQ domain 418 * @clk_nb: pclk clock changes handler 419 * @core_domain_state_synced: flag marking the core domain's state as synced 420 * @core_domain_registered: flag marking the core domain as registered 421 * @wake_type_level_map: Bitmap indicating level type for non-dual edge wakes 422 * @wake_type_dual_edge_map: Bitmap indicating if a wake is dual-edge or not 423 * @wake_sw_status_map: Bitmap to hold raw status of wakes without mask 424 * @wake_cntrl_level_map: Bitmap to hold wake levels to be programmed in 425 * cntrl register associated with each wake during system suspend. 426 */ 427 struct tegra_pmc { 428 struct device *dev; 429 void __iomem *base; 430 void __iomem *wake; 431 void __iomem *aotag; 432 void __iomem *scratch; 433 struct clk *clk; 434 435 const struct tegra_pmc_soc *soc; 436 bool tz_only; 437 438 unsigned long rate; 439 440 enum tegra_suspend_mode suspend_mode; 441 u32 cpu_good_time; 442 u32 cpu_off_time; 443 u32 core_osc_time; 444 u32 core_pmu_time; 445 u32 core_off_time; 446 bool corereq_high; 447 bool sysclkreq_high; 448 bool combined_req; 449 bool cpu_pwr_good_en; 450 u32 lp0_vec_phys; 451 u32 lp0_vec_size; 452 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX); 453 454 struct mutex powergates_lock; 455 456 struct pinctrl_dev *pctl_dev; 457 458 struct irq_domain *domain; 459 struct irq_chip irq; 460 461 struct notifier_block clk_nb; 462 463 bool core_domain_state_synced; 464 bool core_domain_registered; 465 466 unsigned long *wake_type_level_map; 467 unsigned long *wake_type_dual_edge_map; 468 unsigned long *wake_sw_status_map; 469 unsigned long *wake_cntrl_level_map; 470 struct syscore_ops syscore; 471 }; 472 473 static struct tegra_pmc *pmc = &(struct tegra_pmc) { 474 .base = NULL, 475 .suspend_mode = TEGRA_SUSPEND_NOT_READY, 476 }; 477 478 static inline struct tegra_powergate * 479 to_powergate(struct generic_pm_domain *domain) 480 { 481 return container_of(domain, struct tegra_powergate, genpd); 482 } 483 484 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset) 485 { 486 struct arm_smccc_res res; 487 488 if (pmc->tz_only) { 489 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0, 490 0, 0, 0, &res); 491 if (res.a0) { 492 if (pmc->dev) 493 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", 494 __func__, res.a0); 495 else 496 pr_warn("%s(): SMC failed: %lu\n", __func__, 497 res.a0); 498 } 499 500 return res.a1; 501 } 502 503 return readl(pmc->base + offset); 504 } 505 506 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value, 507 unsigned long offset) 508 { 509 struct arm_smccc_res res; 510 511 if (pmc->tz_only) { 512 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset, 513 value, 0, 0, 0, 0, &res); 514 if (res.a0) { 515 if (pmc->dev) 516 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", 517 __func__, res.a0); 518 else 519 pr_warn("%s(): SMC failed: %lu\n", __func__, 520 res.a0); 521 } 522 } else { 523 writel(value, pmc->base + offset); 524 } 525 } 526 527 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset) 528 { 529 if (pmc->tz_only) 530 return tegra_pmc_readl(pmc, offset); 531 532 return readl(pmc->scratch + offset); 533 } 534 535 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value, 536 unsigned long offset) 537 { 538 if (pmc->tz_only) 539 tegra_pmc_writel(pmc, value, offset); 540 else 541 writel(value, pmc->scratch + offset); 542 } 543 544 /* 545 * TODO Figure out a way to call this with the struct tegra_pmc * passed in. 546 * This currently doesn't work because readx_poll_timeout() can only operate 547 * on functions that take a single argument. 548 */ 549 static inline bool tegra_powergate_state(int id) 550 { 551 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 552 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0; 553 else 554 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0; 555 } 556 557 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id) 558 { 559 return (pmc->soc && pmc->soc->powergates[id]); 560 } 561 562 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id) 563 { 564 return test_bit(id, pmc->powergates_available); 565 } 566 567 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) 568 { 569 unsigned int i; 570 571 if (!pmc || !pmc->soc || !name) 572 return -EINVAL; 573 574 for (i = 0; i < pmc->soc->num_powergates; i++) { 575 if (!tegra_powergate_is_valid(pmc, i)) 576 continue; 577 578 if (!strcmp(name, pmc->soc->powergates[i])) 579 return i; 580 } 581 582 return -ENODEV; 583 } 584 585 static int tegra20_powergate_set(struct tegra_pmc *pmc, unsigned int id, 586 bool new_state) 587 { 588 unsigned int retries = 100; 589 bool status; 590 int ret; 591 592 /* 593 * As per TRM documentation, the toggle command will be dropped by PMC 594 * if there is contention with a HW-initiated toggling (i.e. CPU core 595 * power-gated), the command should be retried in that case. 596 */ 597 do { 598 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 599 600 /* wait for PMC to execute the command */ 601 ret = readx_poll_timeout(tegra_powergate_state, id, status, 602 status == new_state, 1, 10); 603 } while (ret == -ETIMEDOUT && retries--); 604 605 return ret; 606 } 607 608 static inline bool tegra_powergate_toggle_ready(struct tegra_pmc *pmc) 609 { 610 return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START); 611 } 612 613 static int tegra114_powergate_set(struct tegra_pmc *pmc, unsigned int id, 614 bool new_state) 615 { 616 bool status; 617 int err; 618 619 /* wait while PMC power gating is contended */ 620 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status, 621 status == true, 1, 100); 622 if (err) 623 return err; 624 625 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 626 627 /* wait for PMC to accept the command */ 628 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status, 629 status == true, 1, 100); 630 if (err) 631 return err; 632 633 /* wait for PMC to execute the command */ 634 err = readx_poll_timeout(tegra_powergate_state, id, status, 635 status == new_state, 10, 100000); 636 if (err) 637 return err; 638 639 return 0; 640 } 641 642 /** 643 * tegra_powergate_set() - set the state of a partition 644 * @pmc: power management controller 645 * @id: partition ID 646 * @new_state: new state of the partition 647 */ 648 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id, 649 bool new_state) 650 { 651 int err; 652 653 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 654 return -EINVAL; 655 656 mutex_lock(&pmc->powergates_lock); 657 658 if (tegra_powergate_state(id) == new_state) { 659 mutex_unlock(&pmc->powergates_lock); 660 return 0; 661 } 662 663 err = pmc->soc->powergate_set(pmc, id, new_state); 664 665 mutex_unlock(&pmc->powergates_lock); 666 667 return err; 668 } 669 670 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc, 671 unsigned int id) 672 { 673 u32 mask; 674 675 mutex_lock(&pmc->powergates_lock); 676 677 /* 678 * On Tegra124 and later, the clamps for the GPU are controlled by a 679 * separate register (with different semantics). 680 */ 681 if (id == TEGRA_POWERGATE_3D) { 682 if (pmc->soc->has_gpu_clamps) { 683 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL); 684 goto out; 685 } 686 } 687 688 /* 689 * Tegra 2 has a bug where PCIE and VDE clamping masks are 690 * swapped relatively to the partition ids 691 */ 692 if (id == TEGRA_POWERGATE_VDEC) 693 mask = (1 << TEGRA_POWERGATE_PCIE); 694 else if (id == TEGRA_POWERGATE_PCIE) 695 mask = (1 << TEGRA_POWERGATE_VDEC); 696 else 697 mask = (1 << id); 698 699 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING); 700 701 out: 702 mutex_unlock(&pmc->powergates_lock); 703 704 return 0; 705 } 706 707 static int tegra_powergate_prepare_clocks(struct tegra_powergate *pg) 708 { 709 unsigned long safe_rate = 100 * 1000 * 1000; 710 unsigned int i; 711 int err; 712 713 for (i = 0; i < pg->num_clks; i++) { 714 pg->clk_rates[i] = clk_get_rate(pg->clks[i]); 715 716 if (!pg->clk_rates[i]) { 717 err = -EINVAL; 718 goto out; 719 } 720 721 if (pg->clk_rates[i] <= safe_rate) 722 continue; 723 724 /* 725 * We don't know whether voltage state is okay for the 726 * current clock rate, hence it's better to temporally 727 * switch clock to a safe rate which is suitable for 728 * all voltages, before enabling the clock. 729 */ 730 err = clk_set_rate(pg->clks[i], safe_rate); 731 if (err) 732 goto out; 733 } 734 735 return 0; 736 737 out: 738 while (i--) 739 clk_set_rate(pg->clks[i], pg->clk_rates[i]); 740 741 return err; 742 } 743 744 static int tegra_powergate_unprepare_clocks(struct tegra_powergate *pg) 745 { 746 unsigned int i; 747 int err; 748 749 for (i = 0; i < pg->num_clks; i++) { 750 err = clk_set_rate(pg->clks[i], pg->clk_rates[i]); 751 if (err) 752 return err; 753 } 754 755 return 0; 756 } 757 758 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg) 759 { 760 unsigned int i; 761 762 for (i = 0; i < pg->num_clks; i++) 763 clk_disable_unprepare(pg->clks[i]); 764 } 765 766 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg) 767 { 768 unsigned int i; 769 int err; 770 771 for (i = 0; i < pg->num_clks; i++) { 772 err = clk_prepare_enable(pg->clks[i]); 773 if (err) 774 goto out; 775 } 776 777 return 0; 778 779 out: 780 while (i--) 781 clk_disable_unprepare(pg->clks[i]); 782 783 return err; 784 } 785 786 static int tegra_powergate_power_up(struct tegra_powergate *pg, 787 bool disable_clocks) 788 { 789 int err; 790 791 err = reset_control_assert(pg->reset); 792 if (err) 793 return err; 794 795 usleep_range(10, 20); 796 797 err = tegra_powergate_set(pg->pmc, pg->id, true); 798 if (err < 0) 799 return err; 800 801 usleep_range(10, 20); 802 803 err = tegra_powergate_prepare_clocks(pg); 804 if (err) 805 goto powergate_off; 806 807 err = tegra_powergate_enable_clocks(pg); 808 if (err) 809 goto unprepare_clks; 810 811 usleep_range(10, 20); 812 813 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id); 814 if (err) 815 goto disable_clks; 816 817 usleep_range(10, 20); 818 819 err = reset_control_deassert(pg->reset); 820 if (err) 821 goto disable_clks; 822 823 usleep_range(10, 20); 824 825 if (pg->pmc->soc->needs_mbist_war) 826 err = tegra210_clk_handle_mbist_war(pg->id); 827 if (err) 828 goto disable_clks; 829 830 if (disable_clocks) 831 tegra_powergate_disable_clocks(pg); 832 833 err = tegra_powergate_unprepare_clocks(pg); 834 if (err) 835 return err; 836 837 return 0; 838 839 disable_clks: 840 tegra_powergate_disable_clocks(pg); 841 usleep_range(10, 20); 842 843 unprepare_clks: 844 tegra_powergate_unprepare_clocks(pg); 845 846 powergate_off: 847 tegra_powergate_set(pg->pmc, pg->id, false); 848 849 return err; 850 } 851 852 static int tegra_powergate_power_down(struct tegra_powergate *pg) 853 { 854 int err; 855 856 err = tegra_powergate_prepare_clocks(pg); 857 if (err) 858 return err; 859 860 err = tegra_powergate_enable_clocks(pg); 861 if (err) 862 goto unprepare_clks; 863 864 usleep_range(10, 20); 865 866 err = reset_control_assert(pg->reset); 867 if (err) 868 goto disable_clks; 869 870 usleep_range(10, 20); 871 872 tegra_powergate_disable_clocks(pg); 873 874 usleep_range(10, 20); 875 876 err = tegra_powergate_set(pg->pmc, pg->id, false); 877 if (err) 878 goto assert_resets; 879 880 err = tegra_powergate_unprepare_clocks(pg); 881 if (err) 882 return err; 883 884 return 0; 885 886 assert_resets: 887 tegra_powergate_enable_clocks(pg); 888 usleep_range(10, 20); 889 reset_control_deassert(pg->reset); 890 usleep_range(10, 20); 891 892 disable_clks: 893 tegra_powergate_disable_clocks(pg); 894 895 unprepare_clks: 896 tegra_powergate_unprepare_clocks(pg); 897 898 return err; 899 } 900 901 static int tegra_genpd_power_on(struct generic_pm_domain *domain) 902 { 903 struct tegra_powergate *pg = to_powergate(domain); 904 struct device *dev = pg->pmc->dev; 905 int err; 906 907 err = tegra_powergate_power_up(pg, true); 908 if (err) { 909 dev_err(dev, "failed to turn on PM domain %s: %d\n", 910 pg->genpd.name, err); 911 goto out; 912 } 913 914 reset_control_release(pg->reset); 915 916 out: 917 return err; 918 } 919 920 static int tegra_genpd_power_off(struct generic_pm_domain *domain) 921 { 922 struct tegra_powergate *pg = to_powergate(domain); 923 struct device *dev = pg->pmc->dev; 924 int err; 925 926 err = reset_control_acquire(pg->reset); 927 if (err < 0) { 928 dev_err(dev, "failed to acquire resets for PM domain %s: %d\n", 929 pg->genpd.name, err); 930 return err; 931 } 932 933 err = tegra_powergate_power_down(pg); 934 if (err) { 935 dev_err(dev, "failed to turn off PM domain %s: %d\n", 936 pg->genpd.name, err); 937 reset_control_release(pg->reset); 938 } 939 940 return err; 941 } 942 943 /** 944 * tegra_powergate_power_on() - power on partition 945 * @id: partition ID 946 */ 947 int tegra_powergate_power_on(unsigned int id) 948 { 949 if (!tegra_powergate_is_available(pmc, id)) 950 return -EINVAL; 951 952 return tegra_powergate_set(pmc, id, true); 953 } 954 EXPORT_SYMBOL(tegra_powergate_power_on); 955 956 /** 957 * tegra_powergate_power_off() - power off partition 958 * @id: partition ID 959 */ 960 int tegra_powergate_power_off(unsigned int id) 961 { 962 if (!tegra_powergate_is_available(pmc, id)) 963 return -EINVAL; 964 965 return tegra_powergate_set(pmc, id, false); 966 } 967 EXPORT_SYMBOL(tegra_powergate_power_off); 968 969 /** 970 * tegra_powergate_is_powered() - check if partition is powered 971 * @pmc: power management controller 972 * @id: partition ID 973 */ 974 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id) 975 { 976 if (!tegra_powergate_is_valid(pmc, id)) 977 return -EINVAL; 978 979 return tegra_powergate_state(id); 980 } 981 982 /** 983 * tegra_powergate_remove_clamping() - remove power clamps for partition 984 * @id: partition ID 985 */ 986 int tegra_powergate_remove_clamping(unsigned int id) 987 { 988 if (!tegra_powergate_is_available(pmc, id)) 989 return -EINVAL; 990 991 return __tegra_powergate_remove_clamping(pmc, id); 992 } 993 EXPORT_SYMBOL(tegra_powergate_remove_clamping); 994 995 /** 996 * tegra_powergate_sequence_power_up() - power up partition 997 * @id: partition ID 998 * @clk: clock for partition 999 * @rst: reset for partition 1000 * 1001 * Must be called with clk disabled, and returns with clk enabled. 1002 */ 1003 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, 1004 struct reset_control *rst) 1005 { 1006 struct tegra_powergate *pg; 1007 int err; 1008 1009 if (!tegra_powergate_is_available(pmc, id)) 1010 return -EINVAL; 1011 1012 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 1013 if (!pg) 1014 return -ENOMEM; 1015 1016 pg->clk_rates = kzalloc(sizeof(*pg->clk_rates), GFP_KERNEL); 1017 if (!pg->clk_rates) { 1018 kfree(pg->clks); 1019 return -ENOMEM; 1020 } 1021 1022 pg->id = id; 1023 pg->clks = &clk; 1024 pg->num_clks = 1; 1025 pg->reset = rst; 1026 pg->pmc = pmc; 1027 1028 err = tegra_powergate_power_up(pg, false); 1029 if (err) 1030 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id, 1031 err); 1032 1033 kfree(pg->clk_rates); 1034 kfree(pg); 1035 1036 return err; 1037 } 1038 EXPORT_SYMBOL(tegra_powergate_sequence_power_up); 1039 1040 /** 1041 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID 1042 * @pmc: power management controller 1043 * @cpuid: CPU partition ID 1044 * 1045 * Returns the partition ID corresponding to the CPU partition ID or a 1046 * negative error code on failure. 1047 */ 1048 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc, 1049 unsigned int cpuid) 1050 { 1051 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) 1052 return pmc->soc->cpu_powergates[cpuid]; 1053 1054 return -EINVAL; 1055 } 1056 1057 /** 1058 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered 1059 * @cpuid: CPU partition ID 1060 */ 1061 bool tegra_pmc_cpu_is_powered(unsigned int cpuid) 1062 { 1063 int id; 1064 1065 id = tegra_get_cpu_powergate_id(pmc, cpuid); 1066 if (id < 0) 1067 return false; 1068 1069 return tegra_powergate_is_powered(pmc, id); 1070 } 1071 1072 /** 1073 * tegra_pmc_cpu_power_on() - power on CPU partition 1074 * @cpuid: CPU partition ID 1075 */ 1076 int tegra_pmc_cpu_power_on(unsigned int cpuid) 1077 { 1078 int id; 1079 1080 id = tegra_get_cpu_powergate_id(pmc, cpuid); 1081 if (id < 0) 1082 return id; 1083 1084 return tegra_powergate_set(pmc, id, true); 1085 } 1086 1087 /** 1088 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition 1089 * @cpuid: CPU partition ID 1090 */ 1091 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid) 1092 { 1093 int id; 1094 1095 id = tegra_get_cpu_powergate_id(pmc, cpuid); 1096 if (id < 0) 1097 return id; 1098 1099 return tegra_powergate_remove_clamping(id); 1100 } 1101 1102 static void tegra_pmc_program_reboot_reason(const char *cmd) 1103 { 1104 u32 value; 1105 1106 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0); 1107 value &= ~PMC_SCRATCH0_MODE_MASK; 1108 1109 if (cmd) { 1110 if (strcmp(cmd, "recovery") == 0) 1111 value |= PMC_SCRATCH0_MODE_RECOVERY; 1112 1113 if (strcmp(cmd, "bootloader") == 0) 1114 value |= PMC_SCRATCH0_MODE_BOOTLOADER; 1115 1116 if (strcmp(cmd, "forced-recovery") == 0) 1117 value |= PMC_SCRATCH0_MODE_RCM; 1118 } 1119 1120 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0); 1121 } 1122 1123 static int tegra_pmc_reboot_notify(struct notifier_block *this, 1124 unsigned long action, void *data) 1125 { 1126 if (action == SYS_RESTART) 1127 tegra_pmc_program_reboot_reason(data); 1128 1129 return NOTIFY_DONE; 1130 } 1131 1132 static struct notifier_block tegra_pmc_reboot_notifier = { 1133 .notifier_call = tegra_pmc_reboot_notify, 1134 }; 1135 1136 static void tegra_pmc_restart(void) 1137 { 1138 u32 value; 1139 1140 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */ 1141 value = tegra_pmc_readl(pmc, PMC_CNTRL); 1142 value |= PMC_CNTRL_MAIN_RST; 1143 tegra_pmc_writel(pmc, value, PMC_CNTRL); 1144 } 1145 1146 static int tegra_pmc_restart_handler(struct sys_off_data *data) 1147 { 1148 tegra_pmc_restart(); 1149 1150 return NOTIFY_DONE; 1151 } 1152 1153 static int tegra_pmc_power_off_handler(struct sys_off_data *data) 1154 { 1155 /* 1156 * Reboot Nexus 7 into special bootloader mode if USB cable is 1157 * connected in order to display battery status and power off. 1158 */ 1159 if (of_machine_is_compatible("asus,grouper") && 1160 power_supply_is_system_supplied()) { 1161 const u32 go_to_charger_mode = 0xa5a55a5a; 1162 1163 tegra_pmc_writel(pmc, go_to_charger_mode, PMC_SCRATCH37); 1164 tegra_pmc_restart(); 1165 } 1166 1167 return NOTIFY_DONE; 1168 } 1169 1170 static int powergate_show(struct seq_file *s, void *data) 1171 { 1172 unsigned int i; 1173 int status; 1174 1175 seq_printf(s, " powergate powered\n"); 1176 seq_printf(s, "------------------\n"); 1177 1178 for (i = 0; i < pmc->soc->num_powergates; i++) { 1179 status = tegra_powergate_is_powered(pmc, i); 1180 if (status < 0) 1181 continue; 1182 1183 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], 1184 status ? "yes" : "no"); 1185 } 1186 1187 return 0; 1188 } 1189 1190 DEFINE_SHOW_ATTRIBUTE(powergate); 1191 1192 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg, 1193 struct device_node *np) 1194 { 1195 struct clk *clk; 1196 unsigned int i, count; 1197 int err; 1198 1199 count = of_clk_get_parent_count(np); 1200 if (count == 0) 1201 return -ENODEV; 1202 1203 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL); 1204 if (!pg->clks) 1205 return -ENOMEM; 1206 1207 pg->clk_rates = kcalloc(count, sizeof(*pg->clk_rates), GFP_KERNEL); 1208 if (!pg->clk_rates) { 1209 kfree(pg->clks); 1210 return -ENOMEM; 1211 } 1212 1213 for (i = 0; i < count; i++) { 1214 pg->clks[i] = of_clk_get(np, i); 1215 if (IS_ERR(pg->clks[i])) { 1216 err = PTR_ERR(pg->clks[i]); 1217 goto err; 1218 } 1219 } 1220 1221 pg->num_clks = count; 1222 1223 return 0; 1224 1225 err: 1226 while (i--) 1227 clk_put(pg->clks[i]); 1228 1229 kfree(pg->clk_rates); 1230 kfree(pg->clks); 1231 1232 return err; 1233 } 1234 1235 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg, 1236 struct device_node *np, bool off) 1237 { 1238 struct device *dev = pg->pmc->dev; 1239 int err; 1240 1241 pg->reset = of_reset_control_array_get_exclusive_released(np); 1242 if (IS_ERR(pg->reset)) { 1243 err = PTR_ERR(pg->reset); 1244 dev_err(dev, "failed to get device resets: %d\n", err); 1245 return err; 1246 } 1247 1248 err = reset_control_acquire(pg->reset); 1249 if (err < 0) { 1250 pr_err("failed to acquire resets: %d\n", err); 1251 goto out; 1252 } 1253 1254 if (off) { 1255 err = reset_control_assert(pg->reset); 1256 } else { 1257 err = reset_control_deassert(pg->reset); 1258 if (err < 0) 1259 goto out; 1260 1261 reset_control_release(pg->reset); 1262 } 1263 1264 out: 1265 if (err) { 1266 reset_control_release(pg->reset); 1267 reset_control_put(pg->reset); 1268 } 1269 1270 return err; 1271 } 1272 1273 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) 1274 { 1275 struct device *dev = pmc->dev; 1276 struct tegra_powergate *pg; 1277 int id, err = 0; 1278 bool off; 1279 1280 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 1281 if (!pg) 1282 return -ENOMEM; 1283 1284 id = tegra_powergate_lookup(pmc, np->name); 1285 if (id < 0) { 1286 dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id); 1287 err = -ENODEV; 1288 goto free_mem; 1289 } 1290 1291 /* 1292 * Clear the bit for this powergate so it cannot be managed 1293 * directly via the legacy APIs for controlling powergates. 1294 */ 1295 clear_bit(id, pmc->powergates_available); 1296 1297 pg->id = id; 1298 pg->genpd.name = np->name; 1299 pg->genpd.power_off = tegra_genpd_power_off; 1300 pg->genpd.power_on = tegra_genpd_power_on; 1301 pg->pmc = pmc; 1302 1303 off = !tegra_powergate_is_powered(pmc, pg->id); 1304 1305 err = tegra_powergate_of_get_clks(pg, np); 1306 if (err < 0) { 1307 dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err); 1308 goto set_available; 1309 } 1310 1311 err = tegra_powergate_of_get_resets(pg, np, off); 1312 if (err < 0) { 1313 dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err); 1314 goto remove_clks; 1315 } 1316 1317 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) { 1318 if (off) 1319 WARN_ON(tegra_powergate_power_up(pg, true)); 1320 1321 goto remove_resets; 1322 } 1323 1324 err = pm_genpd_init(&pg->genpd, NULL, off); 1325 if (err < 0) { 1326 dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np, 1327 err); 1328 goto remove_resets; 1329 } 1330 1331 err = of_genpd_add_provider_simple(np, &pg->genpd); 1332 if (err < 0) { 1333 dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n", 1334 np, err); 1335 goto remove_genpd; 1336 } 1337 1338 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name); 1339 1340 return 0; 1341 1342 remove_genpd: 1343 pm_genpd_remove(&pg->genpd); 1344 1345 remove_resets: 1346 reset_control_put(pg->reset); 1347 1348 remove_clks: 1349 while (pg->num_clks--) 1350 clk_put(pg->clks[pg->num_clks]); 1351 1352 kfree(pg->clks); 1353 1354 set_available: 1355 set_bit(id, pmc->powergates_available); 1356 1357 free_mem: 1358 kfree(pg); 1359 1360 return err; 1361 } 1362 1363 bool tegra_pmc_core_domain_state_synced(void) 1364 { 1365 return pmc->core_domain_state_synced; 1366 } 1367 1368 static int 1369 tegra_pmc_core_pd_set_performance_state(struct generic_pm_domain *genpd, 1370 unsigned int level) 1371 { 1372 struct dev_pm_opp *opp; 1373 int err; 1374 1375 opp = dev_pm_opp_find_level_ceil(&genpd->dev, &level); 1376 if (IS_ERR(opp)) { 1377 dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n", 1378 level, opp); 1379 return PTR_ERR(opp); 1380 } 1381 1382 mutex_lock(&pmc->powergates_lock); 1383 err = dev_pm_opp_set_opp(pmc->dev, opp); 1384 mutex_unlock(&pmc->powergates_lock); 1385 1386 dev_pm_opp_put(opp); 1387 1388 if (err) { 1389 dev_err(&genpd->dev, "failed to set voltage to %duV: %d\n", 1390 level, err); 1391 return err; 1392 } 1393 1394 return 0; 1395 } 1396 1397 static int tegra_pmc_core_pd_add(struct tegra_pmc *pmc, struct device_node *np) 1398 { 1399 struct generic_pm_domain *genpd; 1400 const char *rname[] = { "core", NULL}; 1401 int err; 1402 1403 genpd = devm_kzalloc(pmc->dev, sizeof(*genpd), GFP_KERNEL); 1404 if (!genpd) 1405 return -ENOMEM; 1406 1407 genpd->name = "core"; 1408 genpd->set_performance_state = tegra_pmc_core_pd_set_performance_state; 1409 1410 err = devm_pm_opp_set_regulators(pmc->dev, rname); 1411 if (err) 1412 return dev_err_probe(pmc->dev, err, 1413 "failed to set core OPP regulator\n"); 1414 1415 err = pm_genpd_init(genpd, NULL, false); 1416 if (err) { 1417 dev_err(pmc->dev, "failed to init core genpd: %d\n", err); 1418 return err; 1419 } 1420 1421 err = of_genpd_add_provider_simple(np, genpd); 1422 if (err) { 1423 dev_err(pmc->dev, "failed to add core genpd: %d\n", err); 1424 goto remove_genpd; 1425 } 1426 1427 pmc->core_domain_registered = true; 1428 1429 return 0; 1430 1431 remove_genpd: 1432 pm_genpd_remove(genpd); 1433 1434 return err; 1435 } 1436 1437 static int tegra_powergate_init(struct tegra_pmc *pmc, 1438 struct device_node *parent) 1439 { 1440 struct of_phandle_args child_args, parent_args; 1441 struct device_node *np, *child; 1442 int err = 0; 1443 1444 /* 1445 * Core power domain is the parent of powergate domains, hence it 1446 * should be registered first. 1447 */ 1448 np = of_get_child_by_name(parent, "core-domain"); 1449 if (np) { 1450 err = tegra_pmc_core_pd_add(pmc, np); 1451 of_node_put(np); 1452 if (err) 1453 return err; 1454 } 1455 1456 np = of_get_child_by_name(parent, "powergates"); 1457 if (!np) 1458 return 0; 1459 1460 for_each_child_of_node(np, child) { 1461 err = tegra_powergate_add(pmc, child); 1462 if (err < 0) { 1463 of_node_put(child); 1464 break; 1465 } 1466 1467 if (of_parse_phandle_with_args(child, "power-domains", 1468 "#power-domain-cells", 1469 0, &parent_args)) 1470 continue; 1471 1472 child_args.np = child; 1473 child_args.args_count = 0; 1474 1475 err = of_genpd_add_subdomain(&parent_args, &child_args); 1476 of_node_put(parent_args.np); 1477 if (err) { 1478 of_node_put(child); 1479 break; 1480 } 1481 } 1482 1483 of_node_put(np); 1484 1485 return err; 1486 } 1487 1488 static void tegra_powergate_remove(struct generic_pm_domain *genpd) 1489 { 1490 struct tegra_powergate *pg = to_powergate(genpd); 1491 1492 reset_control_put(pg->reset); 1493 1494 while (pg->num_clks--) 1495 clk_put(pg->clks[pg->num_clks]); 1496 1497 kfree(pg->clks); 1498 1499 set_bit(pg->id, pmc->powergates_available); 1500 1501 kfree(pg); 1502 } 1503 1504 static void tegra_powergate_remove_all(struct device_node *parent) 1505 { 1506 struct generic_pm_domain *genpd; 1507 struct device_node *np, *child; 1508 1509 np = of_get_child_by_name(parent, "powergates"); 1510 if (!np) 1511 return; 1512 1513 for_each_child_of_node(np, child) { 1514 of_genpd_del_provider(child); 1515 1516 genpd = of_genpd_remove_last(child); 1517 if (IS_ERR(genpd)) 1518 continue; 1519 1520 tegra_powergate_remove(genpd); 1521 } 1522 1523 of_node_put(np); 1524 1525 np = of_get_child_by_name(parent, "core-domain"); 1526 if (np) { 1527 of_genpd_del_provider(np); 1528 of_genpd_remove_last(np); 1529 } 1530 } 1531 1532 static const struct tegra_io_pad_soc * 1533 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id) 1534 { 1535 unsigned int i; 1536 1537 for (i = 0; i < pmc->soc->num_io_pads; i++) 1538 if (pmc->soc->io_pads[i].id == id) 1539 return &pmc->soc->io_pads[i]; 1540 1541 return NULL; 1542 } 1543 1544 static int tegra_io_pad_prepare(struct tegra_pmc *pmc, 1545 const struct tegra_io_pad_soc *pad, 1546 unsigned long *request, 1547 unsigned long *status, 1548 u32 *mask) 1549 { 1550 unsigned long rate, value; 1551 1552 if (pad->dpd == UINT_MAX) 1553 return -EINVAL; 1554 1555 *request = pad->request; 1556 *status = pad->status; 1557 *mask = BIT(pad->dpd); 1558 1559 if (pmc->clk) { 1560 rate = pmc->rate; 1561 if (!rate) { 1562 dev_err(pmc->dev, "failed to get clock rate\n"); 1563 return -ENODEV; 1564 } 1565 1566 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE); 1567 1568 /* must be at least 200 ns, in APB (PCLK) clock cycles */ 1569 value = DIV_ROUND_UP(1000000000, rate); 1570 value = DIV_ROUND_UP(200, value); 1571 tegra_pmc_writel(pmc, value, SEL_DPD_TIM); 1572 } 1573 1574 return 0; 1575 } 1576 1577 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset, 1578 u32 mask, u32 val, unsigned long timeout) 1579 { 1580 u32 value; 1581 1582 timeout = jiffies + msecs_to_jiffies(timeout); 1583 1584 while (time_after(timeout, jiffies)) { 1585 value = tegra_pmc_readl(pmc, offset); 1586 if ((value & mask) == val) 1587 return 0; 1588 1589 usleep_range(250, 1000); 1590 } 1591 1592 return -ETIMEDOUT; 1593 } 1594 1595 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc) 1596 { 1597 if (pmc->clk) 1598 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE); 1599 } 1600 1601 /** 1602 * tegra_io_pad_power_enable() - enable power to I/O pad 1603 * @id: Tegra I/O pad ID for which to enable power 1604 * 1605 * Returns: 0 on success or a negative error code on failure. 1606 */ 1607 int tegra_io_pad_power_enable(enum tegra_io_pad id) 1608 { 1609 const struct tegra_io_pad_soc *pad; 1610 unsigned long request, status; 1611 u32 mask; 1612 int err; 1613 1614 pad = tegra_io_pad_find(pmc, id); 1615 if (!pad) { 1616 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); 1617 return -ENOENT; 1618 } 1619 1620 mutex_lock(&pmc->powergates_lock); 1621 1622 err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask); 1623 if (err < 0) { 1624 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); 1625 goto unlock; 1626 } 1627 1628 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request); 1629 1630 err = tegra_io_pad_poll(pmc, status, mask, 0, 250); 1631 if (err < 0) { 1632 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err); 1633 goto unlock; 1634 } 1635 1636 tegra_io_pad_unprepare(pmc); 1637 1638 unlock: 1639 mutex_unlock(&pmc->powergates_lock); 1640 return err; 1641 } 1642 EXPORT_SYMBOL(tegra_io_pad_power_enable); 1643 1644 /** 1645 * tegra_io_pad_power_disable() - disable power to I/O pad 1646 * @id: Tegra I/O pad ID for which to disable power 1647 * 1648 * Returns: 0 on success or a negative error code on failure. 1649 */ 1650 int tegra_io_pad_power_disable(enum tegra_io_pad id) 1651 { 1652 const struct tegra_io_pad_soc *pad; 1653 unsigned long request, status; 1654 u32 mask; 1655 int err; 1656 1657 pad = tegra_io_pad_find(pmc, id); 1658 if (!pad) { 1659 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); 1660 return -ENOENT; 1661 } 1662 1663 mutex_lock(&pmc->powergates_lock); 1664 1665 err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask); 1666 if (err < 0) { 1667 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); 1668 goto unlock; 1669 } 1670 1671 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request); 1672 1673 err = tegra_io_pad_poll(pmc, status, mask, mask, 250); 1674 if (err < 0) { 1675 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err); 1676 goto unlock; 1677 } 1678 1679 tegra_io_pad_unprepare(pmc); 1680 1681 unlock: 1682 mutex_unlock(&pmc->powergates_lock); 1683 return err; 1684 } 1685 EXPORT_SYMBOL(tegra_io_pad_power_disable); 1686 1687 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id) 1688 { 1689 const struct tegra_io_pad_soc *pad; 1690 unsigned long status; 1691 u32 mask, value; 1692 1693 pad = tegra_io_pad_find(pmc, id); 1694 if (!pad) { 1695 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); 1696 return -ENOENT; 1697 } 1698 1699 if (pad->dpd == UINT_MAX) 1700 return -EINVAL; 1701 1702 status = pad->status; 1703 mask = BIT(pad->dpd); 1704 1705 value = tegra_pmc_readl(pmc, status); 1706 1707 return !(value & mask); 1708 } 1709 1710 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id, 1711 int voltage) 1712 { 1713 const struct tegra_io_pad_soc *pad; 1714 u32 value; 1715 1716 pad = tegra_io_pad_find(pmc, id); 1717 if (!pad) 1718 return -ENOENT; 1719 1720 if (pad->voltage == UINT_MAX) 1721 return -ENOTSUPP; 1722 1723 mutex_lock(&pmc->powergates_lock); 1724 1725 if (pmc->soc->has_impl_33v_pwr) { 1726 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); 1727 1728 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) 1729 value &= ~BIT(pad->voltage); 1730 else 1731 value |= BIT(pad->voltage); 1732 1733 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR); 1734 } else { 1735 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */ 1736 value = tegra_pmc_readl(pmc, PMC_PWR_DET); 1737 value |= BIT(pad->voltage); 1738 tegra_pmc_writel(pmc, value, PMC_PWR_DET); 1739 1740 /* update I/O voltage */ 1741 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); 1742 1743 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) 1744 value &= ~BIT(pad->voltage); 1745 else 1746 value |= BIT(pad->voltage); 1747 1748 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE); 1749 } 1750 1751 mutex_unlock(&pmc->powergates_lock); 1752 1753 usleep_range(100, 250); 1754 1755 return 0; 1756 } 1757 1758 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id) 1759 { 1760 const struct tegra_io_pad_soc *pad; 1761 u32 value; 1762 1763 pad = tegra_io_pad_find(pmc, id); 1764 if (!pad) 1765 return -ENOENT; 1766 1767 if (pad->voltage == UINT_MAX) 1768 return -ENOTSUPP; 1769 1770 if (pmc->soc->has_impl_33v_pwr) 1771 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); 1772 else 1773 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); 1774 1775 if ((value & BIT(pad->voltage)) == 0) 1776 return TEGRA_IO_PAD_VOLTAGE_1V8; 1777 1778 return TEGRA_IO_PAD_VOLTAGE_3V3; 1779 } 1780 1781 #ifdef CONFIG_PM_SLEEP 1782 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) 1783 { 1784 return pmc->suspend_mode; 1785 } 1786 1787 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) 1788 { 1789 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE) 1790 return; 1791 1792 pmc->suspend_mode = mode; 1793 } 1794 1795 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) 1796 { 1797 unsigned long long rate = 0; 1798 u64 ticks; 1799 u32 value; 1800 1801 switch (mode) { 1802 case TEGRA_SUSPEND_LP1: 1803 rate = 32768; 1804 break; 1805 1806 case TEGRA_SUSPEND_LP2: 1807 rate = pmc->rate; 1808 break; 1809 1810 default: 1811 break; 1812 } 1813 1814 if (WARN_ON_ONCE(rate == 0)) 1815 rate = 100000000; 1816 1817 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; 1818 do_div(ticks, USEC_PER_SEC); 1819 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER); 1820 1821 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; 1822 do_div(ticks, USEC_PER_SEC); 1823 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER); 1824 1825 value = tegra_pmc_readl(pmc, PMC_CNTRL); 1826 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; 1827 value |= PMC_CNTRL_CPU_PWRREQ_OE; 1828 tegra_pmc_writel(pmc, value, PMC_CNTRL); 1829 } 1830 #endif 1831 1832 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) 1833 { 1834 u32 value, values[2]; 1835 1836 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { 1837 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1838 } else { 1839 switch (value) { 1840 case 0: 1841 pmc->suspend_mode = TEGRA_SUSPEND_LP0; 1842 break; 1843 1844 case 1: 1845 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1846 break; 1847 1848 case 2: 1849 pmc->suspend_mode = TEGRA_SUSPEND_LP2; 1850 break; 1851 1852 default: 1853 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1854 break; 1855 } 1856 } 1857 1858 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); 1859 1860 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) 1861 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1862 1863 pmc->cpu_good_time = value; 1864 1865 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) 1866 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1867 1868 pmc->cpu_off_time = value; 1869 1870 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", 1871 values, ARRAY_SIZE(values))) 1872 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1873 1874 pmc->core_osc_time = values[0]; 1875 pmc->core_pmu_time = values[1]; 1876 1877 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) 1878 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1879 1880 pmc->core_off_time = value; 1881 1882 pmc->corereq_high = of_property_read_bool(np, 1883 "nvidia,core-power-req-active-high"); 1884 1885 pmc->sysclkreq_high = of_property_read_bool(np, 1886 "nvidia,sys-clock-req-active-high"); 1887 1888 pmc->combined_req = of_property_read_bool(np, 1889 "nvidia,combined-power-req"); 1890 1891 pmc->cpu_pwr_good_en = of_property_read_bool(np, 1892 "nvidia,cpu-pwr-good-en"); 1893 1894 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, 1895 ARRAY_SIZE(values))) 1896 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) 1897 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1898 1899 pmc->lp0_vec_phys = values[0]; 1900 pmc->lp0_vec_size = values[1]; 1901 1902 return 0; 1903 } 1904 1905 static int tegra_pmc_init(struct tegra_pmc *pmc) 1906 { 1907 if (pmc->soc->max_wake_events > 0) { 1908 pmc->wake_type_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); 1909 if (!pmc->wake_type_level_map) 1910 return -ENOMEM; 1911 1912 pmc->wake_type_dual_edge_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); 1913 if (!pmc->wake_type_dual_edge_map) 1914 return -ENOMEM; 1915 1916 pmc->wake_sw_status_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); 1917 if (!pmc->wake_sw_status_map) 1918 return -ENOMEM; 1919 1920 pmc->wake_cntrl_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); 1921 if (!pmc->wake_cntrl_level_map) 1922 return -ENOMEM; 1923 } 1924 1925 if (pmc->soc->init) 1926 pmc->soc->init(pmc); 1927 1928 return 0; 1929 } 1930 1931 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) 1932 { 1933 static const char disabled[] = "emergency thermal reset disabled"; 1934 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux; 1935 struct device *dev = pmc->dev; 1936 struct device_node *np; 1937 u32 value, checksum; 1938 1939 if (!pmc->soc->has_tsense_reset) 1940 return; 1941 1942 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip"); 1943 if (!np) { 1944 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); 1945 return; 1946 } 1947 1948 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { 1949 dev_err(dev, "I2C controller ID missing, %s.\n", disabled); 1950 goto out; 1951 } 1952 1953 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { 1954 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); 1955 goto out; 1956 } 1957 1958 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { 1959 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); 1960 goto out; 1961 } 1962 1963 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { 1964 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); 1965 goto out; 1966 } 1967 1968 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) 1969 pinmux = 0; 1970 1971 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); 1972 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE; 1973 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); 1974 1975 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) | 1976 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT); 1977 tegra_pmc_writel(pmc, value, PMC_SCRATCH54); 1978 1979 value = PMC_SCRATCH55_RESET_TEGRA; 1980 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT; 1981 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT; 1982 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT; 1983 1984 /* 1985 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will 1986 * contain the checksum and are currently zero, so they are not added. 1987 */ 1988 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff) 1989 + ((value >> 24) & 0xff); 1990 checksum &= 0xff; 1991 checksum = 0x100 - checksum; 1992 1993 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT; 1994 1995 tegra_pmc_writel(pmc, value, PMC_SCRATCH55); 1996 1997 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); 1998 value |= PMC_SENSOR_CTRL_ENABLE_RST; 1999 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); 2000 2001 dev_info(pmc->dev, "emergency thermal reset enabled\n"); 2002 2003 out: 2004 of_node_put(np); 2005 } 2006 2007 static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev) 2008 { 2009 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2010 2011 return pmc->soc->num_io_pads; 2012 } 2013 2014 static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl, 2015 unsigned int group) 2016 { 2017 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl); 2018 2019 return pmc->soc->io_pads[group].name; 2020 } 2021 2022 static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev, 2023 unsigned int group, 2024 const unsigned int **pins, 2025 unsigned int *num_pins) 2026 { 2027 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2028 2029 *pins = &pmc->soc->io_pads[group].id; 2030 *num_pins = 1; 2031 2032 return 0; 2033 } 2034 2035 static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = { 2036 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count, 2037 .get_group_name = tegra_io_pad_pinctrl_get_group_name, 2038 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins, 2039 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 2040 .dt_free_map = pinconf_generic_dt_free_map, 2041 }; 2042 2043 static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev, 2044 unsigned int pin, unsigned long *config) 2045 { 2046 enum pin_config_param param = pinconf_to_config_param(*config); 2047 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2048 const struct tegra_io_pad_soc *pad; 2049 int ret; 2050 u32 arg; 2051 2052 pad = tegra_io_pad_find(pmc, pin); 2053 if (!pad) 2054 return -EINVAL; 2055 2056 switch (param) { 2057 case PIN_CONFIG_POWER_SOURCE: 2058 ret = tegra_io_pad_get_voltage(pmc, pad->id); 2059 if (ret < 0) 2060 return ret; 2061 2062 arg = ret; 2063 break; 2064 2065 case PIN_CONFIG_MODE_LOW_POWER: 2066 ret = tegra_io_pad_is_powered(pmc, pad->id); 2067 if (ret < 0) 2068 return ret; 2069 2070 arg = !ret; 2071 break; 2072 2073 default: 2074 return -EINVAL; 2075 } 2076 2077 *config = pinconf_to_config_packed(param, arg); 2078 2079 return 0; 2080 } 2081 2082 static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev, 2083 unsigned int pin, unsigned long *configs, 2084 unsigned int num_configs) 2085 { 2086 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2087 const struct tegra_io_pad_soc *pad; 2088 enum pin_config_param param; 2089 unsigned int i; 2090 int err; 2091 u32 arg; 2092 2093 pad = tegra_io_pad_find(pmc, pin); 2094 if (!pad) 2095 return -EINVAL; 2096 2097 for (i = 0; i < num_configs; ++i) { 2098 param = pinconf_to_config_param(configs[i]); 2099 arg = pinconf_to_config_argument(configs[i]); 2100 2101 switch (param) { 2102 case PIN_CONFIG_MODE_LOW_POWER: 2103 if (arg) 2104 err = tegra_io_pad_power_disable(pad->id); 2105 else 2106 err = tegra_io_pad_power_enable(pad->id); 2107 if (err) 2108 return err; 2109 break; 2110 case PIN_CONFIG_POWER_SOURCE: 2111 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 && 2112 arg != TEGRA_IO_PAD_VOLTAGE_3V3) 2113 return -EINVAL; 2114 err = tegra_io_pad_set_voltage(pmc, pad->id, arg); 2115 if (err) 2116 return err; 2117 break; 2118 default: 2119 return -EINVAL; 2120 } 2121 } 2122 2123 return 0; 2124 } 2125 2126 static const struct pinconf_ops tegra_io_pad_pinconf_ops = { 2127 .pin_config_get = tegra_io_pad_pinconf_get, 2128 .pin_config_set = tegra_io_pad_pinconf_set, 2129 .is_generic = true, 2130 }; 2131 2132 static struct pinctrl_desc tegra_pmc_pctl_desc = { 2133 .pctlops = &tegra_io_pad_pinctrl_ops, 2134 .confops = &tegra_io_pad_pinconf_ops, 2135 }; 2136 2137 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc) 2138 { 2139 int err; 2140 2141 if (!pmc->soc->num_pin_descs) 2142 return 0; 2143 2144 tegra_pmc_pctl_desc.name = dev_name(pmc->dev); 2145 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs; 2146 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs; 2147 2148 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc, 2149 pmc); 2150 if (IS_ERR(pmc->pctl_dev)) { 2151 err = PTR_ERR(pmc->pctl_dev); 2152 dev_err(pmc->dev, "failed to register pin controller: %d\n", 2153 err); 2154 return err; 2155 } 2156 2157 return 0; 2158 } 2159 2160 static ssize_t reset_reason_show(struct device *dev, 2161 struct device_attribute *attr, char *buf) 2162 { 2163 u32 value; 2164 2165 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); 2166 value &= pmc->soc->regs->rst_source_mask; 2167 value >>= pmc->soc->regs->rst_source_shift; 2168 2169 if (WARN_ON(value >= pmc->soc->num_reset_sources)) 2170 return sprintf(buf, "%s\n", "UNKNOWN"); 2171 2172 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]); 2173 } 2174 2175 static DEVICE_ATTR_RO(reset_reason); 2176 2177 static ssize_t reset_level_show(struct device *dev, 2178 struct device_attribute *attr, char *buf) 2179 { 2180 u32 value; 2181 2182 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); 2183 value &= pmc->soc->regs->rst_level_mask; 2184 value >>= pmc->soc->regs->rst_level_shift; 2185 2186 if (WARN_ON(value >= pmc->soc->num_reset_levels)) 2187 return sprintf(buf, "%s\n", "UNKNOWN"); 2188 2189 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]); 2190 } 2191 2192 static DEVICE_ATTR_RO(reset_level); 2193 2194 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc) 2195 { 2196 struct device *dev = pmc->dev; 2197 int err = 0; 2198 2199 if (pmc->soc->reset_sources) { 2200 err = device_create_file(dev, &dev_attr_reset_reason); 2201 if (err < 0) 2202 dev_warn(dev, 2203 "failed to create attr \"reset_reason\": %d\n", 2204 err); 2205 } 2206 2207 if (pmc->soc->reset_levels) { 2208 err = device_create_file(dev, &dev_attr_reset_level); 2209 if (err < 0) 2210 dev_warn(dev, 2211 "failed to create attr \"reset_level\": %d\n", 2212 err); 2213 } 2214 } 2215 2216 static int tegra_pmc_irq_translate(struct irq_domain *domain, 2217 struct irq_fwspec *fwspec, 2218 unsigned long *hwirq, 2219 unsigned int *type) 2220 { 2221 if (WARN_ON(fwspec->param_count < 2)) 2222 return -EINVAL; 2223 2224 *hwirq = fwspec->param[0]; 2225 *type = fwspec->param[1]; 2226 2227 return 0; 2228 } 2229 2230 static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq, 2231 unsigned int num_irqs, void *data) 2232 { 2233 struct tegra_pmc *pmc = domain->host_data; 2234 const struct tegra_pmc_soc *soc = pmc->soc; 2235 struct irq_fwspec *fwspec = data; 2236 unsigned int i; 2237 int err = 0; 2238 2239 if (WARN_ON(num_irqs > 1)) 2240 return -EINVAL; 2241 2242 for (i = 0; i < soc->num_wake_events; i++) { 2243 const struct tegra_wake_event *event = &soc->wake_events[i]; 2244 2245 /* IRQ and simple wake events */ 2246 if (fwspec->param_count == 2) { 2247 struct irq_fwspec spec; 2248 2249 if (event->id != fwspec->param[0]) 2250 continue; 2251 2252 err = irq_domain_set_hwirq_and_chip(domain, virq, 2253 event->id, 2254 &pmc->irq, pmc); 2255 if (err < 0) 2256 break; 2257 2258 /* simple hierarchies stop at the PMC level */ 2259 if (event->irq == 0) { 2260 err = irq_domain_disconnect_hierarchy(domain->parent, virq); 2261 break; 2262 } 2263 2264 spec.fwnode = &pmc->dev->of_node->fwnode; 2265 spec.param_count = 3; 2266 spec.param[0] = GIC_SPI; 2267 spec.param[1] = event->irq; 2268 spec.param[2] = fwspec->param[1]; 2269 2270 err = irq_domain_alloc_irqs_parent(domain, virq, 2271 num_irqs, &spec); 2272 2273 break; 2274 } 2275 2276 /* GPIO wake events */ 2277 if (fwspec->param_count == 3) { 2278 if (event->gpio.instance != fwspec->param[0] || 2279 event->gpio.pin != fwspec->param[1]) 2280 continue; 2281 2282 err = irq_domain_set_hwirq_and_chip(domain, virq, 2283 event->id, 2284 &pmc->irq, pmc); 2285 2286 /* GPIO hierarchies stop at the PMC level */ 2287 if (!err && domain->parent) 2288 err = irq_domain_disconnect_hierarchy(domain->parent, 2289 virq); 2290 break; 2291 } 2292 } 2293 2294 /* If there is no wake-up event, there is no PMC mapping */ 2295 if (i == soc->num_wake_events) 2296 err = irq_domain_disconnect_hierarchy(domain, virq); 2297 2298 return err; 2299 } 2300 2301 static const struct irq_domain_ops tegra_pmc_irq_domain_ops = { 2302 .translate = tegra_pmc_irq_translate, 2303 .alloc = tegra_pmc_irq_alloc, 2304 }; 2305 2306 static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on) 2307 { 2308 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2309 unsigned int offset, bit; 2310 u32 value; 2311 2312 offset = data->hwirq / 32; 2313 bit = data->hwirq % 32; 2314 2315 /* clear wake status */ 2316 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS); 2317 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS); 2318 2319 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS); 2320 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS); 2321 2322 /* enable PMC wake */ 2323 if (data->hwirq >= 32) 2324 offset = PMC_WAKE2_MASK; 2325 else 2326 offset = PMC_WAKE_MASK; 2327 2328 value = tegra_pmc_readl(pmc, offset); 2329 2330 if (on) 2331 value |= BIT(bit); 2332 else 2333 value &= ~BIT(bit); 2334 2335 tegra_pmc_writel(pmc, value, offset); 2336 2337 return 0; 2338 } 2339 2340 static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type) 2341 { 2342 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2343 unsigned int offset, bit; 2344 u32 value; 2345 2346 offset = data->hwirq / 32; 2347 bit = data->hwirq % 32; 2348 2349 if (data->hwirq >= 32) 2350 offset = PMC_WAKE2_LEVEL; 2351 else 2352 offset = PMC_WAKE_LEVEL; 2353 2354 value = tegra_pmc_readl(pmc, offset); 2355 2356 switch (type) { 2357 case IRQ_TYPE_EDGE_RISING: 2358 case IRQ_TYPE_LEVEL_HIGH: 2359 value |= BIT(bit); 2360 break; 2361 2362 case IRQ_TYPE_EDGE_FALLING: 2363 case IRQ_TYPE_LEVEL_LOW: 2364 value &= ~BIT(bit); 2365 break; 2366 2367 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: 2368 value ^= BIT(bit); 2369 break; 2370 2371 default: 2372 return -EINVAL; 2373 } 2374 2375 tegra_pmc_writel(pmc, value, offset); 2376 2377 return 0; 2378 } 2379 2380 static void tegra186_pmc_set_wake_filters(struct tegra_pmc *pmc) 2381 { 2382 u32 value; 2383 2384 /* SW Wake (wake83) needs SR_CAPTURE filter to be enabled */ 2385 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID)); 2386 value |= WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN; 2387 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID)); 2388 dev_dbg(pmc->dev, "WAKE_AOWAKE_CNTRL_83 = 0x%x\n", value); 2389 } 2390 2391 static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) 2392 { 2393 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2394 unsigned int offset, bit; 2395 u32 value; 2396 2397 offset = data->hwirq / 32; 2398 bit = data->hwirq % 32; 2399 2400 /* clear wake status */ 2401 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq)); 2402 2403 /* route wake to tier 2 */ 2404 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); 2405 2406 if (!on) 2407 value &= ~(1 << bit); 2408 else 2409 value |= 1 << bit; 2410 2411 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); 2412 2413 /* enable wakeup event */ 2414 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq)); 2415 2416 return 0; 2417 } 2418 2419 static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type) 2420 { 2421 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2422 u32 value; 2423 2424 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); 2425 2426 switch (type) { 2427 case IRQ_TYPE_EDGE_RISING: 2428 case IRQ_TYPE_LEVEL_HIGH: 2429 value |= WAKE_AOWAKE_CNTRL_LEVEL; 2430 set_bit(data->hwirq, pmc->wake_type_level_map); 2431 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map); 2432 break; 2433 2434 case IRQ_TYPE_EDGE_FALLING: 2435 case IRQ_TYPE_LEVEL_LOW: 2436 value &= ~WAKE_AOWAKE_CNTRL_LEVEL; 2437 clear_bit(data->hwirq, pmc->wake_type_level_map); 2438 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map); 2439 break; 2440 2441 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: 2442 value ^= WAKE_AOWAKE_CNTRL_LEVEL; 2443 clear_bit(data->hwirq, pmc->wake_type_level_map); 2444 set_bit(data->hwirq, pmc->wake_type_dual_edge_map); 2445 break; 2446 2447 default: 2448 return -EINVAL; 2449 } 2450 2451 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); 2452 2453 return 0; 2454 } 2455 2456 static void tegra_irq_mask_parent(struct irq_data *data) 2457 { 2458 if (data->parent_data) 2459 irq_chip_mask_parent(data); 2460 } 2461 2462 static void tegra_irq_unmask_parent(struct irq_data *data) 2463 { 2464 if (data->parent_data) 2465 irq_chip_unmask_parent(data); 2466 } 2467 2468 static void tegra_irq_eoi_parent(struct irq_data *data) 2469 { 2470 if (data->parent_data) 2471 irq_chip_eoi_parent(data); 2472 } 2473 2474 static int tegra_irq_set_affinity_parent(struct irq_data *data, 2475 const struct cpumask *dest, 2476 bool force) 2477 { 2478 if (data->parent_data) 2479 return irq_chip_set_affinity_parent(data, dest, force); 2480 2481 return -EINVAL; 2482 } 2483 2484 static int tegra_pmc_irq_init(struct tegra_pmc *pmc) 2485 { 2486 struct irq_domain *parent = NULL; 2487 struct device_node *np; 2488 2489 np = of_irq_find_parent(pmc->dev->of_node); 2490 if (np) { 2491 parent = irq_find_host(np); 2492 of_node_put(np); 2493 } 2494 2495 if (!parent) 2496 return 0; 2497 2498 pmc->irq.name = dev_name(pmc->dev); 2499 pmc->irq.irq_mask = tegra_irq_mask_parent; 2500 pmc->irq.irq_unmask = tegra_irq_unmask_parent; 2501 pmc->irq.irq_eoi = tegra_irq_eoi_parent; 2502 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent; 2503 pmc->irq.irq_set_type = pmc->soc->irq_set_type; 2504 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake; 2505 2506 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node, 2507 &tegra_pmc_irq_domain_ops, pmc); 2508 if (!pmc->domain) { 2509 dev_err(pmc->dev, "failed to allocate domain\n"); 2510 return -ENOMEM; 2511 } 2512 2513 return 0; 2514 } 2515 2516 static int tegra_pmc_clk_notify_cb(struct notifier_block *nb, 2517 unsigned long action, void *ptr) 2518 { 2519 struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb); 2520 struct clk_notifier_data *data = ptr; 2521 2522 switch (action) { 2523 case PRE_RATE_CHANGE: 2524 mutex_lock(&pmc->powergates_lock); 2525 break; 2526 2527 case POST_RATE_CHANGE: 2528 pmc->rate = data->new_rate; 2529 fallthrough; 2530 2531 case ABORT_RATE_CHANGE: 2532 mutex_unlock(&pmc->powergates_lock); 2533 break; 2534 2535 default: 2536 WARN_ON_ONCE(1); 2537 return notifier_from_errno(-EINVAL); 2538 } 2539 2540 return NOTIFY_OK; 2541 } 2542 2543 static void pmc_clk_fence_udelay(u32 offset) 2544 { 2545 tegra_pmc_readl(pmc, offset); 2546 /* pmc clk propagation delay 2 us */ 2547 udelay(2); 2548 } 2549 2550 static u8 pmc_clk_mux_get_parent(struct clk_hw *hw) 2551 { 2552 struct pmc_clk *clk = to_pmc_clk(hw); 2553 u32 val; 2554 2555 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift; 2556 val &= PMC_CLK_OUT_MUX_MASK; 2557 2558 return val; 2559 } 2560 2561 static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index) 2562 { 2563 struct pmc_clk *clk = to_pmc_clk(hw); 2564 u32 val; 2565 2566 val = tegra_pmc_readl(pmc, clk->offs); 2567 val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift); 2568 val |= index << clk->mux_shift; 2569 tegra_pmc_writel(pmc, val, clk->offs); 2570 pmc_clk_fence_udelay(clk->offs); 2571 2572 return 0; 2573 } 2574 2575 static int pmc_clk_is_enabled(struct clk_hw *hw) 2576 { 2577 struct pmc_clk *clk = to_pmc_clk(hw); 2578 u32 val; 2579 2580 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift); 2581 2582 return val ? 1 : 0; 2583 } 2584 2585 static void pmc_clk_set_state(unsigned long offs, u32 shift, int state) 2586 { 2587 u32 val; 2588 2589 val = tegra_pmc_readl(pmc, offs); 2590 val = state ? (val | BIT(shift)) : (val & ~BIT(shift)); 2591 tegra_pmc_writel(pmc, val, offs); 2592 pmc_clk_fence_udelay(offs); 2593 } 2594 2595 static int pmc_clk_enable(struct clk_hw *hw) 2596 { 2597 struct pmc_clk *clk = to_pmc_clk(hw); 2598 2599 pmc_clk_set_state(clk->offs, clk->force_en_shift, 1); 2600 2601 return 0; 2602 } 2603 2604 static void pmc_clk_disable(struct clk_hw *hw) 2605 { 2606 struct pmc_clk *clk = to_pmc_clk(hw); 2607 2608 pmc_clk_set_state(clk->offs, clk->force_en_shift, 0); 2609 } 2610 2611 static const struct clk_ops pmc_clk_ops = { 2612 .get_parent = pmc_clk_mux_get_parent, 2613 .set_parent = pmc_clk_mux_set_parent, 2614 .determine_rate = __clk_mux_determine_rate, 2615 .is_enabled = pmc_clk_is_enabled, 2616 .enable = pmc_clk_enable, 2617 .disable = pmc_clk_disable, 2618 }; 2619 2620 static struct clk * 2621 tegra_pmc_clk_out_register(struct tegra_pmc *pmc, 2622 const struct pmc_clk_init_data *data, 2623 unsigned long offset) 2624 { 2625 struct clk_init_data init; 2626 struct pmc_clk *pmc_clk; 2627 2628 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL); 2629 if (!pmc_clk) 2630 return ERR_PTR(-ENOMEM); 2631 2632 init.name = data->name; 2633 init.ops = &pmc_clk_ops; 2634 init.parent_names = data->parents; 2635 init.num_parents = data->num_parents; 2636 init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT | 2637 CLK_SET_PARENT_GATE; 2638 2639 pmc_clk->hw.init = &init; 2640 pmc_clk->offs = offset; 2641 pmc_clk->mux_shift = data->mux_shift; 2642 pmc_clk->force_en_shift = data->force_en_shift; 2643 2644 return clk_register(NULL, &pmc_clk->hw); 2645 } 2646 2647 static int pmc_clk_gate_is_enabled(struct clk_hw *hw) 2648 { 2649 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2650 2651 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0; 2652 } 2653 2654 static int pmc_clk_gate_enable(struct clk_hw *hw) 2655 { 2656 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2657 2658 pmc_clk_set_state(gate->offs, gate->shift, 1); 2659 2660 return 0; 2661 } 2662 2663 static void pmc_clk_gate_disable(struct clk_hw *hw) 2664 { 2665 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2666 2667 pmc_clk_set_state(gate->offs, gate->shift, 0); 2668 } 2669 2670 static const struct clk_ops pmc_clk_gate_ops = { 2671 .is_enabled = pmc_clk_gate_is_enabled, 2672 .enable = pmc_clk_gate_enable, 2673 .disable = pmc_clk_gate_disable, 2674 }; 2675 2676 static struct clk * 2677 tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name, 2678 const char *parent_name, unsigned long offset, 2679 u32 shift) 2680 { 2681 struct clk_init_data init; 2682 struct pmc_clk_gate *gate; 2683 2684 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL); 2685 if (!gate) 2686 return ERR_PTR(-ENOMEM); 2687 2688 init.name = name; 2689 init.ops = &pmc_clk_gate_ops; 2690 init.parent_names = &parent_name; 2691 init.num_parents = 1; 2692 init.flags = 0; 2693 2694 gate->hw.init = &init; 2695 gate->offs = offset; 2696 gate->shift = shift; 2697 2698 return clk_register(NULL, &gate->hw); 2699 } 2700 2701 static void tegra_pmc_clock_register(struct tegra_pmc *pmc, 2702 struct device_node *np) 2703 { 2704 struct clk *clk; 2705 struct clk_onecell_data *clk_data; 2706 unsigned int num_clks; 2707 int i, err; 2708 2709 num_clks = pmc->soc->num_pmc_clks; 2710 if (pmc->soc->has_blink_output) 2711 num_clks += 1; 2712 2713 if (!num_clks) 2714 return; 2715 2716 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL); 2717 if (!clk_data) 2718 return; 2719 2720 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX, 2721 sizeof(*clk_data->clks), GFP_KERNEL); 2722 if (!clk_data->clks) 2723 return; 2724 2725 clk_data->clk_num = TEGRA_PMC_CLK_MAX; 2726 2727 for (i = 0; i < TEGRA_PMC_CLK_MAX; i++) 2728 clk_data->clks[i] = ERR_PTR(-ENOENT); 2729 2730 for (i = 0; i < pmc->soc->num_pmc_clks; i++) { 2731 const struct pmc_clk_init_data *data; 2732 2733 data = pmc->soc->pmc_clks_data + i; 2734 2735 clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL); 2736 if (IS_ERR(clk)) { 2737 dev_warn(pmc->dev, "unable to register clock %s: %d\n", 2738 data->name, PTR_ERR_OR_ZERO(clk)); 2739 return; 2740 } 2741 2742 err = clk_register_clkdev(clk, data->name, NULL); 2743 if (err) { 2744 dev_warn(pmc->dev, 2745 "unable to register %s clock lookup: %d\n", 2746 data->name, err); 2747 return; 2748 } 2749 2750 clk_data->clks[data->clk_id] = clk; 2751 } 2752 2753 if (pmc->soc->has_blink_output) { 2754 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER); 2755 clk = tegra_pmc_clk_gate_register(pmc, 2756 "pmc_blink_override", 2757 "clk_32k", 2758 PMC_DPD_PADS_ORIDE, 2759 PMC_DPD_PADS_ORIDE_BLINK); 2760 if (IS_ERR(clk)) { 2761 dev_warn(pmc->dev, 2762 "unable to register pmc_blink_override: %d\n", 2763 PTR_ERR_OR_ZERO(clk)); 2764 return; 2765 } 2766 2767 clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink", 2768 "pmc_blink_override", 2769 PMC_CNTRL, 2770 PMC_CNTRL_BLINK_EN); 2771 if (IS_ERR(clk)) { 2772 dev_warn(pmc->dev, 2773 "unable to register pmc_blink: %d\n", 2774 PTR_ERR_OR_ZERO(clk)); 2775 return; 2776 } 2777 2778 err = clk_register_clkdev(clk, "pmc_blink", NULL); 2779 if (err) { 2780 dev_warn(pmc->dev, 2781 "unable to register pmc_blink lookup: %d\n", 2782 err); 2783 return; 2784 } 2785 2786 clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk; 2787 } 2788 2789 err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data); 2790 if (err) 2791 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n", 2792 err); 2793 } 2794 2795 static const struct regmap_range pmc_usb_sleepwalk_ranges[] = { 2796 regmap_reg_range(PMC_USB_DEBOUNCE_DEL, PMC_USB_AO), 2797 regmap_reg_range(PMC_UTMIP_UHSIC_TRIGGERS, PMC_UTMIP_UHSIC_SAVED_STATE), 2798 regmap_reg_range(PMC_UTMIP_TERM_PAD_CFG, PMC_UTMIP_UHSIC_FAKE), 2799 regmap_reg_range(PMC_UTMIP_UHSIC_LINE_WAKEUP, PMC_UTMIP_UHSIC_LINE_WAKEUP), 2800 regmap_reg_range(PMC_UTMIP_BIAS_MASTER_CNTRL, PMC_UTMIP_MASTER_CONFIG), 2801 regmap_reg_range(PMC_UTMIP_UHSIC2_TRIGGERS, PMC_UTMIP_MASTER2_CONFIG), 2802 regmap_reg_range(PMC_UTMIP_PAD_CFG0, PMC_UTMIP_UHSIC_SLEEP_CFG1), 2803 regmap_reg_range(PMC_UTMIP_SLEEPWALK_P3, PMC_UTMIP_SLEEPWALK_P3), 2804 }; 2805 2806 static const struct regmap_access_table pmc_usb_sleepwalk_table = { 2807 .yes_ranges = pmc_usb_sleepwalk_ranges, 2808 .n_yes_ranges = ARRAY_SIZE(pmc_usb_sleepwalk_ranges), 2809 }; 2810 2811 static int tegra_pmc_regmap_readl(void *context, unsigned int offset, unsigned int *value) 2812 { 2813 struct tegra_pmc *pmc = context; 2814 2815 *value = tegra_pmc_readl(pmc, offset); 2816 return 0; 2817 } 2818 2819 static int tegra_pmc_regmap_writel(void *context, unsigned int offset, unsigned int value) 2820 { 2821 struct tegra_pmc *pmc = context; 2822 2823 tegra_pmc_writel(pmc, value, offset); 2824 return 0; 2825 } 2826 2827 static const struct regmap_config usb_sleepwalk_regmap_config = { 2828 .name = "usb_sleepwalk", 2829 .reg_bits = 32, 2830 .val_bits = 32, 2831 .reg_stride = 4, 2832 .fast_io = true, 2833 .rd_table = &pmc_usb_sleepwalk_table, 2834 .wr_table = &pmc_usb_sleepwalk_table, 2835 .reg_read = tegra_pmc_regmap_readl, 2836 .reg_write = tegra_pmc_regmap_writel, 2837 }; 2838 2839 static int tegra_pmc_regmap_init(struct tegra_pmc *pmc) 2840 { 2841 struct regmap *regmap; 2842 int err; 2843 2844 if (pmc->soc->has_usb_sleepwalk) { 2845 regmap = devm_regmap_init(pmc->dev, NULL, pmc, &usb_sleepwalk_regmap_config); 2846 if (IS_ERR(regmap)) { 2847 err = PTR_ERR(regmap); 2848 dev_err(pmc->dev, "failed to allocate register map (%d)\n", err); 2849 return err; 2850 } 2851 } 2852 2853 return 0; 2854 } 2855 2856 static void tegra_pmc_reset_suspend_mode(void *data) 2857 { 2858 pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY; 2859 } 2860 2861 static int tegra_pmc_probe(struct platform_device *pdev) 2862 { 2863 void __iomem *base; 2864 struct resource *res; 2865 int err; 2866 2867 /* 2868 * Early initialisation should have configured an initial 2869 * register mapping and setup the soc data pointer. If these 2870 * are not valid then something went badly wrong! 2871 */ 2872 if (WARN_ON(!pmc->base || !pmc->soc)) 2873 return -ENODEV; 2874 2875 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); 2876 if (err < 0) 2877 return err; 2878 2879 err = devm_add_action_or_reset(&pdev->dev, tegra_pmc_reset_suspend_mode, 2880 NULL); 2881 if (err) 2882 return err; 2883 2884 /* take over the memory region from the early initialization */ 2885 base = devm_platform_ioremap_resource(pdev, 0); 2886 if (IS_ERR(base)) 2887 return PTR_ERR(base); 2888 2889 if (pmc->soc->has_single_mmio_aperture) { 2890 pmc->wake = base; 2891 pmc->aotag = base; 2892 pmc->scratch = base; 2893 } else { 2894 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 2895 "wake"); 2896 pmc->wake = devm_ioremap_resource(&pdev->dev, res); 2897 if (IS_ERR(pmc->wake)) 2898 return PTR_ERR(pmc->wake); 2899 2900 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 2901 "aotag"); 2902 pmc->aotag = devm_ioremap_resource(&pdev->dev, res); 2903 if (IS_ERR(pmc->aotag)) 2904 return PTR_ERR(pmc->aotag); 2905 2906 /* "scratch" is an optional aperture */ 2907 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 2908 "scratch"); 2909 if (res) { 2910 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); 2911 if (IS_ERR(pmc->scratch)) 2912 return PTR_ERR(pmc->scratch); 2913 } else { 2914 pmc->scratch = NULL; 2915 } 2916 } 2917 2918 pmc->clk = devm_clk_get_optional(&pdev->dev, "pclk"); 2919 if (IS_ERR(pmc->clk)) 2920 return dev_err_probe(&pdev->dev, PTR_ERR(pmc->clk), 2921 "failed to get pclk\n"); 2922 2923 /* 2924 * PMC should be last resort for restarting since it soft-resets 2925 * CPU without resetting everything else. 2926 */ 2927 if (pmc->scratch) { 2928 err = devm_register_reboot_notifier(&pdev->dev, 2929 &tegra_pmc_reboot_notifier); 2930 if (err) { 2931 dev_err(&pdev->dev, 2932 "unable to register reboot notifier, %d\n", 2933 err); 2934 return err; 2935 } 2936 } 2937 2938 err = devm_register_sys_off_handler(&pdev->dev, 2939 SYS_OFF_MODE_RESTART, 2940 SYS_OFF_PRIO_LOW, 2941 tegra_pmc_restart_handler, NULL); 2942 if (err) { 2943 dev_err(&pdev->dev, "failed to register sys-off handler: %d\n", 2944 err); 2945 return err; 2946 } 2947 2948 /* 2949 * PMC should be primary power-off method if it soft-resets CPU, 2950 * asking bootloader to shutdown hardware. 2951 */ 2952 err = devm_register_sys_off_handler(&pdev->dev, 2953 SYS_OFF_MODE_POWER_OFF, 2954 SYS_OFF_PRIO_FIRMWARE, 2955 tegra_pmc_power_off_handler, NULL); 2956 if (err) { 2957 dev_err(&pdev->dev, "failed to register sys-off handler: %d\n", 2958 err); 2959 return err; 2960 } 2961 2962 /* 2963 * PCLK clock rate can't be retrieved using CLK API because it 2964 * causes lockup if CPU enters LP2 idle state from some other 2965 * CLK notifier, hence we're caching the rate's value locally. 2966 */ 2967 if (pmc->clk) { 2968 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb; 2969 err = devm_clk_notifier_register(&pdev->dev, pmc->clk, 2970 &pmc->clk_nb); 2971 if (err) { 2972 dev_err(&pdev->dev, 2973 "failed to register clk notifier\n"); 2974 return err; 2975 } 2976 2977 pmc->rate = clk_get_rate(pmc->clk); 2978 } 2979 2980 pmc->dev = &pdev->dev; 2981 2982 err = tegra_pmc_init(pmc); 2983 if (err < 0) { 2984 dev_err(&pdev->dev, "failed to initialize PMC: %d\n", err); 2985 return err; 2986 } 2987 2988 tegra_pmc_init_tsense_reset(pmc); 2989 2990 tegra_pmc_reset_sysfs_init(pmc); 2991 2992 err = tegra_pmc_pinctrl_init(pmc); 2993 if (err) 2994 goto cleanup_sysfs; 2995 2996 err = tegra_pmc_regmap_init(pmc); 2997 if (err < 0) 2998 goto cleanup_sysfs; 2999 3000 err = tegra_powergate_init(pmc, pdev->dev.of_node); 3001 if (err < 0) 3002 goto cleanup_powergates; 3003 3004 err = tegra_pmc_irq_init(pmc); 3005 if (err < 0) 3006 goto cleanup_powergates; 3007 3008 mutex_lock(&pmc->powergates_lock); 3009 iounmap(pmc->base); 3010 pmc->base = base; 3011 mutex_unlock(&pmc->powergates_lock); 3012 3013 tegra_pmc_clock_register(pmc, pdev->dev.of_node); 3014 platform_set_drvdata(pdev, pmc); 3015 tegra_pm_init_suspend(); 3016 3017 /* Some wakes require specific filter configuration */ 3018 if (pmc->soc->set_wake_filters) 3019 pmc->soc->set_wake_filters(pmc); 3020 3021 debugfs_create_file("powergate", 0444, NULL, NULL, &powergate_fops); 3022 3023 return 0; 3024 3025 cleanup_powergates: 3026 tegra_powergate_remove_all(pdev->dev.of_node); 3027 cleanup_sysfs: 3028 device_remove_file(&pdev->dev, &dev_attr_reset_reason); 3029 device_remove_file(&pdev->dev, &dev_attr_reset_level); 3030 3031 return err; 3032 } 3033 3034 /* 3035 * Ensures that sufficient time is passed for a register write to 3036 * serialize into the 32KHz domain. 3037 */ 3038 static void wke_32kwritel(struct tegra_pmc *pmc, u32 value, unsigned int offset) 3039 { 3040 writel(value, pmc->wake + offset); 3041 udelay(130); 3042 } 3043 3044 static void wke_write_wake_level(struct tegra_pmc *pmc, int wake, int level) 3045 { 3046 unsigned int offset = WAKE_AOWAKE_CNTRL(wake); 3047 u32 value; 3048 3049 value = readl(pmc->wake + offset); 3050 if (level) 3051 value |= WAKE_AOWAKE_CNTRL_LEVEL; 3052 else 3053 value &= ~WAKE_AOWAKE_CNTRL_LEVEL; 3054 3055 writel(value, pmc->wake + offset); 3056 } 3057 3058 static void wke_write_wake_levels(struct tegra_pmc *pmc) 3059 { 3060 unsigned int i; 3061 3062 for (i = 0; i < pmc->soc->max_wake_events; i++) 3063 wke_write_wake_level(pmc, i, test_bit(i, pmc->wake_cntrl_level_map)); 3064 } 3065 3066 static void wke_clear_sw_wake_status(struct tegra_pmc *pmc) 3067 { 3068 wke_32kwritel(pmc, 1, WAKE_AOWAKE_SW_STATUS_W_0); 3069 } 3070 3071 static void wke_read_sw_wake_status(struct tegra_pmc *pmc) 3072 { 3073 unsigned long status; 3074 unsigned int wake, i; 3075 3076 for (i = 0; i < pmc->soc->max_wake_events; i++) 3077 wke_write_wake_level(pmc, i, 0); 3078 3079 wke_clear_sw_wake_status(pmc); 3080 3081 wke_32kwritel(pmc, 1, WAKE_LATCH_SW); 3082 3083 /* 3084 * WAKE_AOWAKE_SW_STATUS is edge triggered, so in order to 3085 * obtain the current status of the input wake signals, change 3086 * the polarity of the wake level from 0->1 while latching to force 3087 * a positive edge if the sampled signal is '1'. 3088 */ 3089 for (i = 0; i < pmc->soc->max_wake_events; i++) 3090 wke_write_wake_level(pmc, i, 1); 3091 3092 /* 3093 * Wait for the update to be synced into the 32kHz domain, 3094 * and let enough time lapse, so that the wake signals have time to 3095 * be sampled. 3096 */ 3097 udelay(300); 3098 3099 wke_32kwritel(pmc, 0, WAKE_LATCH_SW); 3100 3101 bitmap_zero(pmc->wake_sw_status_map, pmc->soc->max_wake_events); 3102 3103 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { 3104 status = readl(pmc->wake + WAKE_AOWAKE_SW_STATUS(i)); 3105 3106 for_each_set_bit(wake, &status, 32) 3107 set_bit(wake + (i * 32), pmc->wake_sw_status_map); 3108 } 3109 } 3110 3111 static void wke_clear_wake_status(struct tegra_pmc *pmc) 3112 { 3113 unsigned long status; 3114 unsigned int i, wake; 3115 u32 mask; 3116 3117 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { 3118 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i)); 3119 status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask; 3120 3121 for_each_set_bit(wake, &status, 32) 3122 wke_32kwritel(pmc, 0x1, WAKE_AOWAKE_STATUS_W((i * 32) + wake)); 3123 } 3124 } 3125 3126 /* translate sc7 wake sources back into IRQs to catch edge triggered wakeups */ 3127 static void tegra186_pmc_process_wake_events(struct tegra_pmc *pmc, unsigned int index, 3128 unsigned long status) 3129 { 3130 unsigned int wake; 3131 3132 dev_dbg(pmc->dev, "Wake[%d:%d] status=%#lx\n", (index * 32) + 31, index * 32, status); 3133 3134 for_each_set_bit(wake, &status, 32) { 3135 irq_hw_number_t hwirq = wake + 32 * index; 3136 struct irq_desc *desc; 3137 unsigned int irq; 3138 3139 irq = irq_find_mapping(pmc->domain, hwirq); 3140 3141 desc = irq_to_desc(irq); 3142 if (!desc || !desc->action || !desc->action->name) { 3143 dev_dbg(pmc->dev, "Resume caused by WAKE%ld, IRQ %d\n", hwirq, irq); 3144 continue; 3145 } 3146 3147 dev_dbg(pmc->dev, "Resume caused by WAKE%ld, %s\n", hwirq, desc->action->name); 3148 generic_handle_irq(irq); 3149 } 3150 } 3151 3152 static void tegra186_pmc_wake_syscore_resume(void) 3153 { 3154 u32 status, mask; 3155 unsigned int i; 3156 3157 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { 3158 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i)); 3159 status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask; 3160 3161 tegra186_pmc_process_wake_events(pmc, i, status); 3162 } 3163 } 3164 3165 static int tegra186_pmc_wake_syscore_suspend(void) 3166 { 3167 wke_read_sw_wake_status(pmc); 3168 3169 /* flip the wakeup trigger for dual-edge triggered pads 3170 * which are currently asserting as wakeups 3171 */ 3172 bitmap_andnot(pmc->wake_cntrl_level_map, pmc->wake_type_dual_edge_map, 3173 pmc->wake_sw_status_map, pmc->soc->max_wake_events); 3174 bitmap_or(pmc->wake_cntrl_level_map, pmc->wake_cntrl_level_map, 3175 pmc->wake_type_level_map, pmc->soc->max_wake_events); 3176 3177 /* Clear PMC Wake Status registers while going to suspend */ 3178 wke_clear_wake_status(pmc); 3179 wke_write_wake_levels(pmc); 3180 3181 return 0; 3182 } 3183 3184 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 3185 static int tegra_pmc_suspend(struct device *dev) 3186 { 3187 struct tegra_pmc *pmc = dev_get_drvdata(dev); 3188 3189 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41); 3190 3191 return 0; 3192 } 3193 3194 static int tegra_pmc_resume(struct device *dev) 3195 { 3196 struct tegra_pmc *pmc = dev_get_drvdata(dev); 3197 3198 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41); 3199 3200 return 0; 3201 } 3202 3203 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume); 3204 3205 #endif 3206 3207 static const char * const tegra20_powergates[] = { 3208 [TEGRA_POWERGATE_CPU] = "cpu", 3209 [TEGRA_POWERGATE_3D] = "td", 3210 [TEGRA_POWERGATE_VENC] = "venc", 3211 [TEGRA_POWERGATE_VDEC] = "vdec", 3212 [TEGRA_POWERGATE_PCIE] = "pcie", 3213 [TEGRA_POWERGATE_L2] = "l2", 3214 [TEGRA_POWERGATE_MPE] = "mpe", 3215 }; 3216 3217 static const struct tegra_pmc_regs tegra20_pmc_regs = { 3218 .scratch0 = 0x50, 3219 .rst_status = 0x1b4, 3220 .rst_source_shift = 0x0, 3221 .rst_source_mask = 0x7, 3222 .rst_level_shift = 0x0, 3223 .rst_level_mask = 0x0, 3224 }; 3225 3226 static void tegra20_pmc_init(struct tegra_pmc *pmc) 3227 { 3228 u32 value, osc, pmu, off; 3229 3230 /* Always enable CPU power request */ 3231 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3232 value |= PMC_CNTRL_CPU_PWRREQ_OE; 3233 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3234 3235 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3236 3237 if (pmc->sysclkreq_high) 3238 value &= ~PMC_CNTRL_SYSCLK_POLARITY; 3239 else 3240 value |= PMC_CNTRL_SYSCLK_POLARITY; 3241 3242 if (pmc->corereq_high) 3243 value &= ~PMC_CNTRL_PWRREQ_POLARITY; 3244 else 3245 value |= PMC_CNTRL_PWRREQ_POLARITY; 3246 3247 /* configure the output polarity while the request is tristated */ 3248 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3249 3250 /* now enable the request */ 3251 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3252 value |= PMC_CNTRL_SYSCLK_OE; 3253 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3254 3255 /* program core timings which are applicable only for suspend state */ 3256 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) { 3257 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000); 3258 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000); 3259 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000); 3260 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff), 3261 PMC_COREPWRGOOD_TIMER); 3262 tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER); 3263 } 3264 } 3265 3266 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 3267 struct device_node *np, 3268 bool invert) 3269 { 3270 u32 value; 3271 3272 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3273 3274 if (invert) 3275 value |= PMC_CNTRL_INTR_POLARITY; 3276 else 3277 value &= ~PMC_CNTRL_INTR_POLARITY; 3278 3279 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3280 } 3281 3282 static const struct tegra_pmc_soc tegra20_pmc_soc = { 3283 .supports_core_domain = true, 3284 .num_powergates = ARRAY_SIZE(tegra20_powergates), 3285 .powergates = tegra20_powergates, 3286 .num_cpu_powergates = 0, 3287 .cpu_powergates = NULL, 3288 .has_tsense_reset = false, 3289 .has_gpu_clamps = false, 3290 .needs_mbist_war = false, 3291 .has_impl_33v_pwr = false, 3292 .maybe_tz_only = false, 3293 .num_io_pads = 0, 3294 .io_pads = NULL, 3295 .num_pin_descs = 0, 3296 .pin_descs = NULL, 3297 .regs = &tegra20_pmc_regs, 3298 .init = tegra20_pmc_init, 3299 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3300 .powergate_set = tegra20_powergate_set, 3301 .reset_sources = NULL, 3302 .num_reset_sources = 0, 3303 .reset_levels = NULL, 3304 .num_reset_levels = 0, 3305 .pmc_clks_data = NULL, 3306 .num_pmc_clks = 0, 3307 .has_blink_output = true, 3308 .has_usb_sleepwalk = true, 3309 .has_single_mmio_aperture = true, 3310 }; 3311 3312 static const char * const tegra30_powergates[] = { 3313 [TEGRA_POWERGATE_CPU] = "cpu0", 3314 [TEGRA_POWERGATE_3D] = "td", 3315 [TEGRA_POWERGATE_VENC] = "venc", 3316 [TEGRA_POWERGATE_VDEC] = "vdec", 3317 [TEGRA_POWERGATE_PCIE] = "pcie", 3318 [TEGRA_POWERGATE_L2] = "l2", 3319 [TEGRA_POWERGATE_MPE] = "mpe", 3320 [TEGRA_POWERGATE_HEG] = "heg", 3321 [TEGRA_POWERGATE_SATA] = "sata", 3322 [TEGRA_POWERGATE_CPU1] = "cpu1", 3323 [TEGRA_POWERGATE_CPU2] = "cpu2", 3324 [TEGRA_POWERGATE_CPU3] = "cpu3", 3325 [TEGRA_POWERGATE_CELP] = "celp", 3326 [TEGRA_POWERGATE_3D1] = "td2", 3327 }; 3328 3329 static const u8 tegra30_cpu_powergates[] = { 3330 TEGRA_POWERGATE_CPU, 3331 TEGRA_POWERGATE_CPU1, 3332 TEGRA_POWERGATE_CPU2, 3333 TEGRA_POWERGATE_CPU3, 3334 }; 3335 3336 static const char * const tegra30_reset_sources[] = { 3337 "POWER_ON_RESET", 3338 "WATCHDOG", 3339 "SENSOR", 3340 "SW_MAIN", 3341 "LP0" 3342 }; 3343 3344 static const struct tegra_pmc_soc tegra30_pmc_soc = { 3345 .supports_core_domain = true, 3346 .num_powergates = ARRAY_SIZE(tegra30_powergates), 3347 .powergates = tegra30_powergates, 3348 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), 3349 .cpu_powergates = tegra30_cpu_powergates, 3350 .has_tsense_reset = true, 3351 .has_gpu_clamps = false, 3352 .needs_mbist_war = false, 3353 .has_impl_33v_pwr = false, 3354 .maybe_tz_only = false, 3355 .num_io_pads = 0, 3356 .io_pads = NULL, 3357 .num_pin_descs = 0, 3358 .pin_descs = NULL, 3359 .regs = &tegra20_pmc_regs, 3360 .init = tegra20_pmc_init, 3361 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3362 .powergate_set = tegra20_powergate_set, 3363 .reset_sources = tegra30_reset_sources, 3364 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 3365 .reset_levels = NULL, 3366 .num_reset_levels = 0, 3367 .pmc_clks_data = tegra_pmc_clks_data, 3368 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3369 .has_blink_output = true, 3370 .has_usb_sleepwalk = true, 3371 .has_single_mmio_aperture = true, 3372 }; 3373 3374 static const char * const tegra114_powergates[] = { 3375 [TEGRA_POWERGATE_CPU] = "crail", 3376 [TEGRA_POWERGATE_3D] = "td", 3377 [TEGRA_POWERGATE_VENC] = "venc", 3378 [TEGRA_POWERGATE_VDEC] = "vdec", 3379 [TEGRA_POWERGATE_MPE] = "mpe", 3380 [TEGRA_POWERGATE_HEG] = "heg", 3381 [TEGRA_POWERGATE_CPU1] = "cpu1", 3382 [TEGRA_POWERGATE_CPU2] = "cpu2", 3383 [TEGRA_POWERGATE_CPU3] = "cpu3", 3384 [TEGRA_POWERGATE_CELP] = "celp", 3385 [TEGRA_POWERGATE_CPU0] = "cpu0", 3386 [TEGRA_POWERGATE_C0NC] = "c0nc", 3387 [TEGRA_POWERGATE_C1NC] = "c1nc", 3388 [TEGRA_POWERGATE_DIS] = "dis", 3389 [TEGRA_POWERGATE_DISB] = "disb", 3390 [TEGRA_POWERGATE_XUSBA] = "xusba", 3391 [TEGRA_POWERGATE_XUSBB] = "xusbb", 3392 [TEGRA_POWERGATE_XUSBC] = "xusbc", 3393 }; 3394 3395 static const u8 tegra114_cpu_powergates[] = { 3396 TEGRA_POWERGATE_CPU0, 3397 TEGRA_POWERGATE_CPU1, 3398 TEGRA_POWERGATE_CPU2, 3399 TEGRA_POWERGATE_CPU3, 3400 }; 3401 3402 static const struct tegra_pmc_soc tegra114_pmc_soc = { 3403 .supports_core_domain = false, 3404 .num_powergates = ARRAY_SIZE(tegra114_powergates), 3405 .powergates = tegra114_powergates, 3406 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), 3407 .cpu_powergates = tegra114_cpu_powergates, 3408 .has_tsense_reset = true, 3409 .has_gpu_clamps = false, 3410 .needs_mbist_war = false, 3411 .has_impl_33v_pwr = false, 3412 .maybe_tz_only = false, 3413 .num_io_pads = 0, 3414 .io_pads = NULL, 3415 .num_pin_descs = 0, 3416 .pin_descs = NULL, 3417 .regs = &tegra20_pmc_regs, 3418 .init = tegra20_pmc_init, 3419 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3420 .powergate_set = tegra114_powergate_set, 3421 .reset_sources = tegra30_reset_sources, 3422 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 3423 .reset_levels = NULL, 3424 .num_reset_levels = 0, 3425 .pmc_clks_data = tegra_pmc_clks_data, 3426 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3427 .has_blink_output = true, 3428 .has_usb_sleepwalk = true, 3429 .has_single_mmio_aperture = true, 3430 }; 3431 3432 static const char * const tegra124_powergates[] = { 3433 [TEGRA_POWERGATE_CPU] = "crail", 3434 [TEGRA_POWERGATE_3D] = "3d", 3435 [TEGRA_POWERGATE_VENC] = "venc", 3436 [TEGRA_POWERGATE_PCIE] = "pcie", 3437 [TEGRA_POWERGATE_VDEC] = "vdec", 3438 [TEGRA_POWERGATE_MPE] = "mpe", 3439 [TEGRA_POWERGATE_HEG] = "heg", 3440 [TEGRA_POWERGATE_SATA] = "sata", 3441 [TEGRA_POWERGATE_CPU1] = "cpu1", 3442 [TEGRA_POWERGATE_CPU2] = "cpu2", 3443 [TEGRA_POWERGATE_CPU3] = "cpu3", 3444 [TEGRA_POWERGATE_CELP] = "celp", 3445 [TEGRA_POWERGATE_CPU0] = "cpu0", 3446 [TEGRA_POWERGATE_C0NC] = "c0nc", 3447 [TEGRA_POWERGATE_C1NC] = "c1nc", 3448 [TEGRA_POWERGATE_SOR] = "sor", 3449 [TEGRA_POWERGATE_DIS] = "dis", 3450 [TEGRA_POWERGATE_DISB] = "disb", 3451 [TEGRA_POWERGATE_XUSBA] = "xusba", 3452 [TEGRA_POWERGATE_XUSBB] = "xusbb", 3453 [TEGRA_POWERGATE_XUSBC] = "xusbc", 3454 [TEGRA_POWERGATE_VIC] = "vic", 3455 [TEGRA_POWERGATE_IRAM] = "iram", 3456 }; 3457 3458 static const u8 tegra124_cpu_powergates[] = { 3459 TEGRA_POWERGATE_CPU0, 3460 TEGRA_POWERGATE_CPU1, 3461 TEGRA_POWERGATE_CPU2, 3462 TEGRA_POWERGATE_CPU3, 3463 }; 3464 3465 #define TEGRA_IO_PAD(_id, _dpd, _request, _status, _voltage, _name) \ 3466 ((struct tegra_io_pad_soc) { \ 3467 .id = (_id), \ 3468 .dpd = (_dpd), \ 3469 .request = (_request), \ 3470 .status = (_status), \ 3471 .voltage = (_voltage), \ 3472 .name = (_name), \ 3473 }) 3474 3475 #define TEGRA_IO_PIN_DESC(_id, _name) \ 3476 ((struct pinctrl_pin_desc) { \ 3477 .number = (_id), \ 3478 .name = (_name), \ 3479 }) 3480 3481 static const struct tegra_io_pad_soc tegra124_io_pads[] = { 3482 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, UINT_MAX, "audio"), 3483 TEGRA_IO_PAD(TEGRA_IO_PAD_BB, 15, 0x1b8, 0x1bc, UINT_MAX, "bb"), 3484 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, UINT_MAX, "cam"), 3485 TEGRA_IO_PAD(TEGRA_IO_PAD_COMP, 22, 0x1b8, 0x1bc, UINT_MAX, "comp"), 3486 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, UINT_MAX, "csia"), 3487 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, UINT_MAX, "csib"), 3488 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, UINT_MAX, "csie"), 3489 TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, UINT_MAX, "dsi"), 3490 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, UINT_MAX, "dsib"), 3491 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, UINT_MAX, "dsic"), 3492 TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, UINT_MAX, "dsid"), 3493 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, UINT_MAX, "hdmi"), 3494 TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, UINT_MAX, "hsic"), 3495 TEGRA_IO_PAD(TEGRA_IO_PAD_HV, 6, 0x1c0, 0x1c4, UINT_MAX, "hv"), 3496 TEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, UINT_MAX, "lvds"), 3497 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, UINT_MAX, "mipi-bias"), 3498 TEGRA_IO_PAD(TEGRA_IO_PAD_NAND, 13, 0x1b8, 0x1bc, UINT_MAX, "nand"), 3499 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, "pex-bias"), 3500 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, "pex-clk1"), 3501 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"), 3502 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x1c0, 0x1c4, UINT_MAX, "pex-cntrl"), 3503 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, UINT_MAX, "sdmmc1"), 3504 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, UINT_MAX, "sdmmc3"), 3505 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 3, 0x1c0, 0x1c4, UINT_MAX, "sdmmc4"), 3506 TEGRA_IO_PAD(TEGRA_IO_PAD_SYS_DDC, 26, 0x1c0, 0x1c4, UINT_MAX, "sys_ddc"), 3507 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, UINT_MAX, "uart"), 3508 TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, UINT_MAX, "usb0"), 3509 TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, UINT_MAX, "usb1"), 3510 TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, UINT_MAX, "usb2"), 3511 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, UINT_MAX, "usb_bias"), 3512 }; 3513 3514 static const struct pinctrl_pin_desc tegra124_pin_descs[] = { 3515 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), 3516 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_BB, "bb"), 3517 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), 3518 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_COMP, "comp"), 3519 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 3520 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 3521 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 3522 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"), 3523 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"), 3524 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"), 3525 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"), 3526 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI, "hdmi"), 3527 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"), 3528 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HV, "hv"), 3529 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_LVDS, "lvds"), 3530 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), 3531 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_NAND, "nand"), 3532 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"), 3533 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), 3534 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), 3535 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), 3536 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1, "sdmmc1"), 3537 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3, "sdmmc3"), 3538 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"), 3539 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SYS_DDC, "sys_ddc"), 3540 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), 3541 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"), 3542 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"), 3543 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"), 3544 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb_bias"), 3545 }; 3546 3547 static const struct tegra_pmc_soc tegra124_pmc_soc = { 3548 .supports_core_domain = false, 3549 .num_powergates = ARRAY_SIZE(tegra124_powergates), 3550 .powergates = tegra124_powergates, 3551 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), 3552 .cpu_powergates = tegra124_cpu_powergates, 3553 .has_tsense_reset = true, 3554 .has_gpu_clamps = true, 3555 .needs_mbist_war = false, 3556 .has_impl_33v_pwr = false, 3557 .maybe_tz_only = false, 3558 .num_io_pads = ARRAY_SIZE(tegra124_io_pads), 3559 .io_pads = tegra124_io_pads, 3560 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs), 3561 .pin_descs = tegra124_pin_descs, 3562 .regs = &tegra20_pmc_regs, 3563 .init = tegra20_pmc_init, 3564 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3565 .powergate_set = tegra114_powergate_set, 3566 .reset_sources = tegra30_reset_sources, 3567 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 3568 .reset_levels = NULL, 3569 .num_reset_levels = 0, 3570 .pmc_clks_data = tegra_pmc_clks_data, 3571 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3572 .has_blink_output = true, 3573 .has_usb_sleepwalk = true, 3574 .has_single_mmio_aperture = true, 3575 }; 3576 3577 static const char * const tegra210_powergates[] = { 3578 [TEGRA_POWERGATE_CPU] = "crail", 3579 [TEGRA_POWERGATE_3D] = "3d", 3580 [TEGRA_POWERGATE_VENC] = "venc", 3581 [TEGRA_POWERGATE_PCIE] = "pcie", 3582 [TEGRA_POWERGATE_MPE] = "mpe", 3583 [TEGRA_POWERGATE_SATA] = "sata", 3584 [TEGRA_POWERGATE_CPU1] = "cpu1", 3585 [TEGRA_POWERGATE_CPU2] = "cpu2", 3586 [TEGRA_POWERGATE_CPU3] = "cpu3", 3587 [TEGRA_POWERGATE_CPU0] = "cpu0", 3588 [TEGRA_POWERGATE_C0NC] = "c0nc", 3589 [TEGRA_POWERGATE_SOR] = "sor", 3590 [TEGRA_POWERGATE_DIS] = "dis", 3591 [TEGRA_POWERGATE_DISB] = "disb", 3592 [TEGRA_POWERGATE_XUSBA] = "xusba", 3593 [TEGRA_POWERGATE_XUSBB] = "xusbb", 3594 [TEGRA_POWERGATE_XUSBC] = "xusbc", 3595 [TEGRA_POWERGATE_VIC] = "vic", 3596 [TEGRA_POWERGATE_IRAM] = "iram", 3597 [TEGRA_POWERGATE_NVDEC] = "nvdec", 3598 [TEGRA_POWERGATE_NVJPG] = "nvjpg", 3599 [TEGRA_POWERGATE_AUD] = "aud", 3600 [TEGRA_POWERGATE_DFD] = "dfd", 3601 [TEGRA_POWERGATE_VE2] = "ve2", 3602 }; 3603 3604 static const u8 tegra210_cpu_powergates[] = { 3605 TEGRA_POWERGATE_CPU0, 3606 TEGRA_POWERGATE_CPU1, 3607 TEGRA_POWERGATE_CPU2, 3608 TEGRA_POWERGATE_CPU3, 3609 }; 3610 3611 static const struct tegra_io_pad_soc tegra210_io_pads[] = { 3612 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, 5, "audio"), 3613 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x1c0, 0x1c4, 18, "audio-hv"), 3614 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, 10, "cam"), 3615 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, UINT_MAX, "csia"), 3616 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, UINT_MAX, "csib"), 3617 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 10, 0x1c0, 0x1c4, UINT_MAX, "csic"), 3618 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 11, 0x1c0, 0x1c4, UINT_MAX, "csid"), 3619 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, UINT_MAX, "csie"), 3620 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 13, 0x1c0, 0x1c4, UINT_MAX, "csif"), 3621 TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x1b8, 0x1bc, 19, "dbg"), 3622 TEGRA_IO_PAD(TEGRA_IO_PAD_DEBUG_NONAO, 26, 0x1b8, 0x1bc, UINT_MAX, "debug-nonao"), 3623 TEGRA_IO_PAD(TEGRA_IO_PAD_DMIC, 18, 0x1c0, 0x1c4, 20, "dmic"), 3624 TEGRA_IO_PAD(TEGRA_IO_PAD_DP, 19, 0x1c0, 0x1c4, UINT_MAX, "dp"), 3625 TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, UINT_MAX, "dsi"), 3626 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, UINT_MAX, "dsib"), 3627 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, UINT_MAX, "dsic"), 3628 TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, UINT_MAX, "dsid"), 3629 TEGRA_IO_PAD(TEGRA_IO_PAD_EMMC, 3, 0x1c0, 0x1c4, UINT_MAX, "emmc"), 3630 TEGRA_IO_PAD(TEGRA_IO_PAD_EMMC2, 5, 0x1c0, 0x1c4, UINT_MAX, "emmc2"), 3631 TEGRA_IO_PAD(TEGRA_IO_PAD_GPIO, 27, 0x1b8, 0x1bc, 21, "gpio"), 3632 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, UINT_MAX, "hdmi"), 3633 TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, UINT_MAX, "hsic"), 3634 TEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, UINT_MAX, "lvds"), 3635 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, UINT_MAX, "mipi-bias"), 3636 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, "pex-bias"), 3637 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, "pex-clk1"), 3638 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"), 3639 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, UINT_MAX, UINT_MAX, 11, "pex-cntrl"), 3640 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, 12, "sdmmc1"), 3641 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, 13, "sdmmc3"), 3642 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 14, 0x1c0, 0x1c4, 22, "spi"), 3643 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI_HV, 15, 0x1c0, 0x1c4, 23, "spi-hv"), 3644 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, 2, "uart"), 3645 TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, UINT_MAX, "usb0"), 3646 TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, UINT_MAX, "usb1"), 3647 TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, UINT_MAX, "usb2"), 3648 TEGRA_IO_PAD(TEGRA_IO_PAD_USB3, 18, 0x1b8, 0x1bc, UINT_MAX, "usb3"), 3649 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, UINT_MAX, "usb-bias"), 3650 }; 3651 3652 static const struct pinctrl_pin_desc tegra210_pin_descs[] = { 3653 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), 3654 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), 3655 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), 3656 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 3657 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 3658 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), 3659 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), 3660 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 3661 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), 3662 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"), 3663 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DEBUG_NONAO, "debug-nonao"), 3664 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DMIC, "dmic"), 3665 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DP, "dp"), 3666 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"), 3667 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"), 3668 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"), 3669 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"), 3670 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EMMC, "emmc"), 3671 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EMMC2, "emmc2"), 3672 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GPIO, "gpio"), 3673 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI, "hdmi"), 3674 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"), 3675 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_LVDS, "lvds"), 3676 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), 3677 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"), 3678 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), 3679 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), 3680 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), 3681 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1, "sdmmc1"), 3682 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3, "sdmmc3"), 3683 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"), 3684 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI_HV, "spi-hv"), 3685 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), 3686 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"), 3687 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"), 3688 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"), 3689 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB3, "usb3"), 3690 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"), 3691 }; 3692 3693 static const char * const tegra210_reset_sources[] = { 3694 "POWER_ON_RESET", 3695 "WATCHDOG", 3696 "SENSOR", 3697 "SW_MAIN", 3698 "LP0", 3699 "AOTAG" 3700 }; 3701 3702 static const struct tegra_wake_event tegra210_wake_events[] = { 3703 TEGRA_WAKE_IRQ("rtc", 16, 2), 3704 TEGRA_WAKE_IRQ("pmu", 51, 86), 3705 }; 3706 3707 static const struct tegra_pmc_soc tegra210_pmc_soc = { 3708 .supports_core_domain = false, 3709 .num_powergates = ARRAY_SIZE(tegra210_powergates), 3710 .powergates = tegra210_powergates, 3711 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates), 3712 .cpu_powergates = tegra210_cpu_powergates, 3713 .has_tsense_reset = true, 3714 .has_gpu_clamps = true, 3715 .needs_mbist_war = true, 3716 .has_impl_33v_pwr = false, 3717 .maybe_tz_only = true, 3718 .num_io_pads = ARRAY_SIZE(tegra210_io_pads), 3719 .io_pads = tegra210_io_pads, 3720 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs), 3721 .pin_descs = tegra210_pin_descs, 3722 .regs = &tegra20_pmc_regs, 3723 .init = tegra20_pmc_init, 3724 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3725 .powergate_set = tegra114_powergate_set, 3726 .irq_set_wake = tegra210_pmc_irq_set_wake, 3727 .irq_set_type = tegra210_pmc_irq_set_type, 3728 .reset_sources = tegra210_reset_sources, 3729 .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources), 3730 .reset_levels = NULL, 3731 .num_reset_levels = 0, 3732 .num_wake_events = ARRAY_SIZE(tegra210_wake_events), 3733 .wake_events = tegra210_wake_events, 3734 .pmc_clks_data = tegra_pmc_clks_data, 3735 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3736 .has_blink_output = true, 3737 .has_usb_sleepwalk = true, 3738 .has_single_mmio_aperture = true, 3739 }; 3740 3741 static const struct tegra_io_pad_soc tegra186_io_pads[] = { 3742 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, UINT_MAX, "csia"), 3743 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, UINT_MAX, "csib"), 3744 TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x74, 0x78, UINT_MAX, "dsi"), 3745 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, UINT_MAX, "mipi-bias"), 3746 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, UINT_MAX, "pex-clk-bias"), 3747 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, UINT_MAX, "pex-clk3"), 3748 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"), 3749 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, UINT_MAX, "pex-clk1"), 3750 TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x74, 0x78, UINT_MAX, "usb0"), 3751 TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x74, 0x78, UINT_MAX, "usb1"), 3752 TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x74, 0x78, UINT_MAX, "usb2"), 3753 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x74, 0x78, UINT_MAX, "usb-bias"), 3754 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x74, 0x78, UINT_MAX, "uart"), 3755 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x74, 0x78, UINT_MAX, "audio"), 3756 TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x74, 0x78, UINT_MAX, "hsic"), 3757 TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x74, 0x78, UINT_MAX, "dbg"), 3758 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, "hdmi-dp0"), 3759 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, UINT_MAX, "hdmi-dp1"), 3760 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, UINT_MAX, "pex-cntrl"), 3761 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC2_HV, 2, 0x7c, 0x80, 5, "sdmmc2-hv"), 3762 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 4, 0x7c, 0x80, UINT_MAX, "sdmmc4"), 3763 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 6, 0x7c, 0x80, UINT_MAX, "cam"), 3764 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 8, 0x7c, 0x80, UINT_MAX, "dsib"), 3765 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 9, 0x7c, 0x80, UINT_MAX, "dsic"), 3766 TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 10, 0x7c, 0x80, UINT_MAX, "dsid"), 3767 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 11, 0x7c, 0x80, UINT_MAX, "csic"), 3768 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 12, 0x7c, 0x80, UINT_MAX, "csid"), 3769 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 13, 0x7c, 0x80, UINT_MAX, "csie"), 3770 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 14, 0x7c, 0x80, UINT_MAX, "csif"), 3771 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 15, 0x7c, 0x80, UINT_MAX, "spi"), 3772 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 17, 0x7c, 0x80, UINT_MAX, "ufs"), 3773 TEGRA_IO_PAD(TEGRA_IO_PAD_DMIC_HV, 20, 0x7c, 0x80, 2, "dmic-hv"), 3774 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 21, 0x7c, 0x80, UINT_MAX, "edp"), 3775 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, 4, "sdmmc1-hv"), 3776 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, 6, "sdmmc3-hv"), 3777 TEGRA_IO_PAD(TEGRA_IO_PAD_CONN, 28, 0x7c, 0x80, UINT_MAX, "conn"), 3778 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, 1, "audio-hv"), 3779 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"), 3780 }; 3781 3782 static const struct pinctrl_pin_desc tegra186_pin_descs[] = { 3783 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 3784 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 3785 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"), 3786 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), 3787 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"), 3788 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"), 3789 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), 3790 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), 3791 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"), 3792 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"), 3793 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"), 3794 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"), 3795 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), 3796 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), 3797 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"), 3798 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"), 3799 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"), 3800 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"), 3801 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), 3802 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC2_HV, "sdmmc2-hv"), 3803 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"), 3804 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), 3805 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"), 3806 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"), 3807 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"), 3808 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), 3809 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), 3810 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 3811 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), 3812 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"), 3813 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"), 3814 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DMIC_HV, "dmic-hv"), 3815 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"), 3816 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"), 3817 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"), 3818 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CONN, "conn"), 3819 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), 3820 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"), 3821 }; 3822 3823 static const struct tegra_pmc_regs tegra186_pmc_regs = { 3824 .scratch0 = 0x2000, 3825 .rst_status = 0x70, 3826 .rst_source_shift = 0x2, 3827 .rst_source_mask = 0x3c, 3828 .rst_level_shift = 0x0, 3829 .rst_level_mask = 0x3, 3830 }; 3831 3832 static void tegra186_pmc_init(struct tegra_pmc *pmc) 3833 { 3834 pmc->syscore.suspend = tegra186_pmc_wake_syscore_suspend; 3835 pmc->syscore.resume = tegra186_pmc_wake_syscore_resume; 3836 3837 register_syscore_ops(&pmc->syscore); 3838 } 3839 3840 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 3841 struct device_node *np, 3842 bool invert) 3843 { 3844 struct resource regs; 3845 void __iomem *wake; 3846 u32 value; 3847 int index; 3848 3849 index = of_property_match_string(np, "reg-names", "wake"); 3850 if (index < 0) { 3851 dev_err(pmc->dev, "failed to find PMC wake registers\n"); 3852 return; 3853 } 3854 3855 of_address_to_resource(np, index, ®s); 3856 3857 wake = ioremap(regs.start, resource_size(®s)); 3858 if (!wake) { 3859 dev_err(pmc->dev, "failed to map PMC wake registers\n"); 3860 return; 3861 } 3862 3863 value = readl(wake + WAKE_AOWAKE_CTRL); 3864 3865 if (invert) 3866 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY; 3867 else 3868 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY; 3869 3870 writel(value, wake + WAKE_AOWAKE_CTRL); 3871 3872 iounmap(wake); 3873 } 3874 3875 static const char * const tegra186_reset_sources[] = { 3876 "SYS_RESET", 3877 "AOWDT", 3878 "MCCPLEXWDT", 3879 "BPMPWDT", 3880 "SCEWDT", 3881 "SPEWDT", 3882 "APEWDT", 3883 "BCCPLEXWDT", 3884 "SENSOR", 3885 "AOTAG", 3886 "VFSENSOR", 3887 "SWREST", 3888 "SC7", 3889 "HSM", 3890 "CORESIGHT" 3891 }; 3892 3893 static const char * const tegra186_reset_levels[] = { 3894 "L0", "L1", "L2", "WARM" 3895 }; 3896 3897 static const struct tegra_wake_event tegra186_wake_events[] = { 3898 TEGRA_WAKE_IRQ("pmu", 24, 209), 3899 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)), 3900 TEGRA_WAKE_IRQ("rtc", 73, 10), 3901 }; 3902 3903 static const struct tegra_pmc_soc tegra186_pmc_soc = { 3904 .supports_core_domain = false, 3905 .num_powergates = 0, 3906 .powergates = NULL, 3907 .num_cpu_powergates = 0, 3908 .cpu_powergates = NULL, 3909 .has_tsense_reset = false, 3910 .has_gpu_clamps = false, 3911 .needs_mbist_war = false, 3912 .has_impl_33v_pwr = true, 3913 .maybe_tz_only = false, 3914 .num_io_pads = ARRAY_SIZE(tegra186_io_pads), 3915 .io_pads = tegra186_io_pads, 3916 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs), 3917 .pin_descs = tegra186_pin_descs, 3918 .regs = &tegra186_pmc_regs, 3919 .init = tegra186_pmc_init, 3920 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 3921 .set_wake_filters = tegra186_pmc_set_wake_filters, 3922 .irq_set_wake = tegra186_pmc_irq_set_wake, 3923 .irq_set_type = tegra186_pmc_irq_set_type, 3924 .reset_sources = tegra186_reset_sources, 3925 .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources), 3926 .reset_levels = tegra186_reset_levels, 3927 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 3928 .num_wake_events = ARRAY_SIZE(tegra186_wake_events), 3929 .wake_events = tegra186_wake_events, 3930 .max_wake_events = 96, 3931 .max_wake_vectors = 3, 3932 .pmc_clks_data = NULL, 3933 .num_pmc_clks = 0, 3934 .has_blink_output = false, 3935 .has_usb_sleepwalk = false, 3936 .has_single_mmio_aperture = false, 3937 }; 3938 3939 static const struct tegra_io_pad_soc tegra194_io_pads[] = { 3940 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, UINT_MAX, "csia"), 3941 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, UINT_MAX, "csib"), 3942 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, UINT_MAX, "mipi-bias"), 3943 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, UINT_MAX, "pex-clk-bias"), 3944 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, UINT_MAX, "pex-clk3"), 3945 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"), 3946 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, UINT_MAX, "pex-clk1"), 3947 TEGRA_IO_PAD(TEGRA_IO_PAD_EQOS, 8, 0x74, 0x78, UINT_MAX, "eqos"), 3948 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, 0x74, 0x78, UINT_MAX, "pex-clk-2-bias"), 3949 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2, 10, 0x74, 0x78, UINT_MAX, "pex-clk-2"), 3950 TEGRA_IO_PAD(TEGRA_IO_PAD_DAP3, 11, 0x74, 0x78, UINT_MAX, "dap3"), 3951 TEGRA_IO_PAD(TEGRA_IO_PAD_DAP5, 12, 0x74, 0x78, UINT_MAX, "dap5"), 3952 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x74, 0x78, UINT_MAX, "uart"), 3953 TEGRA_IO_PAD(TEGRA_IO_PAD_PWR_CTL, 15, 0x74, 0x78, UINT_MAX, "pwr-ctl"), 3954 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO53, 16, 0x74, 0x78, UINT_MAX, "soc-gpio53"), 3955 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x74, 0x78, UINT_MAX, "audio"), 3956 TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM2, 18, 0x74, 0x78, UINT_MAX, "gp-pwm2"), 3957 TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM3, 19, 0x74, 0x78, UINT_MAX, "gp-pwm3"), 3958 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO12, 20, 0x74, 0x78, UINT_MAX, "soc-gpio12"), 3959 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO13, 21, 0x74, 0x78, UINT_MAX, "soc-gpio13"), 3960 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO10, 22, 0x74, 0x78, UINT_MAX, "soc-gpio10"), 3961 TEGRA_IO_PAD(TEGRA_IO_PAD_UART4, 23, 0x74, 0x78, UINT_MAX, "uart4"), 3962 TEGRA_IO_PAD(TEGRA_IO_PAD_UART5, 24, 0x74, 0x78, UINT_MAX, "uart5"), 3963 TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x74, 0x78, UINT_MAX, "dbg"), 3964 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP3, 26, 0x74, 0x78, UINT_MAX, "hdmi-dp3"), 3965 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP2, 27, 0x74, 0x78, UINT_MAX, "hdmi-dp2"), 3966 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, "hdmi-dp0"), 3967 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, UINT_MAX, "hdmi-dp1"), 3968 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, UINT_MAX, "pex-cntrl"), 3969 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CTL2, 1, 0x7c, 0x80, UINT_MAX, "pex-ctl2"), 3970 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L0_RST, 2, 0x7c, 0x80, UINT_MAX, "pex-l0-rst"), 3971 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L1_RST, 3, 0x7c, 0x80, UINT_MAX, "pex-l1-rst"), 3972 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 4, 0x7c, 0x80, UINT_MAX, "sdmmc4"), 3973 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L5_RST, 5, 0x7c, 0x80, UINT_MAX, "pex-l5-rst"), 3974 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 6, 0x7c, 0x80, UINT_MAX, "cam"), 3975 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 11, 0x7c, 0x80, UINT_MAX, "csic"), 3976 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 12, 0x7c, 0x80, UINT_MAX, "csid"), 3977 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 13, 0x7c, 0x80, UINT_MAX, "csie"), 3978 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 14, 0x7c, 0x80, UINT_MAX, "csif"), 3979 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 15, 0x7c, 0x80, UINT_MAX, "spi"), 3980 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 17, 0x7c, 0x80, UINT_MAX, "ufs"), 3981 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 18, 0x7c, 0x80, UINT_MAX, "csig"), 3982 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 19, 0x7c, 0x80, UINT_MAX, "csih"), 3983 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 21, 0x7c, 0x80, UINT_MAX, "edp"), 3984 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, 4, "sdmmc1-hv"), 3985 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, 6, "sdmmc3-hv"), 3986 TEGRA_IO_PAD(TEGRA_IO_PAD_CONN, 28, 0x7c, 0x80, UINT_MAX, "conn"), 3987 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, 1, "audio-hv"), 3988 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"), 3989 }; 3990 3991 static const struct pinctrl_pin_desc tegra194_pin_descs[] = { 3992 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 3993 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 3994 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), 3995 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"), 3996 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"), 3997 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), 3998 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), 3999 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EQOS, "eqos"), 4000 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2_BIAS, "pex-clk-2-bias"), 4001 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2, "pex-clk-2"), 4002 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DAP3, "dap3"), 4003 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DAP5, "dap5"), 4004 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), 4005 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PWR_CTL, "pwr-ctl"), 4006 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO53, "soc-gpio53"), 4007 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), 4008 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM2, "gp-pwm2"), 4009 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM3, "gp-pwm3"), 4010 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO12, "soc-gpio12"), 4011 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO13, "soc-gpio13"), 4012 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO10, "soc-gpio10"), 4013 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART4, "uart4"), 4014 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART5, "uart5"), 4015 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"), 4016 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP3, "hdmi-dp3"), 4017 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP2, "hdmi-dp2"), 4018 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"), 4019 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"), 4020 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), 4021 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CTL2, "pex-ctl2"), 4022 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L0_RST, "pex-l0-rst"), 4023 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L1_RST, "pex-l1-rst"), 4024 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"), 4025 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L5_RST, "pex-l5-rst"), 4026 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), 4027 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), 4028 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), 4029 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 4030 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), 4031 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"), 4032 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"), 4033 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIG, "csig"), 4034 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIH, "csih"), 4035 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"), 4036 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"), 4037 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"), 4038 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CONN, "conn"), 4039 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), 4040 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"), 4041 }; 4042 4043 static const struct tegra_pmc_regs tegra194_pmc_regs = { 4044 .scratch0 = 0x2000, 4045 .rst_status = 0x70, 4046 .rst_source_shift = 0x2, 4047 .rst_source_mask = 0x7c, 4048 .rst_level_shift = 0x0, 4049 .rst_level_mask = 0x3, 4050 }; 4051 4052 static const char * const tegra194_reset_sources[] = { 4053 "SYS_RESET_N", 4054 "AOWDT", 4055 "BCCPLEXWDT", 4056 "BPMPWDT", 4057 "SCEWDT", 4058 "SPEWDT", 4059 "APEWDT", 4060 "LCCPLEXWDT", 4061 "SENSOR", 4062 "AOTAG", 4063 "VFSENSOR", 4064 "MAINSWRST", 4065 "SC7", 4066 "HSM", 4067 "CSITE", 4068 "RCEWDT", 4069 "PVA0WDT", 4070 "PVA1WDT", 4071 "L1A_ASYNC", 4072 "BPMPBOOT", 4073 "FUSECRC", 4074 }; 4075 4076 static const struct tegra_wake_event tegra194_wake_events[] = { 4077 TEGRA_WAKE_IRQ("pmu", 24, 209), 4078 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)), 4079 TEGRA_WAKE_IRQ("rtc", 73, 10), 4080 TEGRA_WAKE_SIMPLE("usb3-port-0", 76), 4081 TEGRA_WAKE_SIMPLE("usb3-port-1", 77), 4082 TEGRA_WAKE_SIMPLE("usb3-port-2-3", 78), 4083 TEGRA_WAKE_SIMPLE("usb2-port-0", 79), 4084 TEGRA_WAKE_SIMPLE("usb2-port-1", 80), 4085 TEGRA_WAKE_SIMPLE("usb2-port-2", 81), 4086 TEGRA_WAKE_SIMPLE("usb2-port-3", 82), 4087 }; 4088 4089 static const struct tegra_pmc_soc tegra194_pmc_soc = { 4090 .supports_core_domain = false, 4091 .num_powergates = 0, 4092 .powergates = NULL, 4093 .num_cpu_powergates = 0, 4094 .cpu_powergates = NULL, 4095 .has_tsense_reset = false, 4096 .has_gpu_clamps = false, 4097 .needs_mbist_war = false, 4098 .has_impl_33v_pwr = true, 4099 .maybe_tz_only = false, 4100 .num_io_pads = ARRAY_SIZE(tegra194_io_pads), 4101 .io_pads = tegra194_io_pads, 4102 .num_pin_descs = ARRAY_SIZE(tegra194_pin_descs), 4103 .pin_descs = tegra194_pin_descs, 4104 .regs = &tegra194_pmc_regs, 4105 .init = tegra186_pmc_init, 4106 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 4107 .set_wake_filters = tegra186_pmc_set_wake_filters, 4108 .irq_set_wake = tegra186_pmc_irq_set_wake, 4109 .irq_set_type = tegra186_pmc_irq_set_type, 4110 .reset_sources = tegra194_reset_sources, 4111 .num_reset_sources = ARRAY_SIZE(tegra194_reset_sources), 4112 .reset_levels = tegra186_reset_levels, 4113 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 4114 .num_wake_events = ARRAY_SIZE(tegra194_wake_events), 4115 .wake_events = tegra194_wake_events, 4116 .max_wake_events = 96, 4117 .max_wake_vectors = 3, 4118 .pmc_clks_data = NULL, 4119 .num_pmc_clks = 0, 4120 .has_blink_output = false, 4121 .has_usb_sleepwalk = false, 4122 .has_single_mmio_aperture = false, 4123 }; 4124 4125 static const struct tegra_io_pad_soc tegra234_io_pads[] = { 4126 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0xe0c0, 0xe0c4, UINT_MAX, "csia"), 4127 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0xe0c0, 0xe0c4, UINT_MAX, "csib"), 4128 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 0, 0xe0d0, 0xe0d4, UINT_MAX, "hdmi-dp0"), 4129 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 2, 0xe0c0, 0xe0c4, UINT_MAX, "csic"), 4130 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 3, 0xe0c0, 0xe0c4, UINT_MAX, "csid"), 4131 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 4, 0xe0c0, 0xe0c4, UINT_MAX, "csie"), 4132 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 5, 0xe0c0, 0xe0c4, UINT_MAX, "csif"), 4133 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 0, 0xe064, 0xe068, UINT_MAX, "ufs"), 4134 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 1, 0xe05c, 0xe060, UINT_MAX, "edp"), 4135 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 0, 0xe054, 0xe058, 4, "sdmmc1-hv"), 4136 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, UINT_MAX, UINT_MAX, UINT_MAX, 6, "sdmmc3-hv"), 4137 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 1, "audio-hv"), 4138 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"), 4139 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 6, 0xe0c0, 0xe0c4, UINT_MAX, "csig"), 4140 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 7, 0xe0c0, 0xe0c4, UINT_MAX, "csih"), 4141 }; 4142 4143 static const struct pinctrl_pin_desc tegra234_pin_descs[] = { 4144 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 4145 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 4146 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"), 4147 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), 4148 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), 4149 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 4150 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), 4151 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"), 4152 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"), 4153 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"), 4154 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"), 4155 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), 4156 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"), 4157 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIG, "csig"), 4158 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIH, "csih"), 4159 }; 4160 4161 static const struct tegra_pmc_regs tegra234_pmc_regs = { 4162 .scratch0 = 0x2000, 4163 .rst_status = 0x70, 4164 .rst_source_shift = 0x2, 4165 .rst_source_mask = 0xfc, 4166 .rst_level_shift = 0x0, 4167 .rst_level_mask = 0x3, 4168 }; 4169 4170 static const char * const tegra234_reset_sources[] = { 4171 "SYS_RESET_N", /* 0x0 */ 4172 "AOWDT", 4173 "BCCPLEXWDT", 4174 "BPMPWDT", 4175 "SCEWDT", 4176 "SPEWDT", 4177 "APEWDT", 4178 "LCCPLEXWDT", 4179 "SENSOR", /* 0x8 */ 4180 NULL, 4181 NULL, 4182 "MAINSWRST", 4183 "SC7", 4184 "HSM", 4185 NULL, 4186 "RCEWDT", 4187 NULL, /* 0x10 */ 4188 NULL, 4189 NULL, 4190 "BPMPBOOT", 4191 "FUSECRC", 4192 "DCEWDT", 4193 "PSCWDT", 4194 "PSC", 4195 "CSITE_SW", /* 0x18 */ 4196 "POD", 4197 "SCPM", 4198 "VREFRO_POWERBAD", 4199 "VMON", 4200 "FMON", 4201 "FSI_R5WDT", 4202 "FSI_THERM", 4203 "FSI_R52C0WDT", /* 0x20 */ 4204 "FSI_R52C1WDT", 4205 "FSI_R52C2WDT", 4206 "FSI_R52C3WDT", 4207 "FSI_FMON", 4208 "FSI_VMON", /* 0x25 */ 4209 }; 4210 4211 static const struct tegra_wake_event tegra234_wake_events[] = { 4212 TEGRA_WAKE_GPIO("sd-wake", 8, 0, TEGRA234_MAIN_GPIO(G, 7)), 4213 TEGRA_WAKE_IRQ("pmu", 24, 209), 4214 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA234_AON_GPIO(EE, 4)), 4215 TEGRA_WAKE_GPIO("mgbe", 56, 0, TEGRA234_MAIN_GPIO(Y, 3)), 4216 TEGRA_WAKE_IRQ("rtc", 73, 10), 4217 TEGRA_WAKE_IRQ("sw-wake", SW_WAKE_ID, 179), 4218 }; 4219 4220 static const struct tegra_pmc_soc tegra234_pmc_soc = { 4221 .supports_core_domain = false, 4222 .num_powergates = 0, 4223 .powergates = NULL, 4224 .num_cpu_powergates = 0, 4225 .cpu_powergates = NULL, 4226 .has_tsense_reset = false, 4227 .has_gpu_clamps = false, 4228 .needs_mbist_war = false, 4229 .has_impl_33v_pwr = true, 4230 .maybe_tz_only = false, 4231 .num_io_pads = ARRAY_SIZE(tegra234_io_pads), 4232 .io_pads = tegra234_io_pads, 4233 .num_pin_descs = ARRAY_SIZE(tegra234_pin_descs), 4234 .pin_descs = tegra234_pin_descs, 4235 .regs = &tegra234_pmc_regs, 4236 .init = tegra186_pmc_init, 4237 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 4238 .set_wake_filters = tegra186_pmc_set_wake_filters, 4239 .irq_set_wake = tegra186_pmc_irq_set_wake, 4240 .irq_set_type = tegra186_pmc_irq_set_type, 4241 .reset_sources = tegra234_reset_sources, 4242 .num_reset_sources = ARRAY_SIZE(tegra234_reset_sources), 4243 .reset_levels = tegra186_reset_levels, 4244 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 4245 .num_wake_events = ARRAY_SIZE(tegra234_wake_events), 4246 .wake_events = tegra234_wake_events, 4247 .max_wake_events = 96, 4248 .max_wake_vectors = 3, 4249 .pmc_clks_data = NULL, 4250 .num_pmc_clks = 0, 4251 .has_blink_output = false, 4252 .has_single_mmio_aperture = false, 4253 }; 4254 4255 static const struct of_device_id tegra_pmc_match[] = { 4256 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc }, 4257 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc }, 4258 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc }, 4259 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc }, 4260 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc }, 4261 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc }, 4262 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc }, 4263 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc }, 4264 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc }, 4265 { } 4266 }; 4267 4268 static void tegra_pmc_sync_state(struct device *dev) 4269 { 4270 int err; 4271 4272 /* 4273 * Newer device-trees have power domains, but we need to prepare all 4274 * device drivers with runtime PM and OPP support first, otherwise 4275 * state syncing is unsafe. 4276 */ 4277 if (!pmc->soc->supports_core_domain) 4278 return; 4279 4280 /* 4281 * Older device-trees don't have core PD, and thus, there are 4282 * no dependencies that will block the state syncing. We shouldn't 4283 * mark the domain as synced in this case. 4284 */ 4285 if (!pmc->core_domain_registered) 4286 return; 4287 4288 pmc->core_domain_state_synced = true; 4289 4290 /* this is a no-op if core regulator isn't used */ 4291 mutex_lock(&pmc->powergates_lock); 4292 err = dev_pm_opp_sync_regulators(dev); 4293 mutex_unlock(&pmc->powergates_lock); 4294 4295 if (err) 4296 dev_err(dev, "failed to sync regulators: %d\n", err); 4297 } 4298 4299 static struct platform_driver tegra_pmc_driver = { 4300 .driver = { 4301 .name = "tegra-pmc", 4302 .suppress_bind_attrs = true, 4303 .of_match_table = tegra_pmc_match, 4304 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 4305 .pm = &tegra_pmc_pm_ops, 4306 #endif 4307 .sync_state = tegra_pmc_sync_state, 4308 }, 4309 .probe = tegra_pmc_probe, 4310 }; 4311 builtin_platform_driver(tegra_pmc_driver); 4312 4313 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc) 4314 { 4315 u32 value, saved; 4316 4317 saved = readl(pmc->base + pmc->soc->regs->scratch0); 4318 value = saved ^ 0xffffffff; 4319 4320 if (value == 0xffffffff) 4321 value = 0xdeadbeef; 4322 4323 /* write pattern and read it back */ 4324 writel(value, pmc->base + pmc->soc->regs->scratch0); 4325 value = readl(pmc->base + pmc->soc->regs->scratch0); 4326 4327 /* if we read all-zeroes, access is restricted to TZ only */ 4328 if (value == 0) { 4329 pr_info("access to PMC is restricted to TZ\n"); 4330 return true; 4331 } 4332 4333 /* restore original value */ 4334 writel(saved, pmc->base + pmc->soc->regs->scratch0); 4335 4336 return false; 4337 } 4338 4339 /* 4340 * Early initialization to allow access to registers in the very early boot 4341 * process. 4342 */ 4343 static int __init tegra_pmc_early_init(void) 4344 { 4345 const struct of_device_id *match; 4346 struct device_node *np; 4347 struct resource regs; 4348 unsigned int i; 4349 bool invert; 4350 4351 mutex_init(&pmc->powergates_lock); 4352 4353 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match); 4354 if (!np) { 4355 /* 4356 * Fall back to legacy initialization for 32-bit ARM only. All 4357 * 64-bit ARM device tree files for Tegra are required to have 4358 * a PMC node. 4359 * 4360 * This is for backwards-compatibility with old device trees 4361 * that didn't contain a PMC node. Note that in this case the 4362 * SoC data can't be matched and therefore powergating is 4363 * disabled. 4364 */ 4365 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 4366 pr_warn("DT node not found, powergating disabled\n"); 4367 4368 regs.start = 0x7000e400; 4369 regs.end = 0x7000e7ff; 4370 regs.flags = IORESOURCE_MEM; 4371 4372 pr_warn("Using memory region %pR\n", ®s); 4373 } else { 4374 /* 4375 * At this point we're not running on Tegra, so play 4376 * nice with multi-platform kernels. 4377 */ 4378 return 0; 4379 } 4380 } else { 4381 /* 4382 * Extract information from the device tree if we've found a 4383 * matching node. 4384 */ 4385 if (of_address_to_resource(np, 0, ®s) < 0) { 4386 pr_err("failed to get PMC registers\n"); 4387 of_node_put(np); 4388 return -ENXIO; 4389 } 4390 } 4391 4392 pmc->base = ioremap(regs.start, resource_size(®s)); 4393 if (!pmc->base) { 4394 pr_err("failed to map PMC registers\n"); 4395 of_node_put(np); 4396 return -ENXIO; 4397 } 4398 4399 if (of_device_is_available(np)) { 4400 pmc->soc = match->data; 4401 4402 if (pmc->soc->maybe_tz_only) 4403 pmc->tz_only = tegra_pmc_detect_tz_only(pmc); 4404 4405 /* Create a bitmap of the available and valid partitions */ 4406 for (i = 0; i < pmc->soc->num_powergates; i++) 4407 if (pmc->soc->powergates[i]) 4408 set_bit(i, pmc->powergates_available); 4409 4410 /* 4411 * Invert the interrupt polarity if a PMC device tree node 4412 * exists and contains the nvidia,invert-interrupt property. 4413 */ 4414 invert = of_property_read_bool(np, "nvidia,invert-interrupt"); 4415 4416 pmc->soc->setup_irq_polarity(pmc, np, invert); 4417 4418 of_node_put(np); 4419 } 4420 4421 return 0; 4422 } 4423 early_initcall(tegra_pmc_early_init); 4424