1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * drivers/soc/tegra/pmc.c 4 * 5 * Copyright (c) 2010 Google, Inc 6 * Copyright (c) 2018-2024, NVIDIA CORPORATION. All rights reserved. 7 * 8 * Author: 9 * Colin Cross <ccross@google.com> 10 */ 11 12 #define pr_fmt(fmt) "tegra-pmc: " fmt 13 14 #include <linux/arm-smccc.h> 15 #include <linux/clk.h> 16 #include <linux/clk-provider.h> 17 #include <linux/clkdev.h> 18 #include <linux/clk/clk-conf.h> 19 #include <linux/clk/tegra.h> 20 #include <linux/debugfs.h> 21 #include <linux/delay.h> 22 #include <linux/device.h> 23 #include <linux/err.h> 24 #include <linux/export.h> 25 #include <linux/init.h> 26 #include <linux/interrupt.h> 27 #include <linux/io.h> 28 #include <linux/iopoll.h> 29 #include <linux/irqdomain.h> 30 #include <linux/irq.h> 31 #include <linux/kernel.h> 32 #include <linux/of_address.h> 33 #include <linux/of_clk.h> 34 #include <linux/of.h> 35 #include <linux/of_irq.h> 36 #include <linux/of_platform.h> 37 #include <linux/pinctrl/pinconf-generic.h> 38 #include <linux/pinctrl/pinconf.h> 39 #include <linux/pinctrl/pinctrl.h> 40 #include <linux/platform_device.h> 41 #include <linux/pm_domain.h> 42 #include <linux/pm_opp.h> 43 #include <linux/power_supply.h> 44 #include <linux/reboot.h> 45 #include <linux/regmap.h> 46 #include <linux/reset.h> 47 #include <linux/seq_file.h> 48 #include <linux/slab.h> 49 #include <linux/spinlock.h> 50 #include <linux/string_choices.h> 51 #include <linux/syscore_ops.h> 52 53 #include <soc/tegra/common.h> 54 #include <soc/tegra/fuse.h> 55 #include <soc/tegra/pmc.h> 56 57 #include <dt-bindings/interrupt-controller/arm-gic.h> 58 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 59 #include <dt-bindings/gpio/tegra186-gpio.h> 60 #include <dt-bindings/gpio/tegra194-gpio.h> 61 #include <dt-bindings/gpio/tegra234-gpio.h> 62 #include <dt-bindings/soc/tegra-pmc.h> 63 64 #define PMC_CNTRL 0x0 65 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */ 66 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */ 67 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */ 68 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */ 69 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ 70 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ 71 #define PMC_CNTRL_PWRREQ_POLARITY BIT(8) 72 #define PMC_CNTRL_BLINK_EN 7 73 #define PMC_CNTRL_MAIN_RST BIT(4) 74 75 #define PMC_WAKE_MASK 0x0c 76 #define PMC_WAKE_LEVEL 0x10 77 #define PMC_WAKE_STATUS 0x14 78 #define PMC_SW_WAKE_STATUS 0x18 79 #define PMC_DPD_PADS_ORIDE 0x1c 80 #define PMC_DPD_PADS_ORIDE_BLINK 20 81 82 #define DPD_SAMPLE 0x020 83 #define DPD_SAMPLE_ENABLE BIT(0) 84 #define DPD_SAMPLE_DISABLE (0 << 0) 85 86 #define PWRGATE_TOGGLE 0x30 87 #define PWRGATE_TOGGLE_START BIT(8) 88 89 #define REMOVE_CLAMPING 0x34 90 91 #define PWRGATE_STATUS 0x38 92 93 #define PMC_BLINK_TIMER 0x40 94 #define PMC_IMPL_E_33V_PWR 0x40 95 96 #define PMC_PWR_DET 0x48 97 98 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31) 99 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30) 100 #define PMC_SCRATCH0_MODE_RCM BIT(1) 101 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ 102 PMC_SCRATCH0_MODE_BOOTLOADER | \ 103 PMC_SCRATCH0_MODE_RCM) 104 105 #define PMC_CPUPWRGOOD_TIMER 0xc8 106 #define PMC_CPUPWROFF_TIMER 0xcc 107 #define PMC_COREPWRGOOD_TIMER 0x3c 108 #define PMC_COREPWROFF_TIMER 0xe0 109 110 #define PMC_PWR_DET_VALUE 0xe4 111 112 #define PMC_USB_DEBOUNCE_DEL 0xec 113 #define PMC_USB_AO 0xf0 114 115 #define PMC_SCRATCH37 0x130 116 #define PMC_SCRATCH41 0x140 117 118 #define PMC_WAKE2_MASK 0x160 119 #define PMC_WAKE2_LEVEL 0x164 120 #define PMC_WAKE2_STATUS 0x168 121 #define PMC_SW_WAKE2_STATUS 0x16c 122 123 #define PMC_CLK_OUT_CNTRL 0x1a8 124 #define PMC_CLK_OUT_MUX_MASK GENMASK(1, 0) 125 #define PMC_SENSOR_CTRL 0x1b0 126 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) 127 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) 128 129 #define PMC_RST_STATUS_POR 0 130 #define PMC_RST_STATUS_WATCHDOG 1 131 #define PMC_RST_STATUS_SENSOR 2 132 #define PMC_RST_STATUS_SW_MAIN 3 133 #define PMC_RST_STATUS_LP0 4 134 #define PMC_RST_STATUS_AOTAG 5 135 136 #define IO_DPD_REQ 0x1b8 137 #define IO_DPD_REQ_CODE_IDLE (0U << 30) 138 #define IO_DPD_REQ_CODE_OFF (1U << 30) 139 #define IO_DPD_REQ_CODE_ON (2U << 30) 140 #define IO_DPD_REQ_CODE_MASK (3U << 30) 141 142 #define IO_DPD_STATUS 0x1bc 143 #define IO_DPD2_REQ 0x1c0 144 #define IO_DPD2_STATUS 0x1c4 145 #define SEL_DPD_TIM 0x1c8 146 147 #define PMC_UTMIP_UHSIC_TRIGGERS 0x1ec 148 #define PMC_UTMIP_UHSIC_SAVED_STATE 0x1f0 149 150 #define PMC_UTMIP_TERM_PAD_CFG 0x1f8 151 #define PMC_UTMIP_UHSIC_SLEEP_CFG 0x1fc 152 #define PMC_UTMIP_UHSIC_FAKE 0x218 153 154 #define PMC_SCRATCH54 0x258 155 #define PMC_SCRATCH54_DATA_SHIFT 8 156 #define PMC_SCRATCH54_ADDR_SHIFT 0 157 158 #define PMC_SCRATCH55 0x25c 159 #define PMC_SCRATCH55_RESET_TEGRA BIT(31) 160 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27 161 #define PMC_SCRATCH55_PINMUX_SHIFT 24 162 #define PMC_SCRATCH55_16BITOP BIT(15) 163 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16 164 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0 165 166 #define PMC_UTMIP_UHSIC_LINE_WAKEUP 0x26c 167 168 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x270 169 #define PMC_UTMIP_MASTER_CONFIG 0x274 170 #define PMC_UTMIP_UHSIC2_TRIGGERS 0x27c 171 #define PMC_UTMIP_MASTER2_CONFIG 0x29c 172 173 #define GPU_RG_CNTRL 0x2d4 174 175 #define PMC_UTMIP_PAD_CFG0 0x4c0 176 #define PMC_UTMIP_UHSIC_SLEEP_CFG1 0x4d0 177 #define PMC_UTMIP_SLEEPWALK_P3 0x4e0 178 /* Tegra186 and later */ 179 #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2)) 180 #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3) 181 #define WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN (1 << 1) 182 #define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2)) 183 #define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2)) 184 #define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2)) 185 #define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2)) 186 #define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2)) 187 #define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2)) 188 #define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2)) 189 #define WAKE_AOWAKE_SW_STATUS_W_0 0x49c 190 #define WAKE_AOWAKE_SW_STATUS(x) (0x4a0 + ((x) << 2)) 191 #define WAKE_LATCH_SW 0x498 192 193 #define WAKE_AOWAKE_CTRL 0x4f4 194 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0) 195 196 #define SW_WAKE_ID 83 /* wake83 */ 197 198 /* for secure PMC */ 199 #define TEGRA_SMC_PMC 0xc2fffe00 200 #define TEGRA_SMC_PMC_READ 0xaa 201 #define TEGRA_SMC_PMC_WRITE 0xbb 202 203 struct pmc_clk { 204 struct clk_hw hw; 205 unsigned long offs; 206 u32 mux_shift; 207 u32 force_en_shift; 208 }; 209 210 #define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw) 211 212 struct pmc_clk_gate { 213 struct clk_hw hw; 214 unsigned long offs; 215 u32 shift; 216 }; 217 218 #define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw) 219 220 struct pmc_clk_init_data { 221 char *name; 222 const char *const *parents; 223 int num_parents; 224 int clk_id; 225 u8 mux_shift; 226 u8 force_en_shift; 227 }; 228 229 static const char * const clk_out1_parents[] = { "osc", "osc_div2", 230 "osc_div4", "extern1", 231 }; 232 233 static const char * const clk_out2_parents[] = { "osc", "osc_div2", 234 "osc_div4", "extern2", 235 }; 236 237 static const char * const clk_out3_parents[] = { "osc", "osc_div2", 238 "osc_div4", "extern3", 239 }; 240 241 static const struct pmc_clk_init_data tegra_pmc_clks_data[] = { 242 { 243 .name = "pmc_clk_out_1", 244 .parents = clk_out1_parents, 245 .num_parents = ARRAY_SIZE(clk_out1_parents), 246 .clk_id = TEGRA_PMC_CLK_OUT_1, 247 .mux_shift = 6, 248 .force_en_shift = 2, 249 }, 250 { 251 .name = "pmc_clk_out_2", 252 .parents = clk_out2_parents, 253 .num_parents = ARRAY_SIZE(clk_out2_parents), 254 .clk_id = TEGRA_PMC_CLK_OUT_2, 255 .mux_shift = 14, 256 .force_en_shift = 10, 257 }, 258 { 259 .name = "pmc_clk_out_3", 260 .parents = clk_out3_parents, 261 .num_parents = ARRAY_SIZE(clk_out3_parents), 262 .clk_id = TEGRA_PMC_CLK_OUT_3, 263 .mux_shift = 22, 264 .force_en_shift = 18, 265 }, 266 }; 267 268 struct tegra_powergate { 269 struct generic_pm_domain genpd; 270 struct tegra_pmc *pmc; 271 unsigned int id; 272 struct clk **clks; 273 unsigned int num_clks; 274 unsigned long *clk_rates; 275 struct reset_control *reset; 276 }; 277 278 struct tegra_io_pad_soc { 279 enum tegra_io_pad id; 280 unsigned int dpd; 281 unsigned int request; 282 unsigned int status; 283 unsigned int voltage; 284 const char *name; 285 }; 286 287 struct tegra_pmc_regs { 288 unsigned int scratch0; 289 unsigned int rst_status; 290 unsigned int rst_source_shift; 291 unsigned int rst_source_mask; 292 unsigned int rst_level_shift; 293 unsigned int rst_level_mask; 294 }; 295 296 struct tegra_wake_event { 297 const char *name; 298 unsigned int id; 299 unsigned int irq; 300 struct { 301 unsigned int instance; 302 unsigned int pin; 303 } gpio; 304 }; 305 306 #define TEGRA_WAKE_SIMPLE(_name, _id) \ 307 { \ 308 .name = _name, \ 309 .id = _id, \ 310 .irq = 0, \ 311 .gpio = { \ 312 .instance = UINT_MAX, \ 313 .pin = UINT_MAX, \ 314 }, \ 315 } 316 317 #define TEGRA_WAKE_IRQ(_name, _id, _irq) \ 318 { \ 319 .name = _name, \ 320 .id = _id, \ 321 .irq = _irq, \ 322 .gpio = { \ 323 .instance = UINT_MAX, \ 324 .pin = UINT_MAX, \ 325 }, \ 326 } 327 328 #define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \ 329 { \ 330 .name = _name, \ 331 .id = _id, \ 332 .irq = 0, \ 333 .gpio = { \ 334 .instance = _instance, \ 335 .pin = _pin, \ 336 }, \ 337 } 338 339 struct tegra_pmc_soc { 340 unsigned int num_powergates; 341 const char *const *powergates; 342 unsigned int num_cpu_powergates; 343 const u8 *cpu_powergates; 344 345 bool has_tsense_reset; 346 bool has_gpu_clamps; 347 bool needs_mbist_war; 348 bool has_impl_33v_pwr; 349 bool maybe_tz_only; 350 351 const struct tegra_io_pad_soc *io_pads; 352 unsigned int num_io_pads; 353 354 const struct pinctrl_pin_desc *pin_descs; 355 unsigned int num_pin_descs; 356 357 const struct tegra_pmc_regs *regs; 358 void (*init)(struct tegra_pmc *pmc); 359 void (*setup_irq_polarity)(struct tegra_pmc *pmc, 360 struct device_node *np, 361 bool invert); 362 void (*set_wake_filters)(struct tegra_pmc *pmc); 363 int (*irq_set_wake)(struct irq_data *data, unsigned int on); 364 int (*irq_set_type)(struct irq_data *data, unsigned int type); 365 int (*powergate_set)(struct tegra_pmc *pmc, unsigned int id, 366 bool new_state); 367 368 const char * const *reset_sources; 369 unsigned int num_reset_sources; 370 const char * const *reset_levels; 371 unsigned int num_reset_levels; 372 373 /* 374 * These describe events that can wake the system from sleep (i.e. 375 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2) 376 * are dealt with in the LIC. 377 */ 378 const struct tegra_wake_event *wake_events; 379 unsigned int num_wake_events; 380 unsigned int max_wake_events; 381 unsigned int max_wake_vectors; 382 383 const struct pmc_clk_init_data *pmc_clks_data; 384 unsigned int num_pmc_clks; 385 bool has_blink_output; 386 bool has_usb_sleepwalk; 387 bool supports_core_domain; 388 bool has_single_mmio_aperture; 389 }; 390 391 /** 392 * struct tegra_pmc - NVIDIA Tegra PMC 393 * @dev: pointer to PMC device structure 394 * @base: pointer to I/O remapped register region 395 * @wake: pointer to I/O remapped region for WAKE registers 396 * @aotag: pointer to I/O remapped region for AOTAG registers 397 * @scratch: pointer to I/O remapped region for scratch registers 398 * @clk: pointer to pclk clock 399 * @soc: pointer to SoC data structure 400 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone 401 * @rate: currently configured rate of pclk 402 * @suspend_mode: lowest suspend mode available 403 * @cpu_good_time: CPU power good time (in microseconds) 404 * @cpu_off_time: CPU power off time (in microsecends) 405 * @core_osc_time: core power good OSC time (in microseconds) 406 * @core_pmu_time: core power good PMU time (in microseconds) 407 * @core_off_time: core power off time (in microseconds) 408 * @corereq_high: core power request is active-high 409 * @sysclkreq_high: system clock request is active-high 410 * @combined_req: combined power request for CPU & core 411 * @cpu_pwr_good_en: CPU power good signal is enabled 412 * @lp0_vec_phys: physical base address of the LP0 warm boot code 413 * @lp0_vec_size: size of the LP0 warm boot code 414 * @powergates_available: Bitmap of available power gates 415 * @powergates_lock: mutex for power gate register access 416 * @pctl_dev: pin controller exposed by the PMC 417 * @domain: IRQ domain provided by the PMC 418 * @irq: chip implementation for the IRQ domain 419 * @clk_nb: pclk clock changes handler 420 * @core_domain_state_synced: flag marking the core domain's state as synced 421 * @wake_type_level_map: Bitmap indicating level type for non-dual edge wakes 422 * @wake_type_dual_edge_map: Bitmap indicating if a wake is dual-edge or not 423 * @wake_sw_status_map: Bitmap to hold raw status of wakes without mask 424 * @wake_cntrl_level_map: Bitmap to hold wake levels to be programmed in 425 * cntrl register associated with each wake during system suspend. 426 * @syscore: syscore suspend/resume callbacks 427 */ 428 struct tegra_pmc { 429 struct device *dev; 430 void __iomem *base; 431 void __iomem *wake; 432 void __iomem *aotag; 433 void __iomem *scratch; 434 struct clk *clk; 435 436 const struct tegra_pmc_soc *soc; 437 bool tz_only; 438 439 unsigned long rate; 440 441 enum tegra_suspend_mode suspend_mode; 442 u32 cpu_good_time; 443 u32 cpu_off_time; 444 u32 core_osc_time; 445 u32 core_pmu_time; 446 u32 core_off_time; 447 bool corereq_high; 448 bool sysclkreq_high; 449 bool combined_req; 450 bool cpu_pwr_good_en; 451 u32 lp0_vec_phys; 452 u32 lp0_vec_size; 453 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX); 454 455 struct mutex powergates_lock; 456 457 struct pinctrl_dev *pctl_dev; 458 459 struct irq_domain *domain; 460 struct irq_chip irq; 461 462 struct notifier_block clk_nb; 463 464 bool core_domain_state_synced; 465 466 unsigned long *wake_type_level_map; 467 unsigned long *wake_type_dual_edge_map; 468 unsigned long *wake_sw_status_map; 469 unsigned long *wake_cntrl_level_map; 470 struct syscore syscore; 471 }; 472 473 static struct tegra_pmc *pmc = &(struct tegra_pmc) { 474 .base = NULL, 475 .suspend_mode = TEGRA_SUSPEND_NOT_READY, 476 }; 477 478 static inline struct tegra_powergate * 479 to_powergate(struct generic_pm_domain *domain) 480 { 481 return container_of(domain, struct tegra_powergate, genpd); 482 } 483 484 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset) 485 { 486 struct arm_smccc_res res; 487 488 if (pmc->tz_only) { 489 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0, 490 0, 0, 0, &res); 491 if (res.a0) { 492 if (pmc->dev) 493 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", 494 __func__, res.a0); 495 else 496 pr_warn("%s(): SMC failed: %lu\n", __func__, 497 res.a0); 498 } 499 500 return res.a1; 501 } 502 503 return readl(pmc->base + offset); 504 } 505 506 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value, 507 unsigned long offset) 508 { 509 struct arm_smccc_res res; 510 511 if (pmc->tz_only) { 512 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset, 513 value, 0, 0, 0, 0, &res); 514 if (res.a0) { 515 if (pmc->dev) 516 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", 517 __func__, res.a0); 518 else 519 pr_warn("%s(): SMC failed: %lu\n", __func__, 520 res.a0); 521 } 522 } else { 523 writel(value, pmc->base + offset); 524 } 525 } 526 527 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset) 528 { 529 if (pmc->tz_only) 530 return tegra_pmc_readl(pmc, offset); 531 532 return readl(pmc->scratch + offset); 533 } 534 535 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value, 536 unsigned long offset) 537 { 538 if (pmc->tz_only) 539 tegra_pmc_writel(pmc, value, offset); 540 else 541 writel(value, pmc->scratch + offset); 542 } 543 544 /* 545 * TODO Figure out a way to call this with the struct tegra_pmc * passed in. 546 * This currently doesn't work because readx_poll_timeout() can only operate 547 * on functions that take a single argument. 548 */ 549 static inline bool tegra_powergate_state(int id) 550 { 551 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 552 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0; 553 else 554 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0; 555 } 556 557 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id) 558 { 559 return (pmc->soc && pmc->soc->powergates[id]); 560 } 561 562 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id) 563 { 564 return test_bit(id, pmc->powergates_available); 565 } 566 567 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) 568 { 569 unsigned int i; 570 571 if (!pmc || !pmc->soc || !name) 572 return -EINVAL; 573 574 for (i = 0; i < pmc->soc->num_powergates; i++) { 575 if (!tegra_powergate_is_valid(pmc, i)) 576 continue; 577 578 if (!strcmp(name, pmc->soc->powergates[i])) 579 return i; 580 } 581 582 return -ENODEV; 583 } 584 585 static int tegra20_powergate_set(struct tegra_pmc *pmc, unsigned int id, 586 bool new_state) 587 { 588 unsigned int retries = 100; 589 bool status; 590 int ret; 591 592 /* 593 * As per TRM documentation, the toggle command will be dropped by PMC 594 * if there is contention with a HW-initiated toggling (i.e. CPU core 595 * power-gated), the command should be retried in that case. 596 */ 597 do { 598 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 599 600 /* wait for PMC to execute the command */ 601 ret = readx_poll_timeout(tegra_powergate_state, id, status, 602 status == new_state, 1, 10); 603 } while (ret == -ETIMEDOUT && retries--); 604 605 return ret; 606 } 607 608 static inline bool tegra_powergate_toggle_ready(struct tegra_pmc *pmc) 609 { 610 return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START); 611 } 612 613 static int tegra114_powergate_set(struct tegra_pmc *pmc, unsigned int id, 614 bool new_state) 615 { 616 bool status; 617 int err; 618 619 /* wait while PMC power gating is contended */ 620 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status, 621 status == true, 1, 100); 622 if (err) 623 return err; 624 625 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 626 627 /* wait for PMC to accept the command */ 628 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status, 629 status == true, 1, 100); 630 if (err) 631 return err; 632 633 /* wait for PMC to execute the command */ 634 err = readx_poll_timeout(tegra_powergate_state, id, status, 635 status == new_state, 10, 100000); 636 if (err) 637 return err; 638 639 return 0; 640 } 641 642 /** 643 * tegra_powergate_set() - set the state of a partition 644 * @pmc: power management controller 645 * @id: partition ID 646 * @new_state: new state of the partition 647 */ 648 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id, 649 bool new_state) 650 { 651 int err; 652 653 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 654 return -EINVAL; 655 656 mutex_lock(&pmc->powergates_lock); 657 658 if (tegra_powergate_state(id) == new_state) { 659 mutex_unlock(&pmc->powergates_lock); 660 return 0; 661 } 662 663 err = pmc->soc->powergate_set(pmc, id, new_state); 664 665 mutex_unlock(&pmc->powergates_lock); 666 667 return err; 668 } 669 670 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc, 671 unsigned int id) 672 { 673 u32 mask; 674 675 mutex_lock(&pmc->powergates_lock); 676 677 /* 678 * On Tegra124 and later, the clamps for the GPU are controlled by a 679 * separate register (with different semantics). 680 */ 681 if (id == TEGRA_POWERGATE_3D) { 682 if (pmc->soc->has_gpu_clamps) { 683 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL); 684 goto out; 685 } 686 } 687 688 /* 689 * Tegra 2 has a bug where PCIE and VDE clamping masks are 690 * swapped relatively to the partition ids 691 */ 692 if (id == TEGRA_POWERGATE_VDEC) 693 mask = (1 << TEGRA_POWERGATE_PCIE); 694 else if (id == TEGRA_POWERGATE_PCIE) 695 mask = (1 << TEGRA_POWERGATE_VDEC); 696 else 697 mask = (1 << id); 698 699 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING); 700 701 out: 702 mutex_unlock(&pmc->powergates_lock); 703 704 return 0; 705 } 706 707 static int tegra_powergate_prepare_clocks(struct tegra_powergate *pg) 708 { 709 unsigned long safe_rate = 100 * 1000 * 1000; 710 unsigned int i; 711 int err; 712 713 for (i = 0; i < pg->num_clks; i++) { 714 pg->clk_rates[i] = clk_get_rate(pg->clks[i]); 715 716 if (!pg->clk_rates[i]) { 717 err = -EINVAL; 718 goto out; 719 } 720 721 if (pg->clk_rates[i] <= safe_rate) 722 continue; 723 724 /* 725 * We don't know whether voltage state is okay for the 726 * current clock rate, hence it's better to temporally 727 * switch clock to a safe rate which is suitable for 728 * all voltages, before enabling the clock. 729 */ 730 err = clk_set_rate(pg->clks[i], safe_rate); 731 if (err) 732 goto out; 733 } 734 735 return 0; 736 737 out: 738 while (i--) 739 clk_set_rate(pg->clks[i], pg->clk_rates[i]); 740 741 return err; 742 } 743 744 static int tegra_powergate_unprepare_clocks(struct tegra_powergate *pg) 745 { 746 unsigned int i; 747 int err; 748 749 for (i = 0; i < pg->num_clks; i++) { 750 err = clk_set_rate(pg->clks[i], pg->clk_rates[i]); 751 if (err) 752 return err; 753 } 754 755 return 0; 756 } 757 758 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg) 759 { 760 unsigned int i; 761 762 for (i = 0; i < pg->num_clks; i++) 763 clk_disable_unprepare(pg->clks[i]); 764 } 765 766 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg) 767 { 768 unsigned int i; 769 int err; 770 771 for (i = 0; i < pg->num_clks; i++) { 772 err = clk_prepare_enable(pg->clks[i]); 773 if (err) 774 goto out; 775 } 776 777 return 0; 778 779 out: 780 while (i--) 781 clk_disable_unprepare(pg->clks[i]); 782 783 return err; 784 } 785 786 static int tegra_powergate_power_up(struct tegra_powergate *pg, 787 bool disable_clocks) 788 { 789 int err; 790 791 err = reset_control_assert(pg->reset); 792 if (err) 793 return err; 794 795 usleep_range(10, 20); 796 797 err = tegra_powergate_set(pg->pmc, pg->id, true); 798 if (err < 0) 799 return err; 800 801 usleep_range(10, 20); 802 803 err = tegra_powergate_prepare_clocks(pg); 804 if (err) 805 goto powergate_off; 806 807 err = tegra_powergate_enable_clocks(pg); 808 if (err) 809 goto unprepare_clks; 810 811 usleep_range(10, 20); 812 813 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id); 814 if (err) 815 goto disable_clks; 816 817 usleep_range(10, 20); 818 819 err = reset_control_deassert(pg->reset); 820 if (err) 821 goto disable_clks; 822 823 usleep_range(10, 20); 824 825 if (pg->pmc->soc->needs_mbist_war) 826 err = tegra210_clk_handle_mbist_war(pg->id); 827 if (err) 828 goto disable_clks; 829 830 if (disable_clocks) 831 tegra_powergate_disable_clocks(pg); 832 833 err = tegra_powergate_unprepare_clocks(pg); 834 if (err) 835 return err; 836 837 return 0; 838 839 disable_clks: 840 tegra_powergate_disable_clocks(pg); 841 usleep_range(10, 20); 842 843 unprepare_clks: 844 tegra_powergate_unprepare_clocks(pg); 845 846 powergate_off: 847 tegra_powergate_set(pg->pmc, pg->id, false); 848 849 return err; 850 } 851 852 static int tegra_powergate_power_down(struct tegra_powergate *pg) 853 { 854 int err; 855 856 err = tegra_powergate_prepare_clocks(pg); 857 if (err) 858 return err; 859 860 err = tegra_powergate_enable_clocks(pg); 861 if (err) 862 goto unprepare_clks; 863 864 usleep_range(10, 20); 865 866 err = reset_control_assert(pg->reset); 867 if (err) 868 goto disable_clks; 869 870 usleep_range(10, 20); 871 872 tegra_powergate_disable_clocks(pg); 873 874 usleep_range(10, 20); 875 876 err = tegra_powergate_set(pg->pmc, pg->id, false); 877 if (err) 878 goto assert_resets; 879 880 err = tegra_powergate_unprepare_clocks(pg); 881 if (err) 882 return err; 883 884 return 0; 885 886 assert_resets: 887 tegra_powergate_enable_clocks(pg); 888 usleep_range(10, 20); 889 reset_control_deassert(pg->reset); 890 usleep_range(10, 20); 891 892 disable_clks: 893 tegra_powergate_disable_clocks(pg); 894 895 unprepare_clks: 896 tegra_powergate_unprepare_clocks(pg); 897 898 return err; 899 } 900 901 static int tegra_genpd_power_on(struct generic_pm_domain *domain) 902 { 903 struct tegra_powergate *pg = to_powergate(domain); 904 struct device *dev = pg->pmc->dev; 905 int err; 906 907 err = tegra_powergate_power_up(pg, true); 908 if (err) { 909 dev_err(dev, "failed to turn on PM domain %s: %d\n", 910 pg->genpd.name, err); 911 goto out; 912 } 913 914 reset_control_release(pg->reset); 915 916 out: 917 return err; 918 } 919 920 static int tegra_genpd_power_off(struct generic_pm_domain *domain) 921 { 922 struct tegra_powergate *pg = to_powergate(domain); 923 struct device *dev = pg->pmc->dev; 924 int err; 925 926 err = reset_control_acquire(pg->reset); 927 if (err < 0) { 928 dev_err(dev, "failed to acquire resets for PM domain %s: %d\n", 929 pg->genpd.name, err); 930 return err; 931 } 932 933 err = tegra_powergate_power_down(pg); 934 if (err) { 935 dev_err(dev, "failed to turn off PM domain %s: %d\n", 936 pg->genpd.name, err); 937 reset_control_release(pg->reset); 938 } 939 940 return err; 941 } 942 943 /** 944 * tegra_powergate_power_on() - power on partition 945 * @id: partition ID 946 */ 947 int tegra_powergate_power_on(unsigned int id) 948 { 949 if (!tegra_powergate_is_available(pmc, id)) 950 return -EINVAL; 951 952 return tegra_powergate_set(pmc, id, true); 953 } 954 EXPORT_SYMBOL(tegra_powergate_power_on); 955 956 /** 957 * tegra_powergate_power_off() - power off partition 958 * @id: partition ID 959 */ 960 int tegra_powergate_power_off(unsigned int id) 961 { 962 if (!tegra_powergate_is_available(pmc, id)) 963 return -EINVAL; 964 965 return tegra_powergate_set(pmc, id, false); 966 } 967 EXPORT_SYMBOL(tegra_powergate_power_off); 968 969 /** 970 * tegra_powergate_is_powered() - check if partition is powered 971 * @pmc: power management controller 972 * @id: partition ID 973 */ 974 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id) 975 { 976 if (!tegra_powergate_is_valid(pmc, id)) 977 return -EINVAL; 978 979 return tegra_powergate_state(id); 980 } 981 982 /** 983 * tegra_powergate_remove_clamping() - remove power clamps for partition 984 * @id: partition ID 985 */ 986 int tegra_powergate_remove_clamping(unsigned int id) 987 { 988 if (!tegra_powergate_is_available(pmc, id)) 989 return -EINVAL; 990 991 return __tegra_powergate_remove_clamping(pmc, id); 992 } 993 EXPORT_SYMBOL(tegra_powergate_remove_clamping); 994 995 /** 996 * tegra_powergate_sequence_power_up() - power up partition 997 * @id: partition ID 998 * @clk: clock for partition 999 * @rst: reset for partition 1000 * 1001 * Must be called with clk disabled, and returns with clk enabled. 1002 */ 1003 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, 1004 struct reset_control *rst) 1005 { 1006 struct tegra_powergate *pg; 1007 int err; 1008 1009 if (!tegra_powergate_is_available(pmc, id)) 1010 return -EINVAL; 1011 1012 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 1013 if (!pg) 1014 return -ENOMEM; 1015 1016 pg->clk_rates = kzalloc(sizeof(*pg->clk_rates), GFP_KERNEL); 1017 if (!pg->clk_rates) { 1018 kfree(pg->clks); 1019 return -ENOMEM; 1020 } 1021 1022 pg->id = id; 1023 pg->clks = &clk; 1024 pg->num_clks = 1; 1025 pg->reset = rst; 1026 pg->pmc = pmc; 1027 1028 err = tegra_powergate_power_up(pg, false); 1029 if (err) 1030 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id, 1031 err); 1032 1033 kfree(pg->clk_rates); 1034 kfree(pg); 1035 1036 return err; 1037 } 1038 EXPORT_SYMBOL(tegra_powergate_sequence_power_up); 1039 1040 /** 1041 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID 1042 * @pmc: power management controller 1043 * @cpuid: CPU partition ID 1044 * 1045 * Returns the partition ID corresponding to the CPU partition ID or a 1046 * negative error code on failure. 1047 */ 1048 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc, 1049 unsigned int cpuid) 1050 { 1051 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) 1052 return pmc->soc->cpu_powergates[cpuid]; 1053 1054 return -EINVAL; 1055 } 1056 1057 /** 1058 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered 1059 * @cpuid: CPU partition ID 1060 */ 1061 bool tegra_pmc_cpu_is_powered(unsigned int cpuid) 1062 { 1063 int id; 1064 1065 id = tegra_get_cpu_powergate_id(pmc, cpuid); 1066 if (id < 0) 1067 return false; 1068 1069 return tegra_powergate_is_powered(pmc, id); 1070 } 1071 1072 /** 1073 * tegra_pmc_cpu_power_on() - power on CPU partition 1074 * @cpuid: CPU partition ID 1075 */ 1076 int tegra_pmc_cpu_power_on(unsigned int cpuid) 1077 { 1078 int id; 1079 1080 id = tegra_get_cpu_powergate_id(pmc, cpuid); 1081 if (id < 0) 1082 return id; 1083 1084 return tegra_powergate_set(pmc, id, true); 1085 } 1086 1087 /** 1088 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition 1089 * @cpuid: CPU partition ID 1090 */ 1091 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid) 1092 { 1093 int id; 1094 1095 id = tegra_get_cpu_powergate_id(pmc, cpuid); 1096 if (id < 0) 1097 return id; 1098 1099 return tegra_powergate_remove_clamping(id); 1100 } 1101 1102 static void tegra_pmc_program_reboot_reason(const char *cmd) 1103 { 1104 u32 value; 1105 1106 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0); 1107 value &= ~PMC_SCRATCH0_MODE_MASK; 1108 1109 if (cmd) { 1110 if (strcmp(cmd, "recovery") == 0) 1111 value |= PMC_SCRATCH0_MODE_RECOVERY; 1112 1113 if (strcmp(cmd, "bootloader") == 0) 1114 value |= PMC_SCRATCH0_MODE_BOOTLOADER; 1115 1116 if (strcmp(cmd, "forced-recovery") == 0) 1117 value |= PMC_SCRATCH0_MODE_RCM; 1118 } 1119 1120 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0); 1121 } 1122 1123 static int tegra_pmc_reboot_notify(struct notifier_block *this, 1124 unsigned long action, void *data) 1125 { 1126 if (action == SYS_RESTART) 1127 tegra_pmc_program_reboot_reason(data); 1128 1129 return NOTIFY_DONE; 1130 } 1131 1132 static struct notifier_block tegra_pmc_reboot_notifier = { 1133 .notifier_call = tegra_pmc_reboot_notify, 1134 }; 1135 1136 static void tegra_pmc_restart(void) 1137 { 1138 u32 value; 1139 1140 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */ 1141 value = tegra_pmc_readl(pmc, PMC_CNTRL); 1142 value |= PMC_CNTRL_MAIN_RST; 1143 tegra_pmc_writel(pmc, value, PMC_CNTRL); 1144 } 1145 1146 static int tegra_pmc_restart_handler(struct sys_off_data *data) 1147 { 1148 tegra_pmc_restart(); 1149 1150 return NOTIFY_DONE; 1151 } 1152 1153 static int tegra_pmc_power_off_handler(struct sys_off_data *data) 1154 { 1155 /* 1156 * Reboot Nexus 7 into special bootloader mode if USB cable is 1157 * connected in order to display battery status and power off. 1158 */ 1159 if (of_machine_is_compatible("asus,grouper") && 1160 power_supply_is_system_supplied()) { 1161 const u32 go_to_charger_mode = 0xa5a55a5a; 1162 1163 tegra_pmc_writel(pmc, go_to_charger_mode, PMC_SCRATCH37); 1164 tegra_pmc_restart(); 1165 } 1166 1167 return NOTIFY_DONE; 1168 } 1169 1170 static int powergate_show(struct seq_file *s, void *data) 1171 { 1172 unsigned int i; 1173 int status; 1174 1175 seq_printf(s, " powergate powered\n"); 1176 seq_printf(s, "------------------\n"); 1177 1178 for (i = 0; i < pmc->soc->num_powergates; i++) { 1179 status = tegra_powergate_is_powered(pmc, i); 1180 if (status < 0) 1181 continue; 1182 1183 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], 1184 str_yes_no(status)); 1185 } 1186 1187 return 0; 1188 } 1189 1190 DEFINE_SHOW_ATTRIBUTE(powergate); 1191 1192 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg, 1193 struct device_node *np) 1194 { 1195 struct clk *clk; 1196 unsigned int i, count; 1197 int err; 1198 1199 count = of_clk_get_parent_count(np); 1200 if (count == 0) 1201 return -ENODEV; 1202 1203 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL); 1204 if (!pg->clks) 1205 return -ENOMEM; 1206 1207 pg->clk_rates = kcalloc(count, sizeof(*pg->clk_rates), GFP_KERNEL); 1208 if (!pg->clk_rates) { 1209 kfree(pg->clks); 1210 return -ENOMEM; 1211 } 1212 1213 for (i = 0; i < count; i++) { 1214 pg->clks[i] = of_clk_get(np, i); 1215 if (IS_ERR(pg->clks[i])) { 1216 err = PTR_ERR(pg->clks[i]); 1217 goto err; 1218 } 1219 } 1220 1221 pg->num_clks = count; 1222 1223 return 0; 1224 1225 err: 1226 while (i--) 1227 clk_put(pg->clks[i]); 1228 1229 kfree(pg->clk_rates); 1230 kfree(pg->clks); 1231 1232 return err; 1233 } 1234 1235 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg, 1236 struct device_node *np) 1237 { 1238 struct device *dev = pg->pmc->dev; 1239 int err; 1240 1241 pg->reset = of_reset_control_array_get_exclusive_released(np); 1242 if (IS_ERR(pg->reset)) { 1243 err = PTR_ERR(pg->reset); 1244 dev_err(dev, "failed to get device resets: %d\n", err); 1245 return err; 1246 } 1247 1248 err = reset_control_acquire(pg->reset); 1249 if (err < 0) { 1250 pr_err("failed to acquire resets: %d\n", err); 1251 reset_control_put(pg->reset); 1252 } 1253 1254 return err; 1255 } 1256 1257 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) 1258 { 1259 struct device *dev = pmc->dev; 1260 struct tegra_powergate *pg; 1261 int id, err = 0; 1262 bool off; 1263 1264 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 1265 if (!pg) 1266 return -ENOMEM; 1267 1268 id = tegra_powergate_lookup(pmc, np->name); 1269 if (id < 0) { 1270 dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id); 1271 err = -ENODEV; 1272 goto free_mem; 1273 } 1274 1275 /* 1276 * Clear the bit for this powergate so it cannot be managed 1277 * directly via the legacy APIs for controlling powergates. 1278 */ 1279 clear_bit(id, pmc->powergates_available); 1280 1281 pg->id = id; 1282 pg->genpd.name = np->name; 1283 pg->genpd.flags = GENPD_FLAG_NO_SYNC_STATE; 1284 pg->genpd.power_off = tegra_genpd_power_off; 1285 pg->genpd.power_on = tegra_genpd_power_on; 1286 pg->pmc = pmc; 1287 1288 off = !tegra_powergate_is_powered(pmc, pg->id); 1289 1290 err = tegra_powergate_of_get_clks(pg, np); 1291 if (err < 0) { 1292 dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err); 1293 goto set_available; 1294 } 1295 1296 err = tegra_powergate_of_get_resets(pg, np); 1297 if (err < 0) { 1298 dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err); 1299 goto remove_clks; 1300 } 1301 1302 /* 1303 * If the power-domain is off, then ensure the resets are asserted. 1304 * If the power-domain is on, then power down to ensure that when is 1305 * it turned on the power-domain, clocks and resets are all in the 1306 * expected state. 1307 */ 1308 if (off) { 1309 err = reset_control_assert(pg->reset); 1310 if (err) { 1311 pr_err("failed to assert resets: %d\n", err); 1312 goto remove_resets; 1313 } 1314 } else { 1315 err = tegra_powergate_power_down(pg); 1316 if (err) { 1317 dev_err(dev, "failed to turn off PM domain %s: %d\n", 1318 pg->genpd.name, err); 1319 goto remove_resets; 1320 } 1321 } 1322 1323 /* 1324 * If PM_GENERIC_DOMAINS is not enabled, power-on 1325 * the domain and skip the genpd registration. 1326 */ 1327 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) { 1328 WARN_ON(tegra_powergate_power_up(pg, true)); 1329 goto remove_resets; 1330 } 1331 1332 err = pm_genpd_init(&pg->genpd, NULL, true); 1333 if (err < 0) { 1334 dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np, 1335 err); 1336 goto remove_resets; 1337 } 1338 1339 err = of_genpd_add_provider_simple(np, &pg->genpd); 1340 if (err < 0) { 1341 dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n", 1342 np, err); 1343 goto remove_genpd; 1344 } 1345 1346 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name); 1347 1348 return 0; 1349 1350 remove_genpd: 1351 pm_genpd_remove(&pg->genpd); 1352 1353 remove_resets: 1354 reset_control_put(pg->reset); 1355 1356 remove_clks: 1357 while (pg->num_clks--) 1358 clk_put(pg->clks[pg->num_clks]); 1359 1360 kfree(pg->clks); 1361 1362 set_available: 1363 set_bit(id, pmc->powergates_available); 1364 1365 free_mem: 1366 kfree(pg); 1367 1368 return err; 1369 } 1370 1371 bool tegra_pmc_core_domain_state_synced(void) 1372 { 1373 return pmc->core_domain_state_synced; 1374 } 1375 1376 static int 1377 tegra_pmc_core_pd_set_performance_state(struct generic_pm_domain *genpd, 1378 unsigned int level) 1379 { 1380 struct dev_pm_opp *opp; 1381 int err; 1382 1383 opp = dev_pm_opp_find_level_ceil(&genpd->dev, &level); 1384 if (IS_ERR(opp)) { 1385 dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n", 1386 level, opp); 1387 return PTR_ERR(opp); 1388 } 1389 1390 mutex_lock(&pmc->powergates_lock); 1391 err = dev_pm_opp_set_opp(pmc->dev, opp); 1392 mutex_unlock(&pmc->powergates_lock); 1393 1394 dev_pm_opp_put(opp); 1395 1396 if (err) { 1397 dev_err(&genpd->dev, "failed to set voltage to %duV: %d\n", 1398 level, err); 1399 return err; 1400 } 1401 1402 return 0; 1403 } 1404 1405 static int tegra_pmc_core_pd_add(struct tegra_pmc *pmc, struct device_node *np) 1406 { 1407 struct generic_pm_domain *genpd; 1408 const char *rname[] = { "core", NULL}; 1409 int err; 1410 1411 genpd = devm_kzalloc(pmc->dev, sizeof(*genpd), GFP_KERNEL); 1412 if (!genpd) 1413 return -ENOMEM; 1414 1415 genpd->name = "core"; 1416 genpd->flags = GENPD_FLAG_NO_SYNC_STATE; 1417 genpd->set_performance_state = tegra_pmc_core_pd_set_performance_state; 1418 1419 err = devm_pm_opp_set_regulators(pmc->dev, rname); 1420 if (err) 1421 return dev_err_probe(pmc->dev, err, 1422 "failed to set core OPP regulator\n"); 1423 1424 err = pm_genpd_init(genpd, NULL, false); 1425 if (err) { 1426 dev_err(pmc->dev, "failed to init core genpd: %d\n", err); 1427 return err; 1428 } 1429 1430 err = of_genpd_add_provider_simple(np, genpd); 1431 if (err) { 1432 dev_err(pmc->dev, "failed to add core genpd: %d\n", err); 1433 goto remove_genpd; 1434 } 1435 1436 return 0; 1437 1438 remove_genpd: 1439 pm_genpd_remove(genpd); 1440 1441 return err; 1442 } 1443 1444 static int tegra_powergate_init(struct tegra_pmc *pmc, 1445 struct device_node *parent) 1446 { 1447 struct of_phandle_args child_args, parent_args; 1448 struct device_node *np; 1449 int err = 0; 1450 1451 /* 1452 * Core power domain is the parent of powergate domains, hence it 1453 * should be registered first. 1454 */ 1455 np = of_get_child_by_name(parent, "core-domain"); 1456 if (np) { 1457 err = tegra_pmc_core_pd_add(pmc, np); 1458 of_node_put(np); 1459 if (err) 1460 return err; 1461 } 1462 1463 np = of_get_child_by_name(parent, "powergates"); 1464 if (!np) 1465 return 0; 1466 1467 for_each_child_of_node_scoped(np, child) { 1468 err = tegra_powergate_add(pmc, child); 1469 if (err < 0) 1470 break; 1471 1472 if (of_parse_phandle_with_args(child, "power-domains", 1473 "#power-domain-cells", 1474 0, &parent_args)) 1475 continue; 1476 1477 child_args.np = child; 1478 child_args.args_count = 0; 1479 1480 err = of_genpd_add_subdomain(&parent_args, &child_args); 1481 of_node_put(parent_args.np); 1482 if (err) 1483 break; 1484 } 1485 1486 of_node_put(np); 1487 1488 return err; 1489 } 1490 1491 static void tegra_powergate_remove(struct generic_pm_domain *genpd) 1492 { 1493 struct tegra_powergate *pg = to_powergate(genpd); 1494 1495 reset_control_put(pg->reset); 1496 1497 while (pg->num_clks--) 1498 clk_put(pg->clks[pg->num_clks]); 1499 1500 kfree(pg->clks); 1501 1502 set_bit(pg->id, pmc->powergates_available); 1503 1504 kfree(pg); 1505 } 1506 1507 static void tegra_powergate_remove_all(struct device_node *parent) 1508 { 1509 struct generic_pm_domain *genpd; 1510 struct device_node *np, *child; 1511 1512 np = of_get_child_by_name(parent, "powergates"); 1513 if (!np) 1514 return; 1515 1516 for_each_child_of_node(np, child) { 1517 of_genpd_del_provider(child); 1518 1519 genpd = of_genpd_remove_last(child); 1520 if (IS_ERR(genpd)) 1521 continue; 1522 1523 tegra_powergate_remove(genpd); 1524 } 1525 1526 of_node_put(np); 1527 1528 np = of_get_child_by_name(parent, "core-domain"); 1529 if (np) { 1530 of_genpd_del_provider(np); 1531 of_genpd_remove_last(np); 1532 } 1533 } 1534 1535 static const struct tegra_io_pad_soc * 1536 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id) 1537 { 1538 unsigned int i; 1539 1540 for (i = 0; i < pmc->soc->num_io_pads; i++) 1541 if (pmc->soc->io_pads[i].id == id) 1542 return &pmc->soc->io_pads[i]; 1543 1544 return NULL; 1545 } 1546 1547 static int tegra_io_pad_prepare(struct tegra_pmc *pmc, 1548 const struct tegra_io_pad_soc *pad, 1549 unsigned long *request, 1550 unsigned long *status, 1551 u32 *mask) 1552 { 1553 unsigned long rate, value; 1554 1555 if (pad->dpd == UINT_MAX) 1556 return -EINVAL; 1557 1558 *request = pad->request; 1559 *status = pad->status; 1560 *mask = BIT(pad->dpd); 1561 1562 if (pmc->clk) { 1563 rate = pmc->rate; 1564 if (!rate) { 1565 dev_err(pmc->dev, "failed to get clock rate\n"); 1566 return -ENODEV; 1567 } 1568 1569 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE); 1570 1571 /* must be at least 200 ns, in APB (PCLK) clock cycles */ 1572 value = DIV_ROUND_UP(1000000000, rate); 1573 value = DIV_ROUND_UP(200, value); 1574 tegra_pmc_writel(pmc, value, SEL_DPD_TIM); 1575 } 1576 1577 return 0; 1578 } 1579 1580 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset, 1581 u32 mask, u32 val, unsigned long timeout) 1582 { 1583 u32 value; 1584 1585 timeout = jiffies + msecs_to_jiffies(timeout); 1586 1587 while (time_after(timeout, jiffies)) { 1588 value = tegra_pmc_readl(pmc, offset); 1589 if ((value & mask) == val) 1590 return 0; 1591 1592 usleep_range(250, 1000); 1593 } 1594 1595 return -ETIMEDOUT; 1596 } 1597 1598 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc) 1599 { 1600 if (pmc->clk) 1601 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE); 1602 } 1603 1604 /** 1605 * tegra_io_pad_power_enable() - enable power to I/O pad 1606 * @id: Tegra I/O pad ID for which to enable power 1607 * 1608 * Returns: 0 on success or a negative error code on failure. 1609 */ 1610 int tegra_io_pad_power_enable(enum tegra_io_pad id) 1611 { 1612 const struct tegra_io_pad_soc *pad; 1613 unsigned long request, status; 1614 u32 mask; 1615 int err; 1616 1617 pad = tegra_io_pad_find(pmc, id); 1618 if (!pad) { 1619 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); 1620 return -ENOENT; 1621 } 1622 1623 mutex_lock(&pmc->powergates_lock); 1624 1625 err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask); 1626 if (err < 0) { 1627 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); 1628 goto unlock; 1629 } 1630 1631 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request); 1632 1633 err = tegra_io_pad_poll(pmc, status, mask, 0, 250); 1634 if (err < 0) { 1635 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err); 1636 goto unlock; 1637 } 1638 1639 tegra_io_pad_unprepare(pmc); 1640 1641 unlock: 1642 mutex_unlock(&pmc->powergates_lock); 1643 return err; 1644 } 1645 EXPORT_SYMBOL(tegra_io_pad_power_enable); 1646 1647 /** 1648 * tegra_io_pad_power_disable() - disable power to I/O pad 1649 * @id: Tegra I/O pad ID for which to disable power 1650 * 1651 * Returns: 0 on success or a negative error code on failure. 1652 */ 1653 int tegra_io_pad_power_disable(enum tegra_io_pad id) 1654 { 1655 const struct tegra_io_pad_soc *pad; 1656 unsigned long request, status; 1657 u32 mask; 1658 int err; 1659 1660 pad = tegra_io_pad_find(pmc, id); 1661 if (!pad) { 1662 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); 1663 return -ENOENT; 1664 } 1665 1666 mutex_lock(&pmc->powergates_lock); 1667 1668 err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask); 1669 if (err < 0) { 1670 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); 1671 goto unlock; 1672 } 1673 1674 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request); 1675 1676 err = tegra_io_pad_poll(pmc, status, mask, mask, 250); 1677 if (err < 0) { 1678 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err); 1679 goto unlock; 1680 } 1681 1682 tegra_io_pad_unprepare(pmc); 1683 1684 unlock: 1685 mutex_unlock(&pmc->powergates_lock); 1686 return err; 1687 } 1688 EXPORT_SYMBOL(tegra_io_pad_power_disable); 1689 1690 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id) 1691 { 1692 const struct tegra_io_pad_soc *pad; 1693 unsigned long status; 1694 u32 mask, value; 1695 1696 pad = tegra_io_pad_find(pmc, id); 1697 if (!pad) { 1698 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); 1699 return -ENOENT; 1700 } 1701 1702 if (pad->dpd == UINT_MAX) 1703 return -EINVAL; 1704 1705 status = pad->status; 1706 mask = BIT(pad->dpd); 1707 1708 value = tegra_pmc_readl(pmc, status); 1709 1710 return !(value & mask); 1711 } 1712 1713 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id, 1714 int voltage) 1715 { 1716 const struct tegra_io_pad_soc *pad; 1717 u32 value; 1718 1719 pad = tegra_io_pad_find(pmc, id); 1720 if (!pad) 1721 return -ENOENT; 1722 1723 if (pad->voltage == UINT_MAX) 1724 return -ENOTSUPP; 1725 1726 mutex_lock(&pmc->powergates_lock); 1727 1728 if (pmc->soc->has_impl_33v_pwr) { 1729 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); 1730 1731 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) 1732 value &= ~BIT(pad->voltage); 1733 else 1734 value |= BIT(pad->voltage); 1735 1736 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR); 1737 } else { 1738 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */ 1739 value = tegra_pmc_readl(pmc, PMC_PWR_DET); 1740 value |= BIT(pad->voltage); 1741 tegra_pmc_writel(pmc, value, PMC_PWR_DET); 1742 1743 /* update I/O voltage */ 1744 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); 1745 1746 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) 1747 value &= ~BIT(pad->voltage); 1748 else 1749 value |= BIT(pad->voltage); 1750 1751 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE); 1752 } 1753 1754 mutex_unlock(&pmc->powergates_lock); 1755 1756 usleep_range(100, 250); 1757 1758 return 0; 1759 } 1760 1761 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id) 1762 { 1763 const struct tegra_io_pad_soc *pad; 1764 u32 value; 1765 1766 pad = tegra_io_pad_find(pmc, id); 1767 if (!pad) 1768 return -ENOENT; 1769 1770 if (pad->voltage == UINT_MAX) 1771 return -ENOTSUPP; 1772 1773 if (pmc->soc->has_impl_33v_pwr) 1774 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); 1775 else 1776 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); 1777 1778 if ((value & BIT(pad->voltage)) == 0) 1779 return TEGRA_IO_PAD_VOLTAGE_1V8; 1780 1781 return TEGRA_IO_PAD_VOLTAGE_3V3; 1782 } 1783 1784 #ifdef CONFIG_PM_SLEEP 1785 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) 1786 { 1787 return pmc->suspend_mode; 1788 } 1789 1790 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) 1791 { 1792 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE) 1793 return; 1794 1795 pmc->suspend_mode = mode; 1796 } 1797 1798 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) 1799 { 1800 unsigned long long rate = 0; 1801 u64 ticks; 1802 u32 value; 1803 1804 switch (mode) { 1805 case TEGRA_SUSPEND_LP1: 1806 rate = 32768; 1807 break; 1808 1809 case TEGRA_SUSPEND_LP2: 1810 rate = pmc->rate; 1811 break; 1812 1813 default: 1814 break; 1815 } 1816 1817 if (WARN_ON_ONCE(rate == 0)) 1818 rate = 100000000; 1819 1820 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; 1821 do_div(ticks, USEC_PER_SEC); 1822 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER); 1823 1824 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; 1825 do_div(ticks, USEC_PER_SEC); 1826 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER); 1827 1828 value = tegra_pmc_readl(pmc, PMC_CNTRL); 1829 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; 1830 value |= PMC_CNTRL_CPU_PWRREQ_OE; 1831 tegra_pmc_writel(pmc, value, PMC_CNTRL); 1832 } 1833 #endif 1834 1835 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) 1836 { 1837 u32 value, values[2]; 1838 1839 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { 1840 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1841 } else { 1842 switch (value) { 1843 case 0: 1844 pmc->suspend_mode = TEGRA_SUSPEND_LP0; 1845 break; 1846 1847 case 1: 1848 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1849 break; 1850 1851 case 2: 1852 pmc->suspend_mode = TEGRA_SUSPEND_LP2; 1853 break; 1854 1855 default: 1856 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1857 break; 1858 } 1859 } 1860 1861 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); 1862 1863 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) 1864 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1865 1866 pmc->cpu_good_time = value; 1867 1868 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) 1869 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1870 1871 pmc->cpu_off_time = value; 1872 1873 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", 1874 values, ARRAY_SIZE(values))) 1875 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1876 1877 pmc->core_osc_time = values[0]; 1878 pmc->core_pmu_time = values[1]; 1879 1880 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) 1881 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1882 1883 pmc->core_off_time = value; 1884 1885 pmc->corereq_high = of_property_read_bool(np, 1886 "nvidia,core-power-req-active-high"); 1887 1888 pmc->sysclkreq_high = of_property_read_bool(np, 1889 "nvidia,sys-clock-req-active-high"); 1890 1891 pmc->combined_req = of_property_read_bool(np, 1892 "nvidia,combined-power-req"); 1893 1894 pmc->cpu_pwr_good_en = of_property_read_bool(np, 1895 "nvidia,cpu-pwr-good-en"); 1896 1897 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, 1898 ARRAY_SIZE(values))) 1899 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) 1900 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1901 1902 pmc->lp0_vec_phys = values[0]; 1903 pmc->lp0_vec_size = values[1]; 1904 1905 return 0; 1906 } 1907 1908 static int tegra_pmc_init(struct tegra_pmc *pmc) 1909 { 1910 if (pmc->soc->max_wake_events > 0) { 1911 pmc->wake_type_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); 1912 if (!pmc->wake_type_level_map) 1913 return -ENOMEM; 1914 1915 pmc->wake_type_dual_edge_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); 1916 if (!pmc->wake_type_dual_edge_map) 1917 return -ENOMEM; 1918 1919 pmc->wake_sw_status_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); 1920 if (!pmc->wake_sw_status_map) 1921 return -ENOMEM; 1922 1923 pmc->wake_cntrl_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); 1924 if (!pmc->wake_cntrl_level_map) 1925 return -ENOMEM; 1926 } 1927 1928 if (pmc->soc->init) 1929 pmc->soc->init(pmc); 1930 1931 return 0; 1932 } 1933 1934 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) 1935 { 1936 static const char disabled[] = "emergency thermal reset disabled"; 1937 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux; 1938 struct device *dev = pmc->dev; 1939 struct device_node *np; 1940 u32 value, checksum; 1941 1942 if (!pmc->soc->has_tsense_reset) 1943 return; 1944 1945 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip"); 1946 if (!np) { 1947 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); 1948 return; 1949 } 1950 1951 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { 1952 dev_err(dev, "I2C controller ID missing, %s.\n", disabled); 1953 goto out; 1954 } 1955 1956 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { 1957 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); 1958 goto out; 1959 } 1960 1961 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { 1962 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); 1963 goto out; 1964 } 1965 1966 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { 1967 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); 1968 goto out; 1969 } 1970 1971 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) 1972 pinmux = 0; 1973 1974 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); 1975 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE; 1976 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); 1977 1978 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) | 1979 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT); 1980 tegra_pmc_writel(pmc, value, PMC_SCRATCH54); 1981 1982 value = PMC_SCRATCH55_RESET_TEGRA; 1983 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT; 1984 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT; 1985 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT; 1986 1987 /* 1988 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will 1989 * contain the checksum and are currently zero, so they are not added. 1990 */ 1991 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff) 1992 + ((value >> 24) & 0xff); 1993 checksum &= 0xff; 1994 checksum = 0x100 - checksum; 1995 1996 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT; 1997 1998 tegra_pmc_writel(pmc, value, PMC_SCRATCH55); 1999 2000 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); 2001 value |= PMC_SENSOR_CTRL_ENABLE_RST; 2002 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); 2003 2004 dev_info(pmc->dev, "emergency thermal reset enabled\n"); 2005 2006 out: 2007 of_node_put(np); 2008 } 2009 2010 static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev) 2011 { 2012 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2013 2014 return pmc->soc->num_io_pads; 2015 } 2016 2017 static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl, 2018 unsigned int group) 2019 { 2020 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl); 2021 2022 return pmc->soc->io_pads[group].name; 2023 } 2024 2025 static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev, 2026 unsigned int group, 2027 const unsigned int **pins, 2028 unsigned int *num_pins) 2029 { 2030 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2031 2032 *pins = &pmc->soc->io_pads[group].id; 2033 *num_pins = 1; 2034 2035 return 0; 2036 } 2037 2038 static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = { 2039 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count, 2040 .get_group_name = tegra_io_pad_pinctrl_get_group_name, 2041 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins, 2042 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 2043 .dt_free_map = pinconf_generic_dt_free_map, 2044 }; 2045 2046 static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev, 2047 unsigned int pin, unsigned long *config) 2048 { 2049 enum pin_config_param param = pinconf_to_config_param(*config); 2050 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2051 const struct tegra_io_pad_soc *pad; 2052 int ret; 2053 u32 arg; 2054 2055 pad = tegra_io_pad_find(pmc, pin); 2056 if (!pad) 2057 return -EINVAL; 2058 2059 switch (param) { 2060 case PIN_CONFIG_POWER_SOURCE: 2061 ret = tegra_io_pad_get_voltage(pmc, pad->id); 2062 if (ret < 0) 2063 return ret; 2064 2065 arg = ret; 2066 break; 2067 2068 case PIN_CONFIG_MODE_LOW_POWER: 2069 ret = tegra_io_pad_is_powered(pmc, pad->id); 2070 if (ret < 0) 2071 return ret; 2072 2073 arg = !ret; 2074 break; 2075 2076 default: 2077 return -EINVAL; 2078 } 2079 2080 *config = pinconf_to_config_packed(param, arg); 2081 2082 return 0; 2083 } 2084 2085 static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev, 2086 unsigned int pin, unsigned long *configs, 2087 unsigned int num_configs) 2088 { 2089 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2090 const struct tegra_io_pad_soc *pad; 2091 enum pin_config_param param; 2092 unsigned int i; 2093 int err; 2094 u32 arg; 2095 2096 pad = tegra_io_pad_find(pmc, pin); 2097 if (!pad) 2098 return -EINVAL; 2099 2100 for (i = 0; i < num_configs; ++i) { 2101 param = pinconf_to_config_param(configs[i]); 2102 arg = pinconf_to_config_argument(configs[i]); 2103 2104 switch (param) { 2105 case PIN_CONFIG_MODE_LOW_POWER: 2106 if (arg) 2107 err = tegra_io_pad_power_disable(pad->id); 2108 else 2109 err = tegra_io_pad_power_enable(pad->id); 2110 if (err) 2111 return err; 2112 break; 2113 case PIN_CONFIG_POWER_SOURCE: 2114 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 && 2115 arg != TEGRA_IO_PAD_VOLTAGE_3V3) 2116 return -EINVAL; 2117 err = tegra_io_pad_set_voltage(pmc, pad->id, arg); 2118 if (err) 2119 return err; 2120 break; 2121 default: 2122 return -EINVAL; 2123 } 2124 } 2125 2126 return 0; 2127 } 2128 2129 static const struct pinconf_ops tegra_io_pad_pinconf_ops = { 2130 .pin_config_get = tegra_io_pad_pinconf_get, 2131 .pin_config_set = tegra_io_pad_pinconf_set, 2132 .is_generic = true, 2133 }; 2134 2135 static struct pinctrl_desc tegra_pmc_pctl_desc = { 2136 .pctlops = &tegra_io_pad_pinctrl_ops, 2137 .confops = &tegra_io_pad_pinconf_ops, 2138 }; 2139 2140 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc) 2141 { 2142 int err; 2143 2144 if (!pmc->soc->num_pin_descs) 2145 return 0; 2146 2147 tegra_pmc_pctl_desc.name = dev_name(pmc->dev); 2148 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs; 2149 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs; 2150 2151 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc, 2152 pmc); 2153 if (IS_ERR(pmc->pctl_dev)) { 2154 err = PTR_ERR(pmc->pctl_dev); 2155 dev_err(pmc->dev, "failed to register pin controller: %d\n", 2156 err); 2157 return err; 2158 } 2159 2160 return 0; 2161 } 2162 2163 static ssize_t reset_reason_show(struct device *dev, 2164 struct device_attribute *attr, char *buf) 2165 { 2166 u32 value; 2167 2168 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); 2169 value &= pmc->soc->regs->rst_source_mask; 2170 value >>= pmc->soc->regs->rst_source_shift; 2171 2172 if (WARN_ON(value >= pmc->soc->num_reset_sources)) 2173 return sprintf(buf, "%s\n", "UNKNOWN"); 2174 2175 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]); 2176 } 2177 2178 static DEVICE_ATTR_RO(reset_reason); 2179 2180 static ssize_t reset_level_show(struct device *dev, 2181 struct device_attribute *attr, char *buf) 2182 { 2183 u32 value; 2184 2185 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); 2186 value &= pmc->soc->regs->rst_level_mask; 2187 value >>= pmc->soc->regs->rst_level_shift; 2188 2189 if (WARN_ON(value >= pmc->soc->num_reset_levels)) 2190 return sprintf(buf, "%s\n", "UNKNOWN"); 2191 2192 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]); 2193 } 2194 2195 static DEVICE_ATTR_RO(reset_level); 2196 2197 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc) 2198 { 2199 struct device *dev = pmc->dev; 2200 int err = 0; 2201 2202 if (pmc->soc->reset_sources) { 2203 err = device_create_file(dev, &dev_attr_reset_reason); 2204 if (err < 0) 2205 dev_warn(dev, 2206 "failed to create attr \"reset_reason\": %d\n", 2207 err); 2208 } 2209 2210 if (pmc->soc->reset_levels) { 2211 err = device_create_file(dev, &dev_attr_reset_level); 2212 if (err < 0) 2213 dev_warn(dev, 2214 "failed to create attr \"reset_level\": %d\n", 2215 err); 2216 } 2217 } 2218 2219 static int tegra_pmc_irq_translate(struct irq_domain *domain, 2220 struct irq_fwspec *fwspec, 2221 unsigned long *hwirq, 2222 unsigned int *type) 2223 { 2224 if (WARN_ON(fwspec->param_count < 2)) 2225 return -EINVAL; 2226 2227 *hwirq = fwspec->param[0]; 2228 *type = fwspec->param[1]; 2229 2230 return 0; 2231 } 2232 2233 static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq, 2234 unsigned int num_irqs, void *data) 2235 { 2236 struct tegra_pmc *pmc = domain->host_data; 2237 const struct tegra_pmc_soc *soc = pmc->soc; 2238 struct irq_fwspec *fwspec = data; 2239 unsigned int i; 2240 int err = 0; 2241 2242 if (WARN_ON(num_irqs > 1)) 2243 return -EINVAL; 2244 2245 for (i = 0; i < soc->num_wake_events; i++) { 2246 const struct tegra_wake_event *event = &soc->wake_events[i]; 2247 2248 /* IRQ and simple wake events */ 2249 if (fwspec->param_count == 2) { 2250 struct irq_fwspec spec; 2251 2252 if (event->id != fwspec->param[0]) 2253 continue; 2254 2255 err = irq_domain_set_hwirq_and_chip(domain, virq, 2256 event->id, 2257 &pmc->irq, pmc); 2258 if (err < 0) 2259 break; 2260 2261 /* simple hierarchies stop at the PMC level */ 2262 if (event->irq == 0) { 2263 err = irq_domain_disconnect_hierarchy(domain->parent, virq); 2264 break; 2265 } 2266 2267 spec.fwnode = &pmc->dev->of_node->fwnode; 2268 spec.param_count = 3; 2269 spec.param[0] = GIC_SPI; 2270 spec.param[1] = event->irq; 2271 spec.param[2] = fwspec->param[1]; 2272 2273 err = irq_domain_alloc_irqs_parent(domain, virq, 2274 num_irqs, &spec); 2275 2276 break; 2277 } 2278 2279 /* GPIO wake events */ 2280 if (fwspec->param_count == 3) { 2281 if (event->gpio.instance != fwspec->param[0] || 2282 event->gpio.pin != fwspec->param[1]) 2283 continue; 2284 2285 err = irq_domain_set_hwirq_and_chip(domain, virq, 2286 event->id, 2287 &pmc->irq, pmc); 2288 2289 /* GPIO hierarchies stop at the PMC level */ 2290 if (!err && domain->parent) 2291 err = irq_domain_disconnect_hierarchy(domain->parent, 2292 virq); 2293 break; 2294 } 2295 } 2296 2297 /* If there is no wake-up event, there is no PMC mapping */ 2298 if (i == soc->num_wake_events) 2299 err = irq_domain_disconnect_hierarchy(domain, virq); 2300 2301 return err; 2302 } 2303 2304 static const struct irq_domain_ops tegra_pmc_irq_domain_ops = { 2305 .translate = tegra_pmc_irq_translate, 2306 .alloc = tegra_pmc_irq_alloc, 2307 }; 2308 2309 static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on) 2310 { 2311 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2312 unsigned int offset, bit; 2313 u32 value; 2314 2315 offset = data->hwirq / 32; 2316 bit = data->hwirq % 32; 2317 2318 /* clear wake status */ 2319 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS); 2320 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS); 2321 2322 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS); 2323 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS); 2324 2325 /* enable PMC wake */ 2326 if (data->hwirq >= 32) 2327 offset = PMC_WAKE2_MASK; 2328 else 2329 offset = PMC_WAKE_MASK; 2330 2331 value = tegra_pmc_readl(pmc, offset); 2332 2333 if (on) 2334 value |= BIT(bit); 2335 else 2336 value &= ~BIT(bit); 2337 2338 tegra_pmc_writel(pmc, value, offset); 2339 2340 return 0; 2341 } 2342 2343 static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type) 2344 { 2345 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2346 unsigned int offset, bit; 2347 u32 value; 2348 2349 offset = data->hwirq / 32; 2350 bit = data->hwirq % 32; 2351 2352 if (data->hwirq >= 32) 2353 offset = PMC_WAKE2_LEVEL; 2354 else 2355 offset = PMC_WAKE_LEVEL; 2356 2357 value = tegra_pmc_readl(pmc, offset); 2358 2359 switch (type) { 2360 case IRQ_TYPE_EDGE_RISING: 2361 case IRQ_TYPE_LEVEL_HIGH: 2362 value |= BIT(bit); 2363 break; 2364 2365 case IRQ_TYPE_EDGE_FALLING: 2366 case IRQ_TYPE_LEVEL_LOW: 2367 value &= ~BIT(bit); 2368 break; 2369 2370 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: 2371 value ^= BIT(bit); 2372 break; 2373 2374 default: 2375 return -EINVAL; 2376 } 2377 2378 tegra_pmc_writel(pmc, value, offset); 2379 2380 return 0; 2381 } 2382 2383 static void tegra186_pmc_set_wake_filters(struct tegra_pmc *pmc) 2384 { 2385 u32 value; 2386 2387 /* SW Wake (wake83) needs SR_CAPTURE filter to be enabled */ 2388 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID)); 2389 value |= WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN; 2390 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID)); 2391 dev_dbg(pmc->dev, "WAKE_AOWAKE_CNTRL_83 = 0x%x\n", value); 2392 } 2393 2394 static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) 2395 { 2396 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2397 unsigned int offset, bit; 2398 u32 value; 2399 2400 offset = data->hwirq / 32; 2401 bit = data->hwirq % 32; 2402 2403 /* clear wake status */ 2404 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq)); 2405 2406 /* route wake to tier 2 */ 2407 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); 2408 2409 if (!on) 2410 value &= ~(1 << bit); 2411 else 2412 value |= 1 << bit; 2413 2414 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); 2415 2416 /* enable wakeup event */ 2417 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq)); 2418 2419 return 0; 2420 } 2421 2422 static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type) 2423 { 2424 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2425 u32 value; 2426 2427 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); 2428 2429 switch (type) { 2430 case IRQ_TYPE_EDGE_RISING: 2431 case IRQ_TYPE_LEVEL_HIGH: 2432 value |= WAKE_AOWAKE_CNTRL_LEVEL; 2433 set_bit(data->hwirq, pmc->wake_type_level_map); 2434 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map); 2435 break; 2436 2437 case IRQ_TYPE_EDGE_FALLING: 2438 case IRQ_TYPE_LEVEL_LOW: 2439 value &= ~WAKE_AOWAKE_CNTRL_LEVEL; 2440 clear_bit(data->hwirq, pmc->wake_type_level_map); 2441 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map); 2442 break; 2443 2444 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: 2445 value ^= WAKE_AOWAKE_CNTRL_LEVEL; 2446 clear_bit(data->hwirq, pmc->wake_type_level_map); 2447 set_bit(data->hwirq, pmc->wake_type_dual_edge_map); 2448 break; 2449 2450 default: 2451 return -EINVAL; 2452 } 2453 2454 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); 2455 2456 return 0; 2457 } 2458 2459 static void tegra_irq_mask_parent(struct irq_data *data) 2460 { 2461 if (data->parent_data) 2462 irq_chip_mask_parent(data); 2463 } 2464 2465 static void tegra_irq_unmask_parent(struct irq_data *data) 2466 { 2467 if (data->parent_data) 2468 irq_chip_unmask_parent(data); 2469 } 2470 2471 static void tegra_irq_eoi_parent(struct irq_data *data) 2472 { 2473 if (data->parent_data) 2474 irq_chip_eoi_parent(data); 2475 } 2476 2477 static int tegra_irq_set_affinity_parent(struct irq_data *data, 2478 const struct cpumask *dest, 2479 bool force) 2480 { 2481 if (data->parent_data) 2482 return irq_chip_set_affinity_parent(data, dest, force); 2483 2484 return -EINVAL; 2485 } 2486 2487 static int tegra_pmc_irq_init(struct tegra_pmc *pmc) 2488 { 2489 struct irq_domain *parent = NULL; 2490 struct device_node *np; 2491 2492 np = of_irq_find_parent(pmc->dev->of_node); 2493 if (np) { 2494 parent = irq_find_host(np); 2495 of_node_put(np); 2496 } 2497 2498 if (!parent) 2499 return 0; 2500 2501 pmc->irq.name = dev_name(pmc->dev); 2502 pmc->irq.irq_mask = tegra_irq_mask_parent; 2503 pmc->irq.irq_unmask = tegra_irq_unmask_parent; 2504 pmc->irq.irq_eoi = tegra_irq_eoi_parent; 2505 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent; 2506 pmc->irq.irq_set_type = pmc->soc->irq_set_type; 2507 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake; 2508 2509 pmc->domain = irq_domain_create_hierarchy(parent, 0, 96, dev_fwnode(pmc->dev), 2510 &tegra_pmc_irq_domain_ops, pmc); 2511 if (!pmc->domain) { 2512 dev_err(pmc->dev, "failed to allocate domain\n"); 2513 return -ENOMEM; 2514 } 2515 2516 return 0; 2517 } 2518 2519 static int tegra_pmc_clk_notify_cb(struct notifier_block *nb, 2520 unsigned long action, void *ptr) 2521 { 2522 struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb); 2523 struct clk_notifier_data *data = ptr; 2524 2525 switch (action) { 2526 case PRE_RATE_CHANGE: 2527 mutex_lock(&pmc->powergates_lock); 2528 break; 2529 2530 case POST_RATE_CHANGE: 2531 pmc->rate = data->new_rate; 2532 fallthrough; 2533 2534 case ABORT_RATE_CHANGE: 2535 mutex_unlock(&pmc->powergates_lock); 2536 break; 2537 2538 default: 2539 WARN_ON_ONCE(1); 2540 return notifier_from_errno(-EINVAL); 2541 } 2542 2543 return NOTIFY_OK; 2544 } 2545 2546 static void pmc_clk_fence_udelay(u32 offset) 2547 { 2548 tegra_pmc_readl(pmc, offset); 2549 /* pmc clk propagation delay 2 us */ 2550 udelay(2); 2551 } 2552 2553 static u8 pmc_clk_mux_get_parent(struct clk_hw *hw) 2554 { 2555 struct pmc_clk *clk = to_pmc_clk(hw); 2556 u32 val; 2557 2558 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift; 2559 val &= PMC_CLK_OUT_MUX_MASK; 2560 2561 return val; 2562 } 2563 2564 static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index) 2565 { 2566 struct pmc_clk *clk = to_pmc_clk(hw); 2567 u32 val; 2568 2569 val = tegra_pmc_readl(pmc, clk->offs); 2570 val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift); 2571 val |= index << clk->mux_shift; 2572 tegra_pmc_writel(pmc, val, clk->offs); 2573 pmc_clk_fence_udelay(clk->offs); 2574 2575 return 0; 2576 } 2577 2578 static int pmc_clk_is_enabled(struct clk_hw *hw) 2579 { 2580 struct pmc_clk *clk = to_pmc_clk(hw); 2581 u32 val; 2582 2583 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift); 2584 2585 return val ? 1 : 0; 2586 } 2587 2588 static void pmc_clk_set_state(unsigned long offs, u32 shift, int state) 2589 { 2590 u32 val; 2591 2592 val = tegra_pmc_readl(pmc, offs); 2593 val = state ? (val | BIT(shift)) : (val & ~BIT(shift)); 2594 tegra_pmc_writel(pmc, val, offs); 2595 pmc_clk_fence_udelay(offs); 2596 } 2597 2598 static int pmc_clk_enable(struct clk_hw *hw) 2599 { 2600 struct pmc_clk *clk = to_pmc_clk(hw); 2601 2602 pmc_clk_set_state(clk->offs, clk->force_en_shift, 1); 2603 2604 return 0; 2605 } 2606 2607 static void pmc_clk_disable(struct clk_hw *hw) 2608 { 2609 struct pmc_clk *clk = to_pmc_clk(hw); 2610 2611 pmc_clk_set_state(clk->offs, clk->force_en_shift, 0); 2612 } 2613 2614 static const struct clk_ops pmc_clk_ops = { 2615 .get_parent = pmc_clk_mux_get_parent, 2616 .set_parent = pmc_clk_mux_set_parent, 2617 .determine_rate = __clk_mux_determine_rate, 2618 .is_enabled = pmc_clk_is_enabled, 2619 .enable = pmc_clk_enable, 2620 .disable = pmc_clk_disable, 2621 }; 2622 2623 static struct clk * 2624 tegra_pmc_clk_out_register(struct tegra_pmc *pmc, 2625 const struct pmc_clk_init_data *data, 2626 unsigned long offset) 2627 { 2628 struct clk_init_data init; 2629 struct pmc_clk *pmc_clk; 2630 2631 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL); 2632 if (!pmc_clk) 2633 return ERR_PTR(-ENOMEM); 2634 2635 init.name = data->name; 2636 init.ops = &pmc_clk_ops; 2637 init.parent_names = data->parents; 2638 init.num_parents = data->num_parents; 2639 init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT | 2640 CLK_SET_PARENT_GATE; 2641 2642 pmc_clk->hw.init = &init; 2643 pmc_clk->offs = offset; 2644 pmc_clk->mux_shift = data->mux_shift; 2645 pmc_clk->force_en_shift = data->force_en_shift; 2646 2647 return clk_register(NULL, &pmc_clk->hw); 2648 } 2649 2650 static int pmc_clk_gate_is_enabled(struct clk_hw *hw) 2651 { 2652 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2653 2654 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0; 2655 } 2656 2657 static int pmc_clk_gate_enable(struct clk_hw *hw) 2658 { 2659 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2660 2661 pmc_clk_set_state(gate->offs, gate->shift, 1); 2662 2663 return 0; 2664 } 2665 2666 static void pmc_clk_gate_disable(struct clk_hw *hw) 2667 { 2668 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2669 2670 pmc_clk_set_state(gate->offs, gate->shift, 0); 2671 } 2672 2673 static const struct clk_ops pmc_clk_gate_ops = { 2674 .is_enabled = pmc_clk_gate_is_enabled, 2675 .enable = pmc_clk_gate_enable, 2676 .disable = pmc_clk_gate_disable, 2677 }; 2678 2679 static struct clk * 2680 tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name, 2681 const char *parent_name, unsigned long offset, 2682 u32 shift) 2683 { 2684 struct clk_init_data init; 2685 struct pmc_clk_gate *gate; 2686 2687 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL); 2688 if (!gate) 2689 return ERR_PTR(-ENOMEM); 2690 2691 init.name = name; 2692 init.ops = &pmc_clk_gate_ops; 2693 init.parent_names = &parent_name; 2694 init.num_parents = 1; 2695 init.flags = 0; 2696 2697 gate->hw.init = &init; 2698 gate->offs = offset; 2699 gate->shift = shift; 2700 2701 return clk_register(NULL, &gate->hw); 2702 } 2703 2704 static void tegra_pmc_clock_register(struct tegra_pmc *pmc, 2705 struct device_node *np) 2706 { 2707 struct clk *clk; 2708 struct clk_onecell_data *clk_data; 2709 unsigned int num_clks; 2710 int i, err; 2711 2712 num_clks = pmc->soc->num_pmc_clks; 2713 if (pmc->soc->has_blink_output) 2714 num_clks += 1; 2715 2716 if (!num_clks) 2717 return; 2718 2719 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL); 2720 if (!clk_data) 2721 return; 2722 2723 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX, 2724 sizeof(*clk_data->clks), GFP_KERNEL); 2725 if (!clk_data->clks) 2726 return; 2727 2728 clk_data->clk_num = TEGRA_PMC_CLK_MAX; 2729 2730 for (i = 0; i < TEGRA_PMC_CLK_MAX; i++) 2731 clk_data->clks[i] = ERR_PTR(-ENOENT); 2732 2733 for (i = 0; i < pmc->soc->num_pmc_clks; i++) { 2734 const struct pmc_clk_init_data *data; 2735 2736 data = pmc->soc->pmc_clks_data + i; 2737 2738 clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL); 2739 if (IS_ERR(clk)) { 2740 dev_warn(pmc->dev, "unable to register clock %s: %d\n", 2741 data->name, PTR_ERR_OR_ZERO(clk)); 2742 return; 2743 } 2744 2745 err = clk_register_clkdev(clk, data->name, NULL); 2746 if (err) { 2747 dev_warn(pmc->dev, 2748 "unable to register %s clock lookup: %d\n", 2749 data->name, err); 2750 return; 2751 } 2752 2753 clk_data->clks[data->clk_id] = clk; 2754 } 2755 2756 if (pmc->soc->has_blink_output) { 2757 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER); 2758 clk = tegra_pmc_clk_gate_register(pmc, 2759 "pmc_blink_override", 2760 "clk_32k", 2761 PMC_DPD_PADS_ORIDE, 2762 PMC_DPD_PADS_ORIDE_BLINK); 2763 if (IS_ERR(clk)) { 2764 dev_warn(pmc->dev, 2765 "unable to register pmc_blink_override: %d\n", 2766 PTR_ERR_OR_ZERO(clk)); 2767 return; 2768 } 2769 2770 clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink", 2771 "pmc_blink_override", 2772 PMC_CNTRL, 2773 PMC_CNTRL_BLINK_EN); 2774 if (IS_ERR(clk)) { 2775 dev_warn(pmc->dev, 2776 "unable to register pmc_blink: %d\n", 2777 PTR_ERR_OR_ZERO(clk)); 2778 return; 2779 } 2780 2781 err = clk_register_clkdev(clk, "pmc_blink", NULL); 2782 if (err) { 2783 dev_warn(pmc->dev, 2784 "unable to register pmc_blink lookup: %d\n", 2785 err); 2786 return; 2787 } 2788 2789 clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk; 2790 } 2791 2792 err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data); 2793 if (err) 2794 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n", 2795 err); 2796 } 2797 2798 static const struct regmap_range pmc_usb_sleepwalk_ranges[] = { 2799 regmap_reg_range(PMC_USB_DEBOUNCE_DEL, PMC_USB_AO), 2800 regmap_reg_range(PMC_UTMIP_UHSIC_TRIGGERS, PMC_UTMIP_UHSIC_SAVED_STATE), 2801 regmap_reg_range(PMC_UTMIP_TERM_PAD_CFG, PMC_UTMIP_UHSIC_FAKE), 2802 regmap_reg_range(PMC_UTMIP_UHSIC_LINE_WAKEUP, PMC_UTMIP_UHSIC_LINE_WAKEUP), 2803 regmap_reg_range(PMC_UTMIP_BIAS_MASTER_CNTRL, PMC_UTMIP_MASTER_CONFIG), 2804 regmap_reg_range(PMC_UTMIP_UHSIC2_TRIGGERS, PMC_UTMIP_MASTER2_CONFIG), 2805 regmap_reg_range(PMC_UTMIP_PAD_CFG0, PMC_UTMIP_UHSIC_SLEEP_CFG1), 2806 regmap_reg_range(PMC_UTMIP_SLEEPWALK_P3, PMC_UTMIP_SLEEPWALK_P3), 2807 }; 2808 2809 static const struct regmap_access_table pmc_usb_sleepwalk_table = { 2810 .yes_ranges = pmc_usb_sleepwalk_ranges, 2811 .n_yes_ranges = ARRAY_SIZE(pmc_usb_sleepwalk_ranges), 2812 }; 2813 2814 static int tegra_pmc_regmap_readl(void *context, unsigned int offset, unsigned int *value) 2815 { 2816 struct tegra_pmc *pmc = context; 2817 2818 *value = tegra_pmc_readl(pmc, offset); 2819 return 0; 2820 } 2821 2822 static int tegra_pmc_regmap_writel(void *context, unsigned int offset, unsigned int value) 2823 { 2824 struct tegra_pmc *pmc = context; 2825 2826 tegra_pmc_writel(pmc, value, offset); 2827 return 0; 2828 } 2829 2830 static const struct regmap_config usb_sleepwalk_regmap_config = { 2831 .name = "usb_sleepwalk", 2832 .reg_bits = 32, 2833 .val_bits = 32, 2834 .reg_stride = 4, 2835 .fast_io = true, 2836 .rd_table = &pmc_usb_sleepwalk_table, 2837 .wr_table = &pmc_usb_sleepwalk_table, 2838 .reg_read = tegra_pmc_regmap_readl, 2839 .reg_write = tegra_pmc_regmap_writel, 2840 }; 2841 2842 static int tegra_pmc_regmap_init(struct tegra_pmc *pmc) 2843 { 2844 struct regmap *regmap; 2845 int err; 2846 2847 if (pmc->soc->has_usb_sleepwalk) { 2848 regmap = devm_regmap_init(pmc->dev, NULL, pmc, &usb_sleepwalk_regmap_config); 2849 if (IS_ERR(regmap)) { 2850 err = PTR_ERR(regmap); 2851 dev_err(pmc->dev, "failed to allocate register map (%d)\n", err); 2852 return err; 2853 } 2854 } 2855 2856 return 0; 2857 } 2858 2859 static void tegra_pmc_reset_suspend_mode(void *data) 2860 { 2861 pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY; 2862 } 2863 2864 static int tegra_pmc_probe(struct platform_device *pdev) 2865 { 2866 void __iomem *base; 2867 struct resource *res; 2868 int err; 2869 2870 /* 2871 * Early initialisation should have configured an initial 2872 * register mapping and setup the soc data pointer. If these 2873 * are not valid then something went badly wrong! 2874 */ 2875 if (WARN_ON(!pmc->base || !pmc->soc)) 2876 return -ENODEV; 2877 2878 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); 2879 if (err < 0) 2880 return err; 2881 2882 err = devm_add_action_or_reset(&pdev->dev, tegra_pmc_reset_suspend_mode, 2883 NULL); 2884 if (err) 2885 return err; 2886 2887 /* take over the memory region from the early initialization */ 2888 base = devm_platform_ioremap_resource(pdev, 0); 2889 if (IS_ERR(base)) 2890 return PTR_ERR(base); 2891 2892 if (pmc->soc->has_single_mmio_aperture) { 2893 pmc->wake = base; 2894 pmc->aotag = base; 2895 pmc->scratch = base; 2896 } else { 2897 pmc->wake = devm_platform_ioremap_resource_byname(pdev, "wake"); 2898 if (IS_ERR(pmc->wake)) 2899 return PTR_ERR(pmc->wake); 2900 2901 /* "aotag" is an optional aperture */ 2902 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 2903 "aotag"); 2904 if (res) { 2905 pmc->aotag = devm_ioremap_resource(&pdev->dev, res); 2906 if (IS_ERR(pmc->aotag)) 2907 return PTR_ERR(pmc->aotag); 2908 } else { 2909 pmc->aotag = NULL; 2910 } 2911 2912 /* "scratch" is an optional aperture */ 2913 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 2914 "scratch"); 2915 if (res) { 2916 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); 2917 if (IS_ERR(pmc->scratch)) 2918 return PTR_ERR(pmc->scratch); 2919 } else { 2920 pmc->scratch = NULL; 2921 } 2922 } 2923 2924 pmc->clk = devm_clk_get_optional(&pdev->dev, "pclk"); 2925 if (IS_ERR(pmc->clk)) 2926 return dev_err_probe(&pdev->dev, PTR_ERR(pmc->clk), 2927 "failed to get pclk\n"); 2928 2929 /* 2930 * PMC should be last resort for restarting since it soft-resets 2931 * CPU without resetting everything else. 2932 */ 2933 if (pmc->scratch) { 2934 err = devm_register_reboot_notifier(&pdev->dev, 2935 &tegra_pmc_reboot_notifier); 2936 if (err) { 2937 dev_err(&pdev->dev, 2938 "unable to register reboot notifier, %d\n", 2939 err); 2940 return err; 2941 } 2942 } 2943 2944 err = devm_register_sys_off_handler(&pdev->dev, 2945 SYS_OFF_MODE_RESTART, 2946 SYS_OFF_PRIO_LOW, 2947 tegra_pmc_restart_handler, NULL); 2948 if (err) { 2949 dev_err(&pdev->dev, "failed to register sys-off handler: %d\n", 2950 err); 2951 return err; 2952 } 2953 2954 /* 2955 * PMC should be primary power-off method if it soft-resets CPU, 2956 * asking bootloader to shutdown hardware. 2957 */ 2958 err = devm_register_sys_off_handler(&pdev->dev, 2959 SYS_OFF_MODE_POWER_OFF, 2960 SYS_OFF_PRIO_FIRMWARE, 2961 tegra_pmc_power_off_handler, NULL); 2962 if (err) { 2963 dev_err(&pdev->dev, "failed to register sys-off handler: %d\n", 2964 err); 2965 return err; 2966 } 2967 2968 /* 2969 * PCLK clock rate can't be retrieved using CLK API because it 2970 * causes lockup if CPU enters LP2 idle state from some other 2971 * CLK notifier, hence we're caching the rate's value locally. 2972 */ 2973 if (pmc->clk) { 2974 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb; 2975 err = devm_clk_notifier_register(&pdev->dev, pmc->clk, 2976 &pmc->clk_nb); 2977 if (err) { 2978 dev_err(&pdev->dev, 2979 "failed to register clk notifier\n"); 2980 return err; 2981 } 2982 2983 pmc->rate = clk_get_rate(pmc->clk); 2984 } 2985 2986 pmc->dev = &pdev->dev; 2987 2988 err = tegra_pmc_init(pmc); 2989 if (err < 0) { 2990 dev_err(&pdev->dev, "failed to initialize PMC: %d\n", err); 2991 return err; 2992 } 2993 2994 tegra_pmc_init_tsense_reset(pmc); 2995 2996 tegra_pmc_reset_sysfs_init(pmc); 2997 2998 err = tegra_pmc_pinctrl_init(pmc); 2999 if (err) 3000 goto cleanup_sysfs; 3001 3002 err = tegra_pmc_regmap_init(pmc); 3003 if (err < 0) 3004 goto cleanup_sysfs; 3005 3006 err = tegra_powergate_init(pmc, pdev->dev.of_node); 3007 if (err < 0) 3008 goto cleanup_powergates; 3009 3010 err = tegra_pmc_irq_init(pmc); 3011 if (err < 0) 3012 goto cleanup_powergates; 3013 3014 mutex_lock(&pmc->powergates_lock); 3015 iounmap(pmc->base); 3016 pmc->base = base; 3017 mutex_unlock(&pmc->powergates_lock); 3018 3019 tegra_pmc_clock_register(pmc, pdev->dev.of_node); 3020 platform_set_drvdata(pdev, pmc); 3021 tegra_pm_init_suspend(); 3022 3023 /* Some wakes require specific filter configuration */ 3024 if (pmc->soc->set_wake_filters) 3025 pmc->soc->set_wake_filters(pmc); 3026 3027 debugfs_create_file("powergate", 0444, NULL, NULL, &powergate_fops); 3028 3029 return 0; 3030 3031 cleanup_powergates: 3032 tegra_powergate_remove_all(pdev->dev.of_node); 3033 cleanup_sysfs: 3034 device_remove_file(&pdev->dev, &dev_attr_reset_reason); 3035 device_remove_file(&pdev->dev, &dev_attr_reset_level); 3036 3037 return err; 3038 } 3039 3040 /* 3041 * Ensures that sufficient time is passed for a register write to 3042 * serialize into the 32KHz domain. 3043 */ 3044 static void wke_32kwritel(struct tegra_pmc *pmc, u32 value, unsigned int offset) 3045 { 3046 writel(value, pmc->wake + offset); 3047 udelay(130); 3048 } 3049 3050 static void wke_write_wake_level(struct tegra_pmc *pmc, int wake, int level) 3051 { 3052 unsigned int offset = WAKE_AOWAKE_CNTRL(wake); 3053 u32 value; 3054 3055 value = readl(pmc->wake + offset); 3056 if (level) 3057 value |= WAKE_AOWAKE_CNTRL_LEVEL; 3058 else 3059 value &= ~WAKE_AOWAKE_CNTRL_LEVEL; 3060 3061 writel(value, pmc->wake + offset); 3062 } 3063 3064 static void wke_write_wake_levels(struct tegra_pmc *pmc) 3065 { 3066 unsigned int i; 3067 3068 for (i = 0; i < pmc->soc->max_wake_events; i++) 3069 wke_write_wake_level(pmc, i, test_bit(i, pmc->wake_cntrl_level_map)); 3070 } 3071 3072 static void wke_clear_sw_wake_status(struct tegra_pmc *pmc) 3073 { 3074 wke_32kwritel(pmc, 1, WAKE_AOWAKE_SW_STATUS_W_0); 3075 } 3076 3077 static void wke_read_sw_wake_status(struct tegra_pmc *pmc) 3078 { 3079 unsigned long status; 3080 unsigned int wake, i; 3081 3082 for (i = 0; i < pmc->soc->max_wake_events; i++) 3083 wke_write_wake_level(pmc, i, 0); 3084 3085 wke_clear_sw_wake_status(pmc); 3086 3087 wke_32kwritel(pmc, 1, WAKE_LATCH_SW); 3088 3089 /* 3090 * WAKE_AOWAKE_SW_STATUS is edge triggered, so in order to 3091 * obtain the current status of the input wake signals, change 3092 * the polarity of the wake level from 0->1 while latching to force 3093 * a positive edge if the sampled signal is '1'. 3094 */ 3095 for (i = 0; i < pmc->soc->max_wake_events; i++) 3096 wke_write_wake_level(pmc, i, 1); 3097 3098 /* 3099 * Wait for the update to be synced into the 32kHz domain, 3100 * and let enough time lapse, so that the wake signals have time to 3101 * be sampled. 3102 */ 3103 udelay(300); 3104 3105 wke_32kwritel(pmc, 0, WAKE_LATCH_SW); 3106 3107 bitmap_zero(pmc->wake_sw_status_map, pmc->soc->max_wake_events); 3108 3109 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { 3110 status = readl(pmc->wake + WAKE_AOWAKE_SW_STATUS(i)); 3111 3112 for_each_set_bit(wake, &status, 32) 3113 set_bit(wake + (i * 32), pmc->wake_sw_status_map); 3114 } 3115 } 3116 3117 static void wke_clear_wake_status(struct tegra_pmc *pmc) 3118 { 3119 unsigned long status; 3120 unsigned int i, wake; 3121 u32 mask; 3122 3123 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { 3124 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i)); 3125 status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask; 3126 3127 for_each_set_bit(wake, &status, 32) 3128 wke_32kwritel(pmc, 0x1, WAKE_AOWAKE_STATUS_W((i * 32) + wake)); 3129 } 3130 } 3131 3132 /* translate sc7 wake sources back into IRQs to catch edge triggered wakeups */ 3133 static void tegra186_pmc_process_wake_events(struct tegra_pmc *pmc, unsigned int index, 3134 unsigned long status) 3135 { 3136 unsigned int wake; 3137 3138 dev_dbg(pmc->dev, "Wake[%d:%d] status=%#lx\n", (index * 32) + 31, index * 32, status); 3139 3140 for_each_set_bit(wake, &status, 32) { 3141 irq_hw_number_t hwirq = wake + 32 * index; 3142 struct irq_desc *desc; 3143 unsigned int irq; 3144 3145 irq = irq_find_mapping(pmc->domain, hwirq); 3146 3147 desc = irq_to_desc(irq); 3148 if (!desc || !desc->action || !desc->action->name) { 3149 dev_dbg(pmc->dev, "Resume caused by WAKE%ld, IRQ %d\n", hwirq, irq); 3150 continue; 3151 } 3152 3153 dev_dbg(pmc->dev, "Resume caused by WAKE%ld, %s\n", hwirq, desc->action->name); 3154 generic_handle_irq(irq); 3155 } 3156 } 3157 3158 static void tegra186_pmc_wake_syscore_resume(void *data) 3159 { 3160 u32 status, mask; 3161 unsigned int i; 3162 3163 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { 3164 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i)); 3165 status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask; 3166 3167 tegra186_pmc_process_wake_events(pmc, i, status); 3168 } 3169 } 3170 3171 static int tegra186_pmc_wake_syscore_suspend(void *data) 3172 { 3173 wke_read_sw_wake_status(pmc); 3174 3175 /* flip the wakeup trigger for dual-edge triggered pads 3176 * which are currently asserting as wakeups 3177 */ 3178 bitmap_andnot(pmc->wake_cntrl_level_map, pmc->wake_type_dual_edge_map, 3179 pmc->wake_sw_status_map, pmc->soc->max_wake_events); 3180 bitmap_or(pmc->wake_cntrl_level_map, pmc->wake_cntrl_level_map, 3181 pmc->wake_type_level_map, pmc->soc->max_wake_events); 3182 3183 /* Clear PMC Wake Status registers while going to suspend */ 3184 wke_clear_wake_status(pmc); 3185 wke_write_wake_levels(pmc); 3186 3187 return 0; 3188 } 3189 3190 static const struct syscore_ops tegra186_pmc_wake_syscore_ops = { 3191 .suspend = tegra186_pmc_wake_syscore_suspend, 3192 .resume = tegra186_pmc_wake_syscore_resume, 3193 }; 3194 3195 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 3196 static int tegra_pmc_suspend(struct device *dev) 3197 { 3198 struct tegra_pmc *pmc = dev_get_drvdata(dev); 3199 3200 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41); 3201 3202 return 0; 3203 } 3204 3205 static int tegra_pmc_resume(struct device *dev) 3206 { 3207 struct tegra_pmc *pmc = dev_get_drvdata(dev); 3208 3209 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41); 3210 3211 return 0; 3212 } 3213 3214 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume); 3215 3216 #endif 3217 3218 static const char * const tegra20_powergates[] = { 3219 [TEGRA_POWERGATE_CPU] = "cpu", 3220 [TEGRA_POWERGATE_3D] = "td", 3221 [TEGRA_POWERGATE_VENC] = "venc", 3222 [TEGRA_POWERGATE_VDEC] = "vdec", 3223 [TEGRA_POWERGATE_PCIE] = "pcie", 3224 [TEGRA_POWERGATE_L2] = "l2", 3225 [TEGRA_POWERGATE_MPE] = "mpe", 3226 }; 3227 3228 static const struct tegra_pmc_regs tegra20_pmc_regs = { 3229 .scratch0 = 0x50, 3230 .rst_status = 0x1b4, 3231 .rst_source_shift = 0x0, 3232 .rst_source_mask = 0x7, 3233 .rst_level_shift = 0x0, 3234 .rst_level_mask = 0x0, 3235 }; 3236 3237 static void tegra20_pmc_init(struct tegra_pmc *pmc) 3238 { 3239 u32 value, osc, pmu, off; 3240 3241 /* Always enable CPU power request */ 3242 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3243 value |= PMC_CNTRL_CPU_PWRREQ_OE; 3244 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3245 3246 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3247 3248 if (pmc->sysclkreq_high) 3249 value &= ~PMC_CNTRL_SYSCLK_POLARITY; 3250 else 3251 value |= PMC_CNTRL_SYSCLK_POLARITY; 3252 3253 if (pmc->corereq_high) 3254 value &= ~PMC_CNTRL_PWRREQ_POLARITY; 3255 else 3256 value |= PMC_CNTRL_PWRREQ_POLARITY; 3257 3258 /* configure the output polarity while the request is tristated */ 3259 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3260 3261 /* now enable the request */ 3262 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3263 value |= PMC_CNTRL_SYSCLK_OE; 3264 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3265 3266 /* program core timings which are applicable only for suspend state */ 3267 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) { 3268 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000); 3269 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000); 3270 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000); 3271 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff), 3272 PMC_COREPWRGOOD_TIMER); 3273 tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER); 3274 } 3275 } 3276 3277 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 3278 struct device_node *np, 3279 bool invert) 3280 { 3281 u32 value; 3282 3283 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3284 3285 if (invert) 3286 value |= PMC_CNTRL_INTR_POLARITY; 3287 else 3288 value &= ~PMC_CNTRL_INTR_POLARITY; 3289 3290 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3291 } 3292 3293 static const struct tegra_pmc_soc tegra20_pmc_soc = { 3294 .supports_core_domain = true, 3295 .num_powergates = ARRAY_SIZE(tegra20_powergates), 3296 .powergates = tegra20_powergates, 3297 .num_cpu_powergates = 0, 3298 .cpu_powergates = NULL, 3299 .has_tsense_reset = false, 3300 .has_gpu_clamps = false, 3301 .needs_mbist_war = false, 3302 .has_impl_33v_pwr = false, 3303 .maybe_tz_only = false, 3304 .num_io_pads = 0, 3305 .io_pads = NULL, 3306 .num_pin_descs = 0, 3307 .pin_descs = NULL, 3308 .regs = &tegra20_pmc_regs, 3309 .init = tegra20_pmc_init, 3310 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3311 .powergate_set = tegra20_powergate_set, 3312 .reset_sources = NULL, 3313 .num_reset_sources = 0, 3314 .reset_levels = NULL, 3315 .num_reset_levels = 0, 3316 .pmc_clks_data = NULL, 3317 .num_pmc_clks = 0, 3318 .has_blink_output = true, 3319 .has_usb_sleepwalk = true, 3320 .has_single_mmio_aperture = true, 3321 }; 3322 3323 static const char * const tegra30_powergates[] = { 3324 [TEGRA_POWERGATE_CPU] = "cpu0", 3325 [TEGRA_POWERGATE_3D] = "td", 3326 [TEGRA_POWERGATE_VENC] = "venc", 3327 [TEGRA_POWERGATE_VDEC] = "vdec", 3328 [TEGRA_POWERGATE_PCIE] = "pcie", 3329 [TEGRA_POWERGATE_L2] = "l2", 3330 [TEGRA_POWERGATE_MPE] = "mpe", 3331 [TEGRA_POWERGATE_HEG] = "heg", 3332 [TEGRA_POWERGATE_SATA] = "sata", 3333 [TEGRA_POWERGATE_CPU1] = "cpu1", 3334 [TEGRA_POWERGATE_CPU2] = "cpu2", 3335 [TEGRA_POWERGATE_CPU3] = "cpu3", 3336 [TEGRA_POWERGATE_CELP] = "celp", 3337 [TEGRA_POWERGATE_3D1] = "td2", 3338 }; 3339 3340 static const u8 tegra30_cpu_powergates[] = { 3341 TEGRA_POWERGATE_CPU, 3342 TEGRA_POWERGATE_CPU1, 3343 TEGRA_POWERGATE_CPU2, 3344 TEGRA_POWERGATE_CPU3, 3345 }; 3346 3347 static const char * const tegra30_reset_sources[] = { 3348 "POWER_ON_RESET", 3349 "WATCHDOG", 3350 "SENSOR", 3351 "SW_MAIN", 3352 "LP0" 3353 }; 3354 3355 static const struct tegra_pmc_soc tegra30_pmc_soc = { 3356 .supports_core_domain = true, 3357 .num_powergates = ARRAY_SIZE(tegra30_powergates), 3358 .powergates = tegra30_powergates, 3359 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), 3360 .cpu_powergates = tegra30_cpu_powergates, 3361 .has_tsense_reset = true, 3362 .has_gpu_clamps = false, 3363 .needs_mbist_war = false, 3364 .has_impl_33v_pwr = false, 3365 .maybe_tz_only = false, 3366 .num_io_pads = 0, 3367 .io_pads = NULL, 3368 .num_pin_descs = 0, 3369 .pin_descs = NULL, 3370 .regs = &tegra20_pmc_regs, 3371 .init = tegra20_pmc_init, 3372 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3373 .powergate_set = tegra20_powergate_set, 3374 .reset_sources = tegra30_reset_sources, 3375 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 3376 .reset_levels = NULL, 3377 .num_reset_levels = 0, 3378 .pmc_clks_data = tegra_pmc_clks_data, 3379 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3380 .has_blink_output = true, 3381 .has_usb_sleepwalk = true, 3382 .has_single_mmio_aperture = true, 3383 }; 3384 3385 static const char * const tegra114_powergates[] = { 3386 [TEGRA_POWERGATE_CPU] = "crail", 3387 [TEGRA_POWERGATE_3D] = "td", 3388 [TEGRA_POWERGATE_VENC] = "venc", 3389 [TEGRA_POWERGATE_VDEC] = "vdec", 3390 [TEGRA_POWERGATE_MPE] = "mpe", 3391 [TEGRA_POWERGATE_HEG] = "heg", 3392 [TEGRA_POWERGATE_CPU1] = "cpu1", 3393 [TEGRA_POWERGATE_CPU2] = "cpu2", 3394 [TEGRA_POWERGATE_CPU3] = "cpu3", 3395 [TEGRA_POWERGATE_CELP] = "celp", 3396 [TEGRA_POWERGATE_CPU0] = "cpu0", 3397 [TEGRA_POWERGATE_C0NC] = "c0nc", 3398 [TEGRA_POWERGATE_C1NC] = "c1nc", 3399 [TEGRA_POWERGATE_DIS] = "dis", 3400 [TEGRA_POWERGATE_DISB] = "disb", 3401 [TEGRA_POWERGATE_XUSBA] = "xusba", 3402 [TEGRA_POWERGATE_XUSBB] = "xusbb", 3403 [TEGRA_POWERGATE_XUSBC] = "xusbc", 3404 }; 3405 3406 static const u8 tegra114_cpu_powergates[] = { 3407 TEGRA_POWERGATE_CPU0, 3408 TEGRA_POWERGATE_CPU1, 3409 TEGRA_POWERGATE_CPU2, 3410 TEGRA_POWERGATE_CPU3, 3411 }; 3412 3413 static const struct tegra_pmc_soc tegra114_pmc_soc = { 3414 .supports_core_domain = false, 3415 .num_powergates = ARRAY_SIZE(tegra114_powergates), 3416 .powergates = tegra114_powergates, 3417 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), 3418 .cpu_powergates = tegra114_cpu_powergates, 3419 .has_tsense_reset = true, 3420 .has_gpu_clamps = false, 3421 .needs_mbist_war = false, 3422 .has_impl_33v_pwr = false, 3423 .maybe_tz_only = false, 3424 .num_io_pads = 0, 3425 .io_pads = NULL, 3426 .num_pin_descs = 0, 3427 .pin_descs = NULL, 3428 .regs = &tegra20_pmc_regs, 3429 .init = tegra20_pmc_init, 3430 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3431 .powergate_set = tegra114_powergate_set, 3432 .reset_sources = tegra30_reset_sources, 3433 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 3434 .reset_levels = NULL, 3435 .num_reset_levels = 0, 3436 .pmc_clks_data = tegra_pmc_clks_data, 3437 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3438 .has_blink_output = true, 3439 .has_usb_sleepwalk = true, 3440 .has_single_mmio_aperture = true, 3441 }; 3442 3443 static const char * const tegra124_powergates[] = { 3444 [TEGRA_POWERGATE_CPU] = "crail", 3445 [TEGRA_POWERGATE_3D] = "3d", 3446 [TEGRA_POWERGATE_VENC] = "venc", 3447 [TEGRA_POWERGATE_PCIE] = "pcie", 3448 [TEGRA_POWERGATE_VDEC] = "vdec", 3449 [TEGRA_POWERGATE_MPE] = "mpe", 3450 [TEGRA_POWERGATE_HEG] = "heg", 3451 [TEGRA_POWERGATE_SATA] = "sata", 3452 [TEGRA_POWERGATE_CPU1] = "cpu1", 3453 [TEGRA_POWERGATE_CPU2] = "cpu2", 3454 [TEGRA_POWERGATE_CPU3] = "cpu3", 3455 [TEGRA_POWERGATE_CELP] = "celp", 3456 [TEGRA_POWERGATE_CPU0] = "cpu0", 3457 [TEGRA_POWERGATE_C0NC] = "c0nc", 3458 [TEGRA_POWERGATE_C1NC] = "c1nc", 3459 [TEGRA_POWERGATE_SOR] = "sor", 3460 [TEGRA_POWERGATE_DIS] = "dis", 3461 [TEGRA_POWERGATE_DISB] = "disb", 3462 [TEGRA_POWERGATE_XUSBA] = "xusba", 3463 [TEGRA_POWERGATE_XUSBB] = "xusbb", 3464 [TEGRA_POWERGATE_XUSBC] = "xusbc", 3465 [TEGRA_POWERGATE_VIC] = "vic", 3466 [TEGRA_POWERGATE_IRAM] = "iram", 3467 }; 3468 3469 static const u8 tegra124_cpu_powergates[] = { 3470 TEGRA_POWERGATE_CPU0, 3471 TEGRA_POWERGATE_CPU1, 3472 TEGRA_POWERGATE_CPU2, 3473 TEGRA_POWERGATE_CPU3, 3474 }; 3475 3476 #define TEGRA_IO_PAD(_id, _dpd, _request, _status, _voltage, _name) \ 3477 ((struct tegra_io_pad_soc) { \ 3478 .id = (_id), \ 3479 .dpd = (_dpd), \ 3480 .request = (_request), \ 3481 .status = (_status), \ 3482 .voltage = (_voltage), \ 3483 .name = (_name), \ 3484 }) 3485 3486 #define TEGRA_IO_PIN_DESC(_id, _name) \ 3487 ((struct pinctrl_pin_desc) { \ 3488 .number = (_id), \ 3489 .name = (_name), \ 3490 }) 3491 3492 static const struct tegra_io_pad_soc tegra124_io_pads[] = { 3493 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, UINT_MAX, "audio"), 3494 TEGRA_IO_PAD(TEGRA_IO_PAD_BB, 15, 0x1b8, 0x1bc, UINT_MAX, "bb"), 3495 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, UINT_MAX, "cam"), 3496 TEGRA_IO_PAD(TEGRA_IO_PAD_COMP, 22, 0x1b8, 0x1bc, UINT_MAX, "comp"), 3497 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, UINT_MAX, "csia"), 3498 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, UINT_MAX, "csib"), 3499 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, UINT_MAX, "csie"), 3500 TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, UINT_MAX, "dsi"), 3501 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, UINT_MAX, "dsib"), 3502 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, UINT_MAX, "dsic"), 3503 TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, UINT_MAX, "dsid"), 3504 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, UINT_MAX, "hdmi"), 3505 TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, UINT_MAX, "hsic"), 3506 TEGRA_IO_PAD(TEGRA_IO_PAD_HV, 6, 0x1c0, 0x1c4, UINT_MAX, "hv"), 3507 TEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, UINT_MAX, "lvds"), 3508 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, UINT_MAX, "mipi-bias"), 3509 TEGRA_IO_PAD(TEGRA_IO_PAD_NAND, 13, 0x1b8, 0x1bc, UINT_MAX, "nand"), 3510 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, "pex-bias"), 3511 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, "pex-clk1"), 3512 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"), 3513 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x1c0, 0x1c4, UINT_MAX, "pex-cntrl"), 3514 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, UINT_MAX, "sdmmc1"), 3515 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, UINT_MAX, "sdmmc3"), 3516 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 3, 0x1c0, 0x1c4, UINT_MAX, "sdmmc4"), 3517 TEGRA_IO_PAD(TEGRA_IO_PAD_SYS_DDC, 26, 0x1c0, 0x1c4, UINT_MAX, "sys_ddc"), 3518 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, UINT_MAX, "uart"), 3519 TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, UINT_MAX, "usb0"), 3520 TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, UINT_MAX, "usb1"), 3521 TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, UINT_MAX, "usb2"), 3522 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, UINT_MAX, "usb_bias"), 3523 }; 3524 3525 static const struct pinctrl_pin_desc tegra124_pin_descs[] = { 3526 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), 3527 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_BB, "bb"), 3528 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), 3529 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_COMP, "comp"), 3530 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 3531 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 3532 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 3533 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"), 3534 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"), 3535 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"), 3536 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"), 3537 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI, "hdmi"), 3538 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"), 3539 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HV, "hv"), 3540 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_LVDS, "lvds"), 3541 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), 3542 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_NAND, "nand"), 3543 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"), 3544 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), 3545 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), 3546 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), 3547 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1, "sdmmc1"), 3548 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3, "sdmmc3"), 3549 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"), 3550 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SYS_DDC, "sys_ddc"), 3551 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), 3552 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"), 3553 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"), 3554 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"), 3555 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb_bias"), 3556 }; 3557 3558 static const struct tegra_pmc_soc tegra124_pmc_soc = { 3559 .supports_core_domain = false, 3560 .num_powergates = ARRAY_SIZE(tegra124_powergates), 3561 .powergates = tegra124_powergates, 3562 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), 3563 .cpu_powergates = tegra124_cpu_powergates, 3564 .has_tsense_reset = true, 3565 .has_gpu_clamps = true, 3566 .needs_mbist_war = false, 3567 .has_impl_33v_pwr = false, 3568 .maybe_tz_only = false, 3569 .num_io_pads = ARRAY_SIZE(tegra124_io_pads), 3570 .io_pads = tegra124_io_pads, 3571 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs), 3572 .pin_descs = tegra124_pin_descs, 3573 .regs = &tegra20_pmc_regs, 3574 .init = tegra20_pmc_init, 3575 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3576 .powergate_set = tegra114_powergate_set, 3577 .reset_sources = tegra30_reset_sources, 3578 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 3579 .reset_levels = NULL, 3580 .num_reset_levels = 0, 3581 .pmc_clks_data = tegra_pmc_clks_data, 3582 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3583 .has_blink_output = true, 3584 .has_usb_sleepwalk = true, 3585 .has_single_mmio_aperture = true, 3586 }; 3587 3588 static const char * const tegra210_powergates[] = { 3589 [TEGRA_POWERGATE_CPU] = "crail", 3590 [TEGRA_POWERGATE_3D] = "3d", 3591 [TEGRA_POWERGATE_VENC] = "venc", 3592 [TEGRA_POWERGATE_PCIE] = "pcie", 3593 [TEGRA_POWERGATE_MPE] = "mpe", 3594 [TEGRA_POWERGATE_SATA] = "sata", 3595 [TEGRA_POWERGATE_CPU1] = "cpu1", 3596 [TEGRA_POWERGATE_CPU2] = "cpu2", 3597 [TEGRA_POWERGATE_CPU3] = "cpu3", 3598 [TEGRA_POWERGATE_CPU0] = "cpu0", 3599 [TEGRA_POWERGATE_C0NC] = "c0nc", 3600 [TEGRA_POWERGATE_SOR] = "sor", 3601 [TEGRA_POWERGATE_DIS] = "dis", 3602 [TEGRA_POWERGATE_DISB] = "disb", 3603 [TEGRA_POWERGATE_XUSBA] = "xusba", 3604 [TEGRA_POWERGATE_XUSBB] = "xusbb", 3605 [TEGRA_POWERGATE_XUSBC] = "xusbc", 3606 [TEGRA_POWERGATE_VIC] = "vic", 3607 [TEGRA_POWERGATE_IRAM] = "iram", 3608 [TEGRA_POWERGATE_NVDEC] = "nvdec", 3609 [TEGRA_POWERGATE_NVJPG] = "nvjpg", 3610 [TEGRA_POWERGATE_AUD] = "aud", 3611 [TEGRA_POWERGATE_DFD] = "dfd", 3612 [TEGRA_POWERGATE_VE2] = "ve2", 3613 }; 3614 3615 static const u8 tegra210_cpu_powergates[] = { 3616 TEGRA_POWERGATE_CPU0, 3617 TEGRA_POWERGATE_CPU1, 3618 TEGRA_POWERGATE_CPU2, 3619 TEGRA_POWERGATE_CPU3, 3620 }; 3621 3622 static const struct tegra_io_pad_soc tegra210_io_pads[] = { 3623 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, 5, "audio"), 3624 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x1c0, 0x1c4, 18, "audio-hv"), 3625 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, 10, "cam"), 3626 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, UINT_MAX, "csia"), 3627 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, UINT_MAX, "csib"), 3628 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 10, 0x1c0, 0x1c4, UINT_MAX, "csic"), 3629 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 11, 0x1c0, 0x1c4, UINT_MAX, "csid"), 3630 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, UINT_MAX, "csie"), 3631 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 13, 0x1c0, 0x1c4, UINT_MAX, "csif"), 3632 TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x1b8, 0x1bc, 19, "dbg"), 3633 TEGRA_IO_PAD(TEGRA_IO_PAD_DEBUG_NONAO, 26, 0x1b8, 0x1bc, UINT_MAX, "debug-nonao"), 3634 TEGRA_IO_PAD(TEGRA_IO_PAD_DMIC, 18, 0x1c0, 0x1c4, 20, "dmic"), 3635 TEGRA_IO_PAD(TEGRA_IO_PAD_DP, 19, 0x1c0, 0x1c4, UINT_MAX, "dp"), 3636 TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, UINT_MAX, "dsi"), 3637 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, UINT_MAX, "dsib"), 3638 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, UINT_MAX, "dsic"), 3639 TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, UINT_MAX, "dsid"), 3640 TEGRA_IO_PAD(TEGRA_IO_PAD_EMMC, 3, 0x1c0, 0x1c4, UINT_MAX, "emmc"), 3641 TEGRA_IO_PAD(TEGRA_IO_PAD_EMMC2, 5, 0x1c0, 0x1c4, UINT_MAX, "emmc2"), 3642 TEGRA_IO_PAD(TEGRA_IO_PAD_GPIO, 27, 0x1b8, 0x1bc, 21, "gpio"), 3643 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, UINT_MAX, "hdmi"), 3644 TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, UINT_MAX, "hsic"), 3645 TEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, UINT_MAX, "lvds"), 3646 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, UINT_MAX, "mipi-bias"), 3647 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, "pex-bias"), 3648 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, "pex-clk1"), 3649 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"), 3650 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, UINT_MAX, UINT_MAX, 11, "pex-cntrl"), 3651 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, 12, "sdmmc1"), 3652 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, 13, "sdmmc3"), 3653 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 14, 0x1c0, 0x1c4, 22, "spi"), 3654 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI_HV, 15, 0x1c0, 0x1c4, 23, "spi-hv"), 3655 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, 2, "uart"), 3656 TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, UINT_MAX, "usb0"), 3657 TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, UINT_MAX, "usb1"), 3658 TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, UINT_MAX, "usb2"), 3659 TEGRA_IO_PAD(TEGRA_IO_PAD_USB3, 18, 0x1b8, 0x1bc, UINT_MAX, "usb3"), 3660 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, UINT_MAX, "usb-bias"), 3661 }; 3662 3663 static const struct pinctrl_pin_desc tegra210_pin_descs[] = { 3664 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), 3665 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), 3666 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), 3667 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 3668 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 3669 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), 3670 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), 3671 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 3672 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), 3673 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"), 3674 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DEBUG_NONAO, "debug-nonao"), 3675 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DMIC, "dmic"), 3676 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DP, "dp"), 3677 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"), 3678 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"), 3679 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"), 3680 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"), 3681 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EMMC, "emmc"), 3682 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EMMC2, "emmc2"), 3683 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GPIO, "gpio"), 3684 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI, "hdmi"), 3685 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"), 3686 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_LVDS, "lvds"), 3687 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), 3688 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"), 3689 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), 3690 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), 3691 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), 3692 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1, "sdmmc1"), 3693 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3, "sdmmc3"), 3694 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"), 3695 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI_HV, "spi-hv"), 3696 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), 3697 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"), 3698 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"), 3699 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"), 3700 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB3, "usb3"), 3701 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"), 3702 }; 3703 3704 static const char * const tegra210_reset_sources[] = { 3705 "POWER_ON_RESET", 3706 "WATCHDOG", 3707 "SENSOR", 3708 "SW_MAIN", 3709 "LP0", 3710 "AOTAG" 3711 }; 3712 3713 static const struct tegra_wake_event tegra210_wake_events[] = { 3714 TEGRA_WAKE_IRQ("rtc", 16, 2), 3715 TEGRA_WAKE_IRQ("pmu", 51, 86), 3716 }; 3717 3718 static const struct tegra_pmc_soc tegra210_pmc_soc = { 3719 .supports_core_domain = false, 3720 .num_powergates = ARRAY_SIZE(tegra210_powergates), 3721 .powergates = tegra210_powergates, 3722 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates), 3723 .cpu_powergates = tegra210_cpu_powergates, 3724 .has_tsense_reset = true, 3725 .has_gpu_clamps = true, 3726 .needs_mbist_war = true, 3727 .has_impl_33v_pwr = false, 3728 .maybe_tz_only = true, 3729 .num_io_pads = ARRAY_SIZE(tegra210_io_pads), 3730 .io_pads = tegra210_io_pads, 3731 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs), 3732 .pin_descs = tegra210_pin_descs, 3733 .regs = &tegra20_pmc_regs, 3734 .init = tegra20_pmc_init, 3735 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3736 .powergate_set = tegra114_powergate_set, 3737 .irq_set_wake = tegra210_pmc_irq_set_wake, 3738 .irq_set_type = tegra210_pmc_irq_set_type, 3739 .reset_sources = tegra210_reset_sources, 3740 .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources), 3741 .reset_levels = NULL, 3742 .num_reset_levels = 0, 3743 .num_wake_events = ARRAY_SIZE(tegra210_wake_events), 3744 .wake_events = tegra210_wake_events, 3745 .pmc_clks_data = tegra_pmc_clks_data, 3746 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3747 .has_blink_output = true, 3748 .has_usb_sleepwalk = true, 3749 .has_single_mmio_aperture = true, 3750 }; 3751 3752 static const struct tegra_io_pad_soc tegra186_io_pads[] = { 3753 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, UINT_MAX, "csia"), 3754 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, UINT_MAX, "csib"), 3755 TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x74, 0x78, UINT_MAX, "dsi"), 3756 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, UINT_MAX, "mipi-bias"), 3757 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, UINT_MAX, "pex-clk-bias"), 3758 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, UINT_MAX, "pex-clk3"), 3759 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"), 3760 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, UINT_MAX, "pex-clk1"), 3761 TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x74, 0x78, UINT_MAX, "usb0"), 3762 TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x74, 0x78, UINT_MAX, "usb1"), 3763 TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x74, 0x78, UINT_MAX, "usb2"), 3764 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x74, 0x78, UINT_MAX, "usb-bias"), 3765 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x74, 0x78, UINT_MAX, "uart"), 3766 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x74, 0x78, UINT_MAX, "audio"), 3767 TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x74, 0x78, UINT_MAX, "hsic"), 3768 TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x74, 0x78, UINT_MAX, "dbg"), 3769 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, "hdmi-dp0"), 3770 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, UINT_MAX, "hdmi-dp1"), 3771 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, UINT_MAX, "pex-cntrl"), 3772 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC2_HV, 2, 0x7c, 0x80, 5, "sdmmc2-hv"), 3773 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 4, 0x7c, 0x80, UINT_MAX, "sdmmc4"), 3774 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 6, 0x7c, 0x80, UINT_MAX, "cam"), 3775 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 8, 0x7c, 0x80, UINT_MAX, "dsib"), 3776 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 9, 0x7c, 0x80, UINT_MAX, "dsic"), 3777 TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 10, 0x7c, 0x80, UINT_MAX, "dsid"), 3778 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 11, 0x7c, 0x80, UINT_MAX, "csic"), 3779 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 12, 0x7c, 0x80, UINT_MAX, "csid"), 3780 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 13, 0x7c, 0x80, UINT_MAX, "csie"), 3781 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 14, 0x7c, 0x80, UINT_MAX, "csif"), 3782 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 15, 0x7c, 0x80, UINT_MAX, "spi"), 3783 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 17, 0x7c, 0x80, UINT_MAX, "ufs"), 3784 TEGRA_IO_PAD(TEGRA_IO_PAD_DMIC_HV, 20, 0x7c, 0x80, 2, "dmic-hv"), 3785 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 21, 0x7c, 0x80, UINT_MAX, "edp"), 3786 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, 4, "sdmmc1-hv"), 3787 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, 6, "sdmmc3-hv"), 3788 TEGRA_IO_PAD(TEGRA_IO_PAD_CONN, 28, 0x7c, 0x80, UINT_MAX, "conn"), 3789 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, 1, "audio-hv"), 3790 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"), 3791 }; 3792 3793 static const struct pinctrl_pin_desc tegra186_pin_descs[] = { 3794 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 3795 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 3796 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"), 3797 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), 3798 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"), 3799 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"), 3800 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), 3801 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), 3802 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"), 3803 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"), 3804 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"), 3805 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"), 3806 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), 3807 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), 3808 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"), 3809 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"), 3810 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"), 3811 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"), 3812 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), 3813 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC2_HV, "sdmmc2-hv"), 3814 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"), 3815 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), 3816 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"), 3817 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"), 3818 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"), 3819 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), 3820 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), 3821 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 3822 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), 3823 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"), 3824 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"), 3825 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DMIC_HV, "dmic-hv"), 3826 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"), 3827 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"), 3828 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"), 3829 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CONN, "conn"), 3830 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), 3831 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"), 3832 }; 3833 3834 static const struct tegra_pmc_regs tegra186_pmc_regs = { 3835 .scratch0 = 0x2000, 3836 .rst_status = 0x70, 3837 .rst_source_shift = 0x2, 3838 .rst_source_mask = 0x3c, 3839 .rst_level_shift = 0x0, 3840 .rst_level_mask = 0x3, 3841 }; 3842 3843 static void tegra186_pmc_init(struct tegra_pmc *pmc) 3844 { 3845 pmc->syscore.ops = &tegra186_pmc_wake_syscore_ops; 3846 register_syscore(&pmc->syscore); 3847 } 3848 3849 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 3850 struct device_node *np, 3851 bool invert) 3852 { 3853 struct resource regs; 3854 void __iomem *wake; 3855 u32 value; 3856 int index; 3857 3858 index = of_property_match_string(np, "reg-names", "wake"); 3859 if (index < 0) { 3860 dev_err(pmc->dev, "failed to find PMC wake registers\n"); 3861 return; 3862 } 3863 3864 of_address_to_resource(np, index, ®s); 3865 3866 wake = ioremap(regs.start, resource_size(®s)); 3867 if (!wake) { 3868 dev_err(pmc->dev, "failed to map PMC wake registers\n"); 3869 return; 3870 } 3871 3872 value = readl(wake + WAKE_AOWAKE_CTRL); 3873 3874 if (invert) 3875 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY; 3876 else 3877 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY; 3878 3879 writel(value, wake + WAKE_AOWAKE_CTRL); 3880 3881 iounmap(wake); 3882 } 3883 3884 static const char * const tegra186_reset_sources[] = { 3885 "SYS_RESET", 3886 "AOWDT", 3887 "MCCPLEXWDT", 3888 "BPMPWDT", 3889 "SCEWDT", 3890 "SPEWDT", 3891 "APEWDT", 3892 "BCCPLEXWDT", 3893 "SENSOR", 3894 "AOTAG", 3895 "VFSENSOR", 3896 "SWREST", 3897 "SC7", 3898 "HSM", 3899 "CORESIGHT" 3900 }; 3901 3902 static const char * const tegra186_reset_levels[] = { 3903 "L0", "L1", "L2", "WARM" 3904 }; 3905 3906 static const struct tegra_wake_event tegra186_wake_events[] = { 3907 TEGRA_WAKE_IRQ("pmu", 24, 209), 3908 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)), 3909 TEGRA_WAKE_IRQ("rtc", 73, 10), 3910 }; 3911 3912 static const struct tegra_pmc_soc tegra186_pmc_soc = { 3913 .supports_core_domain = false, 3914 .num_powergates = 0, 3915 .powergates = NULL, 3916 .num_cpu_powergates = 0, 3917 .cpu_powergates = NULL, 3918 .has_tsense_reset = false, 3919 .has_gpu_clamps = false, 3920 .needs_mbist_war = false, 3921 .has_impl_33v_pwr = true, 3922 .maybe_tz_only = false, 3923 .num_io_pads = ARRAY_SIZE(tegra186_io_pads), 3924 .io_pads = tegra186_io_pads, 3925 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs), 3926 .pin_descs = tegra186_pin_descs, 3927 .regs = &tegra186_pmc_regs, 3928 .init = tegra186_pmc_init, 3929 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 3930 .set_wake_filters = tegra186_pmc_set_wake_filters, 3931 .irq_set_wake = tegra186_pmc_irq_set_wake, 3932 .irq_set_type = tegra186_pmc_irq_set_type, 3933 .reset_sources = tegra186_reset_sources, 3934 .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources), 3935 .reset_levels = tegra186_reset_levels, 3936 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 3937 .num_wake_events = ARRAY_SIZE(tegra186_wake_events), 3938 .wake_events = tegra186_wake_events, 3939 .max_wake_events = 96, 3940 .max_wake_vectors = 3, 3941 .pmc_clks_data = NULL, 3942 .num_pmc_clks = 0, 3943 .has_blink_output = false, 3944 .has_usb_sleepwalk = false, 3945 .has_single_mmio_aperture = false, 3946 }; 3947 3948 static const struct tegra_io_pad_soc tegra194_io_pads[] = { 3949 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, UINT_MAX, "csia"), 3950 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, UINT_MAX, "csib"), 3951 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, UINT_MAX, "mipi-bias"), 3952 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, UINT_MAX, "pex-clk-bias"), 3953 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, UINT_MAX, "pex-clk3"), 3954 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"), 3955 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, UINT_MAX, "pex-clk1"), 3956 TEGRA_IO_PAD(TEGRA_IO_PAD_EQOS, 8, 0x74, 0x78, UINT_MAX, "eqos"), 3957 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, 0x74, 0x78, UINT_MAX, "pex-clk-2-bias"), 3958 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2, 10, 0x74, 0x78, UINT_MAX, "pex-clk-2"), 3959 TEGRA_IO_PAD(TEGRA_IO_PAD_DAP3, 11, 0x74, 0x78, UINT_MAX, "dap3"), 3960 TEGRA_IO_PAD(TEGRA_IO_PAD_DAP5, 12, 0x74, 0x78, UINT_MAX, "dap5"), 3961 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x74, 0x78, UINT_MAX, "uart"), 3962 TEGRA_IO_PAD(TEGRA_IO_PAD_PWR_CTL, 15, 0x74, 0x78, UINT_MAX, "pwr-ctl"), 3963 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO53, 16, 0x74, 0x78, UINT_MAX, "soc-gpio53"), 3964 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x74, 0x78, UINT_MAX, "audio"), 3965 TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM2, 18, 0x74, 0x78, UINT_MAX, "gp-pwm2"), 3966 TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM3, 19, 0x74, 0x78, UINT_MAX, "gp-pwm3"), 3967 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO12, 20, 0x74, 0x78, UINT_MAX, "soc-gpio12"), 3968 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO13, 21, 0x74, 0x78, UINT_MAX, "soc-gpio13"), 3969 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO10, 22, 0x74, 0x78, UINT_MAX, "soc-gpio10"), 3970 TEGRA_IO_PAD(TEGRA_IO_PAD_UART4, 23, 0x74, 0x78, UINT_MAX, "uart4"), 3971 TEGRA_IO_PAD(TEGRA_IO_PAD_UART5, 24, 0x74, 0x78, UINT_MAX, "uart5"), 3972 TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x74, 0x78, UINT_MAX, "dbg"), 3973 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP3, 26, 0x74, 0x78, UINT_MAX, "hdmi-dp3"), 3974 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP2, 27, 0x74, 0x78, UINT_MAX, "hdmi-dp2"), 3975 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, "hdmi-dp0"), 3976 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, UINT_MAX, "hdmi-dp1"), 3977 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, UINT_MAX, "pex-cntrl"), 3978 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CTL2, 1, 0x7c, 0x80, UINT_MAX, "pex-ctl2"), 3979 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L0_RST, 2, 0x7c, 0x80, UINT_MAX, "pex-l0-rst"), 3980 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L1_RST, 3, 0x7c, 0x80, UINT_MAX, "pex-l1-rst"), 3981 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 4, 0x7c, 0x80, UINT_MAX, "sdmmc4"), 3982 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L5_RST, 5, 0x7c, 0x80, UINT_MAX, "pex-l5-rst"), 3983 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 6, 0x7c, 0x80, UINT_MAX, "cam"), 3984 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 11, 0x7c, 0x80, UINT_MAX, "csic"), 3985 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 12, 0x7c, 0x80, UINT_MAX, "csid"), 3986 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 13, 0x7c, 0x80, UINT_MAX, "csie"), 3987 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 14, 0x7c, 0x80, UINT_MAX, "csif"), 3988 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 15, 0x7c, 0x80, UINT_MAX, "spi"), 3989 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 17, 0x7c, 0x80, UINT_MAX, "ufs"), 3990 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 18, 0x7c, 0x80, UINT_MAX, "csig"), 3991 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 19, 0x7c, 0x80, UINT_MAX, "csih"), 3992 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 21, 0x7c, 0x80, UINT_MAX, "edp"), 3993 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, 4, "sdmmc1-hv"), 3994 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, 6, "sdmmc3-hv"), 3995 TEGRA_IO_PAD(TEGRA_IO_PAD_CONN, 28, 0x7c, 0x80, UINT_MAX, "conn"), 3996 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, 1, "audio-hv"), 3997 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"), 3998 }; 3999 4000 static const struct pinctrl_pin_desc tegra194_pin_descs[] = { 4001 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 4002 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 4003 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), 4004 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"), 4005 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"), 4006 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), 4007 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), 4008 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EQOS, "eqos"), 4009 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2_BIAS, "pex-clk-2-bias"), 4010 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2, "pex-clk-2"), 4011 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DAP3, "dap3"), 4012 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DAP5, "dap5"), 4013 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), 4014 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PWR_CTL, "pwr-ctl"), 4015 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO53, "soc-gpio53"), 4016 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), 4017 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM2, "gp-pwm2"), 4018 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM3, "gp-pwm3"), 4019 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO12, "soc-gpio12"), 4020 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO13, "soc-gpio13"), 4021 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO10, "soc-gpio10"), 4022 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART4, "uart4"), 4023 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART5, "uart5"), 4024 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"), 4025 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP3, "hdmi-dp3"), 4026 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP2, "hdmi-dp2"), 4027 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"), 4028 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"), 4029 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), 4030 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CTL2, "pex-ctl2"), 4031 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L0_RST, "pex-l0-rst"), 4032 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L1_RST, "pex-l1-rst"), 4033 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"), 4034 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L5_RST, "pex-l5-rst"), 4035 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), 4036 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), 4037 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), 4038 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 4039 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), 4040 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"), 4041 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"), 4042 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIG, "csig"), 4043 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIH, "csih"), 4044 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"), 4045 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"), 4046 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"), 4047 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CONN, "conn"), 4048 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), 4049 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"), 4050 }; 4051 4052 static const struct tegra_pmc_regs tegra194_pmc_regs = { 4053 .scratch0 = 0x2000, 4054 .rst_status = 0x70, 4055 .rst_source_shift = 0x2, 4056 .rst_source_mask = 0x7c, 4057 .rst_level_shift = 0x0, 4058 .rst_level_mask = 0x3, 4059 }; 4060 4061 static const char * const tegra194_reset_sources[] = { 4062 "SYS_RESET_N", 4063 "AOWDT", 4064 "BCCPLEXWDT", 4065 "BPMPWDT", 4066 "SCEWDT", 4067 "SPEWDT", 4068 "APEWDT", 4069 "LCCPLEXWDT", 4070 "SENSOR", 4071 "AOTAG", 4072 "VFSENSOR", 4073 "MAINSWRST", 4074 "SC7", 4075 "HSM", 4076 "CSITE", 4077 "RCEWDT", 4078 "PVA0WDT", 4079 "PVA1WDT", 4080 "L1A_ASYNC", 4081 "BPMPBOOT", 4082 "FUSECRC", 4083 }; 4084 4085 static const struct tegra_wake_event tegra194_wake_events[] = { 4086 TEGRA_WAKE_GPIO("eqos", 20, 0, TEGRA194_MAIN_GPIO(G, 4)), 4087 TEGRA_WAKE_IRQ("pmu", 24, 209), 4088 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)), 4089 TEGRA_WAKE_IRQ("rtc", 73, 10), 4090 TEGRA_WAKE_SIMPLE("usb3-port-0", 76), 4091 TEGRA_WAKE_SIMPLE("usb3-port-1", 77), 4092 TEGRA_WAKE_SIMPLE("usb3-port-2-3", 78), 4093 TEGRA_WAKE_SIMPLE("usb2-port-0", 79), 4094 TEGRA_WAKE_SIMPLE("usb2-port-1", 80), 4095 TEGRA_WAKE_SIMPLE("usb2-port-2", 81), 4096 TEGRA_WAKE_SIMPLE("usb2-port-3", 82), 4097 }; 4098 4099 static const struct tegra_pmc_soc tegra194_pmc_soc = { 4100 .supports_core_domain = false, 4101 .num_powergates = 0, 4102 .powergates = NULL, 4103 .num_cpu_powergates = 0, 4104 .cpu_powergates = NULL, 4105 .has_tsense_reset = false, 4106 .has_gpu_clamps = false, 4107 .needs_mbist_war = false, 4108 .has_impl_33v_pwr = true, 4109 .maybe_tz_only = false, 4110 .num_io_pads = ARRAY_SIZE(tegra194_io_pads), 4111 .io_pads = tegra194_io_pads, 4112 .num_pin_descs = ARRAY_SIZE(tegra194_pin_descs), 4113 .pin_descs = tegra194_pin_descs, 4114 .regs = &tegra194_pmc_regs, 4115 .init = tegra186_pmc_init, 4116 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 4117 .set_wake_filters = tegra186_pmc_set_wake_filters, 4118 .irq_set_wake = tegra186_pmc_irq_set_wake, 4119 .irq_set_type = tegra186_pmc_irq_set_type, 4120 .reset_sources = tegra194_reset_sources, 4121 .num_reset_sources = ARRAY_SIZE(tegra194_reset_sources), 4122 .reset_levels = tegra186_reset_levels, 4123 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 4124 .num_wake_events = ARRAY_SIZE(tegra194_wake_events), 4125 .wake_events = tegra194_wake_events, 4126 .max_wake_events = 96, 4127 .max_wake_vectors = 3, 4128 .pmc_clks_data = NULL, 4129 .num_pmc_clks = 0, 4130 .has_blink_output = false, 4131 .has_usb_sleepwalk = false, 4132 .has_single_mmio_aperture = false, 4133 }; 4134 4135 static const struct tegra_io_pad_soc tegra234_io_pads[] = { 4136 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0xe0c0, 0xe0c4, UINT_MAX, "csia"), 4137 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0xe0c0, 0xe0c4, UINT_MAX, "csib"), 4138 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 0, 0xe0d0, 0xe0d4, UINT_MAX, "hdmi-dp0"), 4139 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 2, 0xe0c0, 0xe0c4, UINT_MAX, "csic"), 4140 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 3, 0xe0c0, 0xe0c4, UINT_MAX, "csid"), 4141 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 4, 0xe0c0, 0xe0c4, UINT_MAX, "csie"), 4142 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 5, 0xe0c0, 0xe0c4, UINT_MAX, "csif"), 4143 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 0, 0xe064, 0xe068, UINT_MAX, "ufs"), 4144 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 1, 0xe05c, 0xe060, UINT_MAX, "edp"), 4145 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 0, 0xe054, 0xe058, 4, "sdmmc1-hv"), 4146 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, UINT_MAX, UINT_MAX, UINT_MAX, 6, "sdmmc3-hv"), 4147 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 1, "audio-hv"), 4148 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"), 4149 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 6, 0xe0c0, 0xe0c4, UINT_MAX, "csig"), 4150 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 7, 0xe0c0, 0xe0c4, UINT_MAX, "csih"), 4151 }; 4152 4153 static const struct pinctrl_pin_desc tegra234_pin_descs[] = { 4154 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 4155 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 4156 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"), 4157 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), 4158 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), 4159 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 4160 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), 4161 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"), 4162 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"), 4163 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"), 4164 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"), 4165 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), 4166 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"), 4167 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIG, "csig"), 4168 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIH, "csih"), 4169 }; 4170 4171 static const struct tegra_pmc_regs tegra234_pmc_regs = { 4172 .scratch0 = 0x2000, 4173 .rst_status = 0x70, 4174 .rst_source_shift = 0x2, 4175 .rst_source_mask = 0xfc, 4176 .rst_level_shift = 0x0, 4177 .rst_level_mask = 0x3, 4178 }; 4179 4180 static const char * const tegra234_reset_sources[] = { 4181 "SYS_RESET_N", /* 0x0 */ 4182 "AOWDT", 4183 "BCCPLEXWDT", 4184 "BPMPWDT", 4185 "SCEWDT", 4186 "SPEWDT", 4187 "APEWDT", 4188 "LCCPLEXWDT", 4189 "SENSOR", /* 0x8 */ 4190 NULL, 4191 NULL, 4192 "MAINSWRST", 4193 "SC7", 4194 "HSM", 4195 NULL, 4196 "RCEWDT", 4197 NULL, /* 0x10 */ 4198 NULL, 4199 NULL, 4200 "BPMPBOOT", 4201 "FUSECRC", 4202 "DCEWDT", 4203 "PSCWDT", 4204 "PSC", 4205 "CSITE_SW", /* 0x18 */ 4206 "POD", 4207 "SCPM", 4208 "VREFRO_POWERBAD", 4209 "VMON", 4210 "FMON", 4211 "FSI_R5WDT", 4212 "FSI_THERM", 4213 "FSI_R52C0WDT", /* 0x20 */ 4214 "FSI_R52C1WDT", 4215 "FSI_R52C2WDT", 4216 "FSI_R52C3WDT", 4217 "FSI_FMON", 4218 "FSI_VMON", /* 0x25 */ 4219 }; 4220 4221 static const struct tegra_wake_event tegra234_wake_events[] = { 4222 TEGRA_WAKE_GPIO("sd-wake", 8, 0, TEGRA234_MAIN_GPIO(G, 7)), 4223 TEGRA_WAKE_GPIO("eqos", 20, 0, TEGRA234_MAIN_GPIO(G, 4)), 4224 TEGRA_WAKE_IRQ("pmu", 24, 209), 4225 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA234_AON_GPIO(EE, 4)), 4226 TEGRA_WAKE_GPIO("mgbe", 56, 0, TEGRA234_MAIN_GPIO(Y, 3)), 4227 TEGRA_WAKE_IRQ("rtc", 73, 10), 4228 TEGRA_WAKE_IRQ("usb3-port-0", 76, 167), 4229 TEGRA_WAKE_IRQ("usb3-port-1", 77, 167), 4230 TEGRA_WAKE_IRQ("usb3-port-2-3", 78, 167), 4231 TEGRA_WAKE_IRQ("usb2-port-0", 79, 167), 4232 TEGRA_WAKE_IRQ("usb2-port-1", 80, 167), 4233 TEGRA_WAKE_IRQ("usb2-port-2", 81, 167), 4234 TEGRA_WAKE_IRQ("usb2-port-3", 82, 167), 4235 TEGRA_WAKE_IRQ("sw-wake", SW_WAKE_ID, 179), 4236 }; 4237 4238 static const struct tegra_pmc_soc tegra234_pmc_soc = { 4239 .supports_core_domain = false, 4240 .num_powergates = 0, 4241 .powergates = NULL, 4242 .num_cpu_powergates = 0, 4243 .cpu_powergates = NULL, 4244 .has_tsense_reset = false, 4245 .has_gpu_clamps = false, 4246 .needs_mbist_war = false, 4247 .has_impl_33v_pwr = true, 4248 .maybe_tz_only = false, 4249 .num_io_pads = ARRAY_SIZE(tegra234_io_pads), 4250 .io_pads = tegra234_io_pads, 4251 .num_pin_descs = ARRAY_SIZE(tegra234_pin_descs), 4252 .pin_descs = tegra234_pin_descs, 4253 .regs = &tegra234_pmc_regs, 4254 .init = tegra186_pmc_init, 4255 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 4256 .set_wake_filters = tegra186_pmc_set_wake_filters, 4257 .irq_set_wake = tegra186_pmc_irq_set_wake, 4258 .irq_set_type = tegra186_pmc_irq_set_type, 4259 .reset_sources = tegra234_reset_sources, 4260 .num_reset_sources = ARRAY_SIZE(tegra234_reset_sources), 4261 .reset_levels = tegra186_reset_levels, 4262 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 4263 .num_wake_events = ARRAY_SIZE(tegra234_wake_events), 4264 .wake_events = tegra234_wake_events, 4265 .max_wake_events = 96, 4266 .max_wake_vectors = 3, 4267 .pmc_clks_data = NULL, 4268 .num_pmc_clks = 0, 4269 .has_blink_output = false, 4270 .has_single_mmio_aperture = false, 4271 }; 4272 4273 static const struct tegra_pmc_regs tegra264_pmc_regs = { 4274 .scratch0 = 0x684, 4275 .rst_status = 0x4, 4276 .rst_source_shift = 0x2, 4277 .rst_source_mask = 0x1fc, 4278 .rst_level_shift = 0x0, 4279 .rst_level_mask = 0x3, 4280 }; 4281 4282 static const char * const tegra264_reset_sources[] = { 4283 "SYS_RESET_N", /* 0x0 */ 4284 "CSDC_RTC_XTAL", 4285 "VREFRO_POWER_BAD", 4286 "SCPM_SOC_XTAL", 4287 "SCPM_RTC_XTAL", 4288 "FMON_32K", 4289 "FMON_OSC", 4290 "POD_RTC", 4291 "POD_IO", /* 0x8 */ 4292 "POD_PLUS_IO_SPLL", 4293 "POD_PLUS_SOC", 4294 "VMON_PLUS_UV", 4295 "VMON_PLUS_OV", 4296 "FUSECRC_FAULT", 4297 "OSC_FAULT", 4298 "BPMP_BOOT_FAULT", 4299 "SCPM_BPMP_CORE_CLK", /* 0x10 */ 4300 "SCPM_PSC_SE_CLK", 4301 "VMON_SOC_MIN", 4302 "VMON_SOC_MAX", 4303 "VMON_MSS_MIN", 4304 "VMON_MSS_MAX", 4305 "POD_PLUS_IO_VMON", 4306 "NVJTAG_SEL_MONITOR", 4307 "NV_THERM_FAULT", /* 0x18 */ 4308 "FSI_THERM_FAULT", 4309 "PSC_SW", 4310 "SCPM_OESP_SE_CLK", 4311 "SCPM_SB_SE_CLK", 4312 "POD_CPU", 4313 "POD_GPU", 4314 "DCLS_GPU", 4315 "POD_MSS", /* 0x20 */ 4316 "FMON_FSI", 4317 "POD_FSI", 4318 "VMON_FSI_MIN", 4319 "VMON_FSI_MAX", 4320 "VMON_CPU0_MIN", 4321 "VMON_CPU0_MAX", 4322 "BPMP_FMON", 4323 "AO_WDT_POR", /* 0x28 */ 4324 "BPMP_WDT_POR", 4325 "AO_TKE_WDT_POR", 4326 "RCE0_WDT_POR", 4327 "RCE1_WDT_POR", 4328 "DCE_WDT_POR", 4329 "FSI_R5_WDT_POR", 4330 "FSI_R52_0_WDT_POR", 4331 "FSI_R52_1_WDT_POR", /* 0x30 */ 4332 "FSI_R52_2_WDT_POR", 4333 "FSI_R52_3_WDT_POR", 4334 "TOP_0_WDT_POR", 4335 "TOP_1_WDT_POR", 4336 "TOP_2_WDT_POR", 4337 "APE_C0_WDT_POR", 4338 "APE_C1_WDT_POR", 4339 "GPU_TKE_WDT_POR", /* 0x38 */ 4340 "PSC_WDT_POR", 4341 "OESP_WDT_POR", 4342 "SB_WDT_POR", 4343 "SW_MAIN", 4344 "L0L1_RST_OUT_N", 4345 "FSI_HSM", 4346 "CSITE_SW", 4347 "AO_WDT_DBG", /* 0x40 */ 4348 "BPMP_WDT_DBG", 4349 "AO_TKE_WDT_DBG", 4350 "RCE0_WDT_DBG", 4351 "RCE1_WDT_DBG", 4352 "DCE_WDT_DBG", 4353 "FSI_R5_WDT_DBG", 4354 "FSI_R52_0_WDT_DBG", 4355 "FSI_R52_1_WDT_DBG", /* 0x48 */ 4356 "FSI_R52_2_WDT_DBG", 4357 "FSI_R52_3_WDT_DBG", 4358 "TOP_0_WDT_DBG", 4359 "TOP_1_WDT_DBG", 4360 "TOP_2_WDT_DBG", 4361 "APE_C0_WDT_DBG", 4362 "APE_C1_WDT_DBG", 4363 "PSC_WDT_DBG", /* 0x50 */ 4364 "OESP_WDT_DBG", 4365 "SB_WDT_DBG", 4366 "TSC_0_WDT_DBG", 4367 "TSC_1_WDT_DBG", 4368 "L2_RST_OUT_N", 4369 "SC7" 4370 }; 4371 4372 static const struct tegra_wake_event tegra264_wake_events[] = { 4373 }; 4374 4375 static const struct tegra_pmc_soc tegra264_pmc_soc = { 4376 .has_impl_33v_pwr = true, 4377 .regs = &tegra264_pmc_regs, 4378 .init = tegra186_pmc_init, 4379 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 4380 .set_wake_filters = tegra186_pmc_set_wake_filters, 4381 .irq_set_wake = tegra186_pmc_irq_set_wake, 4382 .irq_set_type = tegra186_pmc_irq_set_type, 4383 .reset_sources = tegra264_reset_sources, 4384 .num_reset_sources = ARRAY_SIZE(tegra264_reset_sources), 4385 .reset_levels = tegra186_reset_levels, 4386 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 4387 .wake_events = tegra264_wake_events, 4388 .num_wake_events = ARRAY_SIZE(tegra264_wake_events), 4389 .max_wake_events = 128, 4390 .max_wake_vectors = 4, 4391 }; 4392 4393 static const struct of_device_id tegra_pmc_match[] = { 4394 { .compatible = "nvidia,tegra264-pmc", .data = &tegra264_pmc_soc }, 4395 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc }, 4396 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc }, 4397 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc }, 4398 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc }, 4399 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc }, 4400 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc }, 4401 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc }, 4402 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc }, 4403 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc }, 4404 { } 4405 }; 4406 4407 static void tegra_pmc_sync_state(struct device *dev) 4408 { 4409 struct device_node *np, *child; 4410 int err; 4411 4412 np = of_get_child_by_name(dev->of_node, "powergates"); 4413 if (!np) 4414 return; 4415 4416 for_each_child_of_node(np, child) 4417 of_genpd_sync_state(child); 4418 4419 of_node_put(np); 4420 4421 np = of_get_child_by_name(dev->of_node, "core-domain"); 4422 if (!np) 4423 return; 4424 4425 of_genpd_sync_state(np); 4426 of_node_put(np); 4427 4428 /* 4429 * Newer device-trees have power domains, but we need to prepare all 4430 * device drivers with runtime PM and OPP support first, otherwise 4431 * state syncing is unsafe. 4432 */ 4433 if (!pmc->soc->supports_core_domain) 4434 return; 4435 4436 /* 4437 * Older device-trees don't have core PD, and thus, there are 4438 * no dependencies that will block the state syncing. We shouldn't 4439 * mark the domain as synced in this case. 4440 */ 4441 pmc->core_domain_state_synced = true; 4442 4443 /* this is a no-op if core regulator isn't used */ 4444 mutex_lock(&pmc->powergates_lock); 4445 err = dev_pm_opp_sync_regulators(dev); 4446 mutex_unlock(&pmc->powergates_lock); 4447 4448 if (err) 4449 dev_err(dev, "failed to sync regulators: %d\n", err); 4450 } 4451 4452 static struct platform_driver tegra_pmc_driver = { 4453 .driver = { 4454 .name = "tegra-pmc", 4455 .suppress_bind_attrs = true, 4456 .of_match_table = tegra_pmc_match, 4457 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 4458 .pm = &tegra_pmc_pm_ops, 4459 #endif 4460 .sync_state = tegra_pmc_sync_state, 4461 }, 4462 .probe = tegra_pmc_probe, 4463 }; 4464 builtin_platform_driver(tegra_pmc_driver); 4465 4466 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc) 4467 { 4468 u32 value, saved; 4469 4470 saved = readl(pmc->base + pmc->soc->regs->scratch0); 4471 value = saved ^ 0xffffffff; 4472 4473 if (value == 0xffffffff) 4474 value = 0xdeadbeef; 4475 4476 /* write pattern and read it back */ 4477 writel(value, pmc->base + pmc->soc->regs->scratch0); 4478 value = readl(pmc->base + pmc->soc->regs->scratch0); 4479 4480 /* if we read all-zeroes, access is restricted to TZ only */ 4481 if (value == 0) { 4482 pr_info("access to PMC is restricted to TZ\n"); 4483 return true; 4484 } 4485 4486 /* restore original value */ 4487 writel(saved, pmc->base + pmc->soc->regs->scratch0); 4488 4489 return false; 4490 } 4491 4492 /* 4493 * Early initialization to allow access to registers in the very early boot 4494 * process. 4495 */ 4496 static int __init tegra_pmc_early_init(void) 4497 { 4498 const struct of_device_id *match; 4499 struct device_node *np; 4500 struct resource regs; 4501 unsigned int i; 4502 bool invert; 4503 4504 mutex_init(&pmc->powergates_lock); 4505 4506 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match); 4507 if (!np) { 4508 /* 4509 * Fall back to legacy initialization for 32-bit ARM only. All 4510 * 64-bit ARM device tree files for Tegra are required to have 4511 * a PMC node. 4512 * 4513 * This is for backwards-compatibility with old device trees 4514 * that didn't contain a PMC node. Note that in this case the 4515 * SoC data can't be matched and therefore powergating is 4516 * disabled. 4517 */ 4518 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 4519 pr_warn("DT node not found, powergating disabled\n"); 4520 4521 regs.start = 0x7000e400; 4522 regs.end = 0x7000e7ff; 4523 regs.flags = IORESOURCE_MEM; 4524 4525 pr_warn("Using memory region %pR\n", ®s); 4526 } else { 4527 /* 4528 * At this point we're not running on Tegra, so play 4529 * nice with multi-platform kernels. 4530 */ 4531 return 0; 4532 } 4533 } else { 4534 /* 4535 * Extract information from the device tree if we've found a 4536 * matching node. 4537 */ 4538 if (of_address_to_resource(np, 0, ®s) < 0) { 4539 pr_err("failed to get PMC registers\n"); 4540 of_node_put(np); 4541 return -ENXIO; 4542 } 4543 } 4544 4545 pmc->base = ioremap(regs.start, resource_size(®s)); 4546 if (!pmc->base) { 4547 pr_err("failed to map PMC registers\n"); 4548 of_node_put(np); 4549 return -ENXIO; 4550 } 4551 4552 if (of_device_is_available(np)) { 4553 pmc->soc = match->data; 4554 4555 if (pmc->soc->maybe_tz_only) 4556 pmc->tz_only = tegra_pmc_detect_tz_only(pmc); 4557 4558 /* Create a bitmap of the available and valid partitions */ 4559 for (i = 0; i < pmc->soc->num_powergates; i++) 4560 if (pmc->soc->powergates[i]) 4561 set_bit(i, pmc->powergates_available); 4562 4563 /* 4564 * Invert the interrupt polarity if a PMC device tree node 4565 * exists and contains the nvidia,invert-interrupt property. 4566 */ 4567 invert = of_property_read_bool(np, "nvidia,invert-interrupt"); 4568 4569 pmc->soc->setup_irq_polarity(pmc, np, invert); 4570 4571 of_node_put(np); 4572 } 4573 4574 return 0; 4575 } 4576 early_initcall(tegra_pmc_early_init); 4577