1 /* 2 * drivers/soc/tegra/pmc.c 3 * 4 * Copyright (c) 2010 Google, Inc 5 * 6 * Author: 7 * Colin Cross <ccross@google.com> 8 * 9 * This software is licensed under the terms of the GNU General Public 10 * License version 2, as published by the Free Software Foundation, and 11 * may be copied, distributed, and modified under those terms. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 */ 19 20 #define pr_fmt(fmt) "tegra-pmc: " fmt 21 22 #include <linux/kernel.h> 23 #include <linux/clk.h> 24 #include <linux/clk/tegra.h> 25 #include <linux/debugfs.h> 26 #include <linux/delay.h> 27 #include <linux/err.h> 28 #include <linux/export.h> 29 #include <linux/init.h> 30 #include <linux/io.h> 31 #include <linux/iopoll.h> 32 #include <linux/of.h> 33 #include <linux/of_address.h> 34 #include <linux/of_clk.h> 35 #include <linux/of_platform.h> 36 #include <linux/pinctrl/pinctrl.h> 37 #include <linux/pinctrl/pinconf.h> 38 #include <linux/pinctrl/pinconf-generic.h> 39 #include <linux/platform_device.h> 40 #include <linux/pm_domain.h> 41 #include <linux/reboot.h> 42 #include <linux/reset.h> 43 #include <linux/seq_file.h> 44 #include <linux/slab.h> 45 #include <linux/spinlock.h> 46 47 #include <soc/tegra/common.h> 48 #include <soc/tegra/fuse.h> 49 #include <soc/tegra/pmc.h> 50 51 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 52 53 #define PMC_CNTRL 0x0 54 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */ 55 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */ 56 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */ 57 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */ 58 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ 59 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ 60 #define PMC_CNTRL_MAIN_RST BIT(4) 61 62 #define DPD_SAMPLE 0x020 63 #define DPD_SAMPLE_ENABLE BIT(0) 64 #define DPD_SAMPLE_DISABLE (0 << 0) 65 66 #define PWRGATE_TOGGLE 0x30 67 #define PWRGATE_TOGGLE_START BIT(8) 68 69 #define REMOVE_CLAMPING 0x34 70 71 #define PWRGATE_STATUS 0x38 72 73 #define PMC_IMPL_E_33V_PWR 0x40 74 75 #define PMC_PWR_DET 0x48 76 77 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31) 78 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30) 79 #define PMC_SCRATCH0_MODE_RCM BIT(1) 80 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ 81 PMC_SCRATCH0_MODE_BOOTLOADER | \ 82 PMC_SCRATCH0_MODE_RCM) 83 84 #define PMC_CPUPWRGOOD_TIMER 0xc8 85 #define PMC_CPUPWROFF_TIMER 0xcc 86 87 #define PMC_PWR_DET_VALUE 0xe4 88 89 #define PMC_SCRATCH41 0x140 90 91 #define PMC_SENSOR_CTRL 0x1b0 92 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) 93 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) 94 95 #define PMC_RST_STATUS 0x1b4 96 #define PMC_RST_STATUS_POR 0 97 #define PMC_RST_STATUS_WATCHDOG 1 98 #define PMC_RST_STATUS_SENSOR 2 99 #define PMC_RST_STATUS_SW_MAIN 3 100 #define PMC_RST_STATUS_LP0 4 101 #define PMC_RST_STATUS_AOTAG 5 102 103 #define IO_DPD_REQ 0x1b8 104 #define IO_DPD_REQ_CODE_IDLE (0U << 30) 105 #define IO_DPD_REQ_CODE_OFF (1U << 30) 106 #define IO_DPD_REQ_CODE_ON (2U << 30) 107 #define IO_DPD_REQ_CODE_MASK (3U << 30) 108 109 #define IO_DPD_STATUS 0x1bc 110 #define IO_DPD2_REQ 0x1c0 111 #define IO_DPD2_STATUS 0x1c4 112 #define SEL_DPD_TIM 0x1c8 113 114 #define PMC_SCRATCH54 0x258 115 #define PMC_SCRATCH54_DATA_SHIFT 8 116 #define PMC_SCRATCH54_ADDR_SHIFT 0 117 118 #define PMC_SCRATCH55 0x25c 119 #define PMC_SCRATCH55_RESET_TEGRA BIT(31) 120 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27 121 #define PMC_SCRATCH55_PINMUX_SHIFT 24 122 #define PMC_SCRATCH55_16BITOP BIT(15) 123 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16 124 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0 125 126 #define GPU_RG_CNTRL 0x2d4 127 128 /* Tegra186 and later */ 129 #define WAKE_AOWAKE_CTRL 0x4f4 130 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0) 131 132 struct tegra_powergate { 133 struct generic_pm_domain genpd; 134 struct tegra_pmc *pmc; 135 unsigned int id; 136 struct clk **clks; 137 unsigned int num_clks; 138 struct reset_control *reset; 139 }; 140 141 struct tegra_io_pad_soc { 142 enum tegra_io_pad id; 143 unsigned int dpd; 144 unsigned int voltage; 145 const char *name; 146 }; 147 148 struct tegra_pmc_regs { 149 unsigned int scratch0; 150 unsigned int dpd_req; 151 unsigned int dpd_status; 152 unsigned int dpd2_req; 153 unsigned int dpd2_status; 154 }; 155 156 struct tegra_pmc_soc { 157 unsigned int num_powergates; 158 const char *const *powergates; 159 unsigned int num_cpu_powergates; 160 const u8 *cpu_powergates; 161 162 bool has_tsense_reset; 163 bool has_gpu_clamps; 164 bool needs_mbist_war; 165 bool has_impl_33v_pwr; 166 167 const struct tegra_io_pad_soc *io_pads; 168 unsigned int num_io_pads; 169 170 const struct pinctrl_pin_desc *pin_descs; 171 unsigned int num_pin_descs; 172 173 const struct tegra_pmc_regs *regs; 174 void (*init)(struct tegra_pmc *pmc); 175 void (*setup_irq_polarity)(struct tegra_pmc *pmc, 176 struct device_node *np, 177 bool invert); 178 }; 179 180 /** 181 * struct tegra_pmc - NVIDIA Tegra PMC 182 * @dev: pointer to PMC device structure 183 * @base: pointer to I/O remapped register region 184 * @clk: pointer to pclk clock 185 * @soc: pointer to SoC data structure 186 * @debugfs: pointer to debugfs entry 187 * @rate: currently configured rate of pclk 188 * @suspend_mode: lowest suspend mode available 189 * @cpu_good_time: CPU power good time (in microseconds) 190 * @cpu_off_time: CPU power off time (in microsecends) 191 * @core_osc_time: core power good OSC time (in microseconds) 192 * @core_pmu_time: core power good PMU time (in microseconds) 193 * @core_off_time: core power off time (in microseconds) 194 * @corereq_high: core power request is active-high 195 * @sysclkreq_high: system clock request is active-high 196 * @combined_req: combined power request for CPU & core 197 * @cpu_pwr_good_en: CPU power good signal is enabled 198 * @lp0_vec_phys: physical base address of the LP0 warm boot code 199 * @lp0_vec_size: size of the LP0 warm boot code 200 * @powergates_available: Bitmap of available power gates 201 * @powergates_lock: mutex for power gate register access 202 */ 203 struct tegra_pmc { 204 struct device *dev; 205 void __iomem *base; 206 void __iomem *wake; 207 void __iomem *aotag; 208 void __iomem *scratch; 209 struct clk *clk; 210 struct dentry *debugfs; 211 212 const struct tegra_pmc_soc *soc; 213 214 unsigned long rate; 215 216 enum tegra_suspend_mode suspend_mode; 217 u32 cpu_good_time; 218 u32 cpu_off_time; 219 u32 core_osc_time; 220 u32 core_pmu_time; 221 u32 core_off_time; 222 bool corereq_high; 223 bool sysclkreq_high; 224 bool combined_req; 225 bool cpu_pwr_good_en; 226 u32 lp0_vec_phys; 227 u32 lp0_vec_size; 228 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX); 229 230 struct mutex powergates_lock; 231 232 struct pinctrl_dev *pctl_dev; 233 }; 234 235 static struct tegra_pmc *pmc = &(struct tegra_pmc) { 236 .base = NULL, 237 .suspend_mode = TEGRA_SUSPEND_NONE, 238 }; 239 240 static inline struct tegra_powergate * 241 to_powergate(struct generic_pm_domain *domain) 242 { 243 return container_of(domain, struct tegra_powergate, genpd); 244 } 245 246 static u32 tegra_pmc_readl(unsigned long offset) 247 { 248 return readl(pmc->base + offset); 249 } 250 251 static void tegra_pmc_writel(u32 value, unsigned long offset) 252 { 253 writel(value, pmc->base + offset); 254 } 255 256 static inline bool tegra_powergate_state(int id) 257 { 258 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 259 return (tegra_pmc_readl(GPU_RG_CNTRL) & 0x1) == 0; 260 else 261 return (tegra_pmc_readl(PWRGATE_STATUS) & BIT(id)) != 0; 262 } 263 264 static inline bool tegra_powergate_is_valid(int id) 265 { 266 return (pmc->soc && pmc->soc->powergates[id]); 267 } 268 269 static inline bool tegra_powergate_is_available(int id) 270 { 271 return test_bit(id, pmc->powergates_available); 272 } 273 274 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) 275 { 276 unsigned int i; 277 278 if (!pmc || !pmc->soc || !name) 279 return -EINVAL; 280 281 for (i = 0; i < pmc->soc->num_powergates; i++) { 282 if (!tegra_powergate_is_valid(i)) 283 continue; 284 285 if (!strcmp(name, pmc->soc->powergates[i])) 286 return i; 287 } 288 289 return -ENODEV; 290 } 291 292 /** 293 * tegra_powergate_set() - set the state of a partition 294 * @id: partition ID 295 * @new_state: new state of the partition 296 */ 297 static int tegra_powergate_set(unsigned int id, bool new_state) 298 { 299 bool status; 300 int err; 301 302 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 303 return -EINVAL; 304 305 mutex_lock(&pmc->powergates_lock); 306 307 if (tegra_powergate_state(id) == new_state) { 308 mutex_unlock(&pmc->powergates_lock); 309 return 0; 310 } 311 312 tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 313 314 err = readx_poll_timeout(tegra_powergate_state, id, status, 315 status == new_state, 10, 100000); 316 317 mutex_unlock(&pmc->powergates_lock); 318 319 return err; 320 } 321 322 static int __tegra_powergate_remove_clamping(unsigned int id) 323 { 324 u32 mask; 325 326 mutex_lock(&pmc->powergates_lock); 327 328 /* 329 * On Tegra124 and later, the clamps for the GPU are controlled by a 330 * separate register (with different semantics). 331 */ 332 if (id == TEGRA_POWERGATE_3D) { 333 if (pmc->soc->has_gpu_clamps) { 334 tegra_pmc_writel(0, GPU_RG_CNTRL); 335 goto out; 336 } 337 } 338 339 /* 340 * Tegra 2 has a bug where PCIE and VDE clamping masks are 341 * swapped relatively to the partition ids 342 */ 343 if (id == TEGRA_POWERGATE_VDEC) 344 mask = (1 << TEGRA_POWERGATE_PCIE); 345 else if (id == TEGRA_POWERGATE_PCIE) 346 mask = (1 << TEGRA_POWERGATE_VDEC); 347 else 348 mask = (1 << id); 349 350 tegra_pmc_writel(mask, REMOVE_CLAMPING); 351 352 out: 353 mutex_unlock(&pmc->powergates_lock); 354 355 return 0; 356 } 357 358 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg) 359 { 360 unsigned int i; 361 362 for (i = 0; i < pg->num_clks; i++) 363 clk_disable_unprepare(pg->clks[i]); 364 } 365 366 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg) 367 { 368 unsigned int i; 369 int err; 370 371 for (i = 0; i < pg->num_clks; i++) { 372 err = clk_prepare_enable(pg->clks[i]); 373 if (err) 374 goto out; 375 } 376 377 return 0; 378 379 out: 380 while (i--) 381 clk_disable_unprepare(pg->clks[i]); 382 383 return err; 384 } 385 386 int __weak tegra210_clk_handle_mbist_war(unsigned int id) 387 { 388 return 0; 389 } 390 391 static int tegra_powergate_power_up(struct tegra_powergate *pg, 392 bool disable_clocks) 393 { 394 int err; 395 396 err = reset_control_assert(pg->reset); 397 if (err) 398 return err; 399 400 usleep_range(10, 20); 401 402 err = tegra_powergate_set(pg->id, true); 403 if (err < 0) 404 return err; 405 406 usleep_range(10, 20); 407 408 err = tegra_powergate_enable_clocks(pg); 409 if (err) 410 goto disable_clks; 411 412 usleep_range(10, 20); 413 414 err = __tegra_powergate_remove_clamping(pg->id); 415 if (err) 416 goto disable_clks; 417 418 usleep_range(10, 20); 419 420 err = reset_control_deassert(pg->reset); 421 if (err) 422 goto powergate_off; 423 424 usleep_range(10, 20); 425 426 if (pg->pmc->soc->needs_mbist_war) 427 err = tegra210_clk_handle_mbist_war(pg->id); 428 if (err) 429 goto disable_clks; 430 431 if (disable_clocks) 432 tegra_powergate_disable_clocks(pg); 433 434 return 0; 435 436 disable_clks: 437 tegra_powergate_disable_clocks(pg); 438 usleep_range(10, 20); 439 440 powergate_off: 441 tegra_powergate_set(pg->id, false); 442 443 return err; 444 } 445 446 static int tegra_powergate_power_down(struct tegra_powergate *pg) 447 { 448 int err; 449 450 err = tegra_powergate_enable_clocks(pg); 451 if (err) 452 return err; 453 454 usleep_range(10, 20); 455 456 err = reset_control_assert(pg->reset); 457 if (err) 458 goto disable_clks; 459 460 usleep_range(10, 20); 461 462 tegra_powergate_disable_clocks(pg); 463 464 usleep_range(10, 20); 465 466 err = tegra_powergate_set(pg->id, false); 467 if (err) 468 goto assert_resets; 469 470 return 0; 471 472 assert_resets: 473 tegra_powergate_enable_clocks(pg); 474 usleep_range(10, 20); 475 reset_control_deassert(pg->reset); 476 usleep_range(10, 20); 477 478 disable_clks: 479 tegra_powergate_disable_clocks(pg); 480 481 return err; 482 } 483 484 static int tegra_genpd_power_on(struct generic_pm_domain *domain) 485 { 486 struct tegra_powergate *pg = to_powergate(domain); 487 int err; 488 489 err = tegra_powergate_power_up(pg, true); 490 if (err) 491 pr_err("failed to turn on PM domain %s: %d\n", pg->genpd.name, 492 err); 493 494 return err; 495 } 496 497 static int tegra_genpd_power_off(struct generic_pm_domain *domain) 498 { 499 struct tegra_powergate *pg = to_powergate(domain); 500 int err; 501 502 err = tegra_powergate_power_down(pg); 503 if (err) 504 pr_err("failed to turn off PM domain %s: %d\n", 505 pg->genpd.name, err); 506 507 return err; 508 } 509 510 /** 511 * tegra_powergate_power_on() - power on partition 512 * @id: partition ID 513 */ 514 int tegra_powergate_power_on(unsigned int id) 515 { 516 if (!tegra_powergate_is_available(id)) 517 return -EINVAL; 518 519 return tegra_powergate_set(id, true); 520 } 521 522 /** 523 * tegra_powergate_power_off() - power off partition 524 * @id: partition ID 525 */ 526 int tegra_powergate_power_off(unsigned int id) 527 { 528 if (!tegra_powergate_is_available(id)) 529 return -EINVAL; 530 531 return tegra_powergate_set(id, false); 532 } 533 EXPORT_SYMBOL(tegra_powergate_power_off); 534 535 /** 536 * tegra_powergate_is_powered() - check if partition is powered 537 * @id: partition ID 538 */ 539 int tegra_powergate_is_powered(unsigned int id) 540 { 541 int status; 542 543 if (!tegra_powergate_is_valid(id)) 544 return -EINVAL; 545 546 mutex_lock(&pmc->powergates_lock); 547 status = tegra_powergate_state(id); 548 mutex_unlock(&pmc->powergates_lock); 549 550 return status; 551 } 552 553 /** 554 * tegra_powergate_remove_clamping() - remove power clamps for partition 555 * @id: partition ID 556 */ 557 int tegra_powergate_remove_clamping(unsigned int id) 558 { 559 if (!tegra_powergate_is_available(id)) 560 return -EINVAL; 561 562 return __tegra_powergate_remove_clamping(id); 563 } 564 EXPORT_SYMBOL(tegra_powergate_remove_clamping); 565 566 /** 567 * tegra_powergate_sequence_power_up() - power up partition 568 * @id: partition ID 569 * @clk: clock for partition 570 * @rst: reset for partition 571 * 572 * Must be called with clk disabled, and returns with clk enabled. 573 */ 574 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, 575 struct reset_control *rst) 576 { 577 struct tegra_powergate *pg; 578 int err; 579 580 if (!tegra_powergate_is_available(id)) 581 return -EINVAL; 582 583 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 584 if (!pg) 585 return -ENOMEM; 586 587 pg->id = id; 588 pg->clks = &clk; 589 pg->num_clks = 1; 590 pg->reset = rst; 591 pg->pmc = pmc; 592 593 err = tegra_powergate_power_up(pg, false); 594 if (err) 595 pr_err("failed to turn on partition %d: %d\n", id, err); 596 597 kfree(pg); 598 599 return err; 600 } 601 EXPORT_SYMBOL(tegra_powergate_sequence_power_up); 602 603 /** 604 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID 605 * @cpuid: CPU partition ID 606 * 607 * Returns the partition ID corresponding to the CPU partition ID or a 608 * negative error code on failure. 609 */ 610 static int tegra_get_cpu_powergate_id(unsigned int cpuid) 611 { 612 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) 613 return pmc->soc->cpu_powergates[cpuid]; 614 615 return -EINVAL; 616 } 617 618 /** 619 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered 620 * @cpuid: CPU partition ID 621 */ 622 bool tegra_pmc_cpu_is_powered(unsigned int cpuid) 623 { 624 int id; 625 626 id = tegra_get_cpu_powergate_id(cpuid); 627 if (id < 0) 628 return false; 629 630 return tegra_powergate_is_powered(id); 631 } 632 633 /** 634 * tegra_pmc_cpu_power_on() - power on CPU partition 635 * @cpuid: CPU partition ID 636 */ 637 int tegra_pmc_cpu_power_on(unsigned int cpuid) 638 { 639 int id; 640 641 id = tegra_get_cpu_powergate_id(cpuid); 642 if (id < 0) 643 return id; 644 645 return tegra_powergate_set(id, true); 646 } 647 648 /** 649 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition 650 * @cpuid: CPU partition ID 651 */ 652 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid) 653 { 654 int id; 655 656 id = tegra_get_cpu_powergate_id(cpuid); 657 if (id < 0) 658 return id; 659 660 return tegra_powergate_remove_clamping(id); 661 } 662 663 static int tegra_pmc_restart_notify(struct notifier_block *this, 664 unsigned long action, void *data) 665 { 666 const char *cmd = data; 667 u32 value; 668 669 value = readl(pmc->scratch + pmc->soc->regs->scratch0); 670 value &= ~PMC_SCRATCH0_MODE_MASK; 671 672 if (cmd) { 673 if (strcmp(cmd, "recovery") == 0) 674 value |= PMC_SCRATCH0_MODE_RECOVERY; 675 676 if (strcmp(cmd, "bootloader") == 0) 677 value |= PMC_SCRATCH0_MODE_BOOTLOADER; 678 679 if (strcmp(cmd, "forced-recovery") == 0) 680 value |= PMC_SCRATCH0_MODE_RCM; 681 } 682 683 writel(value, pmc->scratch + pmc->soc->regs->scratch0); 684 685 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */ 686 value = tegra_pmc_readl(PMC_CNTRL); 687 value |= PMC_CNTRL_MAIN_RST; 688 tegra_pmc_writel(value, PMC_CNTRL); 689 690 return NOTIFY_DONE; 691 } 692 693 static struct notifier_block tegra_pmc_restart_handler = { 694 .notifier_call = tegra_pmc_restart_notify, 695 .priority = 128, 696 }; 697 698 static int powergate_show(struct seq_file *s, void *data) 699 { 700 unsigned int i; 701 int status; 702 703 seq_printf(s, " powergate powered\n"); 704 seq_printf(s, "------------------\n"); 705 706 for (i = 0; i < pmc->soc->num_powergates; i++) { 707 status = tegra_powergate_is_powered(i); 708 if (status < 0) 709 continue; 710 711 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], 712 status ? "yes" : "no"); 713 } 714 715 return 0; 716 } 717 718 static int powergate_open(struct inode *inode, struct file *file) 719 { 720 return single_open(file, powergate_show, inode->i_private); 721 } 722 723 static const struct file_operations powergate_fops = { 724 .open = powergate_open, 725 .read = seq_read, 726 .llseek = seq_lseek, 727 .release = single_release, 728 }; 729 730 static int tegra_powergate_debugfs_init(void) 731 { 732 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, 733 &powergate_fops); 734 if (!pmc->debugfs) 735 return -ENOMEM; 736 737 return 0; 738 } 739 740 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg, 741 struct device_node *np) 742 { 743 struct clk *clk; 744 unsigned int i, count; 745 int err; 746 747 count = of_clk_get_parent_count(np); 748 if (count == 0) 749 return -ENODEV; 750 751 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL); 752 if (!pg->clks) 753 return -ENOMEM; 754 755 for (i = 0; i < count; i++) { 756 pg->clks[i] = of_clk_get(np, i); 757 if (IS_ERR(pg->clks[i])) { 758 err = PTR_ERR(pg->clks[i]); 759 goto err; 760 } 761 } 762 763 pg->num_clks = count; 764 765 return 0; 766 767 err: 768 while (i--) 769 clk_put(pg->clks[i]); 770 771 kfree(pg->clks); 772 773 return err; 774 } 775 776 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg, 777 struct device_node *np, bool off) 778 { 779 int err; 780 781 pg->reset = of_reset_control_array_get_exclusive(np); 782 if (IS_ERR(pg->reset)) { 783 err = PTR_ERR(pg->reset); 784 pr_err("failed to get device resets: %d\n", err); 785 return err; 786 } 787 788 if (off) 789 err = reset_control_assert(pg->reset); 790 else 791 err = reset_control_deassert(pg->reset); 792 793 if (err) 794 reset_control_put(pg->reset); 795 796 return err; 797 } 798 799 static void tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) 800 { 801 struct tegra_powergate *pg; 802 int id, err; 803 bool off; 804 805 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 806 if (!pg) 807 return; 808 809 id = tegra_powergate_lookup(pmc, np->name); 810 if (id < 0) { 811 pr_err("powergate lookup failed for %pOFn: %d\n", np, id); 812 goto free_mem; 813 } 814 815 /* 816 * Clear the bit for this powergate so it cannot be managed 817 * directly via the legacy APIs for controlling powergates. 818 */ 819 clear_bit(id, pmc->powergates_available); 820 821 pg->id = id; 822 pg->genpd.name = np->name; 823 pg->genpd.power_off = tegra_genpd_power_off; 824 pg->genpd.power_on = tegra_genpd_power_on; 825 pg->pmc = pmc; 826 827 off = !tegra_powergate_is_powered(pg->id); 828 829 err = tegra_powergate_of_get_clks(pg, np); 830 if (err < 0) { 831 pr_err("failed to get clocks for %pOFn: %d\n", np, err); 832 goto set_available; 833 } 834 835 err = tegra_powergate_of_get_resets(pg, np, off); 836 if (err < 0) { 837 pr_err("failed to get resets for %pOFn: %d\n", np, err); 838 goto remove_clks; 839 } 840 841 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) { 842 if (off) 843 WARN_ON(tegra_powergate_power_up(pg, true)); 844 845 goto remove_resets; 846 } 847 848 /* 849 * FIXME: If XHCI is enabled for Tegra, then power-up the XUSB 850 * host and super-speed partitions. Once the XHCI driver 851 * manages the partitions itself this code can be removed. Note 852 * that we don't register these partitions with the genpd core 853 * to avoid it from powering down the partitions as they appear 854 * to be unused. 855 */ 856 if (IS_ENABLED(CONFIG_USB_XHCI_TEGRA) && 857 (id == TEGRA_POWERGATE_XUSBA || id == TEGRA_POWERGATE_XUSBC)) { 858 if (off) 859 WARN_ON(tegra_powergate_power_up(pg, true)); 860 861 goto remove_resets; 862 } 863 864 err = pm_genpd_init(&pg->genpd, NULL, off); 865 if (err < 0) { 866 pr_err("failed to initialise PM domain %pOFn: %d\n", np, 867 err); 868 goto remove_resets; 869 } 870 871 err = of_genpd_add_provider_simple(np, &pg->genpd); 872 if (err < 0) { 873 pr_err("failed to add PM domain provider for %pOFn: %d\n", 874 np, err); 875 goto remove_genpd; 876 } 877 878 pr_debug("added PM domain %s\n", pg->genpd.name); 879 880 return; 881 882 remove_genpd: 883 pm_genpd_remove(&pg->genpd); 884 885 remove_resets: 886 reset_control_put(pg->reset); 887 888 remove_clks: 889 while (pg->num_clks--) 890 clk_put(pg->clks[pg->num_clks]); 891 892 kfree(pg->clks); 893 894 set_available: 895 set_bit(id, pmc->powergates_available); 896 897 free_mem: 898 kfree(pg); 899 } 900 901 static void tegra_powergate_init(struct tegra_pmc *pmc, 902 struct device_node *parent) 903 { 904 struct device_node *np, *child; 905 unsigned int i; 906 907 /* Create a bitmap of the available and valid partitions */ 908 for (i = 0; i < pmc->soc->num_powergates; i++) 909 if (pmc->soc->powergates[i]) 910 set_bit(i, pmc->powergates_available); 911 912 np = of_get_child_by_name(parent, "powergates"); 913 if (!np) 914 return; 915 916 for_each_child_of_node(np, child) 917 tegra_powergate_add(pmc, child); 918 919 of_node_put(np); 920 } 921 922 static const struct tegra_io_pad_soc * 923 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id) 924 { 925 unsigned int i; 926 927 for (i = 0; i < pmc->soc->num_io_pads; i++) 928 if (pmc->soc->io_pads[i].id == id) 929 return &pmc->soc->io_pads[i]; 930 931 return NULL; 932 } 933 934 static int tegra_io_pad_get_dpd_register_bit(enum tegra_io_pad id, 935 unsigned long *request, 936 unsigned long *status, 937 u32 *mask) 938 { 939 const struct tegra_io_pad_soc *pad; 940 941 pad = tegra_io_pad_find(pmc, id); 942 if (!pad) { 943 pr_err("invalid I/O pad ID %u\n", id); 944 return -ENOENT; 945 } 946 947 if (pad->dpd == UINT_MAX) 948 return -ENOTSUPP; 949 950 *mask = BIT(pad->dpd % 32); 951 952 if (pad->dpd < 32) { 953 *status = pmc->soc->regs->dpd_status; 954 *request = pmc->soc->regs->dpd_req; 955 } else { 956 *status = pmc->soc->regs->dpd2_status; 957 *request = pmc->soc->regs->dpd2_req; 958 } 959 960 return 0; 961 } 962 963 static int tegra_io_pad_prepare(enum tegra_io_pad id, unsigned long *request, 964 unsigned long *status, u32 *mask) 965 { 966 unsigned long rate, value; 967 int err; 968 969 err = tegra_io_pad_get_dpd_register_bit(id, request, status, mask); 970 if (err) 971 return err; 972 973 if (pmc->clk) { 974 rate = clk_get_rate(pmc->clk); 975 if (!rate) { 976 pr_err("failed to get clock rate\n"); 977 return -ENODEV; 978 } 979 980 tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE); 981 982 /* must be at least 200 ns, in APB (PCLK) clock cycles */ 983 value = DIV_ROUND_UP(1000000000, rate); 984 value = DIV_ROUND_UP(200, value); 985 tegra_pmc_writel(value, SEL_DPD_TIM); 986 } 987 988 return 0; 989 } 990 991 static int tegra_io_pad_poll(unsigned long offset, u32 mask, 992 u32 val, unsigned long timeout) 993 { 994 u32 value; 995 996 timeout = jiffies + msecs_to_jiffies(timeout); 997 998 while (time_after(timeout, jiffies)) { 999 value = tegra_pmc_readl(offset); 1000 if ((value & mask) == val) 1001 return 0; 1002 1003 usleep_range(250, 1000); 1004 } 1005 1006 return -ETIMEDOUT; 1007 } 1008 1009 static void tegra_io_pad_unprepare(void) 1010 { 1011 if (pmc->clk) 1012 tegra_pmc_writel(DPD_SAMPLE_DISABLE, DPD_SAMPLE); 1013 } 1014 1015 /** 1016 * tegra_io_pad_power_enable() - enable power to I/O pad 1017 * @id: Tegra I/O pad ID for which to enable power 1018 * 1019 * Returns: 0 on success or a negative error code on failure. 1020 */ 1021 int tegra_io_pad_power_enable(enum tegra_io_pad id) 1022 { 1023 unsigned long request, status; 1024 u32 mask; 1025 int err; 1026 1027 mutex_lock(&pmc->powergates_lock); 1028 1029 err = tegra_io_pad_prepare(id, &request, &status, &mask); 1030 if (err < 0) { 1031 pr_err("failed to prepare I/O pad: %d\n", err); 1032 goto unlock; 1033 } 1034 1035 tegra_pmc_writel(IO_DPD_REQ_CODE_OFF | mask, request); 1036 1037 err = tegra_io_pad_poll(status, mask, 0, 250); 1038 if (err < 0) { 1039 pr_err("failed to enable I/O pad: %d\n", err); 1040 goto unlock; 1041 } 1042 1043 tegra_io_pad_unprepare(); 1044 1045 unlock: 1046 mutex_unlock(&pmc->powergates_lock); 1047 return err; 1048 } 1049 EXPORT_SYMBOL(tegra_io_pad_power_enable); 1050 1051 /** 1052 * tegra_io_pad_power_disable() - disable power to I/O pad 1053 * @id: Tegra I/O pad ID for which to disable power 1054 * 1055 * Returns: 0 on success or a negative error code on failure. 1056 */ 1057 int tegra_io_pad_power_disable(enum tegra_io_pad id) 1058 { 1059 unsigned long request, status; 1060 u32 mask; 1061 int err; 1062 1063 mutex_lock(&pmc->powergates_lock); 1064 1065 err = tegra_io_pad_prepare(id, &request, &status, &mask); 1066 if (err < 0) { 1067 pr_err("failed to prepare I/O pad: %d\n", err); 1068 goto unlock; 1069 } 1070 1071 tegra_pmc_writel(IO_DPD_REQ_CODE_ON | mask, request); 1072 1073 err = tegra_io_pad_poll(status, mask, mask, 250); 1074 if (err < 0) { 1075 pr_err("failed to disable I/O pad: %d\n", err); 1076 goto unlock; 1077 } 1078 1079 tegra_io_pad_unprepare(); 1080 1081 unlock: 1082 mutex_unlock(&pmc->powergates_lock); 1083 return err; 1084 } 1085 EXPORT_SYMBOL(tegra_io_pad_power_disable); 1086 1087 static int tegra_io_pad_is_powered(enum tegra_io_pad id) 1088 { 1089 unsigned long request, status; 1090 u32 mask, value; 1091 int err; 1092 1093 err = tegra_io_pad_get_dpd_register_bit(id, &request, &status, &mask); 1094 if (err) 1095 return err; 1096 1097 value = tegra_pmc_readl(status); 1098 1099 return !(value & mask); 1100 } 1101 1102 static int tegra_io_pad_set_voltage(enum tegra_io_pad id, int voltage) 1103 { 1104 const struct tegra_io_pad_soc *pad; 1105 u32 value; 1106 1107 pad = tegra_io_pad_find(pmc, id); 1108 if (!pad) 1109 return -ENOENT; 1110 1111 if (pad->voltage == UINT_MAX) 1112 return -ENOTSUPP; 1113 1114 mutex_lock(&pmc->powergates_lock); 1115 1116 if (pmc->soc->has_impl_33v_pwr) { 1117 value = tegra_pmc_readl(PMC_IMPL_E_33V_PWR); 1118 1119 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) 1120 value &= ~BIT(pad->voltage); 1121 else 1122 value |= BIT(pad->voltage); 1123 1124 tegra_pmc_writel(value, PMC_IMPL_E_33V_PWR); 1125 } else { 1126 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */ 1127 value = tegra_pmc_readl(PMC_PWR_DET); 1128 value |= BIT(pad->voltage); 1129 tegra_pmc_writel(value, PMC_PWR_DET); 1130 1131 /* update I/O voltage */ 1132 value = tegra_pmc_readl(PMC_PWR_DET_VALUE); 1133 1134 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) 1135 value &= ~BIT(pad->voltage); 1136 else 1137 value |= BIT(pad->voltage); 1138 1139 tegra_pmc_writel(value, PMC_PWR_DET_VALUE); 1140 } 1141 1142 mutex_unlock(&pmc->powergates_lock); 1143 1144 usleep_range(100, 250); 1145 1146 return 0; 1147 } 1148 1149 static int tegra_io_pad_get_voltage(enum tegra_io_pad id) 1150 { 1151 const struct tegra_io_pad_soc *pad; 1152 u32 value; 1153 1154 pad = tegra_io_pad_find(pmc, id); 1155 if (!pad) 1156 return -ENOENT; 1157 1158 if (pad->voltage == UINT_MAX) 1159 return -ENOTSUPP; 1160 1161 if (pmc->soc->has_impl_33v_pwr) 1162 value = tegra_pmc_readl(PMC_IMPL_E_33V_PWR); 1163 else 1164 value = tegra_pmc_readl(PMC_PWR_DET_VALUE); 1165 1166 if ((value & BIT(pad->voltage)) == 0) 1167 return TEGRA_IO_PAD_VOLTAGE_1V8; 1168 1169 return TEGRA_IO_PAD_VOLTAGE_3V3; 1170 } 1171 1172 /** 1173 * tegra_io_rail_power_on() - enable power to I/O rail 1174 * @id: Tegra I/O pad ID for which to enable power 1175 * 1176 * See also: tegra_io_pad_power_enable() 1177 */ 1178 int tegra_io_rail_power_on(unsigned int id) 1179 { 1180 return tegra_io_pad_power_enable(id); 1181 } 1182 EXPORT_SYMBOL(tegra_io_rail_power_on); 1183 1184 /** 1185 * tegra_io_rail_power_off() - disable power to I/O rail 1186 * @id: Tegra I/O pad ID for which to disable power 1187 * 1188 * See also: tegra_io_pad_power_disable() 1189 */ 1190 int tegra_io_rail_power_off(unsigned int id) 1191 { 1192 return tegra_io_pad_power_disable(id); 1193 } 1194 EXPORT_SYMBOL(tegra_io_rail_power_off); 1195 1196 #ifdef CONFIG_PM_SLEEP 1197 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) 1198 { 1199 return pmc->suspend_mode; 1200 } 1201 1202 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) 1203 { 1204 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE) 1205 return; 1206 1207 pmc->suspend_mode = mode; 1208 } 1209 1210 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) 1211 { 1212 unsigned long long rate = 0; 1213 u32 value; 1214 1215 switch (mode) { 1216 case TEGRA_SUSPEND_LP1: 1217 rate = 32768; 1218 break; 1219 1220 case TEGRA_SUSPEND_LP2: 1221 rate = clk_get_rate(pmc->clk); 1222 break; 1223 1224 default: 1225 break; 1226 } 1227 1228 if (WARN_ON_ONCE(rate == 0)) 1229 rate = 100000000; 1230 1231 if (rate != pmc->rate) { 1232 u64 ticks; 1233 1234 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; 1235 do_div(ticks, USEC_PER_SEC); 1236 tegra_pmc_writel(ticks, PMC_CPUPWRGOOD_TIMER); 1237 1238 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; 1239 do_div(ticks, USEC_PER_SEC); 1240 tegra_pmc_writel(ticks, PMC_CPUPWROFF_TIMER); 1241 1242 wmb(); 1243 1244 pmc->rate = rate; 1245 } 1246 1247 value = tegra_pmc_readl(PMC_CNTRL); 1248 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; 1249 value |= PMC_CNTRL_CPU_PWRREQ_OE; 1250 tegra_pmc_writel(value, PMC_CNTRL); 1251 } 1252 #endif 1253 1254 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) 1255 { 1256 u32 value, values[2]; 1257 1258 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { 1259 } else { 1260 switch (value) { 1261 case 0: 1262 pmc->suspend_mode = TEGRA_SUSPEND_LP0; 1263 break; 1264 1265 case 1: 1266 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1267 break; 1268 1269 case 2: 1270 pmc->suspend_mode = TEGRA_SUSPEND_LP2; 1271 break; 1272 1273 default: 1274 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1275 break; 1276 } 1277 } 1278 1279 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); 1280 1281 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) 1282 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1283 1284 pmc->cpu_good_time = value; 1285 1286 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) 1287 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1288 1289 pmc->cpu_off_time = value; 1290 1291 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", 1292 values, ARRAY_SIZE(values))) 1293 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1294 1295 pmc->core_osc_time = values[0]; 1296 pmc->core_pmu_time = values[1]; 1297 1298 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) 1299 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1300 1301 pmc->core_off_time = value; 1302 1303 pmc->corereq_high = of_property_read_bool(np, 1304 "nvidia,core-power-req-active-high"); 1305 1306 pmc->sysclkreq_high = of_property_read_bool(np, 1307 "nvidia,sys-clock-req-active-high"); 1308 1309 pmc->combined_req = of_property_read_bool(np, 1310 "nvidia,combined-power-req"); 1311 1312 pmc->cpu_pwr_good_en = of_property_read_bool(np, 1313 "nvidia,cpu-pwr-good-en"); 1314 1315 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, 1316 ARRAY_SIZE(values))) 1317 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) 1318 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1319 1320 pmc->lp0_vec_phys = values[0]; 1321 pmc->lp0_vec_size = values[1]; 1322 1323 return 0; 1324 } 1325 1326 static void tegra_pmc_init(struct tegra_pmc *pmc) 1327 { 1328 if (pmc->soc->init) 1329 pmc->soc->init(pmc); 1330 } 1331 1332 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) 1333 { 1334 static const char disabled[] = "emergency thermal reset disabled"; 1335 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux; 1336 struct device *dev = pmc->dev; 1337 struct device_node *np; 1338 u32 value, checksum; 1339 1340 if (!pmc->soc->has_tsense_reset) 1341 return; 1342 1343 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip"); 1344 if (!np) { 1345 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); 1346 return; 1347 } 1348 1349 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { 1350 dev_err(dev, "I2C controller ID missing, %s.\n", disabled); 1351 goto out; 1352 } 1353 1354 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { 1355 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); 1356 goto out; 1357 } 1358 1359 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { 1360 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); 1361 goto out; 1362 } 1363 1364 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { 1365 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); 1366 goto out; 1367 } 1368 1369 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) 1370 pinmux = 0; 1371 1372 value = tegra_pmc_readl(PMC_SENSOR_CTRL); 1373 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE; 1374 tegra_pmc_writel(value, PMC_SENSOR_CTRL); 1375 1376 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) | 1377 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT); 1378 tegra_pmc_writel(value, PMC_SCRATCH54); 1379 1380 value = PMC_SCRATCH55_RESET_TEGRA; 1381 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT; 1382 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT; 1383 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT; 1384 1385 /* 1386 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will 1387 * contain the checksum and are currently zero, so they are not added. 1388 */ 1389 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff) 1390 + ((value >> 24) & 0xff); 1391 checksum &= 0xff; 1392 checksum = 0x100 - checksum; 1393 1394 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT; 1395 1396 tegra_pmc_writel(value, PMC_SCRATCH55); 1397 1398 value = tegra_pmc_readl(PMC_SENSOR_CTRL); 1399 value |= PMC_SENSOR_CTRL_ENABLE_RST; 1400 tegra_pmc_writel(value, PMC_SENSOR_CTRL); 1401 1402 dev_info(pmc->dev, "emergency thermal reset enabled\n"); 1403 1404 out: 1405 of_node_put(np); 1406 } 1407 1408 static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev) 1409 { 1410 return pmc->soc->num_io_pads; 1411 } 1412 1413 static const char *tegra_io_pad_pinctrl_get_group_name( 1414 struct pinctrl_dev *pctl, unsigned int group) 1415 { 1416 return pmc->soc->io_pads[group].name; 1417 } 1418 1419 static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev, 1420 unsigned int group, 1421 const unsigned int **pins, 1422 unsigned int *num_pins) 1423 { 1424 *pins = &pmc->soc->io_pads[group].id; 1425 *num_pins = 1; 1426 return 0; 1427 } 1428 1429 static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = { 1430 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count, 1431 .get_group_name = tegra_io_pad_pinctrl_get_group_name, 1432 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins, 1433 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 1434 .dt_free_map = pinconf_generic_dt_free_map, 1435 }; 1436 1437 static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev, 1438 unsigned int pin, unsigned long *config) 1439 { 1440 const struct tegra_io_pad_soc *pad = tegra_io_pad_find(pmc, pin); 1441 enum pin_config_param param = pinconf_to_config_param(*config); 1442 int ret; 1443 u32 arg; 1444 1445 if (!pad) 1446 return -EINVAL; 1447 1448 switch (param) { 1449 case PIN_CONFIG_POWER_SOURCE: 1450 ret = tegra_io_pad_get_voltage(pad->id); 1451 if (ret < 0) 1452 return ret; 1453 arg = ret; 1454 break; 1455 case PIN_CONFIG_LOW_POWER_MODE: 1456 ret = tegra_io_pad_is_powered(pad->id); 1457 if (ret < 0) 1458 return ret; 1459 arg = !ret; 1460 break; 1461 default: 1462 return -EINVAL; 1463 } 1464 1465 *config = pinconf_to_config_packed(param, arg); 1466 1467 return 0; 1468 } 1469 1470 static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev, 1471 unsigned int pin, unsigned long *configs, 1472 unsigned int num_configs) 1473 { 1474 const struct tegra_io_pad_soc *pad = tegra_io_pad_find(pmc, pin); 1475 enum pin_config_param param; 1476 unsigned int i; 1477 int err; 1478 u32 arg; 1479 1480 if (!pad) 1481 return -EINVAL; 1482 1483 for (i = 0; i < num_configs; ++i) { 1484 param = pinconf_to_config_param(configs[i]); 1485 arg = pinconf_to_config_argument(configs[i]); 1486 1487 switch (param) { 1488 case PIN_CONFIG_LOW_POWER_MODE: 1489 if (arg) 1490 err = tegra_io_pad_power_disable(pad->id); 1491 else 1492 err = tegra_io_pad_power_enable(pad->id); 1493 if (err) 1494 return err; 1495 break; 1496 case PIN_CONFIG_POWER_SOURCE: 1497 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 && 1498 arg != TEGRA_IO_PAD_VOLTAGE_3V3) 1499 return -EINVAL; 1500 err = tegra_io_pad_set_voltage(pad->id, arg); 1501 if (err) 1502 return err; 1503 break; 1504 default: 1505 return -EINVAL; 1506 } 1507 } 1508 1509 return 0; 1510 } 1511 1512 static const struct pinconf_ops tegra_io_pad_pinconf_ops = { 1513 .pin_config_get = tegra_io_pad_pinconf_get, 1514 .pin_config_set = tegra_io_pad_pinconf_set, 1515 .is_generic = true, 1516 }; 1517 1518 static struct pinctrl_desc tegra_pmc_pctl_desc = { 1519 .pctlops = &tegra_io_pad_pinctrl_ops, 1520 .confops = &tegra_io_pad_pinconf_ops, 1521 }; 1522 1523 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc) 1524 { 1525 int err = 0; 1526 1527 if (!pmc->soc->num_pin_descs) 1528 return 0; 1529 1530 tegra_pmc_pctl_desc.name = dev_name(pmc->dev); 1531 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs; 1532 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs; 1533 1534 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc, 1535 pmc); 1536 if (IS_ERR(pmc->pctl_dev)) { 1537 err = PTR_ERR(pmc->pctl_dev); 1538 dev_err(pmc->dev, "unable to register pinctrl, %d\n", err); 1539 } 1540 1541 return err; 1542 } 1543 1544 static int tegra_pmc_probe(struct platform_device *pdev) 1545 { 1546 void __iomem *base; 1547 struct resource *res; 1548 int err; 1549 1550 /* 1551 * Early initialisation should have configured an initial 1552 * register mapping and setup the soc data pointer. If these 1553 * are not valid then something went badly wrong! 1554 */ 1555 if (WARN_ON(!pmc->base || !pmc->soc)) 1556 return -ENODEV; 1557 1558 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); 1559 if (err < 0) 1560 return err; 1561 1562 /* take over the memory region from the early initialization */ 1563 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1564 base = devm_ioremap_resource(&pdev->dev, res); 1565 if (IS_ERR(base)) 1566 return PTR_ERR(base); 1567 1568 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake"); 1569 if (res) { 1570 pmc->wake = devm_ioremap_resource(&pdev->dev, res); 1571 if (IS_ERR(pmc->wake)) 1572 return PTR_ERR(pmc->wake); 1573 } else { 1574 pmc->wake = base; 1575 } 1576 1577 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag"); 1578 if (res) { 1579 pmc->aotag = devm_ioremap_resource(&pdev->dev, res); 1580 if (IS_ERR(pmc->aotag)) 1581 return PTR_ERR(pmc->aotag); 1582 } else { 1583 pmc->aotag = base; 1584 } 1585 1586 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch"); 1587 if (res) { 1588 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); 1589 if (IS_ERR(pmc->scratch)) 1590 return PTR_ERR(pmc->scratch); 1591 } else { 1592 pmc->scratch = base; 1593 } 1594 1595 pmc->clk = devm_clk_get(&pdev->dev, "pclk"); 1596 if (IS_ERR(pmc->clk)) { 1597 err = PTR_ERR(pmc->clk); 1598 1599 if (err != -ENOENT) { 1600 dev_err(&pdev->dev, "failed to get pclk: %d\n", err); 1601 return err; 1602 } 1603 1604 pmc->clk = NULL; 1605 } 1606 1607 pmc->dev = &pdev->dev; 1608 1609 tegra_pmc_init(pmc); 1610 1611 tegra_pmc_init_tsense_reset(pmc); 1612 1613 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 1614 err = tegra_powergate_debugfs_init(); 1615 if (err < 0) 1616 return err; 1617 } 1618 1619 err = register_restart_handler(&tegra_pmc_restart_handler); 1620 if (err) { 1621 dev_err(&pdev->dev, "unable to register restart handler, %d\n", 1622 err); 1623 goto cleanup_debugfs; 1624 } 1625 1626 err = tegra_pmc_pinctrl_init(pmc); 1627 if (err) 1628 goto cleanup_restart_handler; 1629 1630 mutex_lock(&pmc->powergates_lock); 1631 iounmap(pmc->base); 1632 pmc->base = base; 1633 mutex_unlock(&pmc->powergates_lock); 1634 1635 return 0; 1636 1637 cleanup_restart_handler: 1638 unregister_restart_handler(&tegra_pmc_restart_handler); 1639 cleanup_debugfs: 1640 debugfs_remove(pmc->debugfs); 1641 return err; 1642 } 1643 1644 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 1645 static int tegra_pmc_suspend(struct device *dev) 1646 { 1647 tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41); 1648 1649 return 0; 1650 } 1651 1652 static int tegra_pmc_resume(struct device *dev) 1653 { 1654 tegra_pmc_writel(0x0, PMC_SCRATCH41); 1655 1656 return 0; 1657 } 1658 1659 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume); 1660 1661 #endif 1662 1663 static const char * const tegra20_powergates[] = { 1664 [TEGRA_POWERGATE_CPU] = "cpu", 1665 [TEGRA_POWERGATE_3D] = "3d", 1666 [TEGRA_POWERGATE_VENC] = "venc", 1667 [TEGRA_POWERGATE_VDEC] = "vdec", 1668 [TEGRA_POWERGATE_PCIE] = "pcie", 1669 [TEGRA_POWERGATE_L2] = "l2", 1670 [TEGRA_POWERGATE_MPE] = "mpe", 1671 }; 1672 1673 static const struct tegra_pmc_regs tegra20_pmc_regs = { 1674 .scratch0 = 0x50, 1675 .dpd_req = 0x1b8, 1676 .dpd_status = 0x1bc, 1677 .dpd2_req = 0x1c0, 1678 .dpd2_status = 0x1c4, 1679 }; 1680 1681 static void tegra20_pmc_init(struct tegra_pmc *pmc) 1682 { 1683 u32 value; 1684 1685 /* Always enable CPU power request */ 1686 value = tegra_pmc_readl(PMC_CNTRL); 1687 value |= PMC_CNTRL_CPU_PWRREQ_OE; 1688 tegra_pmc_writel(value, PMC_CNTRL); 1689 1690 value = tegra_pmc_readl(PMC_CNTRL); 1691 1692 if (pmc->sysclkreq_high) 1693 value &= ~PMC_CNTRL_SYSCLK_POLARITY; 1694 else 1695 value |= PMC_CNTRL_SYSCLK_POLARITY; 1696 1697 /* configure the output polarity while the request is tristated */ 1698 tegra_pmc_writel(value, PMC_CNTRL); 1699 1700 /* now enable the request */ 1701 value = tegra_pmc_readl(PMC_CNTRL); 1702 value |= PMC_CNTRL_SYSCLK_OE; 1703 tegra_pmc_writel(value, PMC_CNTRL); 1704 } 1705 1706 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 1707 struct device_node *np, 1708 bool invert) 1709 { 1710 u32 value; 1711 1712 value = tegra_pmc_readl(PMC_CNTRL); 1713 1714 if (invert) 1715 value |= PMC_CNTRL_INTR_POLARITY; 1716 else 1717 value &= ~PMC_CNTRL_INTR_POLARITY; 1718 1719 tegra_pmc_writel(value, PMC_CNTRL); 1720 } 1721 1722 static const struct tegra_pmc_soc tegra20_pmc_soc = { 1723 .num_powergates = ARRAY_SIZE(tegra20_powergates), 1724 .powergates = tegra20_powergates, 1725 .num_cpu_powergates = 0, 1726 .cpu_powergates = NULL, 1727 .has_tsense_reset = false, 1728 .has_gpu_clamps = false, 1729 .num_io_pads = 0, 1730 .io_pads = NULL, 1731 .num_pin_descs = 0, 1732 .pin_descs = NULL, 1733 .regs = &tegra20_pmc_regs, 1734 .init = tegra20_pmc_init, 1735 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 1736 }; 1737 1738 static const char * const tegra30_powergates[] = { 1739 [TEGRA_POWERGATE_CPU] = "cpu0", 1740 [TEGRA_POWERGATE_3D] = "3d0", 1741 [TEGRA_POWERGATE_VENC] = "venc", 1742 [TEGRA_POWERGATE_VDEC] = "vdec", 1743 [TEGRA_POWERGATE_PCIE] = "pcie", 1744 [TEGRA_POWERGATE_L2] = "l2", 1745 [TEGRA_POWERGATE_MPE] = "mpe", 1746 [TEGRA_POWERGATE_HEG] = "heg", 1747 [TEGRA_POWERGATE_SATA] = "sata", 1748 [TEGRA_POWERGATE_CPU1] = "cpu1", 1749 [TEGRA_POWERGATE_CPU2] = "cpu2", 1750 [TEGRA_POWERGATE_CPU3] = "cpu3", 1751 [TEGRA_POWERGATE_CELP] = "celp", 1752 [TEGRA_POWERGATE_3D1] = "3d1", 1753 }; 1754 1755 static const u8 tegra30_cpu_powergates[] = { 1756 TEGRA_POWERGATE_CPU, 1757 TEGRA_POWERGATE_CPU1, 1758 TEGRA_POWERGATE_CPU2, 1759 TEGRA_POWERGATE_CPU3, 1760 }; 1761 1762 static const struct tegra_pmc_soc tegra30_pmc_soc = { 1763 .num_powergates = ARRAY_SIZE(tegra30_powergates), 1764 .powergates = tegra30_powergates, 1765 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), 1766 .cpu_powergates = tegra30_cpu_powergates, 1767 .has_tsense_reset = true, 1768 .has_gpu_clamps = false, 1769 .has_impl_33v_pwr = false, 1770 .num_io_pads = 0, 1771 .io_pads = NULL, 1772 .num_pin_descs = 0, 1773 .pin_descs = NULL, 1774 .regs = &tegra20_pmc_regs, 1775 .init = tegra20_pmc_init, 1776 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 1777 }; 1778 1779 static const char * const tegra114_powergates[] = { 1780 [TEGRA_POWERGATE_CPU] = "crail", 1781 [TEGRA_POWERGATE_3D] = "3d", 1782 [TEGRA_POWERGATE_VENC] = "venc", 1783 [TEGRA_POWERGATE_VDEC] = "vdec", 1784 [TEGRA_POWERGATE_MPE] = "mpe", 1785 [TEGRA_POWERGATE_HEG] = "heg", 1786 [TEGRA_POWERGATE_CPU1] = "cpu1", 1787 [TEGRA_POWERGATE_CPU2] = "cpu2", 1788 [TEGRA_POWERGATE_CPU3] = "cpu3", 1789 [TEGRA_POWERGATE_CELP] = "celp", 1790 [TEGRA_POWERGATE_CPU0] = "cpu0", 1791 [TEGRA_POWERGATE_C0NC] = "c0nc", 1792 [TEGRA_POWERGATE_C1NC] = "c1nc", 1793 [TEGRA_POWERGATE_DIS] = "dis", 1794 [TEGRA_POWERGATE_DISB] = "disb", 1795 [TEGRA_POWERGATE_XUSBA] = "xusba", 1796 [TEGRA_POWERGATE_XUSBB] = "xusbb", 1797 [TEGRA_POWERGATE_XUSBC] = "xusbc", 1798 }; 1799 1800 static const u8 tegra114_cpu_powergates[] = { 1801 TEGRA_POWERGATE_CPU0, 1802 TEGRA_POWERGATE_CPU1, 1803 TEGRA_POWERGATE_CPU2, 1804 TEGRA_POWERGATE_CPU3, 1805 }; 1806 1807 static const struct tegra_pmc_soc tegra114_pmc_soc = { 1808 .num_powergates = ARRAY_SIZE(tegra114_powergates), 1809 .powergates = tegra114_powergates, 1810 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), 1811 .cpu_powergates = tegra114_cpu_powergates, 1812 .has_tsense_reset = true, 1813 .has_gpu_clamps = false, 1814 .has_impl_33v_pwr = false, 1815 .num_io_pads = 0, 1816 .io_pads = NULL, 1817 .num_pin_descs = 0, 1818 .pin_descs = NULL, 1819 .regs = &tegra20_pmc_regs, 1820 .init = tegra20_pmc_init, 1821 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 1822 }; 1823 1824 static const char * const tegra124_powergates[] = { 1825 [TEGRA_POWERGATE_CPU] = "crail", 1826 [TEGRA_POWERGATE_3D] = "3d", 1827 [TEGRA_POWERGATE_VENC] = "venc", 1828 [TEGRA_POWERGATE_PCIE] = "pcie", 1829 [TEGRA_POWERGATE_VDEC] = "vdec", 1830 [TEGRA_POWERGATE_MPE] = "mpe", 1831 [TEGRA_POWERGATE_HEG] = "heg", 1832 [TEGRA_POWERGATE_SATA] = "sata", 1833 [TEGRA_POWERGATE_CPU1] = "cpu1", 1834 [TEGRA_POWERGATE_CPU2] = "cpu2", 1835 [TEGRA_POWERGATE_CPU3] = "cpu3", 1836 [TEGRA_POWERGATE_CELP] = "celp", 1837 [TEGRA_POWERGATE_CPU0] = "cpu0", 1838 [TEGRA_POWERGATE_C0NC] = "c0nc", 1839 [TEGRA_POWERGATE_C1NC] = "c1nc", 1840 [TEGRA_POWERGATE_SOR] = "sor", 1841 [TEGRA_POWERGATE_DIS] = "dis", 1842 [TEGRA_POWERGATE_DISB] = "disb", 1843 [TEGRA_POWERGATE_XUSBA] = "xusba", 1844 [TEGRA_POWERGATE_XUSBB] = "xusbb", 1845 [TEGRA_POWERGATE_XUSBC] = "xusbc", 1846 [TEGRA_POWERGATE_VIC] = "vic", 1847 [TEGRA_POWERGATE_IRAM] = "iram", 1848 }; 1849 1850 static const u8 tegra124_cpu_powergates[] = { 1851 TEGRA_POWERGATE_CPU0, 1852 TEGRA_POWERGATE_CPU1, 1853 TEGRA_POWERGATE_CPU2, 1854 TEGRA_POWERGATE_CPU3, 1855 }; 1856 1857 #define TEGRA_IO_PAD(_id, _dpd, _voltage, _name) \ 1858 ((struct tegra_io_pad_soc) { \ 1859 .id = (_id), \ 1860 .dpd = (_dpd), \ 1861 .voltage = (_voltage), \ 1862 .name = (_name), \ 1863 }) 1864 1865 #define TEGRA_IO_PIN_DESC(_id, _dpd, _voltage, _name) \ 1866 ((struct pinctrl_pin_desc) { \ 1867 .number = (_id), \ 1868 .name = (_name) \ 1869 }) 1870 1871 #define TEGRA124_IO_PAD_TABLE(_pad) \ 1872 /* .id .dpd .voltage .name */ \ 1873 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \ 1874 _pad(TEGRA_IO_PAD_BB, 15, UINT_MAX, "bb"), \ 1875 _pad(TEGRA_IO_PAD_CAM, 36, UINT_MAX, "cam"), \ 1876 _pad(TEGRA_IO_PAD_COMP, 22, UINT_MAX, "comp"), \ 1877 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 1878 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csb"), \ 1879 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "cse"), \ 1880 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ 1881 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \ 1882 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \ 1883 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \ 1884 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \ 1885 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ 1886 _pad(TEGRA_IO_PAD_HV, 38, UINT_MAX, "hv"), \ 1887 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \ 1888 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 1889 _pad(TEGRA_IO_PAD_NAND, 13, UINT_MAX, "nand"), \ 1890 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \ 1891 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \ 1892 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 1893 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \ 1894 _pad(TEGRA_IO_PAD_SDMMC1, 33, UINT_MAX, "sdmmc1"), \ 1895 _pad(TEGRA_IO_PAD_SDMMC3, 34, UINT_MAX, "sdmmc3"), \ 1896 _pad(TEGRA_IO_PAD_SDMMC4, 35, UINT_MAX, "sdmmc4"), \ 1897 _pad(TEGRA_IO_PAD_SYS_DDC, 58, UINT_MAX, "sys_ddc"), \ 1898 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \ 1899 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ 1900 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ 1901 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ 1902 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb_bias") 1903 1904 static const struct tegra_io_pad_soc tegra124_io_pads[] = { 1905 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PAD) 1906 }; 1907 1908 static const struct pinctrl_pin_desc tegra124_pin_descs[] = { 1909 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 1910 }; 1911 1912 static const struct tegra_pmc_soc tegra124_pmc_soc = { 1913 .num_powergates = ARRAY_SIZE(tegra124_powergates), 1914 .powergates = tegra124_powergates, 1915 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), 1916 .cpu_powergates = tegra124_cpu_powergates, 1917 .has_tsense_reset = true, 1918 .has_gpu_clamps = true, 1919 .has_impl_33v_pwr = false, 1920 .num_io_pads = ARRAY_SIZE(tegra124_io_pads), 1921 .io_pads = tegra124_io_pads, 1922 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs), 1923 .pin_descs = tegra124_pin_descs, 1924 .regs = &tegra20_pmc_regs, 1925 .init = tegra20_pmc_init, 1926 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 1927 }; 1928 1929 static const char * const tegra210_powergates[] = { 1930 [TEGRA_POWERGATE_CPU] = "crail", 1931 [TEGRA_POWERGATE_3D] = "3d", 1932 [TEGRA_POWERGATE_VENC] = "venc", 1933 [TEGRA_POWERGATE_PCIE] = "pcie", 1934 [TEGRA_POWERGATE_MPE] = "mpe", 1935 [TEGRA_POWERGATE_SATA] = "sata", 1936 [TEGRA_POWERGATE_CPU1] = "cpu1", 1937 [TEGRA_POWERGATE_CPU2] = "cpu2", 1938 [TEGRA_POWERGATE_CPU3] = "cpu3", 1939 [TEGRA_POWERGATE_CPU0] = "cpu0", 1940 [TEGRA_POWERGATE_C0NC] = "c0nc", 1941 [TEGRA_POWERGATE_SOR] = "sor", 1942 [TEGRA_POWERGATE_DIS] = "dis", 1943 [TEGRA_POWERGATE_DISB] = "disb", 1944 [TEGRA_POWERGATE_XUSBA] = "xusba", 1945 [TEGRA_POWERGATE_XUSBB] = "xusbb", 1946 [TEGRA_POWERGATE_XUSBC] = "xusbc", 1947 [TEGRA_POWERGATE_VIC] = "vic", 1948 [TEGRA_POWERGATE_IRAM] = "iram", 1949 [TEGRA_POWERGATE_NVDEC] = "nvdec", 1950 [TEGRA_POWERGATE_NVJPG] = "nvjpg", 1951 [TEGRA_POWERGATE_AUD] = "aud", 1952 [TEGRA_POWERGATE_DFD] = "dfd", 1953 [TEGRA_POWERGATE_VE2] = "ve2", 1954 }; 1955 1956 static const u8 tegra210_cpu_powergates[] = { 1957 TEGRA_POWERGATE_CPU0, 1958 TEGRA_POWERGATE_CPU1, 1959 TEGRA_POWERGATE_CPU2, 1960 TEGRA_POWERGATE_CPU3, 1961 }; 1962 1963 #define TEGRA210_IO_PAD_TABLE(_pad) \ 1964 /* .id .dpd .voltage .name */ \ 1965 _pad(TEGRA_IO_PAD_AUDIO, 17, 5, "audio"), \ 1966 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 18, "audio-hv"), \ 1967 _pad(TEGRA_IO_PAD_CAM, 36, 10, "cam"), \ 1968 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 1969 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \ 1970 _pad(TEGRA_IO_PAD_CSIC, 42, UINT_MAX, "csic"), \ 1971 _pad(TEGRA_IO_PAD_CSID, 43, UINT_MAX, "csid"), \ 1972 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "csie"), \ 1973 _pad(TEGRA_IO_PAD_CSIF, 45, UINT_MAX, "csif"), \ 1974 _pad(TEGRA_IO_PAD_DBG, 25, 19, "dbg"), \ 1975 _pad(TEGRA_IO_PAD_DEBUG_NONAO, 26, UINT_MAX, "debug-nonao"), \ 1976 _pad(TEGRA_IO_PAD_DMIC, 50, 20, "dmic"), \ 1977 _pad(TEGRA_IO_PAD_DP, 51, UINT_MAX, "dp"), \ 1978 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ 1979 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \ 1980 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \ 1981 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \ 1982 _pad(TEGRA_IO_PAD_EMMC, 35, UINT_MAX, "emmc"), \ 1983 _pad(TEGRA_IO_PAD_EMMC2, 37, UINT_MAX, "emmc2"), \ 1984 _pad(TEGRA_IO_PAD_GPIO, 27, 21, "gpio"), \ 1985 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \ 1986 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ 1987 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \ 1988 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 1989 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \ 1990 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \ 1991 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 1992 _pad(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, 11, "pex-cntrl"), \ 1993 _pad(TEGRA_IO_PAD_SDMMC1, 33, 12, "sdmmc1"), \ 1994 _pad(TEGRA_IO_PAD_SDMMC3, 34, 13, "sdmmc3"), \ 1995 _pad(TEGRA_IO_PAD_SPI, 46, 22, "spi"), \ 1996 _pad(TEGRA_IO_PAD_SPI_HV, 47, 23, "spi-hv"), \ 1997 _pad(TEGRA_IO_PAD_UART, 14, 2, "uart"), \ 1998 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ 1999 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ 2000 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ 2001 _pad(TEGRA_IO_PAD_USB3, 18, UINT_MAX, "usb3"), \ 2002 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias") 2003 2004 static const struct tegra_io_pad_soc tegra210_io_pads[] = { 2005 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PAD) 2006 }; 2007 2008 static const struct pinctrl_pin_desc tegra210_pin_descs[] = { 2009 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 2010 }; 2011 2012 static const struct tegra_pmc_soc tegra210_pmc_soc = { 2013 .num_powergates = ARRAY_SIZE(tegra210_powergates), 2014 .powergates = tegra210_powergates, 2015 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates), 2016 .cpu_powergates = tegra210_cpu_powergates, 2017 .has_tsense_reset = true, 2018 .has_gpu_clamps = true, 2019 .has_impl_33v_pwr = false, 2020 .needs_mbist_war = true, 2021 .num_io_pads = ARRAY_SIZE(tegra210_io_pads), 2022 .io_pads = tegra210_io_pads, 2023 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs), 2024 .pin_descs = tegra210_pin_descs, 2025 .regs = &tegra20_pmc_regs, 2026 .init = tegra20_pmc_init, 2027 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 2028 }; 2029 2030 #define TEGRA186_IO_PAD_TABLE(_pad) \ 2031 /* .id .dpd .voltage .name */ \ 2032 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 2033 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \ 2034 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ 2035 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 2036 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \ 2037 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \ 2038 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 2039 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \ 2040 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ 2041 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ 2042 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ 2043 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias"), \ 2044 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \ 2045 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \ 2046 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ 2047 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \ 2048 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \ 2049 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \ 2050 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \ 2051 _pad(TEGRA_IO_PAD_SDMMC2_HV, 34, 5, "sdmmc2-hv"), \ 2052 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \ 2053 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \ 2054 _pad(TEGRA_IO_PAD_DSIB, 40, UINT_MAX, "dsib"), \ 2055 _pad(TEGRA_IO_PAD_DSIC, 41, UINT_MAX, "dsic"), \ 2056 _pad(TEGRA_IO_PAD_DSID, 42, UINT_MAX, "dsid"), \ 2057 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \ 2058 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \ 2059 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \ 2060 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \ 2061 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \ 2062 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \ 2063 _pad(TEGRA_IO_PAD_DMIC_HV, 52, 2, "dmic-hv"), \ 2064 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \ 2065 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \ 2066 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \ 2067 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \ 2068 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \ 2069 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv") 2070 2071 static const struct tegra_io_pad_soc tegra186_io_pads[] = { 2072 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PAD) 2073 }; 2074 2075 static const struct pinctrl_pin_desc tegra186_pin_descs[] = { 2076 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 2077 }; 2078 2079 static const struct tegra_pmc_regs tegra186_pmc_regs = { 2080 .scratch0 = 0x2000, 2081 .dpd_req = 0x74, 2082 .dpd_status = 0x78, 2083 .dpd2_req = 0x7c, 2084 .dpd2_status = 0x80, 2085 }; 2086 2087 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 2088 struct device_node *np, 2089 bool invert) 2090 { 2091 struct resource regs; 2092 void __iomem *wake; 2093 u32 value; 2094 int index; 2095 2096 index = of_property_match_string(np, "reg-names", "wake"); 2097 if (index < 0) { 2098 pr_err("failed to find PMC wake registers\n"); 2099 return; 2100 } 2101 2102 of_address_to_resource(np, index, ®s); 2103 2104 wake = ioremap_nocache(regs.start, resource_size(®s)); 2105 if (!wake) { 2106 pr_err("failed to map PMC wake registers\n"); 2107 return; 2108 } 2109 2110 value = readl(wake + WAKE_AOWAKE_CTRL); 2111 2112 if (invert) 2113 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY; 2114 else 2115 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY; 2116 2117 writel(value, wake + WAKE_AOWAKE_CTRL); 2118 2119 iounmap(wake); 2120 } 2121 2122 static const struct tegra_pmc_soc tegra186_pmc_soc = { 2123 .num_powergates = 0, 2124 .powergates = NULL, 2125 .num_cpu_powergates = 0, 2126 .cpu_powergates = NULL, 2127 .has_tsense_reset = false, 2128 .has_gpu_clamps = false, 2129 .has_impl_33v_pwr = true, 2130 .num_io_pads = ARRAY_SIZE(tegra186_io_pads), 2131 .io_pads = tegra186_io_pads, 2132 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs), 2133 .pin_descs = tegra186_pin_descs, 2134 .regs = &tegra186_pmc_regs, 2135 .init = NULL, 2136 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 2137 }; 2138 2139 static const struct of_device_id tegra_pmc_match[] = { 2140 { .compatible = "nvidia,tegra194-pmc", .data = &tegra186_pmc_soc }, 2141 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc }, 2142 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc }, 2143 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc }, 2144 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc }, 2145 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc }, 2146 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc }, 2147 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc }, 2148 { } 2149 }; 2150 2151 static struct platform_driver tegra_pmc_driver = { 2152 .driver = { 2153 .name = "tegra-pmc", 2154 .suppress_bind_attrs = true, 2155 .of_match_table = tegra_pmc_match, 2156 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 2157 .pm = &tegra_pmc_pm_ops, 2158 #endif 2159 }, 2160 .probe = tegra_pmc_probe, 2161 }; 2162 builtin_platform_driver(tegra_pmc_driver); 2163 2164 /* 2165 * Early initialization to allow access to registers in the very early boot 2166 * process. 2167 */ 2168 static int __init tegra_pmc_early_init(void) 2169 { 2170 const struct of_device_id *match; 2171 struct device_node *np; 2172 struct resource regs; 2173 bool invert; 2174 2175 mutex_init(&pmc->powergates_lock); 2176 2177 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match); 2178 if (!np) { 2179 /* 2180 * Fall back to legacy initialization for 32-bit ARM only. All 2181 * 64-bit ARM device tree files for Tegra are required to have 2182 * a PMC node. 2183 * 2184 * This is for backwards-compatibility with old device trees 2185 * that didn't contain a PMC node. Note that in this case the 2186 * SoC data can't be matched and therefore powergating is 2187 * disabled. 2188 */ 2189 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 2190 pr_warn("DT node not found, powergating disabled\n"); 2191 2192 regs.start = 0x7000e400; 2193 regs.end = 0x7000e7ff; 2194 regs.flags = IORESOURCE_MEM; 2195 2196 pr_warn("Using memory region %pR\n", ®s); 2197 } else { 2198 /* 2199 * At this point we're not running on Tegra, so play 2200 * nice with multi-platform kernels. 2201 */ 2202 return 0; 2203 } 2204 } else { 2205 /* 2206 * Extract information from the device tree if we've found a 2207 * matching node. 2208 */ 2209 if (of_address_to_resource(np, 0, ®s) < 0) { 2210 pr_err("failed to get PMC registers\n"); 2211 of_node_put(np); 2212 return -ENXIO; 2213 } 2214 } 2215 2216 pmc->base = ioremap_nocache(regs.start, resource_size(®s)); 2217 if (!pmc->base) { 2218 pr_err("failed to map PMC registers\n"); 2219 of_node_put(np); 2220 return -ENXIO; 2221 } 2222 2223 if (np) { 2224 pmc->soc = match->data; 2225 2226 tegra_powergate_init(pmc, np); 2227 2228 /* 2229 * Invert the interrupt polarity if a PMC device tree node 2230 * exists and contains the nvidia,invert-interrupt property. 2231 */ 2232 invert = of_property_read_bool(np, "nvidia,invert-interrupt"); 2233 2234 pmc->soc->setup_irq_polarity(pmc, np, invert); 2235 2236 of_node_put(np); 2237 } 2238 2239 return 0; 2240 } 2241 early_initcall(tegra_pmc_early_init); 2242