1 /* 2 * drivers/soc/tegra/pmc.c 3 * 4 * Copyright (c) 2010 Google, Inc 5 * 6 * Author: 7 * Colin Cross <ccross@google.com> 8 * 9 * This software is licensed under the terms of the GNU General Public 10 * License version 2, as published by the Free Software Foundation, and 11 * may be copied, distributed, and modified under those terms. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 */ 19 20 #define pr_fmt(fmt) "tegra-pmc: " fmt 21 22 #include <linux/kernel.h> 23 #include <linux/clk.h> 24 #include <linux/clk/tegra.h> 25 #include <linux/debugfs.h> 26 #include <linux/delay.h> 27 #include <linux/err.h> 28 #include <linux/export.h> 29 #include <linux/init.h> 30 #include <linux/io.h> 31 #include <linux/iopoll.h> 32 #include <linux/of.h> 33 #include <linux/of_address.h> 34 #include <linux/of_platform.h> 35 #include <linux/platform_device.h> 36 #include <linux/pm_domain.h> 37 #include <linux/reboot.h> 38 #include <linux/reset.h> 39 #include <linux/seq_file.h> 40 #include <linux/slab.h> 41 #include <linux/spinlock.h> 42 43 #include <soc/tegra/common.h> 44 #include <soc/tegra/fuse.h> 45 #include <soc/tegra/pmc.h> 46 47 #define PMC_CNTRL 0x0 48 #define PMC_CNTRL_SYSCLK_POLARITY (1 << 10) /* sys clk polarity */ 49 #define PMC_CNTRL_SYSCLK_OE (1 << 11) /* system clock enable */ 50 #define PMC_CNTRL_SIDE_EFFECT_LP0 (1 << 14) /* LP0 when CPU pwr gated */ 51 #define PMC_CNTRL_CPU_PWRREQ_POLARITY (1 << 15) /* CPU pwr req polarity */ 52 #define PMC_CNTRL_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */ 53 #define PMC_CNTRL_INTR_POLARITY (1 << 17) /* inverts INTR polarity */ 54 55 #define DPD_SAMPLE 0x020 56 #define DPD_SAMPLE_ENABLE (1 << 0) 57 #define DPD_SAMPLE_DISABLE (0 << 0) 58 59 #define PWRGATE_TOGGLE 0x30 60 #define PWRGATE_TOGGLE_START (1 << 8) 61 62 #define REMOVE_CLAMPING 0x34 63 64 #define PWRGATE_STATUS 0x38 65 66 #define PMC_SCRATCH0 0x50 67 #define PMC_SCRATCH0_MODE_RECOVERY (1 << 31) 68 #define PMC_SCRATCH0_MODE_BOOTLOADER (1 << 30) 69 #define PMC_SCRATCH0_MODE_RCM (1 << 1) 70 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ 71 PMC_SCRATCH0_MODE_BOOTLOADER | \ 72 PMC_SCRATCH0_MODE_RCM) 73 74 #define PMC_CPUPWRGOOD_TIMER 0xc8 75 #define PMC_CPUPWROFF_TIMER 0xcc 76 77 #define PMC_SCRATCH41 0x140 78 79 #define PMC_SENSOR_CTRL 0x1b0 80 #define PMC_SENSOR_CTRL_SCRATCH_WRITE (1 << 2) 81 #define PMC_SENSOR_CTRL_ENABLE_RST (1 << 1) 82 83 #define IO_DPD_REQ 0x1b8 84 #define IO_DPD_REQ_CODE_IDLE (0 << 30) 85 #define IO_DPD_REQ_CODE_OFF (1 << 30) 86 #define IO_DPD_REQ_CODE_ON (2 << 30) 87 #define IO_DPD_REQ_CODE_MASK (3 << 30) 88 89 #define IO_DPD_STATUS 0x1bc 90 #define IO_DPD2_REQ 0x1c0 91 #define IO_DPD2_STATUS 0x1c4 92 #define SEL_DPD_TIM 0x1c8 93 94 #define PMC_SCRATCH54 0x258 95 #define PMC_SCRATCH54_DATA_SHIFT 8 96 #define PMC_SCRATCH54_ADDR_SHIFT 0 97 98 #define PMC_SCRATCH55 0x25c 99 #define PMC_SCRATCH55_RESET_TEGRA (1 << 31) 100 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27 101 #define PMC_SCRATCH55_PINMUX_SHIFT 24 102 #define PMC_SCRATCH55_16BITOP (1 << 15) 103 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16 104 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0 105 106 #define GPU_RG_CNTRL 0x2d4 107 108 struct tegra_powergate { 109 struct generic_pm_domain genpd; 110 struct tegra_pmc *pmc; 111 unsigned int id; 112 struct clk **clks; 113 unsigned int num_clks; 114 struct reset_control **resets; 115 unsigned int num_resets; 116 }; 117 118 struct tegra_pmc_soc { 119 unsigned int num_powergates; 120 const char *const *powergates; 121 unsigned int num_cpu_powergates; 122 const u8 *cpu_powergates; 123 124 bool has_tsense_reset; 125 bool has_gpu_clamps; 126 }; 127 128 /** 129 * struct tegra_pmc - NVIDIA Tegra PMC 130 * @dev: pointer to PMC device structure 131 * @base: pointer to I/O remapped register region 132 * @clk: pointer to pclk clock 133 * @soc: pointer to SoC data structure 134 * @debugfs: pointer to debugfs entry 135 * @rate: currently configured rate of pclk 136 * @suspend_mode: lowest suspend mode available 137 * @cpu_good_time: CPU power good time (in microseconds) 138 * @cpu_off_time: CPU power off time (in microsecends) 139 * @core_osc_time: core power good OSC time (in microseconds) 140 * @core_pmu_time: core power good PMU time (in microseconds) 141 * @core_off_time: core power off time (in microseconds) 142 * @corereq_high: core power request is active-high 143 * @sysclkreq_high: system clock request is active-high 144 * @combined_req: combined power request for CPU & core 145 * @cpu_pwr_good_en: CPU power good signal is enabled 146 * @lp0_vec_phys: physical base address of the LP0 warm boot code 147 * @lp0_vec_size: size of the LP0 warm boot code 148 * @powergates_available: Bitmap of available power gates 149 * @powergates_lock: mutex for power gate register access 150 */ 151 struct tegra_pmc { 152 struct device *dev; 153 void __iomem *base; 154 struct clk *clk; 155 struct dentry *debugfs; 156 157 const struct tegra_pmc_soc *soc; 158 159 unsigned long rate; 160 161 enum tegra_suspend_mode suspend_mode; 162 u32 cpu_good_time; 163 u32 cpu_off_time; 164 u32 core_osc_time; 165 u32 core_pmu_time; 166 u32 core_off_time; 167 bool corereq_high; 168 bool sysclkreq_high; 169 bool combined_req; 170 bool cpu_pwr_good_en; 171 u32 lp0_vec_phys; 172 u32 lp0_vec_size; 173 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX); 174 175 struct mutex powergates_lock; 176 }; 177 178 static struct tegra_pmc *pmc = &(struct tegra_pmc) { 179 .base = NULL, 180 .suspend_mode = TEGRA_SUSPEND_NONE, 181 }; 182 183 static inline struct tegra_powergate * 184 to_powergate(struct generic_pm_domain *domain) 185 { 186 return container_of(domain, struct tegra_powergate, genpd); 187 } 188 189 static u32 tegra_pmc_readl(unsigned long offset) 190 { 191 return readl(pmc->base + offset); 192 } 193 194 static void tegra_pmc_writel(u32 value, unsigned long offset) 195 { 196 writel(value, pmc->base + offset); 197 } 198 199 static inline bool tegra_powergate_state(int id) 200 { 201 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 202 return (tegra_pmc_readl(GPU_RG_CNTRL) & 0x1) == 0; 203 else 204 return (tegra_pmc_readl(PWRGATE_STATUS) & BIT(id)) != 0; 205 } 206 207 static inline bool tegra_powergate_is_valid(int id) 208 { 209 return (pmc->soc && pmc->soc->powergates[id]); 210 } 211 212 static inline bool tegra_powergate_is_available(int id) 213 { 214 return test_bit(id, pmc->powergates_available); 215 } 216 217 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) 218 { 219 unsigned int i; 220 221 if (!pmc || !pmc->soc || !name) 222 return -EINVAL; 223 224 for (i = 0; i < pmc->soc->num_powergates; i++) { 225 if (!tegra_powergate_is_valid(i)) 226 continue; 227 228 if (!strcmp(name, pmc->soc->powergates[i])) 229 return i; 230 } 231 232 dev_err(pmc->dev, "powergate %s not found\n", name); 233 234 return -ENODEV; 235 } 236 237 /** 238 * tegra_powergate_set() - set the state of a partition 239 * @id: partition ID 240 * @new_state: new state of the partition 241 */ 242 static int tegra_powergate_set(unsigned int id, bool new_state) 243 { 244 bool status; 245 int err; 246 247 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 248 return -EINVAL; 249 250 mutex_lock(&pmc->powergates_lock); 251 252 if (tegra_powergate_state(id) == new_state) { 253 mutex_unlock(&pmc->powergates_lock); 254 return 0; 255 } 256 257 tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 258 259 err = readx_poll_timeout(tegra_powergate_state, id, status, 260 status == new_state, 10, 100000); 261 262 mutex_unlock(&pmc->powergates_lock); 263 264 return err; 265 } 266 267 static int __tegra_powergate_remove_clamping(unsigned int id) 268 { 269 u32 mask; 270 271 mutex_lock(&pmc->powergates_lock); 272 273 /* 274 * On Tegra124 and later, the clamps for the GPU are controlled by a 275 * separate register (with different semantics). 276 */ 277 if (id == TEGRA_POWERGATE_3D) { 278 if (pmc->soc->has_gpu_clamps) { 279 tegra_pmc_writel(0, GPU_RG_CNTRL); 280 goto out; 281 } 282 } 283 284 /* 285 * Tegra 2 has a bug where PCIE and VDE clamping masks are 286 * swapped relatively to the partition ids 287 */ 288 if (id == TEGRA_POWERGATE_VDEC) 289 mask = (1 << TEGRA_POWERGATE_PCIE); 290 else if (id == TEGRA_POWERGATE_PCIE) 291 mask = (1 << TEGRA_POWERGATE_VDEC); 292 else 293 mask = (1 << id); 294 295 tegra_pmc_writel(mask, REMOVE_CLAMPING); 296 297 out: 298 mutex_unlock(&pmc->powergates_lock); 299 300 return 0; 301 } 302 303 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg) 304 { 305 unsigned int i; 306 307 for (i = 0; i < pg->num_clks; i++) 308 clk_disable_unprepare(pg->clks[i]); 309 } 310 311 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg) 312 { 313 unsigned int i; 314 int err; 315 316 for (i = 0; i < pg->num_clks; i++) { 317 err = clk_prepare_enable(pg->clks[i]); 318 if (err) 319 goto out; 320 } 321 322 return 0; 323 324 out: 325 while (i--) 326 clk_disable_unprepare(pg->clks[i]); 327 328 return err; 329 } 330 331 static int tegra_powergate_reset_assert(struct tegra_powergate *pg) 332 { 333 unsigned int i; 334 int err; 335 336 for (i = 0; i < pg->num_resets; i++) { 337 err = reset_control_assert(pg->resets[i]); 338 if (err) 339 return err; 340 } 341 342 return 0; 343 } 344 345 static int tegra_powergate_reset_deassert(struct tegra_powergate *pg) 346 { 347 unsigned int i; 348 int err; 349 350 for (i = 0; i < pg->num_resets; i++) { 351 err = reset_control_deassert(pg->resets[i]); 352 if (err) 353 return err; 354 } 355 356 return 0; 357 } 358 359 static int tegra_powergate_power_up(struct tegra_powergate *pg, 360 bool disable_clocks) 361 { 362 int err; 363 364 err = tegra_powergate_reset_assert(pg); 365 if (err) 366 return err; 367 368 usleep_range(10, 20); 369 370 err = tegra_powergate_set(pg->id, true); 371 if (err < 0) 372 return err; 373 374 usleep_range(10, 20); 375 376 err = tegra_powergate_enable_clocks(pg); 377 if (err) 378 goto disable_clks; 379 380 usleep_range(10, 20); 381 382 err = __tegra_powergate_remove_clamping(pg->id); 383 if (err) 384 goto disable_clks; 385 386 usleep_range(10, 20); 387 388 err = tegra_powergate_reset_deassert(pg); 389 if (err) 390 goto powergate_off; 391 392 usleep_range(10, 20); 393 394 if (disable_clocks) 395 tegra_powergate_disable_clocks(pg); 396 397 return 0; 398 399 disable_clks: 400 tegra_powergate_disable_clocks(pg); 401 usleep_range(10, 20); 402 powergate_off: 403 tegra_powergate_set(pg->id, false); 404 405 return err; 406 } 407 408 static int tegra_powergate_power_down(struct tegra_powergate *pg) 409 { 410 int err; 411 412 err = tegra_powergate_enable_clocks(pg); 413 if (err) 414 return err; 415 416 usleep_range(10, 20); 417 418 err = tegra_powergate_reset_assert(pg); 419 if (err) 420 goto disable_clks; 421 422 usleep_range(10, 20); 423 424 tegra_powergate_disable_clocks(pg); 425 426 usleep_range(10, 20); 427 428 err = tegra_powergate_set(pg->id, false); 429 if (err) 430 goto assert_resets; 431 432 return 0; 433 434 assert_resets: 435 tegra_powergate_enable_clocks(pg); 436 usleep_range(10, 20); 437 tegra_powergate_reset_deassert(pg); 438 usleep_range(10, 20); 439 disable_clks: 440 tegra_powergate_disable_clocks(pg); 441 442 return err; 443 } 444 445 static int tegra_genpd_power_on(struct generic_pm_domain *domain) 446 { 447 struct tegra_powergate *pg = to_powergate(domain); 448 struct tegra_pmc *pmc = pg->pmc; 449 int err; 450 451 err = tegra_powergate_power_up(pg, true); 452 if (err) 453 dev_err(pmc->dev, "failed to turn on PM domain %s: %d\n", 454 pg->genpd.name, err); 455 456 return err; 457 } 458 459 static int tegra_genpd_power_off(struct generic_pm_domain *domain) 460 { 461 struct tegra_powergate *pg = to_powergate(domain); 462 struct tegra_pmc *pmc = pg->pmc; 463 int err; 464 465 err = tegra_powergate_power_down(pg); 466 if (err) 467 dev_err(pmc->dev, "failed to turn off PM domain %s: %d\n", 468 pg->genpd.name, err); 469 470 return err; 471 } 472 473 /** 474 * tegra_powergate_power_on() - power on partition 475 * @id: partition ID 476 */ 477 int tegra_powergate_power_on(unsigned int id) 478 { 479 if (!tegra_powergate_is_available(id)) 480 return -EINVAL; 481 482 return tegra_powergate_set(id, true); 483 } 484 485 /** 486 * tegra_powergate_power_off() - power off partition 487 * @id: partition ID 488 */ 489 int tegra_powergate_power_off(unsigned int id) 490 { 491 if (!tegra_powergate_is_available(id)) 492 return -EINVAL; 493 494 return tegra_powergate_set(id, false); 495 } 496 EXPORT_SYMBOL(tegra_powergate_power_off); 497 498 /** 499 * tegra_powergate_is_powered() - check if partition is powered 500 * @id: partition ID 501 */ 502 int tegra_powergate_is_powered(unsigned int id) 503 { 504 int status; 505 506 if (!tegra_powergate_is_valid(id)) 507 return -EINVAL; 508 509 mutex_lock(&pmc->powergates_lock); 510 status = tegra_powergate_state(id); 511 mutex_unlock(&pmc->powergates_lock); 512 513 return status; 514 } 515 516 /** 517 * tegra_powergate_remove_clamping() - remove power clamps for partition 518 * @id: partition ID 519 */ 520 int tegra_powergate_remove_clamping(unsigned int id) 521 { 522 if (!tegra_powergate_is_available(id)) 523 return -EINVAL; 524 525 return __tegra_powergate_remove_clamping(id); 526 } 527 EXPORT_SYMBOL(tegra_powergate_remove_clamping); 528 529 /** 530 * tegra_powergate_sequence_power_up() - power up partition 531 * @id: partition ID 532 * @clk: clock for partition 533 * @rst: reset for partition 534 * 535 * Must be called with clk disabled, and returns with clk enabled. 536 */ 537 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, 538 struct reset_control *rst) 539 { 540 struct tegra_powergate pg; 541 int err; 542 543 pg.id = id; 544 pg.clks = &clk; 545 pg.num_clks = 1; 546 pg.resets = &rst; 547 pg.num_resets = 1; 548 549 err = tegra_powergate_power_up(&pg, false); 550 if (err) 551 pr_err("failed to turn on partition %d: %d\n", id, err); 552 553 return err; 554 } 555 EXPORT_SYMBOL(tegra_powergate_sequence_power_up); 556 557 #ifdef CONFIG_SMP 558 /** 559 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID 560 * @cpuid: CPU partition ID 561 * 562 * Returns the partition ID corresponding to the CPU partition ID or a 563 * negative error code on failure. 564 */ 565 static int tegra_get_cpu_powergate_id(unsigned int cpuid) 566 { 567 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) 568 return pmc->soc->cpu_powergates[cpuid]; 569 570 return -EINVAL; 571 } 572 573 /** 574 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered 575 * @cpuid: CPU partition ID 576 */ 577 bool tegra_pmc_cpu_is_powered(unsigned int cpuid) 578 { 579 int id; 580 581 id = tegra_get_cpu_powergate_id(cpuid); 582 if (id < 0) 583 return false; 584 585 return tegra_powergate_is_powered(id); 586 } 587 588 /** 589 * tegra_pmc_cpu_power_on() - power on CPU partition 590 * @cpuid: CPU partition ID 591 */ 592 int tegra_pmc_cpu_power_on(unsigned int cpuid) 593 { 594 int id; 595 596 id = tegra_get_cpu_powergate_id(cpuid); 597 if (id < 0) 598 return id; 599 600 return tegra_powergate_set(id, true); 601 } 602 603 /** 604 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition 605 * @cpuid: CPU partition ID 606 */ 607 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid) 608 { 609 int id; 610 611 id = tegra_get_cpu_powergate_id(cpuid); 612 if (id < 0) 613 return id; 614 615 return tegra_powergate_remove_clamping(id); 616 } 617 #endif /* CONFIG_SMP */ 618 619 static int tegra_pmc_restart_notify(struct notifier_block *this, 620 unsigned long action, void *data) 621 { 622 const char *cmd = data; 623 u32 value; 624 625 value = tegra_pmc_readl(PMC_SCRATCH0); 626 value &= ~PMC_SCRATCH0_MODE_MASK; 627 628 if (cmd) { 629 if (strcmp(cmd, "recovery") == 0) 630 value |= PMC_SCRATCH0_MODE_RECOVERY; 631 632 if (strcmp(cmd, "bootloader") == 0) 633 value |= PMC_SCRATCH0_MODE_BOOTLOADER; 634 635 if (strcmp(cmd, "forced-recovery") == 0) 636 value |= PMC_SCRATCH0_MODE_RCM; 637 } 638 639 tegra_pmc_writel(value, PMC_SCRATCH0); 640 641 value = tegra_pmc_readl(0); 642 value |= 0x10; 643 tegra_pmc_writel(value, 0); 644 645 return NOTIFY_DONE; 646 } 647 648 static struct notifier_block tegra_pmc_restart_handler = { 649 .notifier_call = tegra_pmc_restart_notify, 650 .priority = 128, 651 }; 652 653 static int powergate_show(struct seq_file *s, void *data) 654 { 655 unsigned int i; 656 int status; 657 658 seq_printf(s, " powergate powered\n"); 659 seq_printf(s, "------------------\n"); 660 661 for (i = 0; i < pmc->soc->num_powergates; i++) { 662 status = tegra_powergate_is_powered(i); 663 if (status < 0) 664 continue; 665 666 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], 667 status ? "yes" : "no"); 668 } 669 670 return 0; 671 } 672 673 static int powergate_open(struct inode *inode, struct file *file) 674 { 675 return single_open(file, powergate_show, inode->i_private); 676 } 677 678 static const struct file_operations powergate_fops = { 679 .open = powergate_open, 680 .read = seq_read, 681 .llseek = seq_lseek, 682 .release = single_release, 683 }; 684 685 static int tegra_powergate_debugfs_init(void) 686 { 687 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, 688 &powergate_fops); 689 if (!pmc->debugfs) 690 return -ENOMEM; 691 692 return 0; 693 } 694 695 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg, 696 struct device_node *np) 697 { 698 struct clk *clk; 699 unsigned int i, count; 700 int err; 701 702 count = of_count_phandle_with_args(np, "clocks", "#clock-cells"); 703 if (count == 0) 704 return -ENODEV; 705 706 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL); 707 if (!pg->clks) 708 return -ENOMEM; 709 710 for (i = 0; i < count; i++) { 711 pg->clks[i] = of_clk_get(np, i); 712 if (IS_ERR(pg->clks[i])) { 713 err = PTR_ERR(pg->clks[i]); 714 goto err; 715 } 716 } 717 718 pg->num_clks = count; 719 720 return 0; 721 722 err: 723 while (i--) 724 clk_put(pg->clks[i]); 725 kfree(pg->clks); 726 727 return err; 728 } 729 730 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg, 731 struct device_node *np) 732 { 733 struct reset_control *rst; 734 unsigned int i, count; 735 int err; 736 737 count = of_count_phandle_with_args(np, "resets", "#reset-cells"); 738 if (count == 0) 739 return -ENODEV; 740 741 pg->resets = kcalloc(count, sizeof(rst), GFP_KERNEL); 742 if (!pg->resets) 743 return -ENOMEM; 744 745 for (i = 0; i < count; i++) { 746 pg->resets[i] = of_reset_control_get_by_index(np, i); 747 if (IS_ERR(pg->resets[i])) { 748 err = PTR_ERR(pg->resets[i]); 749 goto error; 750 } 751 } 752 753 pg->num_resets = count; 754 755 return 0; 756 757 error: 758 while (i--) 759 reset_control_put(pg->resets[i]); 760 kfree(pg->resets); 761 762 return err; 763 } 764 765 static void tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) 766 { 767 struct tegra_powergate *pg; 768 bool off; 769 int id; 770 771 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 772 if (!pg) 773 goto error; 774 775 id = tegra_powergate_lookup(pmc, np->name); 776 if (id < 0) 777 goto free_mem; 778 779 /* 780 * Clear the bit for this powergate so it cannot be managed 781 * directly via the legacy APIs for controlling powergates. 782 */ 783 clear_bit(id, pmc->powergates_available); 784 785 pg->id = id; 786 pg->genpd.name = np->name; 787 pg->genpd.power_off = tegra_genpd_power_off; 788 pg->genpd.power_on = tegra_genpd_power_on; 789 pg->pmc = pmc; 790 791 if (tegra_powergate_of_get_clks(pg, np)) 792 goto set_available; 793 794 if (tegra_powergate_of_get_resets(pg, np)) 795 goto remove_clks; 796 797 off = !tegra_powergate_is_powered(pg->id); 798 799 pm_genpd_init(&pg->genpd, NULL, off); 800 801 if (of_genpd_add_provider_simple(np, &pg->genpd)) 802 goto remove_resets; 803 804 dev_dbg(pmc->dev, "added power domain %s\n", pg->genpd.name); 805 806 return; 807 808 remove_resets: 809 while (pg->num_resets--) 810 reset_control_put(pg->resets[pg->num_resets]); 811 kfree(pg->resets); 812 813 remove_clks: 814 while (pg->num_clks--) 815 clk_put(pg->clks[pg->num_clks]); 816 kfree(pg->clks); 817 818 set_available: 819 set_bit(id, pmc->powergates_available); 820 821 free_mem: 822 kfree(pg); 823 824 error: 825 dev_err(pmc->dev, "failed to create power domain for %s\n", np->name); 826 } 827 828 static void tegra_powergate_init(struct tegra_pmc *pmc) 829 { 830 struct device_node *np, *child; 831 832 np = of_get_child_by_name(pmc->dev->of_node, "powergates"); 833 if (!np) 834 return; 835 836 for_each_child_of_node(np, child) { 837 tegra_powergate_add(pmc, child); 838 of_node_put(child); 839 } 840 841 of_node_put(np); 842 } 843 844 static int tegra_io_rail_prepare(unsigned int id, unsigned long *request, 845 unsigned long *status, unsigned int *bit) 846 { 847 unsigned long rate, value; 848 849 *bit = id % 32; 850 851 /* 852 * There are two sets of 30 bits to select IO rails, but bits 30 and 853 * 31 are control bits rather than IO rail selection bits. 854 */ 855 if (id > 63 || *bit == 30 || *bit == 31) 856 return -EINVAL; 857 858 if (id < 32) { 859 *status = IO_DPD_STATUS; 860 *request = IO_DPD_REQ; 861 } else { 862 *status = IO_DPD2_STATUS; 863 *request = IO_DPD2_REQ; 864 } 865 866 rate = clk_get_rate(pmc->clk); 867 868 tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE); 869 870 /* must be at least 200 ns, in APB (PCLK) clock cycles */ 871 value = DIV_ROUND_UP(1000000000, rate); 872 value = DIV_ROUND_UP(200, value); 873 tegra_pmc_writel(value, SEL_DPD_TIM); 874 875 return 0; 876 } 877 878 static int tegra_io_rail_poll(unsigned long offset, unsigned long mask, 879 unsigned long val, unsigned long timeout) 880 { 881 unsigned long value; 882 883 timeout = jiffies + msecs_to_jiffies(timeout); 884 885 while (time_after(timeout, jiffies)) { 886 value = tegra_pmc_readl(offset); 887 if ((value & mask) == val) 888 return 0; 889 890 usleep_range(250, 1000); 891 } 892 893 return -ETIMEDOUT; 894 } 895 896 static void tegra_io_rail_unprepare(void) 897 { 898 tegra_pmc_writel(DPD_SAMPLE_DISABLE, DPD_SAMPLE); 899 } 900 901 int tegra_io_rail_power_on(unsigned int id) 902 { 903 unsigned long request, status, value; 904 unsigned int bit, mask; 905 int err; 906 907 mutex_lock(&pmc->powergates_lock); 908 909 err = tegra_io_rail_prepare(id, &request, &status, &bit); 910 if (err) 911 goto error; 912 913 mask = 1 << bit; 914 915 value = tegra_pmc_readl(request); 916 value |= mask; 917 value &= ~IO_DPD_REQ_CODE_MASK; 918 value |= IO_DPD_REQ_CODE_OFF; 919 tegra_pmc_writel(value, request); 920 921 err = tegra_io_rail_poll(status, mask, 0, 250); 922 if (err) { 923 pr_info("tegra_io_rail_poll() failed: %d\n", err); 924 goto error; 925 } 926 927 tegra_io_rail_unprepare(); 928 929 error: 930 mutex_unlock(&pmc->powergates_lock); 931 932 return err; 933 } 934 EXPORT_SYMBOL(tegra_io_rail_power_on); 935 936 int tegra_io_rail_power_off(unsigned int id) 937 { 938 unsigned long request, status, value; 939 unsigned int bit, mask; 940 int err; 941 942 mutex_lock(&pmc->powergates_lock); 943 944 err = tegra_io_rail_prepare(id, &request, &status, &bit); 945 if (err) { 946 pr_info("tegra_io_rail_prepare() failed: %d\n", err); 947 goto error; 948 } 949 950 mask = 1 << bit; 951 952 value = tegra_pmc_readl(request); 953 value |= mask; 954 value &= ~IO_DPD_REQ_CODE_MASK; 955 value |= IO_DPD_REQ_CODE_ON; 956 tegra_pmc_writel(value, request); 957 958 err = tegra_io_rail_poll(status, mask, mask, 250); 959 if (err) 960 goto error; 961 962 tegra_io_rail_unprepare(); 963 964 error: 965 mutex_unlock(&pmc->powergates_lock); 966 967 return err; 968 } 969 EXPORT_SYMBOL(tegra_io_rail_power_off); 970 971 #ifdef CONFIG_PM_SLEEP 972 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) 973 { 974 return pmc->suspend_mode; 975 } 976 977 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) 978 { 979 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE) 980 return; 981 982 pmc->suspend_mode = mode; 983 } 984 985 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) 986 { 987 unsigned long long rate = 0; 988 u32 value; 989 990 switch (mode) { 991 case TEGRA_SUSPEND_LP1: 992 rate = 32768; 993 break; 994 995 case TEGRA_SUSPEND_LP2: 996 rate = clk_get_rate(pmc->clk); 997 break; 998 999 default: 1000 break; 1001 } 1002 1003 if (WARN_ON_ONCE(rate == 0)) 1004 rate = 100000000; 1005 1006 if (rate != pmc->rate) { 1007 u64 ticks; 1008 1009 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; 1010 do_div(ticks, USEC_PER_SEC); 1011 tegra_pmc_writel(ticks, PMC_CPUPWRGOOD_TIMER); 1012 1013 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; 1014 do_div(ticks, USEC_PER_SEC); 1015 tegra_pmc_writel(ticks, PMC_CPUPWROFF_TIMER); 1016 1017 wmb(); 1018 1019 pmc->rate = rate; 1020 } 1021 1022 value = tegra_pmc_readl(PMC_CNTRL); 1023 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; 1024 value |= PMC_CNTRL_CPU_PWRREQ_OE; 1025 tegra_pmc_writel(value, PMC_CNTRL); 1026 } 1027 #endif 1028 1029 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) 1030 { 1031 u32 value, values[2]; 1032 1033 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { 1034 } else { 1035 switch (value) { 1036 case 0: 1037 pmc->suspend_mode = TEGRA_SUSPEND_LP0; 1038 break; 1039 1040 case 1: 1041 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1042 break; 1043 1044 case 2: 1045 pmc->suspend_mode = TEGRA_SUSPEND_LP2; 1046 break; 1047 1048 default: 1049 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1050 break; 1051 } 1052 } 1053 1054 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); 1055 1056 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) 1057 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1058 1059 pmc->cpu_good_time = value; 1060 1061 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) 1062 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1063 1064 pmc->cpu_off_time = value; 1065 1066 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", 1067 values, ARRAY_SIZE(values))) 1068 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1069 1070 pmc->core_osc_time = values[0]; 1071 pmc->core_pmu_time = values[1]; 1072 1073 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) 1074 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1075 1076 pmc->core_off_time = value; 1077 1078 pmc->corereq_high = of_property_read_bool(np, 1079 "nvidia,core-power-req-active-high"); 1080 1081 pmc->sysclkreq_high = of_property_read_bool(np, 1082 "nvidia,sys-clock-req-active-high"); 1083 1084 pmc->combined_req = of_property_read_bool(np, 1085 "nvidia,combined-power-req"); 1086 1087 pmc->cpu_pwr_good_en = of_property_read_bool(np, 1088 "nvidia,cpu-pwr-good-en"); 1089 1090 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, 1091 ARRAY_SIZE(values))) 1092 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) 1093 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1094 1095 pmc->lp0_vec_phys = values[0]; 1096 pmc->lp0_vec_size = values[1]; 1097 1098 return 0; 1099 } 1100 1101 static void tegra_pmc_init(struct tegra_pmc *pmc) 1102 { 1103 u32 value; 1104 1105 /* Always enable CPU power request */ 1106 value = tegra_pmc_readl(PMC_CNTRL); 1107 value |= PMC_CNTRL_CPU_PWRREQ_OE; 1108 tegra_pmc_writel(value, PMC_CNTRL); 1109 1110 value = tegra_pmc_readl(PMC_CNTRL); 1111 1112 if (pmc->sysclkreq_high) 1113 value &= ~PMC_CNTRL_SYSCLK_POLARITY; 1114 else 1115 value |= PMC_CNTRL_SYSCLK_POLARITY; 1116 1117 /* configure the output polarity while the request is tristated */ 1118 tegra_pmc_writel(value, PMC_CNTRL); 1119 1120 /* now enable the request */ 1121 value = tegra_pmc_readl(PMC_CNTRL); 1122 value |= PMC_CNTRL_SYSCLK_OE; 1123 tegra_pmc_writel(value, PMC_CNTRL); 1124 } 1125 1126 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) 1127 { 1128 static const char disabled[] = "emergency thermal reset disabled"; 1129 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux; 1130 struct device *dev = pmc->dev; 1131 struct device_node *np; 1132 u32 value, checksum; 1133 1134 if (!pmc->soc->has_tsense_reset) 1135 return; 1136 1137 np = of_find_node_by_name(pmc->dev->of_node, "i2c-thermtrip"); 1138 if (!np) { 1139 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); 1140 return; 1141 } 1142 1143 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { 1144 dev_err(dev, "I2C controller ID missing, %s.\n", disabled); 1145 goto out; 1146 } 1147 1148 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { 1149 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); 1150 goto out; 1151 } 1152 1153 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { 1154 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); 1155 goto out; 1156 } 1157 1158 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { 1159 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); 1160 goto out; 1161 } 1162 1163 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) 1164 pinmux = 0; 1165 1166 value = tegra_pmc_readl(PMC_SENSOR_CTRL); 1167 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE; 1168 tegra_pmc_writel(value, PMC_SENSOR_CTRL); 1169 1170 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) | 1171 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT); 1172 tegra_pmc_writel(value, PMC_SCRATCH54); 1173 1174 value = PMC_SCRATCH55_RESET_TEGRA; 1175 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT; 1176 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT; 1177 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT; 1178 1179 /* 1180 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will 1181 * contain the checksum and are currently zero, so they are not added. 1182 */ 1183 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff) 1184 + ((value >> 24) & 0xff); 1185 checksum &= 0xff; 1186 checksum = 0x100 - checksum; 1187 1188 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT; 1189 1190 tegra_pmc_writel(value, PMC_SCRATCH55); 1191 1192 value = tegra_pmc_readl(PMC_SENSOR_CTRL); 1193 value |= PMC_SENSOR_CTRL_ENABLE_RST; 1194 tegra_pmc_writel(value, PMC_SENSOR_CTRL); 1195 1196 dev_info(pmc->dev, "emergency thermal reset enabled\n"); 1197 1198 out: 1199 of_node_put(np); 1200 } 1201 1202 static int tegra_pmc_probe(struct platform_device *pdev) 1203 { 1204 void __iomem *base; 1205 struct resource *res; 1206 int err; 1207 1208 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); 1209 if (err < 0) 1210 return err; 1211 1212 /* take over the memory region from the early initialization */ 1213 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1214 base = devm_ioremap_resource(&pdev->dev, res); 1215 if (IS_ERR(base)) 1216 return PTR_ERR(base); 1217 1218 pmc->clk = devm_clk_get(&pdev->dev, "pclk"); 1219 if (IS_ERR(pmc->clk)) { 1220 err = PTR_ERR(pmc->clk); 1221 dev_err(&pdev->dev, "failed to get pclk: %d\n", err); 1222 return err; 1223 } 1224 1225 pmc->dev = &pdev->dev; 1226 1227 tegra_pmc_init(pmc); 1228 1229 tegra_pmc_init_tsense_reset(pmc); 1230 1231 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 1232 err = tegra_powergate_debugfs_init(); 1233 if (err < 0) 1234 return err; 1235 } 1236 1237 err = register_restart_handler(&tegra_pmc_restart_handler); 1238 if (err) { 1239 debugfs_remove(pmc->debugfs); 1240 dev_err(&pdev->dev, "unable to register restart handler, %d\n", 1241 err); 1242 return err; 1243 } 1244 1245 tegra_powergate_init(pmc); 1246 1247 mutex_lock(&pmc->powergates_lock); 1248 iounmap(pmc->base); 1249 pmc->base = base; 1250 mutex_unlock(&pmc->powergates_lock); 1251 1252 return 0; 1253 } 1254 1255 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 1256 static int tegra_pmc_suspend(struct device *dev) 1257 { 1258 tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41); 1259 1260 return 0; 1261 } 1262 1263 static int tegra_pmc_resume(struct device *dev) 1264 { 1265 tegra_pmc_writel(0x0, PMC_SCRATCH41); 1266 1267 return 0; 1268 } 1269 1270 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume); 1271 1272 #endif 1273 1274 static const char * const tegra20_powergates[] = { 1275 [TEGRA_POWERGATE_CPU] = "cpu", 1276 [TEGRA_POWERGATE_3D] = "3d", 1277 [TEGRA_POWERGATE_VENC] = "venc", 1278 [TEGRA_POWERGATE_VDEC] = "vdec", 1279 [TEGRA_POWERGATE_PCIE] = "pcie", 1280 [TEGRA_POWERGATE_L2] = "l2", 1281 [TEGRA_POWERGATE_MPE] = "mpe", 1282 }; 1283 1284 static const struct tegra_pmc_soc tegra20_pmc_soc = { 1285 .num_powergates = ARRAY_SIZE(tegra20_powergates), 1286 .powergates = tegra20_powergates, 1287 .num_cpu_powergates = 0, 1288 .cpu_powergates = NULL, 1289 .has_tsense_reset = false, 1290 .has_gpu_clamps = false, 1291 }; 1292 1293 static const char * const tegra30_powergates[] = { 1294 [TEGRA_POWERGATE_CPU] = "cpu0", 1295 [TEGRA_POWERGATE_3D] = "3d0", 1296 [TEGRA_POWERGATE_VENC] = "venc", 1297 [TEGRA_POWERGATE_VDEC] = "vdec", 1298 [TEGRA_POWERGATE_PCIE] = "pcie", 1299 [TEGRA_POWERGATE_L2] = "l2", 1300 [TEGRA_POWERGATE_MPE] = "mpe", 1301 [TEGRA_POWERGATE_HEG] = "heg", 1302 [TEGRA_POWERGATE_SATA] = "sata", 1303 [TEGRA_POWERGATE_CPU1] = "cpu1", 1304 [TEGRA_POWERGATE_CPU2] = "cpu2", 1305 [TEGRA_POWERGATE_CPU3] = "cpu3", 1306 [TEGRA_POWERGATE_CELP] = "celp", 1307 [TEGRA_POWERGATE_3D1] = "3d1", 1308 }; 1309 1310 static const u8 tegra30_cpu_powergates[] = { 1311 TEGRA_POWERGATE_CPU, 1312 TEGRA_POWERGATE_CPU1, 1313 TEGRA_POWERGATE_CPU2, 1314 TEGRA_POWERGATE_CPU3, 1315 }; 1316 1317 static const struct tegra_pmc_soc tegra30_pmc_soc = { 1318 .num_powergates = ARRAY_SIZE(tegra30_powergates), 1319 .powergates = tegra30_powergates, 1320 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), 1321 .cpu_powergates = tegra30_cpu_powergates, 1322 .has_tsense_reset = true, 1323 .has_gpu_clamps = false, 1324 }; 1325 1326 static const char * const tegra114_powergates[] = { 1327 [TEGRA_POWERGATE_CPU] = "crail", 1328 [TEGRA_POWERGATE_3D] = "3d", 1329 [TEGRA_POWERGATE_VENC] = "venc", 1330 [TEGRA_POWERGATE_VDEC] = "vdec", 1331 [TEGRA_POWERGATE_MPE] = "mpe", 1332 [TEGRA_POWERGATE_HEG] = "heg", 1333 [TEGRA_POWERGATE_CPU1] = "cpu1", 1334 [TEGRA_POWERGATE_CPU2] = "cpu2", 1335 [TEGRA_POWERGATE_CPU3] = "cpu3", 1336 [TEGRA_POWERGATE_CELP] = "celp", 1337 [TEGRA_POWERGATE_CPU0] = "cpu0", 1338 [TEGRA_POWERGATE_C0NC] = "c0nc", 1339 [TEGRA_POWERGATE_C1NC] = "c1nc", 1340 [TEGRA_POWERGATE_DIS] = "dis", 1341 [TEGRA_POWERGATE_DISB] = "disb", 1342 [TEGRA_POWERGATE_XUSBA] = "xusba", 1343 [TEGRA_POWERGATE_XUSBB] = "xusbb", 1344 [TEGRA_POWERGATE_XUSBC] = "xusbc", 1345 }; 1346 1347 static const u8 tegra114_cpu_powergates[] = { 1348 TEGRA_POWERGATE_CPU0, 1349 TEGRA_POWERGATE_CPU1, 1350 TEGRA_POWERGATE_CPU2, 1351 TEGRA_POWERGATE_CPU3, 1352 }; 1353 1354 static const struct tegra_pmc_soc tegra114_pmc_soc = { 1355 .num_powergates = ARRAY_SIZE(tegra114_powergates), 1356 .powergates = tegra114_powergates, 1357 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), 1358 .cpu_powergates = tegra114_cpu_powergates, 1359 .has_tsense_reset = true, 1360 .has_gpu_clamps = false, 1361 }; 1362 1363 static const char * const tegra124_powergates[] = { 1364 [TEGRA_POWERGATE_CPU] = "crail", 1365 [TEGRA_POWERGATE_3D] = "3d", 1366 [TEGRA_POWERGATE_VENC] = "venc", 1367 [TEGRA_POWERGATE_PCIE] = "pcie", 1368 [TEGRA_POWERGATE_VDEC] = "vdec", 1369 [TEGRA_POWERGATE_MPE] = "mpe", 1370 [TEGRA_POWERGATE_HEG] = "heg", 1371 [TEGRA_POWERGATE_SATA] = "sata", 1372 [TEGRA_POWERGATE_CPU1] = "cpu1", 1373 [TEGRA_POWERGATE_CPU2] = "cpu2", 1374 [TEGRA_POWERGATE_CPU3] = "cpu3", 1375 [TEGRA_POWERGATE_CELP] = "celp", 1376 [TEGRA_POWERGATE_CPU0] = "cpu0", 1377 [TEGRA_POWERGATE_C0NC] = "c0nc", 1378 [TEGRA_POWERGATE_C1NC] = "c1nc", 1379 [TEGRA_POWERGATE_SOR] = "sor", 1380 [TEGRA_POWERGATE_DIS] = "dis", 1381 [TEGRA_POWERGATE_DISB] = "disb", 1382 [TEGRA_POWERGATE_XUSBA] = "xusba", 1383 [TEGRA_POWERGATE_XUSBB] = "xusbb", 1384 [TEGRA_POWERGATE_XUSBC] = "xusbc", 1385 [TEGRA_POWERGATE_VIC] = "vic", 1386 [TEGRA_POWERGATE_IRAM] = "iram", 1387 }; 1388 1389 static const u8 tegra124_cpu_powergates[] = { 1390 TEGRA_POWERGATE_CPU0, 1391 TEGRA_POWERGATE_CPU1, 1392 TEGRA_POWERGATE_CPU2, 1393 TEGRA_POWERGATE_CPU3, 1394 }; 1395 1396 static const struct tegra_pmc_soc tegra124_pmc_soc = { 1397 .num_powergates = ARRAY_SIZE(tegra124_powergates), 1398 .powergates = tegra124_powergates, 1399 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), 1400 .cpu_powergates = tegra124_cpu_powergates, 1401 .has_tsense_reset = true, 1402 .has_gpu_clamps = true, 1403 }; 1404 1405 static const char * const tegra210_powergates[] = { 1406 [TEGRA_POWERGATE_CPU] = "crail", 1407 [TEGRA_POWERGATE_3D] = "3d", 1408 [TEGRA_POWERGATE_VENC] = "venc", 1409 [TEGRA_POWERGATE_PCIE] = "pcie", 1410 [TEGRA_POWERGATE_MPE] = "mpe", 1411 [TEGRA_POWERGATE_SATA] = "sata", 1412 [TEGRA_POWERGATE_CPU1] = "cpu1", 1413 [TEGRA_POWERGATE_CPU2] = "cpu2", 1414 [TEGRA_POWERGATE_CPU3] = "cpu3", 1415 [TEGRA_POWERGATE_CPU0] = "cpu0", 1416 [TEGRA_POWERGATE_C0NC] = "c0nc", 1417 [TEGRA_POWERGATE_SOR] = "sor", 1418 [TEGRA_POWERGATE_DIS] = "dis", 1419 [TEGRA_POWERGATE_DISB] = "disb", 1420 [TEGRA_POWERGATE_XUSBA] = "xusba", 1421 [TEGRA_POWERGATE_XUSBB] = "xusbb", 1422 [TEGRA_POWERGATE_XUSBC] = "xusbc", 1423 [TEGRA_POWERGATE_VIC] = "vic", 1424 [TEGRA_POWERGATE_IRAM] = "iram", 1425 [TEGRA_POWERGATE_NVDEC] = "nvdec", 1426 [TEGRA_POWERGATE_NVJPG] = "nvjpg", 1427 [TEGRA_POWERGATE_AUD] = "aud", 1428 [TEGRA_POWERGATE_DFD] = "dfd", 1429 [TEGRA_POWERGATE_VE2] = "ve2", 1430 }; 1431 1432 static const u8 tegra210_cpu_powergates[] = { 1433 TEGRA_POWERGATE_CPU0, 1434 TEGRA_POWERGATE_CPU1, 1435 TEGRA_POWERGATE_CPU2, 1436 TEGRA_POWERGATE_CPU3, 1437 }; 1438 1439 static const struct tegra_pmc_soc tegra210_pmc_soc = { 1440 .num_powergates = ARRAY_SIZE(tegra210_powergates), 1441 .powergates = tegra210_powergates, 1442 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates), 1443 .cpu_powergates = tegra210_cpu_powergates, 1444 .has_tsense_reset = true, 1445 .has_gpu_clamps = true, 1446 }; 1447 1448 static const struct of_device_id tegra_pmc_match[] = { 1449 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc }, 1450 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc }, 1451 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc }, 1452 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc }, 1453 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc }, 1454 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc }, 1455 { } 1456 }; 1457 1458 static struct platform_driver tegra_pmc_driver = { 1459 .driver = { 1460 .name = "tegra-pmc", 1461 .suppress_bind_attrs = true, 1462 .of_match_table = tegra_pmc_match, 1463 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 1464 .pm = &tegra_pmc_pm_ops, 1465 #endif 1466 }, 1467 .probe = tegra_pmc_probe, 1468 }; 1469 builtin_platform_driver(tegra_pmc_driver); 1470 1471 /* 1472 * Early initialization to allow access to registers in the very early boot 1473 * process. 1474 */ 1475 static int __init tegra_pmc_early_init(void) 1476 { 1477 const struct of_device_id *match; 1478 struct device_node *np; 1479 struct resource regs; 1480 unsigned int i; 1481 bool invert; 1482 u32 value; 1483 1484 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match); 1485 if (!np) { 1486 /* 1487 * Fall back to legacy initialization for 32-bit ARM only. All 1488 * 64-bit ARM device tree files for Tegra are required to have 1489 * a PMC node. 1490 * 1491 * This is for backwards-compatibility with old device trees 1492 * that didn't contain a PMC node. Note that in this case the 1493 * SoC data can't be matched and therefore powergating is 1494 * disabled. 1495 */ 1496 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 1497 pr_warn("DT node not found, powergating disabled\n"); 1498 1499 regs.start = 0x7000e400; 1500 regs.end = 0x7000e7ff; 1501 regs.flags = IORESOURCE_MEM; 1502 1503 pr_warn("Using memory region %pR\n", ®s); 1504 } else { 1505 /* 1506 * At this point we're not running on Tegra, so play 1507 * nice with multi-platform kernels. 1508 */ 1509 return 0; 1510 } 1511 } else { 1512 /* 1513 * Extract information from the device tree if we've found a 1514 * matching node. 1515 */ 1516 if (of_address_to_resource(np, 0, ®s) < 0) { 1517 pr_err("failed to get PMC registers\n"); 1518 return -ENXIO; 1519 } 1520 1521 pmc->soc = match->data; 1522 } 1523 1524 pmc->base = ioremap_nocache(regs.start, resource_size(®s)); 1525 if (!pmc->base) { 1526 pr_err("failed to map PMC registers\n"); 1527 return -ENXIO; 1528 } 1529 1530 /* Create a bit-map of the available and valid partitions */ 1531 for (i = 0; i < pmc->soc->num_powergates; i++) 1532 if (pmc->soc->powergates[i]) 1533 set_bit(i, pmc->powergates_available); 1534 1535 mutex_init(&pmc->powergates_lock); 1536 1537 /* 1538 * Invert the interrupt polarity if a PMC device tree node exists and 1539 * contains the nvidia,invert-interrupt property. 1540 */ 1541 invert = of_property_read_bool(np, "nvidia,invert-interrupt"); 1542 1543 value = tegra_pmc_readl(PMC_CNTRL); 1544 1545 if (invert) 1546 value |= PMC_CNTRL_INTR_POLARITY; 1547 else 1548 value &= ~PMC_CNTRL_INTR_POLARITY; 1549 1550 tegra_pmc_writel(value, PMC_CNTRL); 1551 1552 return 0; 1553 } 1554 early_initcall(tegra_pmc_early_init); 1555