1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/export.h> 7 #include <linux/kernel.h> 8 #include <linux/of.h> 9 #include <linux/of_address.h> 10 #include <linux/io.h> 11 12 #include <soc/tegra/fuse.h> 13 #include <soc/tegra/common.h> 14 15 #include "fuse.h" 16 17 #define FUSE_SKU_INFO 0x10 18 19 #define ERD_ERR_CONFIG 0x120c 20 #define ERD_MASK_INBAND_ERR 0x1 21 22 #define PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT 4 23 #define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG \ 24 (0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT) 25 #define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT \ 26 (0x3 << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT) 27 28 static void __iomem *apbmisc_base; 29 static bool long_ram_code; 30 static u32 strapping; 31 static u32 chipid; 32 33 u32 tegra_read_chipid(void) 34 { 35 WARN(!chipid, "Tegra APB MISC not yet available\n"); 36 37 return chipid; 38 } 39 40 u8 tegra_get_chip_id(void) 41 { 42 return (tegra_read_chipid() >> 8) & 0xff; 43 } 44 45 u8 tegra_get_major_rev(void) 46 { 47 return (tegra_read_chipid() >> 4) & 0xf; 48 } 49 50 u8 tegra_get_minor_rev(void) 51 { 52 return (tegra_read_chipid() >> 16) & 0xf; 53 } 54 55 u8 tegra_get_platform(void) 56 { 57 return (tegra_read_chipid() >> 20) & 0xf; 58 } 59 60 bool tegra_is_silicon(void) 61 { 62 switch (tegra_get_chip_id()) { 63 case TEGRA194: 64 case TEGRA234: 65 if (tegra_get_platform() == 0) 66 return true; 67 68 return false; 69 } 70 71 /* 72 * Chips prior to Tegra194 have a different way of determining whether 73 * they are silicon or not. Since we never supported simulation on the 74 * older Tegra chips, don't bother extracting the information and just 75 * report that we're running on silicon. 76 */ 77 return true; 78 } 79 80 u32 tegra_read_straps(void) 81 { 82 WARN(!chipid, "Tegra ABP MISC not yet available\n"); 83 84 return strapping; 85 } 86 87 u32 tegra_read_ram_code(void) 88 { 89 u32 straps = tegra_read_straps(); 90 91 if (long_ram_code) 92 straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG; 93 else 94 straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT; 95 96 return straps >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT; 97 } 98 EXPORT_SYMBOL_GPL(tegra_read_ram_code); 99 100 /* 101 * The function sets ERD(Error Response Disable) bit. 102 * This allows to mask inband errors and always send an 103 * OKAY response from CBB to the master which caused error. 104 */ 105 int tegra194_miscreg_mask_serror(void) 106 { 107 if (!apbmisc_base) 108 return -EPROBE_DEFER; 109 110 if (!of_machine_is_compatible("nvidia,tegra194")) { 111 WARN(1, "Only supported for Tegra194 devices!\n"); 112 return -EOPNOTSUPP; 113 } 114 115 writel_relaxed(ERD_MASK_INBAND_ERR, 116 apbmisc_base + ERD_ERR_CONFIG); 117 118 return 0; 119 } 120 EXPORT_SYMBOL(tegra194_miscreg_mask_serror); 121 122 static const struct of_device_id apbmisc_match[] __initconst = { 123 { .compatible = "nvidia,tegra20-apbmisc", }, 124 { .compatible = "nvidia,tegra186-misc", }, 125 { .compatible = "nvidia,tegra194-misc", }, 126 { .compatible = "nvidia,tegra234-misc", }, 127 {}, 128 }; 129 130 void __init tegra_init_revision(void) 131 { 132 u8 chip_id, minor_rev; 133 134 chip_id = tegra_get_chip_id(); 135 minor_rev = tegra_get_minor_rev(); 136 137 switch (minor_rev) { 138 case 1: 139 tegra_sku_info.revision = TEGRA_REVISION_A01; 140 break; 141 case 2: 142 tegra_sku_info.revision = TEGRA_REVISION_A02; 143 break; 144 case 3: 145 if (chip_id == TEGRA20 && (tegra_fuse_read_spare(18) || 146 tegra_fuse_read_spare(19))) 147 tegra_sku_info.revision = TEGRA_REVISION_A03p; 148 else 149 tegra_sku_info.revision = TEGRA_REVISION_A03; 150 break; 151 case 4: 152 tegra_sku_info.revision = TEGRA_REVISION_A04; 153 break; 154 default: 155 tegra_sku_info.revision = TEGRA_REVISION_UNKNOWN; 156 } 157 158 tegra_sku_info.sku_id = tegra_fuse_read_early(FUSE_SKU_INFO); 159 tegra_sku_info.platform = tegra_get_platform(); 160 } 161 162 void __init tegra_init_apbmisc(void) 163 { 164 void __iomem *strapping_base; 165 struct resource apbmisc, straps; 166 struct device_node *np; 167 168 np = of_find_matching_node(NULL, apbmisc_match); 169 if (!np) { 170 /* 171 * Fall back to legacy initialization for 32-bit ARM only. All 172 * 64-bit ARM device tree files for Tegra are required to have 173 * an APBMISC node. 174 * 175 * This is for backwards-compatibility with old device trees 176 * that didn't contain an APBMISC node. 177 */ 178 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 179 /* APBMISC registers (chip revision, ...) */ 180 apbmisc.start = 0x70000800; 181 apbmisc.end = 0x70000863; 182 apbmisc.flags = IORESOURCE_MEM; 183 184 /* strapping options */ 185 if (of_machine_is_compatible("nvidia,tegra124")) { 186 straps.start = 0x7000e864; 187 straps.end = 0x7000e867; 188 } else { 189 straps.start = 0x70000008; 190 straps.end = 0x7000000b; 191 } 192 193 straps.flags = IORESOURCE_MEM; 194 195 pr_warn("Using APBMISC region %pR\n", &apbmisc); 196 pr_warn("Using strapping options registers %pR\n", 197 &straps); 198 } else { 199 /* 200 * At this point we're not running on Tegra, so play 201 * nice with multi-platform kernels. 202 */ 203 return; 204 } 205 } else { 206 /* 207 * Extract information from the device tree if we've found a 208 * matching node. 209 */ 210 if (of_address_to_resource(np, 0, &apbmisc) < 0) { 211 pr_err("failed to get APBMISC registers\n"); 212 goto put; 213 } 214 215 if (of_address_to_resource(np, 1, &straps) < 0) { 216 pr_err("failed to get strapping options registers\n"); 217 goto put; 218 } 219 } 220 221 apbmisc_base = ioremap(apbmisc.start, resource_size(&apbmisc)); 222 if (!apbmisc_base) { 223 pr_err("failed to map APBMISC registers\n"); 224 } else { 225 chipid = readl_relaxed(apbmisc_base + 4); 226 } 227 228 strapping_base = ioremap(straps.start, resource_size(&straps)); 229 if (!strapping_base) { 230 pr_err("failed to map strapping options registers\n"); 231 } else { 232 strapping = readl_relaxed(strapping_base); 233 iounmap(strapping_base); 234 } 235 236 long_ram_code = of_property_read_bool(np, "nvidia,long-ram-code"); 237 238 put: 239 of_node_put(np); 240 } 241