1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013-2022, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/device.h> 7 #include <linux/clk.h> 8 #include <linux/err.h> 9 #include <linux/io.h> 10 #include <linux/kernel.h> 11 #include <linux/nvmem-consumer.h> 12 #include <linux/nvmem-provider.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/random.h> 16 17 #include <soc/tegra/fuse.h> 18 19 #include "fuse.h" 20 21 #define FUSE_BEGIN 0x100 22 23 /* Tegra30 and later */ 24 #define FUSE_VENDOR_CODE 0x100 25 #define FUSE_FAB_CODE 0x104 26 #define FUSE_LOT_CODE_0 0x108 27 #define FUSE_LOT_CODE_1 0x10c 28 #define FUSE_WAFER_ID 0x110 29 #define FUSE_X_COORDINATE 0x114 30 #define FUSE_Y_COORDINATE 0x118 31 32 #define FUSE_HAS_REVISION_INFO BIT(0) 33 34 #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \ 35 defined(CONFIG_ARCH_TEGRA_114_SOC) || \ 36 defined(CONFIG_ARCH_TEGRA_124_SOC) || \ 37 defined(CONFIG_ARCH_TEGRA_132_SOC) || \ 38 defined(CONFIG_ARCH_TEGRA_210_SOC) || \ 39 defined(CONFIG_ARCH_TEGRA_186_SOC) || \ 40 defined(CONFIG_ARCH_TEGRA_194_SOC) || \ 41 defined(CONFIG_ARCH_TEGRA_234_SOC) || \ 42 defined(CONFIG_ARCH_TEGRA_241_SOC) 43 static u32 tegra30_fuse_read_early(struct tegra_fuse *fuse, unsigned int offset) 44 { 45 if (WARN_ON(!fuse->base)) 46 return 0; 47 48 return readl_relaxed(fuse->base + FUSE_BEGIN + offset); 49 } 50 51 static u32 tegra30_fuse_read(struct tegra_fuse *fuse, unsigned int offset) 52 { 53 u32 value; 54 int err; 55 56 err = pm_runtime_resume_and_get(fuse->dev); 57 if (err) 58 return 0; 59 60 value = readl_relaxed(fuse->base + FUSE_BEGIN + offset); 61 62 pm_runtime_put(fuse->dev); 63 64 return value; 65 } 66 67 static void __init tegra30_fuse_add_randomness(void) 68 { 69 u32 randomness[12]; 70 71 randomness[0] = tegra_sku_info.sku_id; 72 randomness[1] = tegra_read_straps(); 73 randomness[2] = tegra_read_chipid(); 74 randomness[3] = tegra_sku_info.cpu_process_id << 16; 75 randomness[3] |= tegra_sku_info.soc_process_id; 76 randomness[4] = tegra_sku_info.cpu_speedo_id << 16; 77 randomness[4] |= tegra_sku_info.soc_speedo_id; 78 randomness[5] = tegra_fuse_read_early(FUSE_VENDOR_CODE); 79 randomness[6] = tegra_fuse_read_early(FUSE_FAB_CODE); 80 randomness[7] = tegra_fuse_read_early(FUSE_LOT_CODE_0); 81 randomness[8] = tegra_fuse_read_early(FUSE_LOT_CODE_1); 82 randomness[9] = tegra_fuse_read_early(FUSE_WAFER_ID); 83 randomness[10] = tegra_fuse_read_early(FUSE_X_COORDINATE); 84 randomness[11] = tegra_fuse_read_early(FUSE_Y_COORDINATE); 85 86 add_device_randomness(randomness, sizeof(randomness)); 87 } 88 89 static void __init tegra30_fuse_init(struct tegra_fuse *fuse) 90 { 91 fuse->read_early = tegra30_fuse_read_early; 92 fuse->read = tegra30_fuse_read; 93 94 tegra_init_revision(); 95 96 if (fuse->soc->speedo_init) 97 fuse->soc->speedo_init(&tegra_sku_info); 98 99 tegra30_fuse_add_randomness(); 100 } 101 #endif 102 103 #ifdef CONFIG_ARCH_TEGRA_3x_SOC 104 static const struct tegra_fuse_info tegra30_fuse_info = { 105 .read = tegra30_fuse_read, 106 .size = 0x2a4, 107 .spare = 0x144, 108 }; 109 110 const struct tegra_fuse_soc tegra30_fuse_soc = { 111 .init = tegra30_fuse_init, 112 .speedo_init = tegra30_init_speedo_data, 113 .info = &tegra30_fuse_info, 114 .soc_attr_group = &tegra_soc_attr_group, 115 .clk_suspend_on = false, 116 }; 117 #endif 118 119 #ifdef CONFIG_ARCH_TEGRA_114_SOC 120 static const struct nvmem_cell_info tegra114_fuse_cells[] = { 121 { 122 .name = "tsensor-cpu1", 123 .offset = 0x084, 124 .bytes = 4, 125 .bit_offset = 0, 126 .nbits = 32, 127 }, { 128 .name = "tsensor-cpu2", 129 .offset = 0x088, 130 .bytes = 4, 131 .bit_offset = 0, 132 .nbits = 32, 133 }, { 134 .name = "tsensor-common", 135 .offset = 0x08c, 136 .bytes = 4, 137 .bit_offset = 0, 138 .nbits = 32, 139 }, { 140 .name = "tsensor-cpu0", 141 .offset = 0x098, 142 .bytes = 4, 143 .bit_offset = 0, 144 .nbits = 32, 145 }, { 146 .name = "xusb-pad-calibration", 147 .offset = 0x0f0, 148 .bytes = 4, 149 .bit_offset = 0, 150 .nbits = 32, 151 }, { 152 .name = "tsensor-cpu3", 153 .offset = 0x12c, 154 .bytes = 4, 155 .bit_offset = 0, 156 .nbits = 32, 157 }, { 158 .name = "tsensor-gpu", 159 .offset = 0x154, 160 .bytes = 4, 161 .bit_offset = 0, 162 .nbits = 32, 163 }, { 164 .name = "tsensor-mem0", 165 .offset = 0x158, 166 .bytes = 4, 167 .bit_offset = 0, 168 .nbits = 32, 169 }, { 170 .name = "tsensor-mem1", 171 .offset = 0x15c, 172 .bytes = 4, 173 .bit_offset = 0, 174 .nbits = 32, 175 }, { 176 .name = "tsensor-pllx", 177 .offset = 0x160, 178 .bytes = 4, 179 .bit_offset = 0, 180 .nbits = 32, 181 }, 182 }; 183 184 static const struct nvmem_cell_lookup tegra114_fuse_lookups[] = { 185 { 186 .nvmem_name = "fuse", 187 .cell_name = "xusb-pad-calibration", 188 .dev_id = "7009f000.padctl", 189 .con_id = "calibration", 190 }, { 191 .nvmem_name = "fuse", 192 .cell_name = "tsensor-common", 193 .dev_id = "700e2000.thermal-sensor", 194 .con_id = "common", 195 }, { 196 .nvmem_name = "fuse", 197 .cell_name = "tsensor-cpu0", 198 .dev_id = "700e2000.thermal-sensor", 199 .con_id = "cpu0", 200 }, { 201 .nvmem_name = "fuse", 202 .cell_name = "tsensor-cpu1", 203 .dev_id = "700e2000.thermal-sensor", 204 .con_id = "cpu1", 205 }, { 206 .nvmem_name = "fuse", 207 .cell_name = "tsensor-cpu2", 208 .dev_id = "700e2000.thermal-sensor", 209 .con_id = "cpu2", 210 }, { 211 .nvmem_name = "fuse", 212 .cell_name = "tsensor-cpu3", 213 .dev_id = "700e2000.thermal-sensor", 214 .con_id = "cpu3", 215 }, { 216 .nvmem_name = "fuse", 217 .cell_name = "tsensor-mem0", 218 .dev_id = "700e2000.thermal-sensor", 219 .con_id = "mem0", 220 }, { 221 .nvmem_name = "fuse", 222 .cell_name = "tsensor-mem1", 223 .dev_id = "700e2000.thermal-sensor", 224 .con_id = "mem1", 225 }, { 226 .nvmem_name = "fuse", 227 .cell_name = "tsensor-gpu", 228 .dev_id = "700e2000.thermal-sensor", 229 .con_id = "gpu", 230 }, { 231 .nvmem_name = "fuse", 232 .cell_name = "tsensor-pllx", 233 .dev_id = "700e2000.thermal-sensor", 234 .con_id = "pllx", 235 }, 236 }; 237 238 static const struct tegra_fuse_info tegra114_fuse_info = { 239 .read = tegra30_fuse_read, 240 .size = 0x2a0, 241 .spare = 0x180, 242 }; 243 244 const struct tegra_fuse_soc tegra114_fuse_soc = { 245 .init = tegra30_fuse_init, 246 .speedo_init = tegra114_init_speedo_data, 247 .info = &tegra114_fuse_info, 248 .lookups = tegra114_fuse_lookups, 249 .num_lookups = ARRAY_SIZE(tegra114_fuse_lookups), 250 .cells = tegra114_fuse_cells, 251 .num_cells = ARRAY_SIZE(tegra114_fuse_cells), 252 .soc_attr_group = &tegra_soc_attr_group, 253 .clk_suspend_on = false, 254 }; 255 #endif 256 257 #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) 258 static const struct nvmem_cell_info tegra124_fuse_cells[] = { 259 { 260 .name = "tsensor-cpu1", 261 .offset = 0x084, 262 .bytes = 4, 263 .bit_offset = 0, 264 .nbits = 32, 265 }, { 266 .name = "tsensor-cpu2", 267 .offset = 0x088, 268 .bytes = 4, 269 .bit_offset = 0, 270 .nbits = 32, 271 }, { 272 .name = "tsensor-cpu0", 273 .offset = 0x098, 274 .bytes = 4, 275 .bit_offset = 0, 276 .nbits = 32, 277 }, { 278 .name = "xusb-pad-calibration", 279 .offset = 0x0f0, 280 .bytes = 4, 281 .bit_offset = 0, 282 .nbits = 32, 283 }, { 284 .name = "tsensor-cpu3", 285 .offset = 0x12c, 286 .bytes = 4, 287 .bit_offset = 0, 288 .nbits = 32, 289 }, { 290 .name = "sata-calibration", 291 .offset = 0x124, 292 .bytes = 4, 293 .bit_offset = 0, 294 .nbits = 32, 295 }, { 296 .name = "tsensor-gpu", 297 .offset = 0x154, 298 .bytes = 4, 299 .bit_offset = 0, 300 .nbits = 32, 301 }, { 302 .name = "tsensor-mem0", 303 .offset = 0x158, 304 .bytes = 4, 305 .bit_offset = 0, 306 .nbits = 32, 307 }, { 308 .name = "tsensor-mem1", 309 .offset = 0x15c, 310 .bytes = 4, 311 .bit_offset = 0, 312 .nbits = 32, 313 }, { 314 .name = "tsensor-pllx", 315 .offset = 0x160, 316 .bytes = 4, 317 .bit_offset = 0, 318 .nbits = 32, 319 }, { 320 .name = "tsensor-common", 321 .offset = 0x180, 322 .bytes = 4, 323 .bit_offset = 0, 324 .nbits = 32, 325 }, { 326 .name = "tsensor-realignment", 327 .offset = 0x1fc, 328 .bytes = 4, 329 .bit_offset = 0, 330 .nbits = 32, 331 }, 332 }; 333 334 static const struct nvmem_cell_lookup tegra124_fuse_lookups[] = { 335 { 336 .nvmem_name = "fuse", 337 .cell_name = "xusb-pad-calibration", 338 .dev_id = "7009f000.padctl", 339 .con_id = "calibration", 340 }, { 341 .nvmem_name = "fuse", 342 .cell_name = "sata-calibration", 343 .dev_id = "70020000.sata", 344 .con_id = "calibration", 345 }, { 346 .nvmem_name = "fuse", 347 .cell_name = "tsensor-common", 348 .dev_id = "700e2000.thermal-sensor", 349 .con_id = "common", 350 }, { 351 .nvmem_name = "fuse", 352 .cell_name = "tsensor-realignment", 353 .dev_id = "700e2000.thermal-sensor", 354 .con_id = "realignment", 355 }, { 356 .nvmem_name = "fuse", 357 .cell_name = "tsensor-cpu0", 358 .dev_id = "700e2000.thermal-sensor", 359 .con_id = "cpu0", 360 }, { 361 .nvmem_name = "fuse", 362 .cell_name = "tsensor-cpu1", 363 .dev_id = "700e2000.thermal-sensor", 364 .con_id = "cpu1", 365 }, { 366 .nvmem_name = "fuse", 367 .cell_name = "tsensor-cpu2", 368 .dev_id = "700e2000.thermal-sensor", 369 .con_id = "cpu2", 370 }, { 371 .nvmem_name = "fuse", 372 .cell_name = "tsensor-cpu3", 373 .dev_id = "700e2000.thermal-sensor", 374 .con_id = "cpu3", 375 }, { 376 .nvmem_name = "fuse", 377 .cell_name = "tsensor-mem0", 378 .dev_id = "700e2000.thermal-sensor", 379 .con_id = "mem0", 380 }, { 381 .nvmem_name = "fuse", 382 .cell_name = "tsensor-mem1", 383 .dev_id = "700e2000.thermal-sensor", 384 .con_id = "mem1", 385 }, { 386 .nvmem_name = "fuse", 387 .cell_name = "tsensor-gpu", 388 .dev_id = "700e2000.thermal-sensor", 389 .con_id = "gpu", 390 }, { 391 .nvmem_name = "fuse", 392 .cell_name = "tsensor-pllx", 393 .dev_id = "700e2000.thermal-sensor", 394 .con_id = "pllx", 395 }, 396 }; 397 398 static const struct tegra_fuse_info tegra124_fuse_info = { 399 .read = tegra30_fuse_read, 400 .size = 0x300, 401 .spare = 0x200, 402 }; 403 404 const struct tegra_fuse_soc tegra124_fuse_soc = { 405 .init = tegra30_fuse_init, 406 .speedo_init = tegra124_init_speedo_data, 407 .info = &tegra124_fuse_info, 408 .lookups = tegra124_fuse_lookups, 409 .num_lookups = ARRAY_SIZE(tegra124_fuse_lookups), 410 .cells = tegra124_fuse_cells, 411 .num_cells = ARRAY_SIZE(tegra124_fuse_cells), 412 .soc_attr_group = &tegra_soc_attr_group, 413 .clk_suspend_on = true, 414 }; 415 #endif 416 417 #if defined(CONFIG_ARCH_TEGRA_210_SOC) 418 static const struct nvmem_cell_info tegra210_fuse_cells[] = { 419 { 420 .name = "tsensor-cpu1", 421 .offset = 0x084, 422 .bytes = 4, 423 .bit_offset = 0, 424 .nbits = 32, 425 }, { 426 .name = "tsensor-cpu2", 427 .offset = 0x088, 428 .bytes = 4, 429 .bit_offset = 0, 430 .nbits = 32, 431 }, { 432 .name = "tsensor-cpu0", 433 .offset = 0x098, 434 .bytes = 4, 435 .bit_offset = 0, 436 .nbits = 32, 437 }, { 438 .name = "xusb-pad-calibration", 439 .offset = 0x0f0, 440 .bytes = 4, 441 .bit_offset = 0, 442 .nbits = 32, 443 }, { 444 .name = "tsensor-cpu3", 445 .offset = 0x12c, 446 .bytes = 4, 447 .bit_offset = 0, 448 .nbits = 32, 449 }, { 450 .name = "sata-calibration", 451 .offset = 0x124, 452 .bytes = 4, 453 .bit_offset = 0, 454 .nbits = 32, 455 }, { 456 .name = "tsensor-gpu", 457 .offset = 0x154, 458 .bytes = 4, 459 .bit_offset = 0, 460 .nbits = 32, 461 }, { 462 .name = "tsensor-mem0", 463 .offset = 0x158, 464 .bytes = 4, 465 .bit_offset = 0, 466 .nbits = 32, 467 }, { 468 .name = "tsensor-mem1", 469 .offset = 0x15c, 470 .bytes = 4, 471 .bit_offset = 0, 472 .nbits = 32, 473 }, { 474 .name = "tsensor-pllx", 475 .offset = 0x160, 476 .bytes = 4, 477 .bit_offset = 0, 478 .nbits = 32, 479 }, { 480 .name = "tsensor-common", 481 .offset = 0x180, 482 .bytes = 4, 483 .bit_offset = 0, 484 .nbits = 32, 485 }, { 486 .name = "gpu-calibration", 487 .offset = 0x204, 488 .bytes = 4, 489 .bit_offset = 0, 490 .nbits = 32, 491 }, { 492 .name = "xusb-pad-calibration-ext", 493 .offset = 0x250, 494 .bytes = 4, 495 .bit_offset = 0, 496 .nbits = 32, 497 }, 498 }; 499 500 static const struct nvmem_cell_lookup tegra210_fuse_lookups[] = { 501 { 502 .nvmem_name = "fuse", 503 .cell_name = "tsensor-cpu1", 504 .dev_id = "700e2000.thermal-sensor", 505 .con_id = "cpu1", 506 }, { 507 .nvmem_name = "fuse", 508 .cell_name = "tsensor-cpu2", 509 .dev_id = "700e2000.thermal-sensor", 510 .con_id = "cpu2", 511 }, { 512 .nvmem_name = "fuse", 513 .cell_name = "tsensor-cpu0", 514 .dev_id = "700e2000.thermal-sensor", 515 .con_id = "cpu0", 516 }, { 517 .nvmem_name = "fuse", 518 .cell_name = "xusb-pad-calibration", 519 .dev_id = "7009f000.padctl", 520 .con_id = "calibration", 521 }, { 522 .nvmem_name = "fuse", 523 .cell_name = "tsensor-cpu3", 524 .dev_id = "700e2000.thermal-sensor", 525 .con_id = "cpu3", 526 }, { 527 .nvmem_name = "fuse", 528 .cell_name = "sata-calibration", 529 .dev_id = "70020000.sata", 530 .con_id = "calibration", 531 }, { 532 .nvmem_name = "fuse", 533 .cell_name = "tsensor-gpu", 534 .dev_id = "700e2000.thermal-sensor", 535 .con_id = "gpu", 536 }, { 537 .nvmem_name = "fuse", 538 .cell_name = "tsensor-mem0", 539 .dev_id = "700e2000.thermal-sensor", 540 .con_id = "mem0", 541 }, { 542 .nvmem_name = "fuse", 543 .cell_name = "tsensor-mem1", 544 .dev_id = "700e2000.thermal-sensor", 545 .con_id = "mem1", 546 }, { 547 .nvmem_name = "fuse", 548 .cell_name = "tsensor-pllx", 549 .dev_id = "700e2000.thermal-sensor", 550 .con_id = "pllx", 551 }, { 552 .nvmem_name = "fuse", 553 .cell_name = "tsensor-common", 554 .dev_id = "700e2000.thermal-sensor", 555 .con_id = "common", 556 }, { 557 .nvmem_name = "fuse", 558 .cell_name = "gpu-calibration", 559 .dev_id = "57000000.gpu", 560 .con_id = "calibration", 561 }, { 562 .nvmem_name = "fuse", 563 .cell_name = "xusb-pad-calibration-ext", 564 .dev_id = "7009f000.padctl", 565 .con_id = "calibration-ext", 566 }, 567 }; 568 569 static const struct tegra_fuse_info tegra210_fuse_info = { 570 .read = tegra30_fuse_read, 571 .size = 0x300, 572 .spare = 0x280, 573 }; 574 575 const struct tegra_fuse_soc tegra210_fuse_soc = { 576 .init = tegra30_fuse_init, 577 .speedo_init = tegra210_init_speedo_data, 578 .info = &tegra210_fuse_info, 579 .lookups = tegra210_fuse_lookups, 580 .cells = tegra210_fuse_cells, 581 .num_cells = ARRAY_SIZE(tegra210_fuse_cells), 582 .num_lookups = ARRAY_SIZE(tegra210_fuse_lookups), 583 .soc_attr_group = &tegra_soc_attr_group, 584 .clk_suspend_on = false, 585 }; 586 #endif 587 588 #if defined(CONFIG_ARCH_TEGRA_186_SOC) 589 static const struct nvmem_cell_info tegra186_fuse_cells[] = { 590 { 591 .name = "xusb-pad-calibration", 592 .offset = 0x0f0, 593 .bytes = 4, 594 .bit_offset = 0, 595 .nbits = 32, 596 }, { 597 .name = "xusb-pad-calibration-ext", 598 .offset = 0x250, 599 .bytes = 4, 600 .bit_offset = 0, 601 .nbits = 32, 602 }, 603 }; 604 605 static const struct nvmem_cell_lookup tegra186_fuse_lookups[] = { 606 { 607 .nvmem_name = "fuse", 608 .cell_name = "xusb-pad-calibration", 609 .dev_id = "3520000.padctl", 610 .con_id = "calibration", 611 }, { 612 .nvmem_name = "fuse", 613 .cell_name = "xusb-pad-calibration-ext", 614 .dev_id = "3520000.padctl", 615 .con_id = "calibration-ext", 616 }, 617 }; 618 619 static const struct nvmem_keepout tegra186_fuse_keepouts[] = { 620 { .start = 0x01c, .end = 0x0f0 }, 621 { .start = 0x138, .end = 0x198 }, 622 { .start = 0x1d8, .end = 0x250 }, 623 { .start = 0x280, .end = 0x290 }, 624 { .start = 0x340, .end = 0x344 } 625 }; 626 627 static const struct tegra_fuse_info tegra186_fuse_info = { 628 .read = tegra30_fuse_read, 629 .size = 0x478, 630 .spare = 0x280, 631 }; 632 633 const struct tegra_fuse_soc tegra186_fuse_soc = { 634 .init = tegra30_fuse_init, 635 .info = &tegra186_fuse_info, 636 .lookups = tegra186_fuse_lookups, 637 .num_lookups = ARRAY_SIZE(tegra186_fuse_lookups), 638 .cells = tegra186_fuse_cells, 639 .num_cells = ARRAY_SIZE(tegra186_fuse_cells), 640 .keepouts = tegra186_fuse_keepouts, 641 .num_keepouts = ARRAY_SIZE(tegra186_fuse_keepouts), 642 .soc_attr_group = &tegra_soc_attr_group, 643 .clk_suspend_on = false, 644 }; 645 #endif 646 647 #if defined(CONFIG_ARCH_TEGRA_194_SOC) 648 static const struct nvmem_cell_info tegra194_fuse_cells[] = { 649 { 650 .name = "xusb-pad-calibration", 651 .offset = 0x0f0, 652 .bytes = 4, 653 .bit_offset = 0, 654 .nbits = 32, 655 }, { 656 .name = "gpu-gcplex-config-fuse", 657 .offset = 0x1c8, 658 .bytes = 4, 659 .bit_offset = 0, 660 .nbits = 32, 661 }, { 662 .name = "xusb-pad-calibration-ext", 663 .offset = 0x250, 664 .bytes = 4, 665 .bit_offset = 0, 666 .nbits = 32, 667 }, { 668 .name = "gpu-pdi0", 669 .offset = 0x300, 670 .bytes = 4, 671 .bit_offset = 0, 672 .nbits = 32, 673 }, { 674 .name = "gpu-pdi1", 675 .offset = 0x304, 676 .bytes = 4, 677 .bit_offset = 0, 678 .nbits = 32, 679 }, 680 }; 681 682 static const struct nvmem_cell_lookup tegra194_fuse_lookups[] = { 683 { 684 .nvmem_name = "fuse", 685 .cell_name = "xusb-pad-calibration", 686 .dev_id = "3520000.padctl", 687 .con_id = "calibration", 688 }, { 689 .nvmem_name = "fuse", 690 .cell_name = "xusb-pad-calibration-ext", 691 .dev_id = "3520000.padctl", 692 .con_id = "calibration-ext", 693 }, { 694 .nvmem_name = "fuse", 695 .cell_name = "gpu-gcplex-config-fuse", 696 .dev_id = "17000000.gpu", 697 .con_id = "gcplex-config-fuse", 698 }, { 699 .nvmem_name = "fuse", 700 .cell_name = "gpu-pdi0", 701 .dev_id = "17000000.gpu", 702 .con_id = "pdi0", 703 }, { 704 .nvmem_name = "fuse", 705 .cell_name = "gpu-pdi1", 706 .dev_id = "17000000.gpu", 707 .con_id = "pdi1", 708 }, 709 }; 710 711 static const struct nvmem_keepout tegra194_fuse_keepouts[] = { 712 { .start = 0x01c, .end = 0x0b8 }, 713 { .start = 0x12c, .end = 0x198 }, 714 { .start = 0x1a0, .end = 0x1bc }, 715 { .start = 0x1d8, .end = 0x250 }, 716 { .start = 0x270, .end = 0x290 }, 717 { .start = 0x310, .end = 0x45c } 718 }; 719 720 static const struct tegra_fuse_info tegra194_fuse_info = { 721 .read = tegra30_fuse_read, 722 .size = 0x650, 723 .spare = 0x280, 724 }; 725 726 const struct tegra_fuse_soc tegra194_fuse_soc = { 727 .init = tegra30_fuse_init, 728 .info = &tegra194_fuse_info, 729 .lookups = tegra194_fuse_lookups, 730 .num_lookups = ARRAY_SIZE(tegra194_fuse_lookups), 731 .cells = tegra194_fuse_cells, 732 .num_cells = ARRAY_SIZE(tegra194_fuse_cells), 733 .keepouts = tegra194_fuse_keepouts, 734 .num_keepouts = ARRAY_SIZE(tegra194_fuse_keepouts), 735 .soc_attr_group = &tegra194_soc_attr_group, 736 .clk_suspend_on = false, 737 }; 738 #endif 739 740 #if defined(CONFIG_ARCH_TEGRA_234_SOC) 741 static const struct nvmem_cell_info tegra234_fuse_cells[] = { 742 { 743 .name = "xusb-pad-calibration", 744 .offset = 0x0f0, 745 .bytes = 4, 746 .bit_offset = 0, 747 .nbits = 32, 748 }, { 749 .name = "xusb-pad-calibration-ext", 750 .offset = 0x250, 751 .bytes = 4, 752 .bit_offset = 0, 753 .nbits = 32, 754 }, 755 }; 756 757 static const struct nvmem_cell_lookup tegra234_fuse_lookups[] = { 758 { 759 .nvmem_name = "fuse", 760 .cell_name = "xusb-pad-calibration", 761 .dev_id = "3520000.padctl", 762 .con_id = "calibration", 763 }, { 764 .nvmem_name = "fuse", 765 .cell_name = "xusb-pad-calibration-ext", 766 .dev_id = "3520000.padctl", 767 .con_id = "calibration-ext", 768 }, 769 }; 770 771 static const struct nvmem_keepout tegra234_fuse_keepouts[] = { 772 { .start = 0x01c, .end = 0x064 }, 773 { .start = 0x084, .end = 0x0a0 }, 774 { .start = 0x0a4, .end = 0x0c8 }, 775 { .start = 0x12c, .end = 0x164 }, 776 { .start = 0x16c, .end = 0x184 }, 777 { .start = 0x190, .end = 0x198 }, 778 { .start = 0x1a0, .end = 0x204 }, 779 { .start = 0x21c, .end = 0x2f0 }, 780 { .start = 0x310, .end = 0x3d8 }, 781 { .start = 0x400, .end = 0x420 }, 782 { .start = 0x444, .end = 0x490 }, 783 { .start = 0x4bc, .end = 0x4f0 }, 784 { .start = 0x4f8, .end = 0x54c }, 785 { .start = 0x57c, .end = 0x7e8 }, 786 { .start = 0x8d0, .end = 0x8d8 }, 787 { .start = 0xacc, .end = 0xf00 } 788 }; 789 790 static const struct tegra_fuse_info tegra234_fuse_info = { 791 .read = tegra30_fuse_read, 792 .size = 0xf90, 793 .spare = 0x280, 794 }; 795 796 const struct tegra_fuse_soc tegra234_fuse_soc = { 797 .init = tegra30_fuse_init, 798 .info = &tegra234_fuse_info, 799 .lookups = tegra234_fuse_lookups, 800 .num_lookups = ARRAY_SIZE(tegra234_fuse_lookups), 801 .cells = tegra234_fuse_cells, 802 .num_cells = ARRAY_SIZE(tegra234_fuse_cells), 803 .keepouts = tegra234_fuse_keepouts, 804 .num_keepouts = ARRAY_SIZE(tegra234_fuse_keepouts), 805 .soc_attr_group = &tegra194_soc_attr_group, 806 .clk_suspend_on = false, 807 }; 808 #endif 809 810 #if defined(CONFIG_ARCH_TEGRA_241_SOC) 811 static const struct tegra_fuse_info tegra241_fuse_info = { 812 .read = tegra30_fuse_read, 813 .size = 0x16008, 814 .spare = 0xcf0, 815 }; 816 817 static const struct nvmem_keepout tegra241_fuse_keepouts[] = { 818 { .start = 0xc, .end = 0x1600c } 819 }; 820 821 const struct tegra_fuse_soc tegra241_fuse_soc = { 822 .init = tegra30_fuse_init, 823 .info = &tegra241_fuse_info, 824 .keepouts = tegra241_fuse_keepouts, 825 .num_keepouts = ARRAY_SIZE(tegra241_fuse_keepouts), 826 .soc_attr_group = &tegra194_soc_attr_group, 827 }; 828 #endif 829