1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013-2022, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/device.h> 7 #include <linux/clk.h> 8 #include <linux/err.h> 9 #include <linux/io.h> 10 #include <linux/kernel.h> 11 #include <linux/nvmem-consumer.h> 12 #include <linux/nvmem-provider.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/random.h> 16 17 #include <soc/tegra/fuse.h> 18 19 #include "fuse.h" 20 21 #define FUSE_BEGIN 0x100 22 23 /* Tegra30 and later */ 24 #define FUSE_VENDOR_CODE 0x100 25 #define FUSE_FAB_CODE 0x104 26 #define FUSE_LOT_CODE_0 0x108 27 #define FUSE_LOT_CODE_1 0x10c 28 #define FUSE_WAFER_ID 0x110 29 #define FUSE_X_COORDINATE 0x114 30 #define FUSE_Y_COORDINATE 0x118 31 32 #define FUSE_HAS_REVISION_INFO BIT(0) 33 34 #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \ 35 defined(CONFIG_ARCH_TEGRA_114_SOC) || \ 36 defined(CONFIG_ARCH_TEGRA_124_SOC) || \ 37 defined(CONFIG_ARCH_TEGRA_132_SOC) || \ 38 defined(CONFIG_ARCH_TEGRA_210_SOC) || \ 39 defined(CONFIG_ARCH_TEGRA_186_SOC) || \ 40 defined(CONFIG_ARCH_TEGRA_194_SOC) || \ 41 defined(CONFIG_ARCH_TEGRA_234_SOC) || \ 42 defined(CONFIG_ARCH_TEGRA_241_SOC) || \ 43 defined(CONFIG_ARCH_TEGRA_264_SOC) 44 static u32 tegra30_fuse_read_early(struct tegra_fuse *fuse, unsigned int offset) 45 { 46 if (WARN_ON(!fuse->base)) 47 return 0; 48 49 return readl_relaxed(fuse->base + FUSE_BEGIN + offset); 50 } 51 52 static u32 tegra30_fuse_read(struct tegra_fuse *fuse, unsigned int offset) 53 { 54 u32 value; 55 int err; 56 57 err = pm_runtime_resume_and_get(fuse->dev); 58 if (err) 59 return 0; 60 61 value = readl_relaxed(fuse->base + FUSE_BEGIN + offset); 62 63 pm_runtime_put(fuse->dev); 64 65 return value; 66 } 67 68 static void __init tegra30_fuse_init(struct tegra_fuse *fuse) 69 { 70 fuse->read_early = tegra30_fuse_read_early; 71 fuse->read = tegra30_fuse_read; 72 73 tegra_init_revision(); 74 75 if (fuse->soc->speedo_init) 76 fuse->soc->speedo_init(&tegra_sku_info); 77 } 78 #endif 79 80 #ifdef CONFIG_ARCH_TEGRA_3x_SOC 81 static const struct tegra_fuse_info tegra30_fuse_info = { 82 .read = tegra30_fuse_read, 83 .size = 0x2a4, 84 .spare = 0x144, 85 }; 86 87 const struct tegra_fuse_soc tegra30_fuse_soc = { 88 .init = tegra30_fuse_init, 89 .speedo_init = tegra30_init_speedo_data, 90 .info = &tegra30_fuse_info, 91 .soc_attr_group = &tegra_soc_attr_group, 92 .clk_suspend_on = false, 93 }; 94 #endif 95 96 #ifdef CONFIG_ARCH_TEGRA_114_SOC 97 static const struct nvmem_cell_info tegra114_fuse_cells[] = { 98 { 99 .name = "tsensor-cpu1", 100 .offset = 0x084, 101 .bytes = 4, 102 .bit_offset = 0, 103 .nbits = 32, 104 }, { 105 .name = "tsensor-cpu2", 106 .offset = 0x088, 107 .bytes = 4, 108 .bit_offset = 0, 109 .nbits = 32, 110 }, { 111 .name = "tsensor-common", 112 .offset = 0x08c, 113 .bytes = 4, 114 .bit_offset = 0, 115 .nbits = 32, 116 }, { 117 .name = "tsensor-cpu0", 118 .offset = 0x098, 119 .bytes = 4, 120 .bit_offset = 0, 121 .nbits = 32, 122 }, { 123 .name = "xusb-pad-calibration", 124 .offset = 0x0f0, 125 .bytes = 4, 126 .bit_offset = 0, 127 .nbits = 32, 128 }, { 129 .name = "tsensor-cpu3", 130 .offset = 0x12c, 131 .bytes = 4, 132 .bit_offset = 0, 133 .nbits = 32, 134 }, { 135 .name = "tsensor-gpu", 136 .offset = 0x154, 137 .bytes = 4, 138 .bit_offset = 0, 139 .nbits = 32, 140 }, { 141 .name = "tsensor-mem0", 142 .offset = 0x158, 143 .bytes = 4, 144 .bit_offset = 0, 145 .nbits = 32, 146 }, { 147 .name = "tsensor-mem1", 148 .offset = 0x15c, 149 .bytes = 4, 150 .bit_offset = 0, 151 .nbits = 32, 152 }, { 153 .name = "tsensor-pllx", 154 .offset = 0x160, 155 .bytes = 4, 156 .bit_offset = 0, 157 .nbits = 32, 158 }, 159 }; 160 161 static const struct nvmem_cell_lookup tegra114_fuse_lookups[] = { 162 { 163 .nvmem_name = "fuse", 164 .cell_name = "xusb-pad-calibration", 165 .dev_id = "7009f000.padctl", 166 .con_id = "calibration", 167 }, { 168 .nvmem_name = "fuse", 169 .cell_name = "tsensor-common", 170 .dev_id = "700e2000.thermal-sensor", 171 .con_id = "common", 172 }, { 173 .nvmem_name = "fuse", 174 .cell_name = "tsensor-cpu0", 175 .dev_id = "700e2000.thermal-sensor", 176 .con_id = "cpu0", 177 }, { 178 .nvmem_name = "fuse", 179 .cell_name = "tsensor-cpu1", 180 .dev_id = "700e2000.thermal-sensor", 181 .con_id = "cpu1", 182 }, { 183 .nvmem_name = "fuse", 184 .cell_name = "tsensor-cpu2", 185 .dev_id = "700e2000.thermal-sensor", 186 .con_id = "cpu2", 187 }, { 188 .nvmem_name = "fuse", 189 .cell_name = "tsensor-cpu3", 190 .dev_id = "700e2000.thermal-sensor", 191 .con_id = "cpu3", 192 }, { 193 .nvmem_name = "fuse", 194 .cell_name = "tsensor-mem0", 195 .dev_id = "700e2000.thermal-sensor", 196 .con_id = "mem0", 197 }, { 198 .nvmem_name = "fuse", 199 .cell_name = "tsensor-mem1", 200 .dev_id = "700e2000.thermal-sensor", 201 .con_id = "mem1", 202 }, { 203 .nvmem_name = "fuse", 204 .cell_name = "tsensor-gpu", 205 .dev_id = "700e2000.thermal-sensor", 206 .con_id = "gpu", 207 }, { 208 .nvmem_name = "fuse", 209 .cell_name = "tsensor-pllx", 210 .dev_id = "700e2000.thermal-sensor", 211 .con_id = "pllx", 212 }, 213 }; 214 215 static const struct tegra_fuse_info tegra114_fuse_info = { 216 .read = tegra30_fuse_read, 217 .size = 0x2a0, 218 .spare = 0x180, 219 }; 220 221 const struct tegra_fuse_soc tegra114_fuse_soc = { 222 .init = tegra30_fuse_init, 223 .speedo_init = tegra114_init_speedo_data, 224 .info = &tegra114_fuse_info, 225 .lookups = tegra114_fuse_lookups, 226 .num_lookups = ARRAY_SIZE(tegra114_fuse_lookups), 227 .cells = tegra114_fuse_cells, 228 .num_cells = ARRAY_SIZE(tegra114_fuse_cells), 229 .soc_attr_group = &tegra_soc_attr_group, 230 .clk_suspend_on = false, 231 }; 232 #endif 233 234 #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) 235 static const struct nvmem_cell_info tegra124_fuse_cells[] = { 236 { 237 .name = "tsensor-cpu1", 238 .offset = 0x084, 239 .bytes = 4, 240 .bit_offset = 0, 241 .nbits = 32, 242 }, { 243 .name = "tsensor-cpu2", 244 .offset = 0x088, 245 .bytes = 4, 246 .bit_offset = 0, 247 .nbits = 32, 248 }, { 249 .name = "tsensor-cpu0", 250 .offset = 0x098, 251 .bytes = 4, 252 .bit_offset = 0, 253 .nbits = 32, 254 }, { 255 .name = "xusb-pad-calibration", 256 .offset = 0x0f0, 257 .bytes = 4, 258 .bit_offset = 0, 259 .nbits = 32, 260 }, { 261 .name = "tsensor-cpu3", 262 .offset = 0x12c, 263 .bytes = 4, 264 .bit_offset = 0, 265 .nbits = 32, 266 }, { 267 .name = "sata-calibration", 268 .offset = 0x124, 269 .bytes = 4, 270 .bit_offset = 0, 271 .nbits = 32, 272 }, { 273 .name = "tsensor-gpu", 274 .offset = 0x154, 275 .bytes = 4, 276 .bit_offset = 0, 277 .nbits = 32, 278 }, { 279 .name = "tsensor-mem0", 280 .offset = 0x158, 281 .bytes = 4, 282 .bit_offset = 0, 283 .nbits = 32, 284 }, { 285 .name = "tsensor-mem1", 286 .offset = 0x15c, 287 .bytes = 4, 288 .bit_offset = 0, 289 .nbits = 32, 290 }, { 291 .name = "tsensor-pllx", 292 .offset = 0x160, 293 .bytes = 4, 294 .bit_offset = 0, 295 .nbits = 32, 296 }, { 297 .name = "tsensor-common", 298 .offset = 0x180, 299 .bytes = 4, 300 .bit_offset = 0, 301 .nbits = 32, 302 }, { 303 .name = "tsensor-realignment", 304 .offset = 0x1fc, 305 .bytes = 4, 306 .bit_offset = 0, 307 .nbits = 32, 308 }, 309 }; 310 311 static const struct nvmem_cell_lookup tegra124_fuse_lookups[] = { 312 { 313 .nvmem_name = "fuse", 314 .cell_name = "xusb-pad-calibration", 315 .dev_id = "7009f000.padctl", 316 .con_id = "calibration", 317 }, { 318 .nvmem_name = "fuse", 319 .cell_name = "sata-calibration", 320 .dev_id = "70020000.sata", 321 .con_id = "calibration", 322 }, { 323 .nvmem_name = "fuse", 324 .cell_name = "tsensor-common", 325 .dev_id = "700e2000.thermal-sensor", 326 .con_id = "common", 327 }, { 328 .nvmem_name = "fuse", 329 .cell_name = "tsensor-realignment", 330 .dev_id = "700e2000.thermal-sensor", 331 .con_id = "realignment", 332 }, { 333 .nvmem_name = "fuse", 334 .cell_name = "tsensor-cpu0", 335 .dev_id = "700e2000.thermal-sensor", 336 .con_id = "cpu0", 337 }, { 338 .nvmem_name = "fuse", 339 .cell_name = "tsensor-cpu1", 340 .dev_id = "700e2000.thermal-sensor", 341 .con_id = "cpu1", 342 }, { 343 .nvmem_name = "fuse", 344 .cell_name = "tsensor-cpu2", 345 .dev_id = "700e2000.thermal-sensor", 346 .con_id = "cpu2", 347 }, { 348 .nvmem_name = "fuse", 349 .cell_name = "tsensor-cpu3", 350 .dev_id = "700e2000.thermal-sensor", 351 .con_id = "cpu3", 352 }, { 353 .nvmem_name = "fuse", 354 .cell_name = "tsensor-mem0", 355 .dev_id = "700e2000.thermal-sensor", 356 .con_id = "mem0", 357 }, { 358 .nvmem_name = "fuse", 359 .cell_name = "tsensor-mem1", 360 .dev_id = "700e2000.thermal-sensor", 361 .con_id = "mem1", 362 }, { 363 .nvmem_name = "fuse", 364 .cell_name = "tsensor-gpu", 365 .dev_id = "700e2000.thermal-sensor", 366 .con_id = "gpu", 367 }, { 368 .nvmem_name = "fuse", 369 .cell_name = "tsensor-pllx", 370 .dev_id = "700e2000.thermal-sensor", 371 .con_id = "pllx", 372 }, 373 }; 374 375 static const struct tegra_fuse_info tegra124_fuse_info = { 376 .read = tegra30_fuse_read, 377 .size = 0x300, 378 .spare = 0x200, 379 }; 380 381 const struct tegra_fuse_soc tegra124_fuse_soc = { 382 .init = tegra30_fuse_init, 383 .speedo_init = tegra124_init_speedo_data, 384 .info = &tegra124_fuse_info, 385 .lookups = tegra124_fuse_lookups, 386 .num_lookups = ARRAY_SIZE(tegra124_fuse_lookups), 387 .cells = tegra124_fuse_cells, 388 .num_cells = ARRAY_SIZE(tegra124_fuse_cells), 389 .soc_attr_group = &tegra_soc_attr_group, 390 .clk_suspend_on = true, 391 }; 392 #endif 393 394 #if defined(CONFIG_ARCH_TEGRA_210_SOC) 395 static const struct nvmem_cell_info tegra210_fuse_cells[] = { 396 { 397 .name = "tsensor-cpu1", 398 .offset = 0x084, 399 .bytes = 4, 400 .bit_offset = 0, 401 .nbits = 32, 402 }, { 403 .name = "tsensor-cpu2", 404 .offset = 0x088, 405 .bytes = 4, 406 .bit_offset = 0, 407 .nbits = 32, 408 }, { 409 .name = "tsensor-cpu0", 410 .offset = 0x098, 411 .bytes = 4, 412 .bit_offset = 0, 413 .nbits = 32, 414 }, { 415 .name = "xusb-pad-calibration", 416 .offset = 0x0f0, 417 .bytes = 4, 418 .bit_offset = 0, 419 .nbits = 32, 420 }, { 421 .name = "tsensor-cpu3", 422 .offset = 0x12c, 423 .bytes = 4, 424 .bit_offset = 0, 425 .nbits = 32, 426 }, { 427 .name = "sata-calibration", 428 .offset = 0x124, 429 .bytes = 4, 430 .bit_offset = 0, 431 .nbits = 32, 432 }, { 433 .name = "tsensor-gpu", 434 .offset = 0x154, 435 .bytes = 4, 436 .bit_offset = 0, 437 .nbits = 32, 438 }, { 439 .name = "tsensor-mem0", 440 .offset = 0x158, 441 .bytes = 4, 442 .bit_offset = 0, 443 .nbits = 32, 444 }, { 445 .name = "tsensor-mem1", 446 .offset = 0x15c, 447 .bytes = 4, 448 .bit_offset = 0, 449 .nbits = 32, 450 }, { 451 .name = "tsensor-pllx", 452 .offset = 0x160, 453 .bytes = 4, 454 .bit_offset = 0, 455 .nbits = 32, 456 }, { 457 .name = "tsensor-common", 458 .offset = 0x180, 459 .bytes = 4, 460 .bit_offset = 0, 461 .nbits = 32, 462 }, { 463 .name = "gpu-calibration", 464 .offset = 0x204, 465 .bytes = 4, 466 .bit_offset = 0, 467 .nbits = 32, 468 }, { 469 .name = "xusb-pad-calibration-ext", 470 .offset = 0x250, 471 .bytes = 4, 472 .bit_offset = 0, 473 .nbits = 32, 474 }, 475 }; 476 477 static const struct nvmem_cell_lookup tegra210_fuse_lookups[] = { 478 { 479 .nvmem_name = "fuse", 480 .cell_name = "tsensor-cpu1", 481 .dev_id = "700e2000.thermal-sensor", 482 .con_id = "cpu1", 483 }, { 484 .nvmem_name = "fuse", 485 .cell_name = "tsensor-cpu2", 486 .dev_id = "700e2000.thermal-sensor", 487 .con_id = "cpu2", 488 }, { 489 .nvmem_name = "fuse", 490 .cell_name = "tsensor-cpu0", 491 .dev_id = "700e2000.thermal-sensor", 492 .con_id = "cpu0", 493 }, { 494 .nvmem_name = "fuse", 495 .cell_name = "xusb-pad-calibration", 496 .dev_id = "7009f000.padctl", 497 .con_id = "calibration", 498 }, { 499 .nvmem_name = "fuse", 500 .cell_name = "tsensor-cpu3", 501 .dev_id = "700e2000.thermal-sensor", 502 .con_id = "cpu3", 503 }, { 504 .nvmem_name = "fuse", 505 .cell_name = "sata-calibration", 506 .dev_id = "70020000.sata", 507 .con_id = "calibration", 508 }, { 509 .nvmem_name = "fuse", 510 .cell_name = "tsensor-gpu", 511 .dev_id = "700e2000.thermal-sensor", 512 .con_id = "gpu", 513 }, { 514 .nvmem_name = "fuse", 515 .cell_name = "tsensor-mem0", 516 .dev_id = "700e2000.thermal-sensor", 517 .con_id = "mem0", 518 }, { 519 .nvmem_name = "fuse", 520 .cell_name = "tsensor-mem1", 521 .dev_id = "700e2000.thermal-sensor", 522 .con_id = "mem1", 523 }, { 524 .nvmem_name = "fuse", 525 .cell_name = "tsensor-pllx", 526 .dev_id = "700e2000.thermal-sensor", 527 .con_id = "pllx", 528 }, { 529 .nvmem_name = "fuse", 530 .cell_name = "tsensor-common", 531 .dev_id = "700e2000.thermal-sensor", 532 .con_id = "common", 533 }, { 534 .nvmem_name = "fuse", 535 .cell_name = "gpu-calibration", 536 .dev_id = "57000000.gpu", 537 .con_id = "calibration", 538 }, { 539 .nvmem_name = "fuse", 540 .cell_name = "xusb-pad-calibration-ext", 541 .dev_id = "7009f000.padctl", 542 .con_id = "calibration-ext", 543 }, 544 }; 545 546 static const struct tegra_fuse_info tegra210_fuse_info = { 547 .read = tegra30_fuse_read, 548 .size = 0x300, 549 .spare = 0x280, 550 }; 551 552 const struct tegra_fuse_soc tegra210_fuse_soc = { 553 .init = tegra30_fuse_init, 554 .speedo_init = tegra210_init_speedo_data, 555 .info = &tegra210_fuse_info, 556 .lookups = tegra210_fuse_lookups, 557 .cells = tegra210_fuse_cells, 558 .num_cells = ARRAY_SIZE(tegra210_fuse_cells), 559 .num_lookups = ARRAY_SIZE(tegra210_fuse_lookups), 560 .soc_attr_group = &tegra_soc_attr_group, 561 .clk_suspend_on = false, 562 }; 563 #endif 564 565 #if defined(CONFIG_ARCH_TEGRA_186_SOC) 566 static const struct nvmem_cell_info tegra186_fuse_cells[] = { 567 { 568 .name = "xusb-pad-calibration", 569 .offset = 0x0f0, 570 .bytes = 4, 571 .bit_offset = 0, 572 .nbits = 32, 573 }, { 574 .name = "xusb-pad-calibration-ext", 575 .offset = 0x250, 576 .bytes = 4, 577 .bit_offset = 0, 578 .nbits = 32, 579 }, 580 }; 581 582 static const struct nvmem_cell_lookup tegra186_fuse_lookups[] = { 583 { 584 .nvmem_name = "fuse", 585 .cell_name = "xusb-pad-calibration", 586 .dev_id = "3520000.padctl", 587 .con_id = "calibration", 588 }, { 589 .nvmem_name = "fuse", 590 .cell_name = "xusb-pad-calibration-ext", 591 .dev_id = "3520000.padctl", 592 .con_id = "calibration-ext", 593 }, 594 }; 595 596 static const struct nvmem_keepout tegra186_fuse_keepouts[] = { 597 { .start = 0x01c, .end = 0x0f0 }, 598 { .start = 0x138, .end = 0x198 }, 599 { .start = 0x1d8, .end = 0x250 }, 600 { .start = 0x280, .end = 0x290 }, 601 { .start = 0x340, .end = 0x344 } 602 }; 603 604 static const struct tegra_fuse_info tegra186_fuse_info = { 605 .read = tegra30_fuse_read, 606 .size = 0x478, 607 .spare = 0x280, 608 }; 609 610 const struct tegra_fuse_soc tegra186_fuse_soc = { 611 .init = tegra30_fuse_init, 612 .info = &tegra186_fuse_info, 613 .lookups = tegra186_fuse_lookups, 614 .num_lookups = ARRAY_SIZE(tegra186_fuse_lookups), 615 .cells = tegra186_fuse_cells, 616 .num_cells = ARRAY_SIZE(tegra186_fuse_cells), 617 .keepouts = tegra186_fuse_keepouts, 618 .num_keepouts = ARRAY_SIZE(tegra186_fuse_keepouts), 619 .soc_attr_group = &tegra_soc_attr_group, 620 .clk_suspend_on = false, 621 }; 622 #endif 623 624 #if defined(CONFIG_ARCH_TEGRA_194_SOC) 625 static const struct nvmem_cell_info tegra194_fuse_cells[] = { 626 { 627 .name = "xusb-pad-calibration", 628 .offset = 0x0f0, 629 .bytes = 4, 630 .bit_offset = 0, 631 .nbits = 32, 632 }, { 633 .name = "gpu-gcplex-config-fuse", 634 .offset = 0x1c8, 635 .bytes = 4, 636 .bit_offset = 0, 637 .nbits = 32, 638 }, { 639 .name = "xusb-pad-calibration-ext", 640 .offset = 0x250, 641 .bytes = 4, 642 .bit_offset = 0, 643 .nbits = 32, 644 }, { 645 .name = "gpu-pdi0", 646 .offset = 0x300, 647 .bytes = 4, 648 .bit_offset = 0, 649 .nbits = 32, 650 }, { 651 .name = "gpu-pdi1", 652 .offset = 0x304, 653 .bytes = 4, 654 .bit_offset = 0, 655 .nbits = 32, 656 }, 657 }; 658 659 static const struct nvmem_cell_lookup tegra194_fuse_lookups[] = { 660 { 661 .nvmem_name = "fuse", 662 .cell_name = "xusb-pad-calibration", 663 .dev_id = "3520000.padctl", 664 .con_id = "calibration", 665 }, { 666 .nvmem_name = "fuse", 667 .cell_name = "xusb-pad-calibration-ext", 668 .dev_id = "3520000.padctl", 669 .con_id = "calibration-ext", 670 }, { 671 .nvmem_name = "fuse", 672 .cell_name = "gpu-gcplex-config-fuse", 673 .dev_id = "17000000.gpu", 674 .con_id = "gcplex-config-fuse", 675 }, { 676 .nvmem_name = "fuse", 677 .cell_name = "gpu-pdi0", 678 .dev_id = "17000000.gpu", 679 .con_id = "pdi0", 680 }, { 681 .nvmem_name = "fuse", 682 .cell_name = "gpu-pdi1", 683 .dev_id = "17000000.gpu", 684 .con_id = "pdi1", 685 }, 686 }; 687 688 static const struct nvmem_keepout tegra194_fuse_keepouts[] = { 689 { .start = 0x01c, .end = 0x0b8 }, 690 { .start = 0x12c, .end = 0x198 }, 691 { .start = 0x1a0, .end = 0x1bc }, 692 { .start = 0x1d8, .end = 0x250 }, 693 { .start = 0x270, .end = 0x290 }, 694 { .start = 0x310, .end = 0x45c } 695 }; 696 697 static const struct tegra_fuse_info tegra194_fuse_info = { 698 .read = tegra30_fuse_read, 699 .size = 0x650, 700 .spare = 0x280, 701 }; 702 703 const struct tegra_fuse_soc tegra194_fuse_soc = { 704 .init = tegra30_fuse_init, 705 .info = &tegra194_fuse_info, 706 .lookups = tegra194_fuse_lookups, 707 .num_lookups = ARRAY_SIZE(tegra194_fuse_lookups), 708 .cells = tegra194_fuse_cells, 709 .num_cells = ARRAY_SIZE(tegra194_fuse_cells), 710 .keepouts = tegra194_fuse_keepouts, 711 .num_keepouts = ARRAY_SIZE(tegra194_fuse_keepouts), 712 .soc_attr_group = &tegra194_soc_attr_group, 713 .clk_suspend_on = false, 714 }; 715 #endif 716 717 #if defined(CONFIG_ARCH_TEGRA_234_SOC) 718 static const struct nvmem_cell_info tegra234_fuse_cells[] = { 719 { 720 .name = "xusb-pad-calibration", 721 .offset = 0x0f0, 722 .bytes = 4, 723 .bit_offset = 0, 724 .nbits = 32, 725 }, { 726 .name = "xusb-pad-calibration-ext", 727 .offset = 0x250, 728 .bytes = 4, 729 .bit_offset = 0, 730 .nbits = 32, 731 }, 732 }; 733 734 static const struct nvmem_cell_lookup tegra234_fuse_lookups[] = { 735 { 736 .nvmem_name = "fuse", 737 .cell_name = "xusb-pad-calibration", 738 .dev_id = "3520000.padctl", 739 .con_id = "calibration", 740 }, { 741 .nvmem_name = "fuse", 742 .cell_name = "xusb-pad-calibration-ext", 743 .dev_id = "3520000.padctl", 744 .con_id = "calibration-ext", 745 }, 746 }; 747 748 static const struct nvmem_keepout tegra234_fuse_keepouts[] = { 749 { .start = 0x01c, .end = 0x064 }, 750 { .start = 0x084, .end = 0x0a0 }, 751 { .start = 0x0a4, .end = 0x0c8 }, 752 { .start = 0x12c, .end = 0x164 }, 753 { .start = 0x16c, .end = 0x184 }, 754 { .start = 0x190, .end = 0x198 }, 755 { .start = 0x1a0, .end = 0x204 }, 756 { .start = 0x21c, .end = 0x2f0 }, 757 { .start = 0x310, .end = 0x3d8 }, 758 { .start = 0x400, .end = 0x420 }, 759 { .start = 0x444, .end = 0x490 }, 760 { .start = 0x4bc, .end = 0x4f0 }, 761 { .start = 0x4f8, .end = 0x54c }, 762 { .start = 0x57c, .end = 0x7e8 }, 763 { .start = 0x8d0, .end = 0x8d8 }, 764 { .start = 0xacc, .end = 0xf00 } 765 }; 766 767 static const struct tegra_fuse_info tegra234_fuse_info = { 768 .read = tegra30_fuse_read, 769 .size = 0xf90, 770 .spare = 0x280, 771 }; 772 773 const struct tegra_fuse_soc tegra234_fuse_soc = { 774 .init = tegra30_fuse_init, 775 .info = &tegra234_fuse_info, 776 .lookups = tegra234_fuse_lookups, 777 .num_lookups = ARRAY_SIZE(tegra234_fuse_lookups), 778 .cells = tegra234_fuse_cells, 779 .num_cells = ARRAY_SIZE(tegra234_fuse_cells), 780 .keepouts = tegra234_fuse_keepouts, 781 .num_keepouts = ARRAY_SIZE(tegra234_fuse_keepouts), 782 .soc_attr_group = &tegra194_soc_attr_group, 783 .clk_suspend_on = false, 784 }; 785 #endif 786 787 #if defined(CONFIG_ARCH_TEGRA_241_SOC) 788 static const struct tegra_fuse_info tegra241_fuse_info = { 789 .read = tegra30_fuse_read, 790 .size = 0x16008, 791 .spare = 0xcf0, 792 }; 793 794 static const struct nvmem_keepout tegra241_fuse_keepouts[] = { 795 { .start = 0xc, .end = 0x1600c } 796 }; 797 798 const struct tegra_fuse_soc tegra241_fuse_soc = { 799 .init = tegra30_fuse_init, 800 .info = &tegra241_fuse_info, 801 .keepouts = tegra241_fuse_keepouts, 802 .num_keepouts = ARRAY_SIZE(tegra241_fuse_keepouts), 803 .soc_attr_group = &tegra194_soc_attr_group, 804 }; 805 #endif 806 807 #ifdef CONFIG_ARCH_TEGRA_264_SOC 808 static const struct nvmem_keepout tegra264_fuse_keepouts[] = { 809 { .start = 0x0019c, .end = 0x001a0 }, 810 { .start = 0x00308, .end = 0x00310 }, 811 { .start = 0x0032c, .end = 0x00334 }, 812 { .start = 0x00350, .end = 0x00354 }, 813 { .start = 0x00494, .end = 0x0049c }, 814 { .start = 0x0078c, .end = 0x00790 }, 815 { .start = 0x007a0, .end = 0x007a8 }, 816 { .start = 0x007dc, .end = 0x007e4 }, 817 { .start = 0x008d8, .end = 0x008dc }, 818 { .start = 0x0096c, .end = 0x00970 }, 819 { .start = 0x00974, .end = 0x0097c }, 820 { .start = 0x009f4, .end = 0x009f8 }, 821 { .start = 0x00a14, .end = 0x00a20 }, 822 { .start = 0x00a44, .end = 0x00a4c }, 823 { .start = 0x00a50, .end = 0x00a58 }, 824 { .start = 0x00a5c, .end = 0x00a64 }, 825 { .start = 0x00a68, .end = 0x00a70 }, 826 { .start = 0x00acc, .end = 0x00ad0 }, 827 { .start = 0x00b0c, .end = 0x00b18 }, 828 { .start = 0x00c80, .end = 0x00c8c }, 829 { .start = 0x00dac, .end = 0x00db4 }, 830 { .start = 0x00db8, .end = 0x00dbc }, 831 { .start = 0x00e0c, .end = 0x00e10 }, 832 { .start = 0x00fd0, .end = 0x01f00 }, 833 { .start = 0x01f1c, .end = 0x10064 }, 834 { .start = 0x10084, .end = 0x100a0 }, 835 { .start = 0x100a4, .end = 0x1019c }, 836 { .start = 0x101a0, .end = 0x101cc }, 837 { .start = 0x101d0, .end = 0x10308 }, 838 { .start = 0x10310, .end = 0x1055c }, 839 { .start = 0x1057c, .end = 0x106b0 }, 840 { .start = 0x106b4, .end = 0x11008 }, 841 { .start = 0x1100c, .end = 0x11018 }, 842 { .start = 0x11020, .end = 0x110b8 }, 843 { .start = 0x110c4, .end = 0x110c8 }, 844 { .start = 0x110e8, .end = 0x110ec }, 845 { .start = 0x110f0, .end = 0x11124 }, 846 { .start = 0x11128, .end = 0x11168 }, 847 { .start = 0x1116c, .end = 0x111b8 }, 848 { .start = 0x111bc, .end = 0x111e4 }, 849 { .start = 0x111e8, .end = 0x111ec }, 850 { .start = 0x111f0, .end = 0x1121c }, 851 { .start = 0x11250, .end = 0x1133c }, 852 { .start = 0x11340, .end = 0x113c8 }, 853 { .start = 0x113d0, .end = 0x11420 }, 854 { .start = 0x11430, .end = 0x11440 }, 855 { .start = 0x11444, .end = 0x11468 }, 856 { .start = 0x1146c, .end = 0x114a8 }, 857 { .start = 0x114ac, .end = 0x115cc }, 858 { .start = 0x115d0, .end = 0x115dc }, 859 { .start = 0x115e0, .end = 0x116b4 }, 860 { .start = 0x116bc, .end = 0x11740 }, 861 { .start = 0x11744, .end = 0x117b8 }, 862 { .start = 0x117bc, .end = 0x11810 }, 863 { .start = 0x11814, .end = 0x11850 }, 864 { .start = 0x11858, .end = 0x118a0 }, 865 { .start = 0x118ac, .end = 0x11b48 }, 866 { .start = 0x11b50, .end = 0x11b5c }, 867 { .start = 0x11b60, .end = 0x11bf8 }, 868 { .start = 0x11bfc, .end = 0x11c18 }, 869 { .start = 0x11c40, .end = 0x12000 }, 870 { .start = 0x12004, .end = 0x12010 }, 871 { .start = 0x12014, .end = 0x120fc }, 872 { .start = 0x1211c, .end = 0x12120 }, 873 { .start = 0x12124, .end = 0x12144 }, 874 { .start = 0x1214c, .end = 0x12300 }, 875 { .start = 0x12308, .end = 0x1236c }, 876 { .start = 0x12370, .end = 0x126ac }, 877 { .start = 0x126b0, .end = 0x12c60 }, 878 { .start = 0x12c64, .end = 0x12d94 }, 879 { .start = 0x12da4, .end = 0x13004 }, 880 { .start = 0x13008, .end = 0x1300c }, 881 { .start = 0x13010, .end = 0x13014 }, 882 { .start = 0x13018, .end = 0x13020 }, 883 { .start = 0x13064, .end = 0x13084 }, 884 { .start = 0x130a0, .end = 0x130a4 }, 885 { .start = 0x130b8, .end = 0x130c4 }, 886 { .start = 0x130c8, .end = 0x130e8 }, 887 { .start = 0x130ec, .end = 0x130f0 }, 888 { .start = 0x130fc, .end = 0x1311c }, 889 { .start = 0x13120, .end = 0x13128 }, 890 { .start = 0x13144, .end = 0x1314c }, 891 { .start = 0x13168, .end = 0x1316c }, 892 { .start = 0x1319c, .end = 0x131a0 }, 893 { .start = 0x131ac, .end = 0x131c0 }, 894 { .start = 0x131cc, .end = 0x131d0 }, 895 { .start = 0x131e4, .end = 0x131e8 }, 896 { .start = 0x131ec, .end = 0x131f0 }, 897 { .start = 0x1321c, .end = 0x13250 }, 898 { .start = 0x132f0, .end = 0x13310 }, 899 { .start = 0x1332c, .end = 0x13334 }, 900 { .start = 0x1333c, .end = 0x13344 }, 901 { .start = 0x13350, .end = 0x13354 }, 902 { .start = 0x1336c, .end = 0x13370 }, 903 { .start = 0x133ac, .end = 0x133b0 }, 904 { .start = 0x133c8, .end = 0x133d0 }, 905 { .start = 0x13420, .end = 0x13430 }, 906 { .start = 0x13440, .end = 0x13444 }, 907 { .start = 0x13468, .end = 0x13470 }, 908 { .start = 0x13494, .end = 0x1349c }, 909 { .start = 0x134a8, .end = 0x134ac }, 910 { .start = 0x13544, .end = 0x1354c }, 911 { .start = 0x1355c, .end = 0x1357c }, 912 { .start = 0x135cc, .end = 0x135e0 }, 913 { .start = 0x135e4, .end = 0x13608 }, 914 { .start = 0x1360c, .end = 0x13620 }, 915 { .start = 0x136ac, .end = 0x136bc }, 916 { .start = 0x136c0, .end = 0x136c8 }, 917 { .start = 0x13714, .end = 0x13718 }, 918 { .start = 0x13724, .end = 0x13728 }, 919 { .start = 0x1372c, .end = 0x13730 }, 920 { .start = 0x13734, .end = 0x1373c }, 921 { .start = 0x13740, .end = 0x13744 }, 922 { .start = 0x13754, .end = 0x13758 }, 923 { .start = 0x13760, .end = 0x13784 }, 924 { .start = 0x1378c, .end = 0x13790 }, 925 { .start = 0x137a0, .end = 0x137a8 }, 926 { .start = 0x137b8, .end = 0x137bc }, 927 { .start = 0x137dc, .end = 0x137e4 }, 928 { .start = 0x137ec, .end = 0x137f0 }, 929 { .start = 0x13800, .end = 0x13818 }, 930 { .start = 0x13820, .end = 0x13828 }, 931 { .start = 0x13830, .end = 0x13858 }, 932 { .start = 0x138a0, .end = 0x138b0 }, 933 { .start = 0x138d0, .end = 0x138dc }, 934 { .start = 0x1396c, .end = 0x13970 }, 935 { .start = 0x13974, .end = 0x1397c }, 936 { .start = 0x139f4, .end = 0x139f8 }, 937 { .start = 0x13a14, .end = 0x13a20 }, 938 { .start = 0x13a44, .end = 0x13a4c }, 939 { .start = 0x13a50, .end = 0x13a58 }, 940 { .start = 0x13a5c, .end = 0x13a64 }, 941 { .start = 0x13a68, .end = 0x13a70 }, 942 { .start = 0x13acc, .end = 0x13ad8 }, 943 { .start = 0x13b0c, .end = 0x13b18 }, 944 { .start = 0x13b48, .end = 0x13b50 }, 945 { .start = 0x13b5c, .end = 0x13b60 }, 946 { .start = 0x13bf8, .end = 0x13bfc }, 947 { .start = 0x13c18, .end = 0x13c40 }, 948 { .start = 0x13c60, .end = 0x13c64 }, 949 { .start = 0x13c74, .end = 0x13c8c }, 950 { .start = 0x13d94, .end = 0x13da4 }, 951 { .start = 0x13dac, .end = 0x13db4 }, 952 { .start = 0x13db8, .end = 0x13dbc }, 953 { .start = 0x13df4, .end = 0x13e04 }, 954 { .start = 0x13e0c, .end = 0x13e10 }, 955 }; 956 957 static const struct tegra_fuse_info tegra264_fuse_info = { 958 .read = tegra30_fuse_read, 959 .size = 0x13eb8, 960 }; 961 962 const struct tegra_fuse_soc tegra264_fuse_soc = { 963 .init = tegra30_fuse_init, 964 .info = &tegra264_fuse_info, 965 .keepouts = tegra264_fuse_keepouts, 966 .num_keepouts = ARRAY_SIZE(tegra264_fuse_keepouts), 967 .soc_attr_group = &tegra194_soc_attr_group, 968 .clk_suspend_on = false, 969 }; 970 #endif 971