1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013-2023, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/acpi.h> 7 #include <linux/clk.h> 8 #include <linux/device.h> 9 #include <linux/kobject.h> 10 #include <linux/init.h> 11 #include <linux/io.h> 12 #include <linux/nvmem-consumer.h> 13 #include <linux/nvmem-provider.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/reset.h> 19 #include <linux/slab.h> 20 #include <linux/sys_soc.h> 21 22 #include <soc/tegra/common.h> 23 #include <soc/tegra/fuse.h> 24 25 #include "fuse.h" 26 27 struct tegra_sku_info tegra_sku_info; 28 EXPORT_SYMBOL(tegra_sku_info); 29 30 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = { 31 [TEGRA_REVISION_UNKNOWN] = "unknown", 32 [TEGRA_REVISION_A01] = "A01", 33 [TEGRA_REVISION_A02] = "A02", 34 [TEGRA_REVISION_A03] = "A03", 35 [TEGRA_REVISION_A03p] = "A03 prime", 36 [TEGRA_REVISION_A04] = "A04", 37 }; 38 39 static const char *tegra_platform_name[TEGRA_PLATFORM_MAX] = { 40 [TEGRA_PLATFORM_SILICON] = "Silicon", 41 [TEGRA_PLATFORM_QT] = "QT", 42 [TEGRA_PLATFORM_SYSTEM_FPGA] = "System FPGA", 43 [TEGRA_PLATFORM_UNIT_FPGA] = "Unit FPGA", 44 [TEGRA_PLATFORM_ASIM_QT] = "Asim QT", 45 [TEGRA_PLATFORM_ASIM_LINSIM] = "Asim Linsim", 46 [TEGRA_PLATFORM_DSIM_ASIM_LINSIM] = "Dsim Asim Linsim", 47 [TEGRA_PLATFORM_VERIFICATION_SIMULATION] = "Verification Simulation", 48 [TEGRA_PLATFORM_VDK] = "VDK", 49 [TEGRA_PLATFORM_VSP] = "VSP", 50 }; 51 52 static const struct of_device_id car_match[] __initconst = { 53 { .compatible = "nvidia,tegra20-car", }, 54 { .compatible = "nvidia,tegra30-car", }, 55 { .compatible = "nvidia,tegra114-car", }, 56 { .compatible = "nvidia,tegra124-car", }, 57 { .compatible = "nvidia,tegra132-car", }, 58 { .compatible = "nvidia,tegra210-car", }, 59 {}, 60 }; 61 62 static struct tegra_fuse *fuse = &(struct tegra_fuse) { 63 .base = NULL, 64 .soc = NULL, 65 }; 66 67 static const struct of_device_id tegra_fuse_match[] = { 68 #ifdef CONFIG_ARCH_TEGRA_234_SOC 69 { .compatible = "nvidia,tegra234-efuse", .data = &tegra234_fuse_soc }, 70 #endif 71 #ifdef CONFIG_ARCH_TEGRA_194_SOC 72 { .compatible = "nvidia,tegra194-efuse", .data = &tegra194_fuse_soc }, 73 #endif 74 #ifdef CONFIG_ARCH_TEGRA_186_SOC 75 { .compatible = "nvidia,tegra186-efuse", .data = &tegra186_fuse_soc }, 76 #endif 77 #ifdef CONFIG_ARCH_TEGRA_210_SOC 78 { .compatible = "nvidia,tegra210-efuse", .data = &tegra210_fuse_soc }, 79 #endif 80 #ifdef CONFIG_ARCH_TEGRA_132_SOC 81 { .compatible = "nvidia,tegra132-efuse", .data = &tegra124_fuse_soc }, 82 #endif 83 #ifdef CONFIG_ARCH_TEGRA_124_SOC 84 { .compatible = "nvidia,tegra124-efuse", .data = &tegra124_fuse_soc }, 85 #endif 86 #ifdef CONFIG_ARCH_TEGRA_114_SOC 87 { .compatible = "nvidia,tegra114-efuse", .data = &tegra114_fuse_soc }, 88 #endif 89 #ifdef CONFIG_ARCH_TEGRA_3x_SOC 90 { .compatible = "nvidia,tegra30-efuse", .data = &tegra30_fuse_soc }, 91 #endif 92 #ifdef CONFIG_ARCH_TEGRA_2x_SOC 93 { .compatible = "nvidia,tegra20-efuse", .data = &tegra20_fuse_soc }, 94 #endif 95 { /* sentinel */ } 96 }; 97 98 static int tegra_fuse_read(void *priv, unsigned int offset, void *value, 99 size_t bytes) 100 { 101 unsigned int count = bytes / 4, i; 102 struct tegra_fuse *fuse = priv; 103 u32 *buffer = value; 104 105 for (i = 0; i < count; i++) 106 buffer[i] = fuse->read(fuse, offset + i * 4); 107 108 return 0; 109 } 110 111 static void tegra_fuse_restore(void *base) 112 { 113 fuse->base = (void __iomem *)base; 114 fuse->clk = NULL; 115 } 116 117 static void tegra_fuse_print_sku_info(struct tegra_sku_info *tegra_sku_info) 118 { 119 pr_info("Tegra Revision: %s SKU: %d CPU Process: %d SoC Process: %d\n", 120 tegra_revision_name[tegra_sku_info->revision], 121 tegra_sku_info->sku_id, tegra_sku_info->cpu_process_id, 122 tegra_sku_info->soc_process_id); 123 pr_debug("Tegra CPU Speedo ID %d, SoC Speedo ID %d\n", 124 tegra_sku_info->cpu_speedo_id, tegra_sku_info->soc_speedo_id); 125 } 126 127 static int tegra_fuse_add_lookups(struct tegra_fuse *fuse) 128 { 129 fuse->lookups = kmemdup_array(fuse->soc->lookups, fuse->soc->num_lookups, 130 sizeof(*fuse->lookups), GFP_KERNEL); 131 if (!fuse->lookups) 132 return -ENOMEM; 133 134 nvmem_add_cell_lookups(fuse->lookups, fuse->soc->num_lookups); 135 136 return 0; 137 } 138 139 static int tegra_fuse_probe(struct platform_device *pdev) 140 { 141 void __iomem *base = fuse->base; 142 struct nvmem_config nvmem; 143 struct resource *res; 144 int err; 145 146 err = devm_add_action(&pdev->dev, tegra_fuse_restore, (void __force *)base); 147 if (err) 148 return err; 149 150 /* take over the memory region from the early initialization */ 151 fuse->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 152 if (IS_ERR(fuse->base)) 153 return PTR_ERR(fuse->base); 154 fuse->phys = res->start; 155 156 /* Initialize the soc data and lookups if using ACPI boot. */ 157 if (is_acpi_node(dev_fwnode(&pdev->dev)) && !fuse->soc) { 158 u8 chip; 159 160 tegra_acpi_init_apbmisc(); 161 162 chip = tegra_get_chip_id(); 163 switch (chip) { 164 #if defined(CONFIG_ARCH_TEGRA_194_SOC) 165 case TEGRA194: 166 fuse->soc = &tegra194_fuse_soc; 167 break; 168 #endif 169 #if defined(CONFIG_ARCH_TEGRA_234_SOC) 170 case TEGRA234: 171 fuse->soc = &tegra234_fuse_soc; 172 break; 173 #endif 174 #if defined(CONFIG_ARCH_TEGRA_241_SOC) 175 case TEGRA241: 176 fuse->soc = &tegra241_fuse_soc; 177 break; 178 #endif 179 default: 180 return dev_err_probe(&pdev->dev, -EINVAL, "Unsupported SoC: %02x\n", chip); 181 } 182 183 fuse->soc->init(fuse); 184 } 185 186 fuse->clk = devm_clk_get_optional(&pdev->dev, "fuse"); 187 if (IS_ERR(fuse->clk)) 188 return dev_err_probe(&pdev->dev, PTR_ERR(fuse->clk), "failed to get FUSE clock\n"); 189 190 platform_set_drvdata(pdev, fuse); 191 fuse->dev = &pdev->dev; 192 193 err = devm_pm_runtime_enable(&pdev->dev); 194 if (err) 195 return err; 196 197 if (fuse->soc->probe) { 198 err = fuse->soc->probe(fuse); 199 if (err < 0) 200 return err; 201 } 202 203 memset(&nvmem, 0, sizeof(nvmem)); 204 nvmem.dev = &pdev->dev; 205 nvmem.name = "fuse"; 206 nvmem.id = -1; 207 nvmem.owner = THIS_MODULE; 208 nvmem.cells = fuse->soc->cells; 209 nvmem.ncells = fuse->soc->num_cells; 210 nvmem.keepout = fuse->soc->keepouts; 211 nvmem.nkeepout = fuse->soc->num_keepouts; 212 nvmem.type = NVMEM_TYPE_OTP; 213 nvmem.read_only = true; 214 nvmem.root_only = false; 215 nvmem.reg_read = tegra_fuse_read; 216 nvmem.size = fuse->soc->info->size; 217 nvmem.word_size = 4; 218 nvmem.stride = 4; 219 nvmem.priv = fuse; 220 221 fuse->nvmem = devm_nvmem_register(&pdev->dev, &nvmem); 222 if (IS_ERR(fuse->nvmem)) { 223 err = PTR_ERR(fuse->nvmem); 224 dev_err(&pdev->dev, "failed to register NVMEM device: %d\n", 225 err); 226 return err; 227 } 228 229 err = tegra_fuse_add_lookups(fuse); 230 if (err) 231 return dev_err_probe(&pdev->dev, err, "failed to add FUSE lookups\n"); 232 233 fuse->rst = devm_reset_control_get_optional(&pdev->dev, "fuse"); 234 if (IS_ERR(fuse->rst)) 235 return dev_err_probe(&pdev->dev, PTR_ERR(fuse->rst), "failed to get FUSE reset\n"); 236 237 /* 238 * FUSE clock is enabled at a boot time, hence this resume/suspend 239 * disables the clock besides the h/w resetting. 240 */ 241 err = pm_runtime_resume_and_get(&pdev->dev); 242 if (err) 243 return err; 244 245 err = reset_control_reset(fuse->rst); 246 pm_runtime_put(&pdev->dev); 247 248 if (err < 0) { 249 dev_err(&pdev->dev, "failed to reset FUSE: %d\n", err); 250 return err; 251 } 252 253 /* release the early I/O memory mapping */ 254 iounmap(base); 255 256 return 0; 257 } 258 259 static int __maybe_unused tegra_fuse_runtime_resume(struct device *dev) 260 { 261 int err; 262 263 err = clk_prepare_enable(fuse->clk); 264 if (err < 0) { 265 dev_err(dev, "failed to enable FUSE clock: %d\n", err); 266 return err; 267 } 268 269 return 0; 270 } 271 272 static int __maybe_unused tegra_fuse_runtime_suspend(struct device *dev) 273 { 274 clk_disable_unprepare(fuse->clk); 275 276 return 0; 277 } 278 279 static int __maybe_unused tegra_fuse_suspend(struct device *dev) 280 { 281 int ret; 282 283 /* 284 * Critical for RAM re-repair operation, which must occur on resume 285 * from LP1 system suspend and as part of CCPLEX cluster switching. 286 */ 287 if (fuse->soc->clk_suspend_on) 288 ret = pm_runtime_resume_and_get(dev); 289 else 290 ret = pm_runtime_force_suspend(dev); 291 292 return ret; 293 } 294 295 static int __maybe_unused tegra_fuse_resume(struct device *dev) 296 { 297 int ret = 0; 298 299 if (fuse->soc->clk_suspend_on) 300 pm_runtime_put(dev); 301 else 302 ret = pm_runtime_force_resume(dev); 303 304 return ret; 305 } 306 307 static const struct dev_pm_ops tegra_fuse_pm = { 308 SET_RUNTIME_PM_OPS(tegra_fuse_runtime_suspend, tegra_fuse_runtime_resume, 309 NULL) 310 SET_SYSTEM_SLEEP_PM_OPS(tegra_fuse_suspend, tegra_fuse_resume) 311 }; 312 313 static const struct acpi_device_id tegra_fuse_acpi_match[] = { 314 { "NVDA200F" }, 315 { /* sentinel */ } 316 }; 317 MODULE_DEVICE_TABLE(acpi, tegra_fuse_acpi_match); 318 319 static struct platform_driver tegra_fuse_driver = { 320 .driver = { 321 .name = "tegra-fuse", 322 .of_match_table = tegra_fuse_match, 323 .acpi_match_table = tegra_fuse_acpi_match, 324 .pm = &tegra_fuse_pm, 325 .suppress_bind_attrs = true, 326 }, 327 .probe = tegra_fuse_probe, 328 }; 329 builtin_platform_driver(tegra_fuse_driver); 330 331 u32 __init tegra_fuse_read_spare(unsigned int spare) 332 { 333 unsigned int offset = fuse->soc->info->spare + spare * 4; 334 335 return fuse->read_early(fuse, offset) & 1; 336 } 337 338 u32 __init tegra_fuse_read_early(unsigned int offset) 339 { 340 return fuse->read_early(fuse, offset); 341 } 342 343 int tegra_fuse_readl(unsigned long offset, u32 *value) 344 { 345 if (!fuse->dev) 346 return -EPROBE_DEFER; 347 348 /* 349 * Wait for fuse->clk to be initialized if device-tree boot is used. 350 */ 351 if (is_of_node(dev_fwnode(fuse->dev)) && !fuse->clk) 352 return -EPROBE_DEFER; 353 354 if (!fuse->read) 355 return -EPROBE_DEFER; 356 357 if (IS_ERR(fuse->clk)) 358 return PTR_ERR(fuse->clk); 359 360 *value = fuse->read(fuse, offset); 361 362 return 0; 363 } 364 EXPORT_SYMBOL(tegra_fuse_readl); 365 366 static void tegra_enable_fuse_clk(void __iomem *base) 367 { 368 u32 reg; 369 370 reg = readl_relaxed(base + 0x48); 371 reg |= 1 << 28; 372 writel(reg, base + 0x48); 373 374 /* 375 * Enable FUSE clock. This needs to be hardcoded because the clock 376 * subsystem is not active during early boot. 377 */ 378 reg = readl(base + 0x14); 379 reg |= 1 << 7; 380 writel(reg, base + 0x14); 381 } 382 383 static ssize_t major_show(struct device *dev, struct device_attribute *attr, 384 char *buf) 385 { 386 return sprintf(buf, "%d\n", tegra_get_major_rev()); 387 } 388 389 static DEVICE_ATTR_RO(major); 390 391 static ssize_t minor_show(struct device *dev, struct device_attribute *attr, 392 char *buf) 393 { 394 return sprintf(buf, "%d\n", tegra_get_minor_rev()); 395 } 396 397 static DEVICE_ATTR_RO(minor); 398 399 static struct attribute *tegra_soc_attr[] = { 400 &dev_attr_major.attr, 401 &dev_attr_minor.attr, 402 NULL, 403 }; 404 405 const struct attribute_group tegra_soc_attr_group = { 406 .attrs = tegra_soc_attr, 407 }; 408 409 #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \ 410 IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) || \ 411 IS_ENABLED(CONFIG_ARCH_TEGRA_241_SOC) 412 static ssize_t platform_show(struct device *dev, struct device_attribute *attr, 413 char *buf) 414 { 415 /* 416 * Displays the value in the 'pre_si_platform' field of the HIDREV 417 * register for Tegra194 devices. A value of 0 indicates that the 418 * platform type is silicon and all other non-zero values indicate 419 * the type of simulation platform is being used. 420 */ 421 return sprintf(buf, "%d\n", tegra_get_platform()); 422 } 423 424 static DEVICE_ATTR_RO(platform); 425 426 static struct attribute *tegra194_soc_attr[] = { 427 &dev_attr_major.attr, 428 &dev_attr_minor.attr, 429 &dev_attr_platform.attr, 430 NULL, 431 }; 432 433 const struct attribute_group tegra194_soc_attr_group = { 434 .attrs = tegra194_soc_attr, 435 }; 436 #endif 437 438 struct device *tegra_soc_device_register(void) 439 { 440 struct soc_device_attribute *attr; 441 struct soc_device *dev; 442 443 attr = kzalloc_obj(*attr); 444 if (!attr) 445 return NULL; 446 447 attr->family = kasprintf(GFP_KERNEL, "Tegra"); 448 if (tegra_is_silicon()) 449 attr->revision = kasprintf(GFP_KERNEL, "%s %s", 450 tegra_platform_name[tegra_sku_info.platform], 451 tegra_revision_name[tegra_sku_info.revision]); 452 else 453 attr->revision = kasprintf(GFP_KERNEL, "%s", 454 tegra_platform_name[tegra_sku_info.platform]); 455 attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id()); 456 attr->custom_attr_group = fuse->soc->soc_attr_group; 457 458 dev = soc_device_register(attr); 459 if (IS_ERR(dev)) { 460 kfree(attr->soc_id); 461 kfree(attr->revision); 462 kfree(attr->family); 463 kfree(attr); 464 return ERR_CAST(dev); 465 } 466 467 return soc_device_to_device(dev); 468 } 469 470 static int __init tegra_init_fuse(void) 471 { 472 const struct of_device_id *match; 473 struct device_node *np; 474 struct resource regs; 475 int err = 0; 476 477 tegra_init_apbmisc(); 478 479 np = of_find_matching_node_and_match(NULL, tegra_fuse_match, &match); 480 if (!np) { 481 /* 482 * Fall back to legacy initialization for 32-bit ARM only. All 483 * 64-bit ARM device tree files for Tegra are required to have 484 * a FUSE node. 485 * 486 * This is for backwards-compatibility with old device trees 487 * that didn't contain a FUSE node. 488 */ 489 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 490 u8 chip = tegra_get_chip_id(); 491 492 regs.start = 0x7000f800; 493 regs.end = 0x7000fbff; 494 regs.flags = IORESOURCE_MEM; 495 496 switch (chip) { 497 #ifdef CONFIG_ARCH_TEGRA_2x_SOC 498 case TEGRA20: 499 fuse->soc = &tegra20_fuse_soc; 500 break; 501 #endif 502 503 #ifdef CONFIG_ARCH_TEGRA_3x_SOC 504 case TEGRA30: 505 fuse->soc = &tegra30_fuse_soc; 506 break; 507 #endif 508 509 #ifdef CONFIG_ARCH_TEGRA_114_SOC 510 case TEGRA114: 511 fuse->soc = &tegra114_fuse_soc; 512 break; 513 #endif 514 515 #ifdef CONFIG_ARCH_TEGRA_124_SOC 516 case TEGRA124: 517 fuse->soc = &tegra124_fuse_soc; 518 break; 519 #endif 520 521 default: 522 pr_warn("Unsupported SoC: %02x\n", chip); 523 break; 524 } 525 } else { 526 /* 527 * At this point we're not running on Tegra, so play 528 * nice with multi-platform kernels. 529 */ 530 return 0; 531 } 532 } else { 533 /* 534 * Extract information from the device tree if we've found a 535 * matching node. 536 */ 537 if (of_address_to_resource(np, 0, ®s) < 0) { 538 pr_err("failed to get FUSE register\n"); 539 return -ENXIO; 540 } 541 542 fuse->soc = match->data; 543 } 544 545 np = of_find_matching_node(NULL, car_match); 546 if (np) { 547 void __iomem *base = of_iomap(np, 0); 548 of_node_put(np); 549 if (base) { 550 tegra_enable_fuse_clk(base); 551 iounmap(base); 552 } else { 553 pr_err("failed to map clock registers\n"); 554 return -ENXIO; 555 } 556 } 557 558 fuse->base = ioremap(regs.start, resource_size(®s)); 559 if (!fuse->base) { 560 pr_err("failed to map FUSE registers\n"); 561 return -ENXIO; 562 } 563 564 fuse->soc->init(fuse); 565 566 tegra_fuse_print_sku_info(&tegra_sku_info); 567 568 return err; 569 } 570 early_initcall(tegra_init_fuse); 571 572 #ifdef CONFIG_ARM64 573 static int __init tegra_init_soc(void) 574 { 575 struct device_node *np; 576 struct device *soc; 577 578 /* make sure we're running on Tegra */ 579 np = of_find_matching_node(NULL, tegra_fuse_match); 580 if (!np) 581 return 0; 582 583 of_node_put(np); 584 585 soc = tegra_soc_device_register(); 586 if (IS_ERR(soc)) { 587 pr_err("failed to register SoC device: %ld\n", PTR_ERR(soc)); 588 return PTR_ERR(soc); 589 } 590 591 return 0; 592 } 593 device_initcall(tegra_init_soc); 594 #endif 595