1 /* 2 * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 * 16 */ 17 18 #include <linux/device.h> 19 #include <linux/kobject.h> 20 #include <linux/kernel.h> 21 #include <linux/platform_device.h> 22 #include <linux/of.h> 23 #include <linux/of_address.h> 24 #include <linux/io.h> 25 26 #include <soc/tegra/common.h> 27 #include <soc/tegra/fuse.h> 28 29 #include "fuse.h" 30 31 static u32 (*fuse_readl)(const unsigned int offset); 32 static int fuse_size; 33 struct tegra_sku_info tegra_sku_info; 34 EXPORT_SYMBOL(tegra_sku_info); 35 36 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = { 37 [TEGRA_REVISION_UNKNOWN] = "unknown", 38 [TEGRA_REVISION_A01] = "A01", 39 [TEGRA_REVISION_A02] = "A02", 40 [TEGRA_REVISION_A03] = "A03", 41 [TEGRA_REVISION_A03p] = "A03 prime", 42 [TEGRA_REVISION_A04] = "A04", 43 }; 44 45 static u8 fuse_readb(const unsigned int offset) 46 { 47 u32 val; 48 49 val = fuse_readl(round_down(offset, 4)); 50 val >>= (offset % 4) * 8; 51 val &= 0xff; 52 53 return val; 54 } 55 56 static ssize_t fuse_read(struct file *fd, struct kobject *kobj, 57 struct bin_attribute *attr, char *buf, 58 loff_t pos, size_t size) 59 { 60 int i; 61 62 if (pos < 0 || pos >= fuse_size) 63 return 0; 64 65 if (size > fuse_size - pos) 66 size = fuse_size - pos; 67 68 for (i = 0; i < size; i++) 69 buf[i] = fuse_readb(pos + i); 70 71 return i; 72 } 73 74 static struct bin_attribute fuse_bin_attr = { 75 .attr = { .name = "fuse", .mode = S_IRUGO, }, 76 .read = fuse_read, 77 }; 78 79 static const struct of_device_id car_match[] __initconst = { 80 { .compatible = "nvidia,tegra20-car", }, 81 { .compatible = "nvidia,tegra30-car", }, 82 { .compatible = "nvidia,tegra114-car", }, 83 { .compatible = "nvidia,tegra124-car", }, 84 { .compatible = "nvidia,tegra132-car", }, 85 {}, 86 }; 87 88 static void tegra_enable_fuse_clk(void __iomem *base) 89 { 90 u32 reg; 91 92 reg = readl_relaxed(base + 0x48); 93 reg |= 1 << 28; 94 writel(reg, base + 0x48); 95 96 /* 97 * Enable FUSE clock. This needs to be hardcoded because the clock 98 * subsystem is not active during early boot. 99 */ 100 reg = readl(base + 0x14); 101 reg |= 1 << 7; 102 writel(reg, base + 0x14); 103 } 104 105 int tegra_fuse_readl(unsigned long offset, u32 *value) 106 { 107 if (!fuse_readl) 108 return -EPROBE_DEFER; 109 110 *value = fuse_readl(offset); 111 112 return 0; 113 } 114 EXPORT_SYMBOL(tegra_fuse_readl); 115 116 int tegra_fuse_create_sysfs(struct device *dev, int size, 117 u32 (*readl)(const unsigned int offset)) 118 { 119 if (fuse_size) 120 return -ENODEV; 121 122 fuse_bin_attr.size = size; 123 fuse_bin_attr.read = fuse_read; 124 125 fuse_size = size; 126 fuse_readl = readl; 127 128 return device_create_bin_file(dev, &fuse_bin_attr); 129 } 130 131 static int __init tegra_init_fuse(void) 132 { 133 struct device_node *np; 134 void __iomem *car_base; 135 136 if (!soc_is_tegra()) 137 return 0; 138 139 tegra_init_apbmisc(); 140 141 np = of_find_matching_node(NULL, car_match); 142 car_base = of_iomap(np, 0); 143 if (car_base) { 144 tegra_enable_fuse_clk(car_base); 145 iounmap(car_base); 146 } else { 147 pr_err("Could not enable fuse clk. ioremap tegra car failed.\n"); 148 return -ENXIO; 149 } 150 151 if (tegra_get_chip_id() == TEGRA20) 152 tegra20_init_fuse_early(); 153 else 154 tegra30_init_fuse_early(); 155 156 pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n", 157 tegra_revision_name[tegra_sku_info.revision], 158 tegra_sku_info.sku_id, tegra_sku_info.cpu_process_id, 159 tegra_sku_info.core_process_id); 160 pr_debug("Tegra CPU Speedo ID %d, Soc Speedo ID %d\n", 161 tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id); 162 163 return 0; 164 } 165 early_initcall(tegra_init_fuse); 166