1783c8f4cSPeter De Schrijver /* 2783c8f4cSPeter De Schrijver * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. 3783c8f4cSPeter De Schrijver * 4783c8f4cSPeter De Schrijver * This program is free software; you can redistribute it and/or modify it 5783c8f4cSPeter De Schrijver * under the terms and conditions of the GNU General Public License, 6783c8f4cSPeter De Schrijver * version 2, as published by the Free Software Foundation. 7783c8f4cSPeter De Schrijver * 8783c8f4cSPeter De Schrijver * This program is distributed in the hope it will be useful, but WITHOUT 9783c8f4cSPeter De Schrijver * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10783c8f4cSPeter De Schrijver * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11783c8f4cSPeter De Schrijver * more details. 12783c8f4cSPeter De Schrijver * 13783c8f4cSPeter De Schrijver * You should have received a copy of the GNU General Public License 14783c8f4cSPeter De Schrijver * along with this program. If not, see <http://www.gnu.org/licenses/>. 15783c8f4cSPeter De Schrijver * 16783c8f4cSPeter De Schrijver */ 17783c8f4cSPeter De Schrijver 187e939de1SThierry Reding #include <linux/clk.h> 19783c8f4cSPeter De Schrijver #include <linux/device.h> 20783c8f4cSPeter De Schrijver #include <linux/kobject.h> 211859217bSPaul Gortmaker #include <linux/init.h> 2227a0342aSThierry Reding #include <linux/io.h> 23783c8f4cSPeter De Schrijver #include <linux/of.h> 24783c8f4cSPeter De Schrijver #include <linux/of_address.h> 2527a0342aSThierry Reding #include <linux/platform_device.h> 2627a0342aSThierry Reding #include <linux/slab.h> 2727a0342aSThierry Reding #include <linux/sys_soc.h> 28783c8f4cSPeter De Schrijver 2924fa5af8SThierry Reding #include <soc/tegra/common.h> 30783c8f4cSPeter De Schrijver #include <soc/tegra/fuse.h> 31783c8f4cSPeter De Schrijver 32783c8f4cSPeter De Schrijver #include "fuse.h" 33783c8f4cSPeter De Schrijver 34783c8f4cSPeter De Schrijver struct tegra_sku_info tegra_sku_info; 35f9fc3661SVince Hsu EXPORT_SYMBOL(tegra_sku_info); 36783c8f4cSPeter De Schrijver 37783c8f4cSPeter De Schrijver static const char *tegra_revision_name[TEGRA_REVISION_MAX] = { 38783c8f4cSPeter De Schrijver [TEGRA_REVISION_UNKNOWN] = "unknown", 39783c8f4cSPeter De Schrijver [TEGRA_REVISION_A01] = "A01", 40783c8f4cSPeter De Schrijver [TEGRA_REVISION_A02] = "A02", 41783c8f4cSPeter De Schrijver [TEGRA_REVISION_A03] = "A03", 42783c8f4cSPeter De Schrijver [TEGRA_REVISION_A03p] = "A03 prime", 43783c8f4cSPeter De Schrijver [TEGRA_REVISION_A04] = "A04", 44783c8f4cSPeter De Schrijver }; 45783c8f4cSPeter De Schrijver 467e939de1SThierry Reding static u8 fuse_readb(struct tegra_fuse *fuse, unsigned int offset) 47783c8f4cSPeter De Schrijver { 48783c8f4cSPeter De Schrijver u32 val; 49783c8f4cSPeter De Schrijver 507e939de1SThierry Reding val = fuse->read(fuse, round_down(offset, 4)); 51783c8f4cSPeter De Schrijver val >>= (offset % 4) * 8; 52783c8f4cSPeter De Schrijver val &= 0xff; 53783c8f4cSPeter De Schrijver 54783c8f4cSPeter De Schrijver return val; 55783c8f4cSPeter De Schrijver } 56783c8f4cSPeter De Schrijver 57783c8f4cSPeter De Schrijver static ssize_t fuse_read(struct file *fd, struct kobject *kobj, 58783c8f4cSPeter De Schrijver struct bin_attribute *attr, char *buf, 59783c8f4cSPeter De Schrijver loff_t pos, size_t size) 60783c8f4cSPeter De Schrijver { 617e939de1SThierry Reding struct device *dev = kobj_to_dev(kobj); 627e939de1SThierry Reding struct tegra_fuse *fuse = dev_get_drvdata(dev); 63783c8f4cSPeter De Schrijver int i; 64783c8f4cSPeter De Schrijver 657e939de1SThierry Reding if (pos < 0 || pos >= attr->size) 66783c8f4cSPeter De Schrijver return 0; 67783c8f4cSPeter De Schrijver 687e939de1SThierry Reding if (size > attr->size - pos) 697e939de1SThierry Reding size = attr->size - pos; 70783c8f4cSPeter De Schrijver 71783c8f4cSPeter De Schrijver for (i = 0; i < size; i++) 727e939de1SThierry Reding buf[i] = fuse_readb(fuse, pos + i); 73783c8f4cSPeter De Schrijver 74783c8f4cSPeter De Schrijver return i; 75783c8f4cSPeter De Schrijver } 76783c8f4cSPeter De Schrijver 77783c8f4cSPeter De Schrijver static struct bin_attribute fuse_bin_attr = { 78783c8f4cSPeter De Schrijver .attr = { .name = "fuse", .mode = S_IRUGO, }, 79783c8f4cSPeter De Schrijver .read = fuse_read, 80783c8f4cSPeter De Schrijver }; 81783c8f4cSPeter De Schrijver 827e939de1SThierry Reding static int tegra_fuse_create_sysfs(struct device *dev, unsigned int size, 837e939de1SThierry Reding const struct tegra_fuse_info *info) 847e939de1SThierry Reding { 857e939de1SThierry Reding fuse_bin_attr.size = size; 867e939de1SThierry Reding 877e939de1SThierry Reding return device_create_bin_file(dev, &fuse_bin_attr); 887e939de1SThierry Reding } 897e939de1SThierry Reding 90783c8f4cSPeter De Schrijver static const struct of_device_id car_match[] __initconst = { 91783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra20-car", }, 92783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra30-car", }, 93783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra114-car", }, 94783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra124-car", }, 959b07eb05SThierry Reding { .compatible = "nvidia,tegra132-car", }, 960dc5a0d8SThierry Reding { .compatible = "nvidia,tegra210-car", }, 97783c8f4cSPeter De Schrijver {}, 98783c8f4cSPeter De Schrijver }; 99783c8f4cSPeter De Schrijver 1007e939de1SThierry Reding static struct tegra_fuse *fuse = &(struct tegra_fuse) { 1017e939de1SThierry Reding .base = NULL, 1027e939de1SThierry Reding .soc = NULL, 1037e939de1SThierry Reding }; 1047e939de1SThierry Reding 1057e939de1SThierry Reding static const struct of_device_id tegra_fuse_match[] = { 10683468fe2STimo Alho #ifdef CONFIG_ARCH_TEGRA_186_SOC 10783468fe2STimo Alho { .compatible = "nvidia,tegra186-efuse", .data = &tegra186_fuse_soc }, 10883468fe2STimo Alho #endif 1090dc5a0d8SThierry Reding #ifdef CONFIG_ARCH_TEGRA_210_SOC 1100dc5a0d8SThierry Reding { .compatible = "nvidia,tegra210-efuse", .data = &tegra210_fuse_soc }, 1110dc5a0d8SThierry Reding #endif 1127e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_132_SOC 1137e939de1SThierry Reding { .compatible = "nvidia,tegra132-efuse", .data = &tegra124_fuse_soc }, 1147e939de1SThierry Reding #endif 1157e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_124_SOC 1167e939de1SThierry Reding { .compatible = "nvidia,tegra124-efuse", .data = &tegra124_fuse_soc }, 1177e939de1SThierry Reding #endif 1187e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_114_SOC 1197e939de1SThierry Reding { .compatible = "nvidia,tegra114-efuse", .data = &tegra114_fuse_soc }, 1207e939de1SThierry Reding #endif 1217e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_3x_SOC 1227e939de1SThierry Reding { .compatible = "nvidia,tegra30-efuse", .data = &tegra30_fuse_soc }, 1237e939de1SThierry Reding #endif 1247e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_2x_SOC 1257e939de1SThierry Reding { .compatible = "nvidia,tegra20-efuse", .data = &tegra20_fuse_soc }, 1267e939de1SThierry Reding #endif 1277e939de1SThierry Reding { /* sentinel */ } 1287e939de1SThierry Reding }; 1297e939de1SThierry Reding 1307e939de1SThierry Reding static int tegra_fuse_probe(struct platform_device *pdev) 1317e939de1SThierry Reding { 1327e939de1SThierry Reding void __iomem *base = fuse->base; 1337e939de1SThierry Reding struct resource *res; 1347e939de1SThierry Reding int err; 1357e939de1SThierry Reding 1367e939de1SThierry Reding /* take over the memory region from the early initialization */ 1377e939de1SThierry Reding res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 13855a042b3SDmitry Osipenko fuse->phys = res->start; 1397e939de1SThierry Reding fuse->base = devm_ioremap_resource(&pdev->dev, res); 14051294bf6STimo Alho if (IS_ERR(fuse->base)) { 14151294bf6STimo Alho err = PTR_ERR(fuse->base); 14251294bf6STimo Alho fuse->base = base; 14351294bf6STimo Alho return err; 14451294bf6STimo Alho } 1457e939de1SThierry Reding 1467e939de1SThierry Reding fuse->clk = devm_clk_get(&pdev->dev, "fuse"); 1477e939de1SThierry Reding if (IS_ERR(fuse->clk)) { 148*f0b2835fSThierry Reding if (PTR_ERR(fuse->clk) != -EPROBE_DEFER) 1497e939de1SThierry Reding dev_err(&pdev->dev, "failed to get FUSE clock: %ld", 1507e939de1SThierry Reding PTR_ERR(fuse->clk)); 151*f0b2835fSThierry Reding 15251294bf6STimo Alho fuse->base = base; 1537e939de1SThierry Reding return PTR_ERR(fuse->clk); 1547e939de1SThierry Reding } 1557e939de1SThierry Reding 1567e939de1SThierry Reding platform_set_drvdata(pdev, fuse); 1577e939de1SThierry Reding fuse->dev = &pdev->dev; 1587e939de1SThierry Reding 1597e939de1SThierry Reding if (fuse->soc->probe) { 1607e939de1SThierry Reding err = fuse->soc->probe(fuse); 16151294bf6STimo Alho if (err < 0) { 16251294bf6STimo Alho fuse->base = base; 1637e939de1SThierry Reding return err; 1647e939de1SThierry Reding } 16551294bf6STimo Alho } 1667e939de1SThierry Reding 1677e939de1SThierry Reding if (tegra_fuse_create_sysfs(&pdev->dev, fuse->soc->info->size, 1687e939de1SThierry Reding fuse->soc->info)) 1697e939de1SThierry Reding return -ENODEV; 1707e939de1SThierry Reding 1717e939de1SThierry Reding /* release the early I/O memory mapping */ 1727e939de1SThierry Reding iounmap(base); 1737e939de1SThierry Reding 1747e939de1SThierry Reding return 0; 1757e939de1SThierry Reding } 1767e939de1SThierry Reding 1777e939de1SThierry Reding static struct platform_driver tegra_fuse_driver = { 1787e939de1SThierry Reding .driver = { 1797e939de1SThierry Reding .name = "tegra-fuse", 1807e939de1SThierry Reding .of_match_table = tegra_fuse_match, 1817e939de1SThierry Reding .suppress_bind_attrs = true, 1827e939de1SThierry Reding }, 1837e939de1SThierry Reding .probe = tegra_fuse_probe, 1847e939de1SThierry Reding }; 1851859217bSPaul Gortmaker builtin_platform_driver(tegra_fuse_driver); 1867e939de1SThierry Reding 1877e939de1SThierry Reding bool __init tegra_fuse_read_spare(unsigned int spare) 1887e939de1SThierry Reding { 1897e939de1SThierry Reding unsigned int offset = fuse->soc->info->spare + spare * 4; 1907e939de1SThierry Reding 1917e939de1SThierry Reding return fuse->read_early(fuse, offset) & 1; 1927e939de1SThierry Reding } 1937e939de1SThierry Reding 1947e939de1SThierry Reding u32 __init tegra_fuse_read_early(unsigned int offset) 1957e939de1SThierry Reding { 1967e939de1SThierry Reding return fuse->read_early(fuse, offset); 1977e939de1SThierry Reding } 1987e939de1SThierry Reding 1997e939de1SThierry Reding int tegra_fuse_readl(unsigned long offset, u32 *value) 2007e939de1SThierry Reding { 2017e939de1SThierry Reding if (!fuse->read) 2027e939de1SThierry Reding return -EPROBE_DEFER; 2037e939de1SThierry Reding 2047e939de1SThierry Reding *value = fuse->read(fuse, offset); 2057e939de1SThierry Reding 2067e939de1SThierry Reding return 0; 2077e939de1SThierry Reding } 2087e939de1SThierry Reding EXPORT_SYMBOL(tegra_fuse_readl); 2097e939de1SThierry Reding 210783c8f4cSPeter De Schrijver static void tegra_enable_fuse_clk(void __iomem *base) 211783c8f4cSPeter De Schrijver { 212783c8f4cSPeter De Schrijver u32 reg; 213783c8f4cSPeter De Schrijver 214783c8f4cSPeter De Schrijver reg = readl_relaxed(base + 0x48); 215783c8f4cSPeter De Schrijver reg |= 1 << 28; 216783c8f4cSPeter De Schrijver writel(reg, base + 0x48); 217783c8f4cSPeter De Schrijver 218783c8f4cSPeter De Schrijver /* 219783c8f4cSPeter De Schrijver * Enable FUSE clock. This needs to be hardcoded because the clock 220783c8f4cSPeter De Schrijver * subsystem is not active during early boot. 221783c8f4cSPeter De Schrijver */ 222783c8f4cSPeter De Schrijver reg = readl(base + 0x14); 223783c8f4cSPeter De Schrijver reg |= 1 << 7; 224783c8f4cSPeter De Schrijver writel(reg, base + 0x14); 225783c8f4cSPeter De Schrijver } 226783c8f4cSPeter De Schrijver 22727a0342aSThierry Reding struct device * __init tegra_soc_device_register(void) 22827a0342aSThierry Reding { 22927a0342aSThierry Reding struct soc_device_attribute *attr; 23027a0342aSThierry Reding struct soc_device *dev; 23127a0342aSThierry Reding 23227a0342aSThierry Reding attr = kzalloc(sizeof(*attr), GFP_KERNEL); 23327a0342aSThierry Reding if (!attr) 23427a0342aSThierry Reding return NULL; 23527a0342aSThierry Reding 23627a0342aSThierry Reding attr->family = kasprintf(GFP_KERNEL, "Tegra"); 23727a0342aSThierry Reding attr->revision = kasprintf(GFP_KERNEL, "%d", tegra_sku_info.revision); 23827a0342aSThierry Reding attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id()); 23927a0342aSThierry Reding 24027a0342aSThierry Reding dev = soc_device_register(attr); 24127a0342aSThierry Reding if (IS_ERR(dev)) { 24227a0342aSThierry Reding kfree(attr->soc_id); 24327a0342aSThierry Reding kfree(attr->revision); 24427a0342aSThierry Reding kfree(attr->family); 24527a0342aSThierry Reding kfree(attr); 24627a0342aSThierry Reding return ERR_CAST(dev); 24727a0342aSThierry Reding } 24827a0342aSThierry Reding 24927a0342aSThierry Reding return soc_device_to_device(dev); 25027a0342aSThierry Reding } 25127a0342aSThierry Reding 25224fa5af8SThierry Reding static int __init tegra_init_fuse(void) 253783c8f4cSPeter De Schrijver { 2547e939de1SThierry Reding const struct of_device_id *match; 255783c8f4cSPeter De Schrijver struct device_node *np; 2567e939de1SThierry Reding struct resource regs; 25724fa5af8SThierry Reding 258783c8f4cSPeter De Schrijver tegra_init_apbmisc(); 259783c8f4cSPeter De Schrijver 2607e939de1SThierry Reding np = of_find_matching_node_and_match(NULL, tegra_fuse_match, &match); 2617e939de1SThierry Reding if (!np) { 2627e939de1SThierry Reding /* 2637e939de1SThierry Reding * Fall back to legacy initialization for 32-bit ARM only. All 2647e939de1SThierry Reding * 64-bit ARM device tree files for Tegra are required to have 2657e939de1SThierry Reding * a FUSE node. 2667e939de1SThierry Reding * 2677e939de1SThierry Reding * This is for backwards-compatibility with old device trees 2687e939de1SThierry Reding * that didn't contain a FUSE node. 2697e939de1SThierry Reding */ 2707e939de1SThierry Reding if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 2717e939de1SThierry Reding u8 chip = tegra_get_chip_id(); 2727e939de1SThierry Reding 2737e939de1SThierry Reding regs.start = 0x7000f800; 2747e939de1SThierry Reding regs.end = 0x7000fbff; 2757e939de1SThierry Reding regs.flags = IORESOURCE_MEM; 2767e939de1SThierry Reding 2777e939de1SThierry Reding switch (chip) { 2787e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_2x_SOC 2797e939de1SThierry Reding case TEGRA20: 2807e939de1SThierry Reding fuse->soc = &tegra20_fuse_soc; 2817e939de1SThierry Reding break; 2827e939de1SThierry Reding #endif 2837e939de1SThierry Reding 2847e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_3x_SOC 2857e939de1SThierry Reding case TEGRA30: 2867e939de1SThierry Reding fuse->soc = &tegra30_fuse_soc; 2877e939de1SThierry Reding break; 2887e939de1SThierry Reding #endif 2897e939de1SThierry Reding 2907e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_114_SOC 2917e939de1SThierry Reding case TEGRA114: 2927e939de1SThierry Reding fuse->soc = &tegra114_fuse_soc; 2937e939de1SThierry Reding break; 2947e939de1SThierry Reding #endif 2957e939de1SThierry Reding 2967e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_124_SOC 2977e939de1SThierry Reding case TEGRA124: 2987e939de1SThierry Reding fuse->soc = &tegra124_fuse_soc; 2997e939de1SThierry Reding break; 3007e939de1SThierry Reding #endif 3017e939de1SThierry Reding 3027e939de1SThierry Reding default: 3037e939de1SThierry Reding pr_warn("Unsupported SoC: %02x\n", chip); 3047e939de1SThierry Reding break; 3057e939de1SThierry Reding } 306783c8f4cSPeter De Schrijver } else { 3077e939de1SThierry Reding /* 3087e939de1SThierry Reding * At this point we're not running on Tegra, so play 3097e939de1SThierry Reding * nice with multi-platform kernels. 3107e939de1SThierry Reding */ 3117e939de1SThierry Reding return 0; 3127e939de1SThierry Reding } 3137e939de1SThierry Reding } else { 3147e939de1SThierry Reding /* 3157e939de1SThierry Reding * Extract information from the device tree if we've found a 3167e939de1SThierry Reding * matching node. 3177e939de1SThierry Reding */ 3187e939de1SThierry Reding if (of_address_to_resource(np, 0, ®s) < 0) { 3197e939de1SThierry Reding pr_err("failed to get FUSE register\n"); 32024fa5af8SThierry Reding return -ENXIO; 321783c8f4cSPeter De Schrijver } 322783c8f4cSPeter De Schrijver 3237e939de1SThierry Reding fuse->soc = match->data; 3247e939de1SThierry Reding } 3257e939de1SThierry Reding 3267e939de1SThierry Reding np = of_find_matching_node(NULL, car_match); 3277e939de1SThierry Reding if (np) { 3287e939de1SThierry Reding void __iomem *base = of_iomap(np, 0); 3297e939de1SThierry Reding if (base) { 3307e939de1SThierry Reding tegra_enable_fuse_clk(base); 3317e939de1SThierry Reding iounmap(base); 3327e939de1SThierry Reding } else { 3337e939de1SThierry Reding pr_err("failed to map clock registers\n"); 3347e939de1SThierry Reding return -ENXIO; 3357e939de1SThierry Reding } 3367e939de1SThierry Reding } 3377e939de1SThierry Reding 3387e939de1SThierry Reding fuse->base = ioremap_nocache(regs.start, resource_size(®s)); 3397e939de1SThierry Reding if (!fuse->base) { 3407e939de1SThierry Reding pr_err("failed to map FUSE registers\n"); 3417e939de1SThierry Reding return -ENXIO; 3427e939de1SThierry Reding } 3437e939de1SThierry Reding 3447e939de1SThierry Reding fuse->soc->init(fuse); 345783c8f4cSPeter De Schrijver 34603b3f4c8SThierry Reding pr_info("Tegra Revision: %s SKU: %d CPU Process: %d SoC Process: %d\n", 347783c8f4cSPeter De Schrijver tegra_revision_name[tegra_sku_info.revision], 348783c8f4cSPeter De Schrijver tegra_sku_info.sku_id, tegra_sku_info.cpu_process_id, 34903b3f4c8SThierry Reding tegra_sku_info.soc_process_id); 35003b3f4c8SThierry Reding pr_debug("Tegra CPU Speedo ID %d, SoC Speedo ID %d\n", 351783c8f4cSPeter De Schrijver tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id); 35224fa5af8SThierry Reding 35327a0342aSThierry Reding 35424fa5af8SThierry Reding return 0; 355783c8f4cSPeter De Schrijver } 35624fa5af8SThierry Reding early_initcall(tegra_init_fuse); 35727a0342aSThierry Reding 35827a0342aSThierry Reding #ifdef CONFIG_ARM64 35927a0342aSThierry Reding static int __init tegra_init_soc(void) 36027a0342aSThierry Reding { 361226cff48SThierry Reding struct device_node *np; 36227a0342aSThierry Reding struct device *soc; 36327a0342aSThierry Reding 364226cff48SThierry Reding /* make sure we're running on Tegra */ 365226cff48SThierry Reding np = of_find_matching_node(NULL, tegra_fuse_match); 366226cff48SThierry Reding if (!np) 367226cff48SThierry Reding return 0; 368226cff48SThierry Reding 369226cff48SThierry Reding of_node_put(np); 370226cff48SThierry Reding 37127a0342aSThierry Reding soc = tegra_soc_device_register(); 37227a0342aSThierry Reding if (IS_ERR(soc)) { 37327a0342aSThierry Reding pr_err("failed to register SoC device: %ld\n", PTR_ERR(soc)); 37427a0342aSThierry Reding return PTR_ERR(soc); 37527a0342aSThierry Reding } 37627a0342aSThierry Reding 37727a0342aSThierry Reding return 0; 37827a0342aSThierry Reding } 3799261b43eSThierry Reding device_initcall(tegra_init_soc); 38027a0342aSThierry Reding #endif 381