19952f691SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2783c8f4cSPeter De Schrijver /* 394250166SSagar Kamble * Copyright (c) 2013-2022, NVIDIA CORPORATION. All rights reserved. 4783c8f4cSPeter De Schrijver */ 5783c8f4cSPeter De Schrijver 67e939de1SThierry Reding #include <linux/clk.h> 7783c8f4cSPeter De Schrijver #include <linux/device.h> 8783c8f4cSPeter De Schrijver #include <linux/kobject.h> 91859217bSPaul Gortmaker #include <linux/init.h> 1027a0342aSThierry Reding #include <linux/io.h> 1196ee12b2SThierry Reding #include <linux/nvmem-consumer.h> 1296ee12b2SThierry Reding #include <linux/nvmem-provider.h> 13783c8f4cSPeter De Schrijver #include <linux/of.h> 14783c8f4cSPeter De Schrijver #include <linux/of_address.h> 1527a0342aSThierry Reding #include <linux/platform_device.h> 1624a15252SDmitry Osipenko #include <linux/pm_runtime.h> 17aeecc50aSDmitry Osipenko #include <linux/reset.h> 1827a0342aSThierry Reding #include <linux/slab.h> 1927a0342aSThierry Reding #include <linux/sys_soc.h> 20783c8f4cSPeter De Schrijver 2124fa5af8SThierry Reding #include <soc/tegra/common.h> 22783c8f4cSPeter De Schrijver #include <soc/tegra/fuse.h> 23783c8f4cSPeter De Schrijver 24783c8f4cSPeter De Schrijver #include "fuse.h" 25783c8f4cSPeter De Schrijver 26783c8f4cSPeter De Schrijver struct tegra_sku_info tegra_sku_info; 27f9fc3661SVince Hsu EXPORT_SYMBOL(tegra_sku_info); 28783c8f4cSPeter De Schrijver 29783c8f4cSPeter De Schrijver static const char *tegra_revision_name[TEGRA_REVISION_MAX] = { 30783c8f4cSPeter De Schrijver [TEGRA_REVISION_UNKNOWN] = "unknown", 31783c8f4cSPeter De Schrijver [TEGRA_REVISION_A01] = "A01", 32783c8f4cSPeter De Schrijver [TEGRA_REVISION_A02] = "A02", 33783c8f4cSPeter De Schrijver [TEGRA_REVISION_A03] = "A03", 34783c8f4cSPeter De Schrijver [TEGRA_REVISION_A03p] = "A03 prime", 35783c8f4cSPeter De Schrijver [TEGRA_REVISION_A04] = "A04", 36783c8f4cSPeter De Schrijver }; 37783c8f4cSPeter De Schrijver 38783c8f4cSPeter De Schrijver static const struct of_device_id car_match[] __initconst = { 39783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra20-car", }, 40783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra30-car", }, 41783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra114-car", }, 42783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra124-car", }, 439b07eb05SThierry Reding { .compatible = "nvidia,tegra132-car", }, 440dc5a0d8SThierry Reding { .compatible = "nvidia,tegra210-car", }, 45783c8f4cSPeter De Schrijver {}, 46783c8f4cSPeter De Schrijver }; 47783c8f4cSPeter De Schrijver 487e939de1SThierry Reding static struct tegra_fuse *fuse = &(struct tegra_fuse) { 497e939de1SThierry Reding .base = NULL, 507e939de1SThierry Reding .soc = NULL, 517e939de1SThierry Reding }; 527e939de1SThierry Reding 537e939de1SThierry Reding static const struct of_device_id tegra_fuse_match[] = { 541f44febfSThierry Reding #ifdef CONFIG_ARCH_TEGRA_234_SOC 551f44febfSThierry Reding { .compatible = "nvidia,tegra234-efuse", .data = &tegra234_fuse_soc }, 561f44febfSThierry Reding #endif 573979a4c6SJC Kuo #ifdef CONFIG_ARCH_TEGRA_194_SOC 583979a4c6SJC Kuo { .compatible = "nvidia,tegra194-efuse", .data = &tegra194_fuse_soc }, 593979a4c6SJC Kuo #endif 6083468fe2STimo Alho #ifdef CONFIG_ARCH_TEGRA_186_SOC 6183468fe2STimo Alho { .compatible = "nvidia,tegra186-efuse", .data = &tegra186_fuse_soc }, 6283468fe2STimo Alho #endif 630dc5a0d8SThierry Reding #ifdef CONFIG_ARCH_TEGRA_210_SOC 640dc5a0d8SThierry Reding { .compatible = "nvidia,tegra210-efuse", .data = &tegra210_fuse_soc }, 650dc5a0d8SThierry Reding #endif 667e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_132_SOC 677e939de1SThierry Reding { .compatible = "nvidia,tegra132-efuse", .data = &tegra124_fuse_soc }, 687e939de1SThierry Reding #endif 697e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_124_SOC 707e939de1SThierry Reding { .compatible = "nvidia,tegra124-efuse", .data = &tegra124_fuse_soc }, 717e939de1SThierry Reding #endif 727e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_114_SOC 737e939de1SThierry Reding { .compatible = "nvidia,tegra114-efuse", .data = &tegra114_fuse_soc }, 747e939de1SThierry Reding #endif 757e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_3x_SOC 767e939de1SThierry Reding { .compatible = "nvidia,tegra30-efuse", .data = &tegra30_fuse_soc }, 777e939de1SThierry Reding #endif 787e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_2x_SOC 797e939de1SThierry Reding { .compatible = "nvidia,tegra20-efuse", .data = &tegra20_fuse_soc }, 807e939de1SThierry Reding #endif 817e939de1SThierry Reding { /* sentinel */ } 827e939de1SThierry Reding }; 837e939de1SThierry Reding 8496ee12b2SThierry Reding static int tegra_fuse_read(void *priv, unsigned int offset, void *value, 8596ee12b2SThierry Reding size_t bytes) 8696ee12b2SThierry Reding { 8796ee12b2SThierry Reding unsigned int count = bytes / 4, i; 8896ee12b2SThierry Reding struct tegra_fuse *fuse = priv; 8996ee12b2SThierry Reding u32 *buffer = value; 9096ee12b2SThierry Reding 9196ee12b2SThierry Reding for (i = 0; i < count; i++) 9296ee12b2SThierry Reding buffer[i] = fuse->read(fuse, offset + i * 4); 9396ee12b2SThierry Reding 9496ee12b2SThierry Reding return 0; 9596ee12b2SThierry Reding } 9696ee12b2SThierry Reding 9788724b78SDmitry Osipenko static void tegra_fuse_restore(void *base) 9888724b78SDmitry Osipenko { 99b631c9c2SThierry Reding fuse->base = (void __iomem *)base; 10088724b78SDmitry Osipenko fuse->clk = NULL; 10188724b78SDmitry Osipenko } 10288724b78SDmitry Osipenko 1037e939de1SThierry Reding static int tegra_fuse_probe(struct platform_device *pdev) 1047e939de1SThierry Reding { 1057e939de1SThierry Reding void __iomem *base = fuse->base; 10696ee12b2SThierry Reding struct nvmem_config nvmem; 1077e939de1SThierry Reding struct resource *res; 1087e939de1SThierry Reding int err; 1097e939de1SThierry Reding 110b631c9c2SThierry Reding err = devm_add_action(&pdev->dev, tegra_fuse_restore, (void __force *)base); 11188724b78SDmitry Osipenko if (err) 11288724b78SDmitry Osipenko return err; 11388724b78SDmitry Osipenko 1147e939de1SThierry Reding /* take over the memory region from the early initialization */ 1157e939de1SThierry Reding res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 11655a042b3SDmitry Osipenko fuse->phys = res->start; 1177e939de1SThierry Reding fuse->base = devm_ioremap_resource(&pdev->dev, res); 11851294bf6STimo Alho if (IS_ERR(fuse->base)) { 11951294bf6STimo Alho err = PTR_ERR(fuse->base); 12051294bf6STimo Alho return err; 12151294bf6STimo Alho } 1227e939de1SThierry Reding 1237e939de1SThierry Reding fuse->clk = devm_clk_get(&pdev->dev, "fuse"); 1247e939de1SThierry Reding if (IS_ERR(fuse->clk)) { 125f0b2835fSThierry Reding if (PTR_ERR(fuse->clk) != -EPROBE_DEFER) 1267e939de1SThierry Reding dev_err(&pdev->dev, "failed to get FUSE clock: %ld", 1277e939de1SThierry Reding PTR_ERR(fuse->clk)); 128f0b2835fSThierry Reding 1297e939de1SThierry Reding return PTR_ERR(fuse->clk); 1307e939de1SThierry Reding } 1317e939de1SThierry Reding 1327e939de1SThierry Reding platform_set_drvdata(pdev, fuse); 1337e939de1SThierry Reding fuse->dev = &pdev->dev; 1347e939de1SThierry Reding 13588724b78SDmitry Osipenko err = devm_pm_runtime_enable(&pdev->dev); 13688724b78SDmitry Osipenko if (err) 13788724b78SDmitry Osipenko return err; 13824a15252SDmitry Osipenko 1397e939de1SThierry Reding if (fuse->soc->probe) { 1407e939de1SThierry Reding err = fuse->soc->probe(fuse); 1419f1022b8SThierry Reding if (err < 0) 14288724b78SDmitry Osipenko return err; 14351294bf6STimo Alho } 1447e939de1SThierry Reding 14596ee12b2SThierry Reding memset(&nvmem, 0, sizeof(nvmem)); 14696ee12b2SThierry Reding nvmem.dev = &pdev->dev; 14796ee12b2SThierry Reding nvmem.name = "fuse"; 14896ee12b2SThierry Reding nvmem.id = -1; 14996ee12b2SThierry Reding nvmem.owner = THIS_MODULE; 150bea06d77SKartik nvmem.cells = fuse->soc->cells; 151bea06d77SKartik nvmem.ncells = fuse->soc->num_cells; 152*cc5b2ad5SKartik nvmem.keepout = fuse->soc->keepouts; 153*cc5b2ad5SKartik nvmem.nkeepout = fuse->soc->num_keepouts; 15496ee12b2SThierry Reding nvmem.type = NVMEM_TYPE_OTP; 15596ee12b2SThierry Reding nvmem.read_only = true; 15696ee12b2SThierry Reding nvmem.root_only = true; 15796ee12b2SThierry Reding nvmem.reg_read = tegra_fuse_read; 15896ee12b2SThierry Reding nvmem.size = fuse->soc->info->size; 15996ee12b2SThierry Reding nvmem.word_size = 4; 16096ee12b2SThierry Reding nvmem.stride = 4; 16196ee12b2SThierry Reding nvmem.priv = fuse; 16296ee12b2SThierry Reding 16396ee12b2SThierry Reding fuse->nvmem = devm_nvmem_register(&pdev->dev, &nvmem); 16496ee12b2SThierry Reding if (IS_ERR(fuse->nvmem)) { 16596ee12b2SThierry Reding err = PTR_ERR(fuse->nvmem); 16696ee12b2SThierry Reding dev_err(&pdev->dev, "failed to register NVMEM device: %d\n", 16796ee12b2SThierry Reding err); 16888724b78SDmitry Osipenko return err; 1699f1022b8SThierry Reding } 1707e939de1SThierry Reding 171aeecc50aSDmitry Osipenko fuse->rst = devm_reset_control_get_optional(&pdev->dev, "fuse"); 172aeecc50aSDmitry Osipenko if (IS_ERR(fuse->rst)) { 173aeecc50aSDmitry Osipenko err = PTR_ERR(fuse->rst); 174aeecc50aSDmitry Osipenko dev_err(&pdev->dev, "failed to get FUSE reset: %pe\n", 175aeecc50aSDmitry Osipenko fuse->rst); 17688724b78SDmitry Osipenko return err; 177aeecc50aSDmitry Osipenko } 178aeecc50aSDmitry Osipenko 179aeecc50aSDmitry Osipenko /* 180aeecc50aSDmitry Osipenko * FUSE clock is enabled at a boot time, hence this resume/suspend 181aeecc50aSDmitry Osipenko * disables the clock besides the h/w resetting. 182aeecc50aSDmitry Osipenko */ 183aeecc50aSDmitry Osipenko err = pm_runtime_resume_and_get(&pdev->dev); 184aeecc50aSDmitry Osipenko if (err) 18588724b78SDmitry Osipenko return err; 186aeecc50aSDmitry Osipenko 187aeecc50aSDmitry Osipenko err = reset_control_reset(fuse->rst); 188aeecc50aSDmitry Osipenko pm_runtime_put(&pdev->dev); 189aeecc50aSDmitry Osipenko 190aeecc50aSDmitry Osipenko if (err < 0) { 191aeecc50aSDmitry Osipenko dev_err(&pdev->dev, "failed to reset FUSE: %d\n", err); 19288724b78SDmitry Osipenko return err; 1937e939de1SThierry Reding } 1947e939de1SThierry Reding 1957e939de1SThierry Reding /* release the early I/O memory mapping */ 1967e939de1SThierry Reding iounmap(base); 1977e939de1SThierry Reding 1987e939de1SThierry Reding return 0; 1997e939de1SThierry Reding } 2007e939de1SThierry Reding 20124a15252SDmitry Osipenko static int __maybe_unused tegra_fuse_runtime_resume(struct device *dev) 20224a15252SDmitry Osipenko { 20324a15252SDmitry Osipenko int err; 20424a15252SDmitry Osipenko 20524a15252SDmitry Osipenko err = clk_prepare_enable(fuse->clk); 20624a15252SDmitry Osipenko if (err < 0) { 20724a15252SDmitry Osipenko dev_err(dev, "failed to enable FUSE clock: %d\n", err); 20824a15252SDmitry Osipenko return err; 20924a15252SDmitry Osipenko } 21024a15252SDmitry Osipenko 21124a15252SDmitry Osipenko return 0; 21224a15252SDmitry Osipenko } 21324a15252SDmitry Osipenko 21424a15252SDmitry Osipenko static int __maybe_unused tegra_fuse_runtime_suspend(struct device *dev) 21524a15252SDmitry Osipenko { 21624a15252SDmitry Osipenko clk_disable_unprepare(fuse->clk); 21724a15252SDmitry Osipenko 21824a15252SDmitry Osipenko return 0; 21924a15252SDmitry Osipenko } 22024a15252SDmitry Osipenko 22159c6fcebSDmitry Osipenko static int __maybe_unused tegra_fuse_suspend(struct device *dev) 22259c6fcebSDmitry Osipenko { 22359c6fcebSDmitry Osipenko int ret; 22459c6fcebSDmitry Osipenko 22559c6fcebSDmitry Osipenko /* 22659c6fcebSDmitry Osipenko * Critical for RAM re-repair operation, which must occur on resume 22759c6fcebSDmitry Osipenko * from LP1 system suspend and as part of CCPLEX cluster switching. 22859c6fcebSDmitry Osipenko */ 22959c6fcebSDmitry Osipenko if (fuse->soc->clk_suspend_on) 23059c6fcebSDmitry Osipenko ret = pm_runtime_resume_and_get(dev); 23159c6fcebSDmitry Osipenko else 23259c6fcebSDmitry Osipenko ret = pm_runtime_force_suspend(dev); 23359c6fcebSDmitry Osipenko 23459c6fcebSDmitry Osipenko return ret; 23559c6fcebSDmitry Osipenko } 23659c6fcebSDmitry Osipenko 23759c6fcebSDmitry Osipenko static int __maybe_unused tegra_fuse_resume(struct device *dev) 23859c6fcebSDmitry Osipenko { 23959c6fcebSDmitry Osipenko int ret = 0; 24059c6fcebSDmitry Osipenko 24159c6fcebSDmitry Osipenko if (fuse->soc->clk_suspend_on) 24259c6fcebSDmitry Osipenko pm_runtime_put(dev); 24359c6fcebSDmitry Osipenko else 24459c6fcebSDmitry Osipenko ret = pm_runtime_force_resume(dev); 24559c6fcebSDmitry Osipenko 24659c6fcebSDmitry Osipenko return ret; 24759c6fcebSDmitry Osipenko } 24859c6fcebSDmitry Osipenko 24924a15252SDmitry Osipenko static const struct dev_pm_ops tegra_fuse_pm = { 25024a15252SDmitry Osipenko SET_RUNTIME_PM_OPS(tegra_fuse_runtime_suspend, tegra_fuse_runtime_resume, 25124a15252SDmitry Osipenko NULL) 25259c6fcebSDmitry Osipenko SET_SYSTEM_SLEEP_PM_OPS(tegra_fuse_suspend, tegra_fuse_resume) 25324a15252SDmitry Osipenko }; 25424a15252SDmitry Osipenko 2557e939de1SThierry Reding static struct platform_driver tegra_fuse_driver = { 2567e939de1SThierry Reding .driver = { 2577e939de1SThierry Reding .name = "tegra-fuse", 2587e939de1SThierry Reding .of_match_table = tegra_fuse_match, 25924a15252SDmitry Osipenko .pm = &tegra_fuse_pm, 2607e939de1SThierry Reding .suppress_bind_attrs = true, 2617e939de1SThierry Reding }, 2627e939de1SThierry Reding .probe = tegra_fuse_probe, 2637e939de1SThierry Reding }; 2641859217bSPaul Gortmaker builtin_platform_driver(tegra_fuse_driver); 2657e939de1SThierry Reding 266a7083763SNathan Chancellor u32 __init tegra_fuse_read_spare(unsigned int spare) 2677e939de1SThierry Reding { 2687e939de1SThierry Reding unsigned int offset = fuse->soc->info->spare + spare * 4; 2697e939de1SThierry Reding 2707e939de1SThierry Reding return fuse->read_early(fuse, offset) & 1; 2717e939de1SThierry Reding } 2727e939de1SThierry Reding 2737e939de1SThierry Reding u32 __init tegra_fuse_read_early(unsigned int offset) 2747e939de1SThierry Reding { 2757e939de1SThierry Reding return fuse->read_early(fuse, offset); 2767e939de1SThierry Reding } 2777e939de1SThierry Reding 2787e939de1SThierry Reding int tegra_fuse_readl(unsigned long offset, u32 *value) 2797e939de1SThierry Reding { 2800a728e0bSNagarjuna Kristam if (!fuse->read || !fuse->clk) 2817e939de1SThierry Reding return -EPROBE_DEFER; 2827e939de1SThierry Reding 2830a728e0bSNagarjuna Kristam if (IS_ERR(fuse->clk)) 2840a728e0bSNagarjuna Kristam return PTR_ERR(fuse->clk); 2850a728e0bSNagarjuna Kristam 2867e939de1SThierry Reding *value = fuse->read(fuse, offset); 2877e939de1SThierry Reding 2887e939de1SThierry Reding return 0; 2897e939de1SThierry Reding } 2907e939de1SThierry Reding EXPORT_SYMBOL(tegra_fuse_readl); 2917e939de1SThierry Reding 292783c8f4cSPeter De Schrijver static void tegra_enable_fuse_clk(void __iomem *base) 293783c8f4cSPeter De Schrijver { 294783c8f4cSPeter De Schrijver u32 reg; 295783c8f4cSPeter De Schrijver 296783c8f4cSPeter De Schrijver reg = readl_relaxed(base + 0x48); 297783c8f4cSPeter De Schrijver reg |= 1 << 28; 298783c8f4cSPeter De Schrijver writel(reg, base + 0x48); 299783c8f4cSPeter De Schrijver 300783c8f4cSPeter De Schrijver /* 301783c8f4cSPeter De Schrijver * Enable FUSE clock. This needs to be hardcoded because the clock 302783c8f4cSPeter De Schrijver * subsystem is not active during early boot. 303783c8f4cSPeter De Schrijver */ 304783c8f4cSPeter De Schrijver reg = readl(base + 0x14); 305783c8f4cSPeter De Schrijver reg |= 1 << 7; 306783c8f4cSPeter De Schrijver writel(reg, base + 0x14); 307783c8f4cSPeter De Schrijver } 308783c8f4cSPeter De Schrijver 309379ac9ebSJon Hunter static ssize_t major_show(struct device *dev, struct device_attribute *attr, 310379ac9ebSJon Hunter char *buf) 311379ac9ebSJon Hunter { 312379ac9ebSJon Hunter return sprintf(buf, "%d\n", tegra_get_major_rev()); 313379ac9ebSJon Hunter } 314379ac9ebSJon Hunter 315379ac9ebSJon Hunter static DEVICE_ATTR_RO(major); 316379ac9ebSJon Hunter 317379ac9ebSJon Hunter static ssize_t minor_show(struct device *dev, struct device_attribute *attr, 318379ac9ebSJon Hunter char *buf) 319379ac9ebSJon Hunter { 320379ac9ebSJon Hunter return sprintf(buf, "%d\n", tegra_get_minor_rev()); 321379ac9ebSJon Hunter } 322379ac9ebSJon Hunter 323379ac9ebSJon Hunter static DEVICE_ATTR_RO(minor); 324379ac9ebSJon Hunter 325379ac9ebSJon Hunter static struct attribute *tegra_soc_attr[] = { 326379ac9ebSJon Hunter &dev_attr_major.attr, 327379ac9ebSJon Hunter &dev_attr_minor.attr, 328379ac9ebSJon Hunter NULL, 329379ac9ebSJon Hunter }; 330379ac9ebSJon Hunter 331379ac9ebSJon Hunter const struct attribute_group tegra_soc_attr_group = { 332379ac9ebSJon Hunter .attrs = tegra_soc_attr, 333379ac9ebSJon Hunter }; 334379ac9ebSJon Hunter 3351f44febfSThierry Reding #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \ 3361f44febfSThierry Reding IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) 337379ac9ebSJon Hunter static ssize_t platform_show(struct device *dev, struct device_attribute *attr, 338379ac9ebSJon Hunter char *buf) 339379ac9ebSJon Hunter { 340379ac9ebSJon Hunter /* 341379ac9ebSJon Hunter * Displays the value in the 'pre_si_platform' field of the HIDREV 342379ac9ebSJon Hunter * register for Tegra194 devices. A value of 0 indicates that the 343379ac9ebSJon Hunter * platform type is silicon and all other non-zero values indicate 344379ac9ebSJon Hunter * the type of simulation platform is being used. 345379ac9ebSJon Hunter */ 346775edf78SThierry Reding return sprintf(buf, "%d\n", tegra_get_platform()); 347379ac9ebSJon Hunter } 348379ac9ebSJon Hunter 349379ac9ebSJon Hunter static DEVICE_ATTR_RO(platform); 350379ac9ebSJon Hunter 351379ac9ebSJon Hunter static struct attribute *tegra194_soc_attr[] = { 352379ac9ebSJon Hunter &dev_attr_major.attr, 353379ac9ebSJon Hunter &dev_attr_minor.attr, 354379ac9ebSJon Hunter &dev_attr_platform.attr, 355379ac9ebSJon Hunter NULL, 356379ac9ebSJon Hunter }; 357379ac9ebSJon Hunter 358379ac9ebSJon Hunter const struct attribute_group tegra194_soc_attr_group = { 359379ac9ebSJon Hunter .attrs = tegra194_soc_attr, 360379ac9ebSJon Hunter }; 361379ac9ebSJon Hunter #endif 362379ac9ebSJon Hunter 36327a0342aSThierry Reding struct device * __init tegra_soc_device_register(void) 36427a0342aSThierry Reding { 36527a0342aSThierry Reding struct soc_device_attribute *attr; 36627a0342aSThierry Reding struct soc_device *dev; 36727a0342aSThierry Reding 36827a0342aSThierry Reding attr = kzalloc(sizeof(*attr), GFP_KERNEL); 36927a0342aSThierry Reding if (!attr) 37027a0342aSThierry Reding return NULL; 37127a0342aSThierry Reding 37227a0342aSThierry Reding attr->family = kasprintf(GFP_KERNEL, "Tegra"); 37337558ac8SJon Hunter attr->revision = kasprintf(GFP_KERNEL, "%s", 37437558ac8SJon Hunter tegra_revision_name[tegra_sku_info.revision]); 37527a0342aSThierry Reding attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id()); 376379ac9ebSJon Hunter attr->custom_attr_group = fuse->soc->soc_attr_group; 37727a0342aSThierry Reding 37827a0342aSThierry Reding dev = soc_device_register(attr); 37927a0342aSThierry Reding if (IS_ERR(dev)) { 38027a0342aSThierry Reding kfree(attr->soc_id); 38127a0342aSThierry Reding kfree(attr->revision); 38227a0342aSThierry Reding kfree(attr->family); 38327a0342aSThierry Reding kfree(attr); 38427a0342aSThierry Reding return ERR_CAST(dev); 38527a0342aSThierry Reding } 38627a0342aSThierry Reding 38727a0342aSThierry Reding return soc_device_to_device(dev); 38827a0342aSThierry Reding } 38927a0342aSThierry Reding 39024fa5af8SThierry Reding static int __init tegra_init_fuse(void) 391783c8f4cSPeter De Schrijver { 3927e939de1SThierry Reding const struct of_device_id *match; 393783c8f4cSPeter De Schrijver struct device_node *np; 3947e939de1SThierry Reding struct resource regs; 39524fa5af8SThierry Reding 396783c8f4cSPeter De Schrijver tegra_init_apbmisc(); 397783c8f4cSPeter De Schrijver 3987e939de1SThierry Reding np = of_find_matching_node_and_match(NULL, tegra_fuse_match, &match); 3997e939de1SThierry Reding if (!np) { 4007e939de1SThierry Reding /* 4017e939de1SThierry Reding * Fall back to legacy initialization for 32-bit ARM only. All 4027e939de1SThierry Reding * 64-bit ARM device tree files for Tegra are required to have 4037e939de1SThierry Reding * a FUSE node. 4047e939de1SThierry Reding * 4057e939de1SThierry Reding * This is for backwards-compatibility with old device trees 4067e939de1SThierry Reding * that didn't contain a FUSE node. 4077e939de1SThierry Reding */ 4087e939de1SThierry Reding if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 4097e939de1SThierry Reding u8 chip = tegra_get_chip_id(); 4107e939de1SThierry Reding 4117e939de1SThierry Reding regs.start = 0x7000f800; 4127e939de1SThierry Reding regs.end = 0x7000fbff; 4137e939de1SThierry Reding regs.flags = IORESOURCE_MEM; 4147e939de1SThierry Reding 4157e939de1SThierry Reding switch (chip) { 4167e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_2x_SOC 4177e939de1SThierry Reding case TEGRA20: 4187e939de1SThierry Reding fuse->soc = &tegra20_fuse_soc; 4197e939de1SThierry Reding break; 4207e939de1SThierry Reding #endif 4217e939de1SThierry Reding 4227e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_3x_SOC 4237e939de1SThierry Reding case TEGRA30: 4247e939de1SThierry Reding fuse->soc = &tegra30_fuse_soc; 4257e939de1SThierry Reding break; 4267e939de1SThierry Reding #endif 4277e939de1SThierry Reding 4287e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_114_SOC 4297e939de1SThierry Reding case TEGRA114: 4307e939de1SThierry Reding fuse->soc = &tegra114_fuse_soc; 4317e939de1SThierry Reding break; 4327e939de1SThierry Reding #endif 4337e939de1SThierry Reding 4347e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_124_SOC 4357e939de1SThierry Reding case TEGRA124: 4367e939de1SThierry Reding fuse->soc = &tegra124_fuse_soc; 4377e939de1SThierry Reding break; 4387e939de1SThierry Reding #endif 4397e939de1SThierry Reding 4407e939de1SThierry Reding default: 4417e939de1SThierry Reding pr_warn("Unsupported SoC: %02x\n", chip); 4427e939de1SThierry Reding break; 4437e939de1SThierry Reding } 444783c8f4cSPeter De Schrijver } else { 4457e939de1SThierry Reding /* 4467e939de1SThierry Reding * At this point we're not running on Tegra, so play 4477e939de1SThierry Reding * nice with multi-platform kernels. 4487e939de1SThierry Reding */ 4497e939de1SThierry Reding return 0; 4507e939de1SThierry Reding } 4517e939de1SThierry Reding } else { 4527e939de1SThierry Reding /* 4537e939de1SThierry Reding * Extract information from the device tree if we've found a 4547e939de1SThierry Reding * matching node. 4557e939de1SThierry Reding */ 4567e939de1SThierry Reding if (of_address_to_resource(np, 0, ®s) < 0) { 4577e939de1SThierry Reding pr_err("failed to get FUSE register\n"); 45824fa5af8SThierry Reding return -ENXIO; 459783c8f4cSPeter De Schrijver } 460783c8f4cSPeter De Schrijver 4617e939de1SThierry Reding fuse->soc = match->data; 4627e939de1SThierry Reding } 4637e939de1SThierry Reding 4647e939de1SThierry Reding np = of_find_matching_node(NULL, car_match); 4657e939de1SThierry Reding if (np) { 4667e939de1SThierry Reding void __iomem *base = of_iomap(np, 0); 467e941712cSLiang He of_node_put(np); 4687e939de1SThierry Reding if (base) { 4697e939de1SThierry Reding tegra_enable_fuse_clk(base); 4707e939de1SThierry Reding iounmap(base); 4717e939de1SThierry Reding } else { 4727e939de1SThierry Reding pr_err("failed to map clock registers\n"); 4737e939de1SThierry Reding return -ENXIO; 4747e939de1SThierry Reding } 4757e939de1SThierry Reding } 4767e939de1SThierry Reding 4774bdc0d67SChristoph Hellwig fuse->base = ioremap(regs.start, resource_size(®s)); 4787e939de1SThierry Reding if (!fuse->base) { 4797e939de1SThierry Reding pr_err("failed to map FUSE registers\n"); 4807e939de1SThierry Reding return -ENXIO; 4817e939de1SThierry Reding } 4827e939de1SThierry Reding 4837e939de1SThierry Reding fuse->soc->init(fuse); 484783c8f4cSPeter De Schrijver 48503b3f4c8SThierry Reding pr_info("Tegra Revision: %s SKU: %d CPU Process: %d SoC Process: %d\n", 486783c8f4cSPeter De Schrijver tegra_revision_name[tegra_sku_info.revision], 487783c8f4cSPeter De Schrijver tegra_sku_info.sku_id, tegra_sku_info.cpu_process_id, 48803b3f4c8SThierry Reding tegra_sku_info.soc_process_id); 48903b3f4c8SThierry Reding pr_debug("Tegra CPU Speedo ID %d, SoC Speedo ID %d\n", 490783c8f4cSPeter De Schrijver tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id); 49124fa5af8SThierry Reding 4929f94faddSThierry Reding if (fuse->soc->lookups) { 4939f94faddSThierry Reding size_t size = sizeof(*fuse->lookups) * fuse->soc->num_lookups; 4949f94faddSThierry Reding 4959f94faddSThierry Reding fuse->lookups = kmemdup(fuse->soc->lookups, size, GFP_KERNEL); 496854d128bSYang Yingliang if (fuse->lookups) 4979f94faddSThierry Reding nvmem_add_cell_lookups(fuse->lookups, fuse->soc->num_lookups); 4989f94faddSThierry Reding } 49927a0342aSThierry Reding 50024fa5af8SThierry Reding return 0; 501783c8f4cSPeter De Schrijver } 50224fa5af8SThierry Reding early_initcall(tegra_init_fuse); 50327a0342aSThierry Reding 50427a0342aSThierry Reding #ifdef CONFIG_ARM64 50527a0342aSThierry Reding static int __init tegra_init_soc(void) 50627a0342aSThierry Reding { 507226cff48SThierry Reding struct device_node *np; 50827a0342aSThierry Reding struct device *soc; 50927a0342aSThierry Reding 510226cff48SThierry Reding /* make sure we're running on Tegra */ 511226cff48SThierry Reding np = of_find_matching_node(NULL, tegra_fuse_match); 512226cff48SThierry Reding if (!np) 513226cff48SThierry Reding return 0; 514226cff48SThierry Reding 515226cff48SThierry Reding of_node_put(np); 516226cff48SThierry Reding 51727a0342aSThierry Reding soc = tegra_soc_device_register(); 51827a0342aSThierry Reding if (IS_ERR(soc)) { 51927a0342aSThierry Reding pr_err("failed to register SoC device: %ld\n", PTR_ERR(soc)); 52027a0342aSThierry Reding return PTR_ERR(soc); 52127a0342aSThierry Reding } 52227a0342aSThierry Reding 52327a0342aSThierry Reding return 0; 52427a0342aSThierry Reding } 5259261b43eSThierry Reding device_initcall(tegra_init_soc); 52627a0342aSThierry Reding #endif 527