19952f691SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2783c8f4cSPeter De Schrijver /* 3783c8f4cSPeter De Schrijver * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. 4783c8f4cSPeter De Schrijver */ 5783c8f4cSPeter De Schrijver 67e939de1SThierry Reding #include <linux/clk.h> 7783c8f4cSPeter De Schrijver #include <linux/device.h> 8783c8f4cSPeter De Schrijver #include <linux/kobject.h> 91859217bSPaul Gortmaker #include <linux/init.h> 1027a0342aSThierry Reding #include <linux/io.h> 1196ee12b2SThierry Reding #include <linux/nvmem-consumer.h> 1296ee12b2SThierry Reding #include <linux/nvmem-provider.h> 13783c8f4cSPeter De Schrijver #include <linux/of.h> 14783c8f4cSPeter De Schrijver #include <linux/of_address.h> 1527a0342aSThierry Reding #include <linux/platform_device.h> 1624a15252SDmitry Osipenko #include <linux/pm_runtime.h> 17*aeecc50aSDmitry Osipenko #include <linux/reset.h> 1827a0342aSThierry Reding #include <linux/slab.h> 1927a0342aSThierry Reding #include <linux/sys_soc.h> 20783c8f4cSPeter De Schrijver 2124fa5af8SThierry Reding #include <soc/tegra/common.h> 22783c8f4cSPeter De Schrijver #include <soc/tegra/fuse.h> 23783c8f4cSPeter De Schrijver 24783c8f4cSPeter De Schrijver #include "fuse.h" 25783c8f4cSPeter De Schrijver 26783c8f4cSPeter De Schrijver struct tegra_sku_info tegra_sku_info; 27f9fc3661SVince Hsu EXPORT_SYMBOL(tegra_sku_info); 28783c8f4cSPeter De Schrijver 29783c8f4cSPeter De Schrijver static const char *tegra_revision_name[TEGRA_REVISION_MAX] = { 30783c8f4cSPeter De Schrijver [TEGRA_REVISION_UNKNOWN] = "unknown", 31783c8f4cSPeter De Schrijver [TEGRA_REVISION_A01] = "A01", 32783c8f4cSPeter De Schrijver [TEGRA_REVISION_A02] = "A02", 33783c8f4cSPeter De Schrijver [TEGRA_REVISION_A03] = "A03", 34783c8f4cSPeter De Schrijver [TEGRA_REVISION_A03p] = "A03 prime", 35783c8f4cSPeter De Schrijver [TEGRA_REVISION_A04] = "A04", 36783c8f4cSPeter De Schrijver }; 37783c8f4cSPeter De Schrijver 38783c8f4cSPeter De Schrijver static const struct of_device_id car_match[] __initconst = { 39783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra20-car", }, 40783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra30-car", }, 41783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra114-car", }, 42783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra124-car", }, 439b07eb05SThierry Reding { .compatible = "nvidia,tegra132-car", }, 440dc5a0d8SThierry Reding { .compatible = "nvidia,tegra210-car", }, 45783c8f4cSPeter De Schrijver {}, 46783c8f4cSPeter De Schrijver }; 47783c8f4cSPeter De Schrijver 487e939de1SThierry Reding static struct tegra_fuse *fuse = &(struct tegra_fuse) { 497e939de1SThierry Reding .base = NULL, 507e939de1SThierry Reding .soc = NULL, 517e939de1SThierry Reding }; 527e939de1SThierry Reding 537e939de1SThierry Reding static const struct of_device_id tegra_fuse_match[] = { 541f44febfSThierry Reding #ifdef CONFIG_ARCH_TEGRA_234_SOC 551f44febfSThierry Reding { .compatible = "nvidia,tegra234-efuse", .data = &tegra234_fuse_soc }, 561f44febfSThierry Reding #endif 573979a4c6SJC Kuo #ifdef CONFIG_ARCH_TEGRA_194_SOC 583979a4c6SJC Kuo { .compatible = "nvidia,tegra194-efuse", .data = &tegra194_fuse_soc }, 593979a4c6SJC Kuo #endif 6083468fe2STimo Alho #ifdef CONFIG_ARCH_TEGRA_186_SOC 6183468fe2STimo Alho { .compatible = "nvidia,tegra186-efuse", .data = &tegra186_fuse_soc }, 6283468fe2STimo Alho #endif 630dc5a0d8SThierry Reding #ifdef CONFIG_ARCH_TEGRA_210_SOC 640dc5a0d8SThierry Reding { .compatible = "nvidia,tegra210-efuse", .data = &tegra210_fuse_soc }, 650dc5a0d8SThierry Reding #endif 667e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_132_SOC 677e939de1SThierry Reding { .compatible = "nvidia,tegra132-efuse", .data = &tegra124_fuse_soc }, 687e939de1SThierry Reding #endif 697e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_124_SOC 707e939de1SThierry Reding { .compatible = "nvidia,tegra124-efuse", .data = &tegra124_fuse_soc }, 717e939de1SThierry Reding #endif 727e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_114_SOC 737e939de1SThierry Reding { .compatible = "nvidia,tegra114-efuse", .data = &tegra114_fuse_soc }, 747e939de1SThierry Reding #endif 757e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_3x_SOC 767e939de1SThierry Reding { .compatible = "nvidia,tegra30-efuse", .data = &tegra30_fuse_soc }, 777e939de1SThierry Reding #endif 787e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_2x_SOC 797e939de1SThierry Reding { .compatible = "nvidia,tegra20-efuse", .data = &tegra20_fuse_soc }, 807e939de1SThierry Reding #endif 817e939de1SThierry Reding { /* sentinel */ } 827e939de1SThierry Reding }; 837e939de1SThierry Reding 8496ee12b2SThierry Reding static int tegra_fuse_read(void *priv, unsigned int offset, void *value, 8596ee12b2SThierry Reding size_t bytes) 8696ee12b2SThierry Reding { 8796ee12b2SThierry Reding unsigned int count = bytes / 4, i; 8896ee12b2SThierry Reding struct tegra_fuse *fuse = priv; 8996ee12b2SThierry Reding u32 *buffer = value; 9096ee12b2SThierry Reding 9196ee12b2SThierry Reding for (i = 0; i < count; i++) 9296ee12b2SThierry Reding buffer[i] = fuse->read(fuse, offset + i * 4); 9396ee12b2SThierry Reding 9496ee12b2SThierry Reding return 0; 9596ee12b2SThierry Reding } 9696ee12b2SThierry Reding 97f4619c7fSThierry Reding static const struct nvmem_cell_info tegra_fuse_cells[] = { 98f4619c7fSThierry Reding { 99f4619c7fSThierry Reding .name = "tsensor-cpu1", 100f4619c7fSThierry Reding .offset = 0x084, 101f4619c7fSThierry Reding .bytes = 4, 102f4619c7fSThierry Reding .bit_offset = 0, 103f4619c7fSThierry Reding .nbits = 32, 104f4619c7fSThierry Reding }, { 105f4619c7fSThierry Reding .name = "tsensor-cpu2", 106f4619c7fSThierry Reding .offset = 0x088, 107f4619c7fSThierry Reding .bytes = 4, 108f4619c7fSThierry Reding .bit_offset = 0, 109f4619c7fSThierry Reding .nbits = 32, 110f4619c7fSThierry Reding }, { 111f4619c7fSThierry Reding .name = "tsensor-cpu0", 112f4619c7fSThierry Reding .offset = 0x098, 113f4619c7fSThierry Reding .bytes = 4, 114f4619c7fSThierry Reding .bit_offset = 0, 115f4619c7fSThierry Reding .nbits = 32, 116f4619c7fSThierry Reding }, { 117f4619c7fSThierry Reding .name = "xusb-pad-calibration", 118f4619c7fSThierry Reding .offset = 0x0f0, 119f4619c7fSThierry Reding .bytes = 4, 120f4619c7fSThierry Reding .bit_offset = 0, 121f4619c7fSThierry Reding .nbits = 32, 122f4619c7fSThierry Reding }, { 123f4619c7fSThierry Reding .name = "tsensor-cpu3", 124f4619c7fSThierry Reding .offset = 0x12c, 125f4619c7fSThierry Reding .bytes = 4, 126f4619c7fSThierry Reding .bit_offset = 0, 127f4619c7fSThierry Reding .nbits = 32, 128f4619c7fSThierry Reding }, { 129f4619c7fSThierry Reding .name = "sata-calibration", 130f4619c7fSThierry Reding .offset = 0x124, 131f4619c7fSThierry Reding .bytes = 1, 132f4619c7fSThierry Reding .bit_offset = 0, 133f4619c7fSThierry Reding .nbits = 2, 134f4619c7fSThierry Reding }, { 135f4619c7fSThierry Reding .name = "tsensor-gpu", 136f4619c7fSThierry Reding .offset = 0x154, 137f4619c7fSThierry Reding .bytes = 4, 138f4619c7fSThierry Reding .bit_offset = 0, 139f4619c7fSThierry Reding .nbits = 32, 140f4619c7fSThierry Reding }, { 141f4619c7fSThierry Reding .name = "tsensor-mem0", 142f4619c7fSThierry Reding .offset = 0x158, 143f4619c7fSThierry Reding .bytes = 4, 144f4619c7fSThierry Reding .bit_offset = 0, 145f4619c7fSThierry Reding .nbits = 32, 146f4619c7fSThierry Reding }, { 147f4619c7fSThierry Reding .name = "tsensor-mem1", 148f4619c7fSThierry Reding .offset = 0x15c, 149f4619c7fSThierry Reding .bytes = 4, 150f4619c7fSThierry Reding .bit_offset = 0, 151f4619c7fSThierry Reding .nbits = 32, 152f4619c7fSThierry Reding }, { 153f4619c7fSThierry Reding .name = "tsensor-pllx", 154f4619c7fSThierry Reding .offset = 0x160, 155f4619c7fSThierry Reding .bytes = 4, 156f4619c7fSThierry Reding .bit_offset = 0, 157f4619c7fSThierry Reding .nbits = 32, 158f4619c7fSThierry Reding }, { 159f4619c7fSThierry Reding .name = "tsensor-common", 160f4619c7fSThierry Reding .offset = 0x180, 161f4619c7fSThierry Reding .bytes = 4, 162f4619c7fSThierry Reding .bit_offset = 0, 163f4619c7fSThierry Reding .nbits = 32, 164f4619c7fSThierry Reding }, { 165f4619c7fSThierry Reding .name = "tsensor-realignment", 166f4619c7fSThierry Reding .offset = 0x1fc, 167f4619c7fSThierry Reding .bytes = 4, 168f4619c7fSThierry Reding .bit_offset = 0, 169f4619c7fSThierry Reding .nbits = 32, 170f4619c7fSThierry Reding }, { 171f4619c7fSThierry Reding .name = "gpu-calibration", 172f4619c7fSThierry Reding .offset = 0x204, 173f4619c7fSThierry Reding .bytes = 4, 174f4619c7fSThierry Reding .bit_offset = 0, 175f4619c7fSThierry Reding .nbits = 32, 176f4619c7fSThierry Reding }, { 177f4619c7fSThierry Reding .name = "xusb-pad-calibration-ext", 178f4619c7fSThierry Reding .offset = 0x250, 179f4619c7fSThierry Reding .bytes = 4, 180f4619c7fSThierry Reding .bit_offset = 0, 181f4619c7fSThierry Reding .nbits = 32, 182f4619c7fSThierry Reding }, 183f4619c7fSThierry Reding }; 184f4619c7fSThierry Reding 1857e939de1SThierry Reding static int tegra_fuse_probe(struct platform_device *pdev) 1867e939de1SThierry Reding { 1877e939de1SThierry Reding void __iomem *base = fuse->base; 18896ee12b2SThierry Reding struct nvmem_config nvmem; 1897e939de1SThierry Reding struct resource *res; 1907e939de1SThierry Reding int err; 1917e939de1SThierry Reding 1927e939de1SThierry Reding /* take over the memory region from the early initialization */ 1937e939de1SThierry Reding res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 19455a042b3SDmitry Osipenko fuse->phys = res->start; 1957e939de1SThierry Reding fuse->base = devm_ioremap_resource(&pdev->dev, res); 19651294bf6STimo Alho if (IS_ERR(fuse->base)) { 19751294bf6STimo Alho err = PTR_ERR(fuse->base); 19851294bf6STimo Alho fuse->base = base; 19951294bf6STimo Alho return err; 20051294bf6STimo Alho } 2017e939de1SThierry Reding 2027e939de1SThierry Reding fuse->clk = devm_clk_get(&pdev->dev, "fuse"); 2037e939de1SThierry Reding if (IS_ERR(fuse->clk)) { 204f0b2835fSThierry Reding if (PTR_ERR(fuse->clk) != -EPROBE_DEFER) 2057e939de1SThierry Reding dev_err(&pdev->dev, "failed to get FUSE clock: %ld", 2067e939de1SThierry Reding PTR_ERR(fuse->clk)); 207f0b2835fSThierry Reding 20851294bf6STimo Alho fuse->base = base; 2097e939de1SThierry Reding return PTR_ERR(fuse->clk); 2107e939de1SThierry Reding } 2117e939de1SThierry Reding 2127e939de1SThierry Reding platform_set_drvdata(pdev, fuse); 2137e939de1SThierry Reding fuse->dev = &pdev->dev; 2147e939de1SThierry Reding 21524a15252SDmitry Osipenko pm_runtime_enable(&pdev->dev); 21624a15252SDmitry Osipenko 2177e939de1SThierry Reding if (fuse->soc->probe) { 2187e939de1SThierry Reding err = fuse->soc->probe(fuse); 2199f1022b8SThierry Reding if (err < 0) 2209f1022b8SThierry Reding goto restore; 22151294bf6STimo Alho } 2227e939de1SThierry Reding 22396ee12b2SThierry Reding memset(&nvmem, 0, sizeof(nvmem)); 22496ee12b2SThierry Reding nvmem.dev = &pdev->dev; 22596ee12b2SThierry Reding nvmem.name = "fuse"; 22696ee12b2SThierry Reding nvmem.id = -1; 22796ee12b2SThierry Reding nvmem.owner = THIS_MODULE; 228f4619c7fSThierry Reding nvmem.cells = tegra_fuse_cells; 229f4619c7fSThierry Reding nvmem.ncells = ARRAY_SIZE(tegra_fuse_cells); 23096ee12b2SThierry Reding nvmem.type = NVMEM_TYPE_OTP; 23196ee12b2SThierry Reding nvmem.read_only = true; 23296ee12b2SThierry Reding nvmem.root_only = true; 23396ee12b2SThierry Reding nvmem.reg_read = tegra_fuse_read; 23496ee12b2SThierry Reding nvmem.size = fuse->soc->info->size; 23596ee12b2SThierry Reding nvmem.word_size = 4; 23696ee12b2SThierry Reding nvmem.stride = 4; 23796ee12b2SThierry Reding nvmem.priv = fuse; 23896ee12b2SThierry Reding 23996ee12b2SThierry Reding fuse->nvmem = devm_nvmem_register(&pdev->dev, &nvmem); 24096ee12b2SThierry Reding if (IS_ERR(fuse->nvmem)) { 24196ee12b2SThierry Reding err = PTR_ERR(fuse->nvmem); 24296ee12b2SThierry Reding dev_err(&pdev->dev, "failed to register NVMEM device: %d\n", 24396ee12b2SThierry Reding err); 2449f1022b8SThierry Reding goto restore; 2459f1022b8SThierry Reding } 2467e939de1SThierry Reding 247*aeecc50aSDmitry Osipenko fuse->rst = devm_reset_control_get_optional(&pdev->dev, "fuse"); 248*aeecc50aSDmitry Osipenko if (IS_ERR(fuse->rst)) { 249*aeecc50aSDmitry Osipenko err = PTR_ERR(fuse->rst); 250*aeecc50aSDmitry Osipenko dev_err(&pdev->dev, "failed to get FUSE reset: %pe\n", 251*aeecc50aSDmitry Osipenko fuse->rst); 252*aeecc50aSDmitry Osipenko goto restore; 253*aeecc50aSDmitry Osipenko } 254*aeecc50aSDmitry Osipenko 255*aeecc50aSDmitry Osipenko /* 256*aeecc50aSDmitry Osipenko * FUSE clock is enabled at a boot time, hence this resume/suspend 257*aeecc50aSDmitry Osipenko * disables the clock besides the h/w resetting. 258*aeecc50aSDmitry Osipenko */ 259*aeecc50aSDmitry Osipenko err = pm_runtime_resume_and_get(&pdev->dev); 260*aeecc50aSDmitry Osipenko if (err) 261*aeecc50aSDmitry Osipenko goto restore; 262*aeecc50aSDmitry Osipenko 263*aeecc50aSDmitry Osipenko err = reset_control_reset(fuse->rst); 264*aeecc50aSDmitry Osipenko pm_runtime_put(&pdev->dev); 265*aeecc50aSDmitry Osipenko 266*aeecc50aSDmitry Osipenko if (err < 0) { 267*aeecc50aSDmitry Osipenko dev_err(&pdev->dev, "failed to reset FUSE: %d\n", err); 268*aeecc50aSDmitry Osipenko goto restore; 269*aeecc50aSDmitry Osipenko } 270*aeecc50aSDmitry Osipenko 2717e939de1SThierry Reding /* release the early I/O memory mapping */ 2727e939de1SThierry Reding iounmap(base); 2737e939de1SThierry Reding 2747e939de1SThierry Reding return 0; 2759f1022b8SThierry Reding 2769f1022b8SThierry Reding restore: 277a65a4ea1SDmitry Osipenko fuse->clk = NULL; 2789f1022b8SThierry Reding fuse->base = base; 27924a15252SDmitry Osipenko pm_runtime_disable(&pdev->dev); 2809f1022b8SThierry Reding return err; 2817e939de1SThierry Reding } 2827e939de1SThierry Reding 28324a15252SDmitry Osipenko static int __maybe_unused tegra_fuse_runtime_resume(struct device *dev) 28424a15252SDmitry Osipenko { 28524a15252SDmitry Osipenko int err; 28624a15252SDmitry Osipenko 28724a15252SDmitry Osipenko err = clk_prepare_enable(fuse->clk); 28824a15252SDmitry Osipenko if (err < 0) { 28924a15252SDmitry Osipenko dev_err(dev, "failed to enable FUSE clock: %d\n", err); 29024a15252SDmitry Osipenko return err; 29124a15252SDmitry Osipenko } 29224a15252SDmitry Osipenko 29324a15252SDmitry Osipenko return 0; 29424a15252SDmitry Osipenko } 29524a15252SDmitry Osipenko 29624a15252SDmitry Osipenko static int __maybe_unused tegra_fuse_runtime_suspend(struct device *dev) 29724a15252SDmitry Osipenko { 29824a15252SDmitry Osipenko clk_disable_unprepare(fuse->clk); 29924a15252SDmitry Osipenko 30024a15252SDmitry Osipenko return 0; 30124a15252SDmitry Osipenko } 30224a15252SDmitry Osipenko 30359c6fcebSDmitry Osipenko static int __maybe_unused tegra_fuse_suspend(struct device *dev) 30459c6fcebSDmitry Osipenko { 30559c6fcebSDmitry Osipenko int ret; 30659c6fcebSDmitry Osipenko 30759c6fcebSDmitry Osipenko /* 30859c6fcebSDmitry Osipenko * Critical for RAM re-repair operation, which must occur on resume 30959c6fcebSDmitry Osipenko * from LP1 system suspend and as part of CCPLEX cluster switching. 31059c6fcebSDmitry Osipenko */ 31159c6fcebSDmitry Osipenko if (fuse->soc->clk_suspend_on) 31259c6fcebSDmitry Osipenko ret = pm_runtime_resume_and_get(dev); 31359c6fcebSDmitry Osipenko else 31459c6fcebSDmitry Osipenko ret = pm_runtime_force_suspend(dev); 31559c6fcebSDmitry Osipenko 31659c6fcebSDmitry Osipenko return ret; 31759c6fcebSDmitry Osipenko } 31859c6fcebSDmitry Osipenko 31959c6fcebSDmitry Osipenko static int __maybe_unused tegra_fuse_resume(struct device *dev) 32059c6fcebSDmitry Osipenko { 32159c6fcebSDmitry Osipenko int ret = 0; 32259c6fcebSDmitry Osipenko 32359c6fcebSDmitry Osipenko if (fuse->soc->clk_suspend_on) 32459c6fcebSDmitry Osipenko pm_runtime_put(dev); 32559c6fcebSDmitry Osipenko else 32659c6fcebSDmitry Osipenko ret = pm_runtime_force_resume(dev); 32759c6fcebSDmitry Osipenko 32859c6fcebSDmitry Osipenko return ret; 32959c6fcebSDmitry Osipenko } 33059c6fcebSDmitry Osipenko 33124a15252SDmitry Osipenko static const struct dev_pm_ops tegra_fuse_pm = { 33224a15252SDmitry Osipenko SET_RUNTIME_PM_OPS(tegra_fuse_runtime_suspend, tegra_fuse_runtime_resume, 33324a15252SDmitry Osipenko NULL) 33459c6fcebSDmitry Osipenko SET_SYSTEM_SLEEP_PM_OPS(tegra_fuse_suspend, tegra_fuse_resume) 33524a15252SDmitry Osipenko }; 33624a15252SDmitry Osipenko 3377e939de1SThierry Reding static struct platform_driver tegra_fuse_driver = { 3387e939de1SThierry Reding .driver = { 3397e939de1SThierry Reding .name = "tegra-fuse", 3407e939de1SThierry Reding .of_match_table = tegra_fuse_match, 34124a15252SDmitry Osipenko .pm = &tegra_fuse_pm, 3427e939de1SThierry Reding .suppress_bind_attrs = true, 3437e939de1SThierry Reding }, 3447e939de1SThierry Reding .probe = tegra_fuse_probe, 3457e939de1SThierry Reding }; 3461859217bSPaul Gortmaker builtin_platform_driver(tegra_fuse_driver); 3477e939de1SThierry Reding 3487e939de1SThierry Reding bool __init tegra_fuse_read_spare(unsigned int spare) 3497e939de1SThierry Reding { 3507e939de1SThierry Reding unsigned int offset = fuse->soc->info->spare + spare * 4; 3517e939de1SThierry Reding 3527e939de1SThierry Reding return fuse->read_early(fuse, offset) & 1; 3537e939de1SThierry Reding } 3547e939de1SThierry Reding 3557e939de1SThierry Reding u32 __init tegra_fuse_read_early(unsigned int offset) 3567e939de1SThierry Reding { 3577e939de1SThierry Reding return fuse->read_early(fuse, offset); 3587e939de1SThierry Reding } 3597e939de1SThierry Reding 3607e939de1SThierry Reding int tegra_fuse_readl(unsigned long offset, u32 *value) 3617e939de1SThierry Reding { 3620a728e0bSNagarjuna Kristam if (!fuse->read || !fuse->clk) 3637e939de1SThierry Reding return -EPROBE_DEFER; 3647e939de1SThierry Reding 3650a728e0bSNagarjuna Kristam if (IS_ERR(fuse->clk)) 3660a728e0bSNagarjuna Kristam return PTR_ERR(fuse->clk); 3670a728e0bSNagarjuna Kristam 3687e939de1SThierry Reding *value = fuse->read(fuse, offset); 3697e939de1SThierry Reding 3707e939de1SThierry Reding return 0; 3717e939de1SThierry Reding } 3727e939de1SThierry Reding EXPORT_SYMBOL(tegra_fuse_readl); 3737e939de1SThierry Reding 374783c8f4cSPeter De Schrijver static void tegra_enable_fuse_clk(void __iomem *base) 375783c8f4cSPeter De Schrijver { 376783c8f4cSPeter De Schrijver u32 reg; 377783c8f4cSPeter De Schrijver 378783c8f4cSPeter De Schrijver reg = readl_relaxed(base + 0x48); 379783c8f4cSPeter De Schrijver reg |= 1 << 28; 380783c8f4cSPeter De Schrijver writel(reg, base + 0x48); 381783c8f4cSPeter De Schrijver 382783c8f4cSPeter De Schrijver /* 383783c8f4cSPeter De Schrijver * Enable FUSE clock. This needs to be hardcoded because the clock 384783c8f4cSPeter De Schrijver * subsystem is not active during early boot. 385783c8f4cSPeter De Schrijver */ 386783c8f4cSPeter De Schrijver reg = readl(base + 0x14); 387783c8f4cSPeter De Schrijver reg |= 1 << 7; 388783c8f4cSPeter De Schrijver writel(reg, base + 0x14); 389783c8f4cSPeter De Schrijver } 390783c8f4cSPeter De Schrijver 391379ac9ebSJon Hunter static ssize_t major_show(struct device *dev, struct device_attribute *attr, 392379ac9ebSJon Hunter char *buf) 393379ac9ebSJon Hunter { 394379ac9ebSJon Hunter return sprintf(buf, "%d\n", tegra_get_major_rev()); 395379ac9ebSJon Hunter } 396379ac9ebSJon Hunter 397379ac9ebSJon Hunter static DEVICE_ATTR_RO(major); 398379ac9ebSJon Hunter 399379ac9ebSJon Hunter static ssize_t minor_show(struct device *dev, struct device_attribute *attr, 400379ac9ebSJon Hunter char *buf) 401379ac9ebSJon Hunter { 402379ac9ebSJon Hunter return sprintf(buf, "%d\n", tegra_get_minor_rev()); 403379ac9ebSJon Hunter } 404379ac9ebSJon Hunter 405379ac9ebSJon Hunter static DEVICE_ATTR_RO(minor); 406379ac9ebSJon Hunter 407379ac9ebSJon Hunter static struct attribute *tegra_soc_attr[] = { 408379ac9ebSJon Hunter &dev_attr_major.attr, 409379ac9ebSJon Hunter &dev_attr_minor.attr, 410379ac9ebSJon Hunter NULL, 411379ac9ebSJon Hunter }; 412379ac9ebSJon Hunter 413379ac9ebSJon Hunter const struct attribute_group tegra_soc_attr_group = { 414379ac9ebSJon Hunter .attrs = tegra_soc_attr, 415379ac9ebSJon Hunter }; 416379ac9ebSJon Hunter 4171f44febfSThierry Reding #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \ 4181f44febfSThierry Reding IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) 419379ac9ebSJon Hunter static ssize_t platform_show(struct device *dev, struct device_attribute *attr, 420379ac9ebSJon Hunter char *buf) 421379ac9ebSJon Hunter { 422379ac9ebSJon Hunter /* 423379ac9ebSJon Hunter * Displays the value in the 'pre_si_platform' field of the HIDREV 424379ac9ebSJon Hunter * register for Tegra194 devices. A value of 0 indicates that the 425379ac9ebSJon Hunter * platform type is silicon and all other non-zero values indicate 426379ac9ebSJon Hunter * the type of simulation platform is being used. 427379ac9ebSJon Hunter */ 428775edf78SThierry Reding return sprintf(buf, "%d\n", tegra_get_platform()); 429379ac9ebSJon Hunter } 430379ac9ebSJon Hunter 431379ac9ebSJon Hunter static DEVICE_ATTR_RO(platform); 432379ac9ebSJon Hunter 433379ac9ebSJon Hunter static struct attribute *tegra194_soc_attr[] = { 434379ac9ebSJon Hunter &dev_attr_major.attr, 435379ac9ebSJon Hunter &dev_attr_minor.attr, 436379ac9ebSJon Hunter &dev_attr_platform.attr, 437379ac9ebSJon Hunter NULL, 438379ac9ebSJon Hunter }; 439379ac9ebSJon Hunter 440379ac9ebSJon Hunter const struct attribute_group tegra194_soc_attr_group = { 441379ac9ebSJon Hunter .attrs = tegra194_soc_attr, 442379ac9ebSJon Hunter }; 443379ac9ebSJon Hunter #endif 444379ac9ebSJon Hunter 44527a0342aSThierry Reding struct device * __init tegra_soc_device_register(void) 44627a0342aSThierry Reding { 44727a0342aSThierry Reding struct soc_device_attribute *attr; 44827a0342aSThierry Reding struct soc_device *dev; 44927a0342aSThierry Reding 45027a0342aSThierry Reding attr = kzalloc(sizeof(*attr), GFP_KERNEL); 45127a0342aSThierry Reding if (!attr) 45227a0342aSThierry Reding return NULL; 45327a0342aSThierry Reding 45427a0342aSThierry Reding attr->family = kasprintf(GFP_KERNEL, "Tegra"); 45537558ac8SJon Hunter attr->revision = kasprintf(GFP_KERNEL, "%s", 45637558ac8SJon Hunter tegra_revision_name[tegra_sku_info.revision]); 45727a0342aSThierry Reding attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id()); 458379ac9ebSJon Hunter attr->custom_attr_group = fuse->soc->soc_attr_group; 45927a0342aSThierry Reding 46027a0342aSThierry Reding dev = soc_device_register(attr); 46127a0342aSThierry Reding if (IS_ERR(dev)) { 46227a0342aSThierry Reding kfree(attr->soc_id); 46327a0342aSThierry Reding kfree(attr->revision); 46427a0342aSThierry Reding kfree(attr->family); 46527a0342aSThierry Reding kfree(attr); 46627a0342aSThierry Reding return ERR_CAST(dev); 46727a0342aSThierry Reding } 46827a0342aSThierry Reding 46927a0342aSThierry Reding return soc_device_to_device(dev); 47027a0342aSThierry Reding } 47127a0342aSThierry Reding 47224fa5af8SThierry Reding static int __init tegra_init_fuse(void) 473783c8f4cSPeter De Schrijver { 4747e939de1SThierry Reding const struct of_device_id *match; 475783c8f4cSPeter De Schrijver struct device_node *np; 4767e939de1SThierry Reding struct resource regs; 47724fa5af8SThierry Reding 478783c8f4cSPeter De Schrijver tegra_init_apbmisc(); 479783c8f4cSPeter De Schrijver 4807e939de1SThierry Reding np = of_find_matching_node_and_match(NULL, tegra_fuse_match, &match); 4817e939de1SThierry Reding if (!np) { 4827e939de1SThierry Reding /* 4837e939de1SThierry Reding * Fall back to legacy initialization for 32-bit ARM only. All 4847e939de1SThierry Reding * 64-bit ARM device tree files for Tegra are required to have 4857e939de1SThierry Reding * a FUSE node. 4867e939de1SThierry Reding * 4877e939de1SThierry Reding * This is for backwards-compatibility with old device trees 4887e939de1SThierry Reding * that didn't contain a FUSE node. 4897e939de1SThierry Reding */ 4907e939de1SThierry Reding if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 4917e939de1SThierry Reding u8 chip = tegra_get_chip_id(); 4927e939de1SThierry Reding 4937e939de1SThierry Reding regs.start = 0x7000f800; 4947e939de1SThierry Reding regs.end = 0x7000fbff; 4957e939de1SThierry Reding regs.flags = IORESOURCE_MEM; 4967e939de1SThierry Reding 4977e939de1SThierry Reding switch (chip) { 4987e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_2x_SOC 4997e939de1SThierry Reding case TEGRA20: 5007e939de1SThierry Reding fuse->soc = &tegra20_fuse_soc; 5017e939de1SThierry Reding break; 5027e939de1SThierry Reding #endif 5037e939de1SThierry Reding 5047e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_3x_SOC 5057e939de1SThierry Reding case TEGRA30: 5067e939de1SThierry Reding fuse->soc = &tegra30_fuse_soc; 5077e939de1SThierry Reding break; 5087e939de1SThierry Reding #endif 5097e939de1SThierry Reding 5107e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_114_SOC 5117e939de1SThierry Reding case TEGRA114: 5127e939de1SThierry Reding fuse->soc = &tegra114_fuse_soc; 5137e939de1SThierry Reding break; 5147e939de1SThierry Reding #endif 5157e939de1SThierry Reding 5167e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_124_SOC 5177e939de1SThierry Reding case TEGRA124: 5187e939de1SThierry Reding fuse->soc = &tegra124_fuse_soc; 5197e939de1SThierry Reding break; 5207e939de1SThierry Reding #endif 5217e939de1SThierry Reding 5227e939de1SThierry Reding default: 5237e939de1SThierry Reding pr_warn("Unsupported SoC: %02x\n", chip); 5247e939de1SThierry Reding break; 5257e939de1SThierry Reding } 526783c8f4cSPeter De Schrijver } else { 5277e939de1SThierry Reding /* 5287e939de1SThierry Reding * At this point we're not running on Tegra, so play 5297e939de1SThierry Reding * nice with multi-platform kernels. 5307e939de1SThierry Reding */ 5317e939de1SThierry Reding return 0; 5327e939de1SThierry Reding } 5337e939de1SThierry Reding } else { 5347e939de1SThierry Reding /* 5357e939de1SThierry Reding * Extract information from the device tree if we've found a 5367e939de1SThierry Reding * matching node. 5377e939de1SThierry Reding */ 5387e939de1SThierry Reding if (of_address_to_resource(np, 0, ®s) < 0) { 5397e939de1SThierry Reding pr_err("failed to get FUSE register\n"); 54024fa5af8SThierry Reding return -ENXIO; 541783c8f4cSPeter De Schrijver } 542783c8f4cSPeter De Schrijver 5437e939de1SThierry Reding fuse->soc = match->data; 5447e939de1SThierry Reding } 5457e939de1SThierry Reding 5467e939de1SThierry Reding np = of_find_matching_node(NULL, car_match); 5477e939de1SThierry Reding if (np) { 5487e939de1SThierry Reding void __iomem *base = of_iomap(np, 0); 5497e939de1SThierry Reding if (base) { 5507e939de1SThierry Reding tegra_enable_fuse_clk(base); 5517e939de1SThierry Reding iounmap(base); 5527e939de1SThierry Reding } else { 5537e939de1SThierry Reding pr_err("failed to map clock registers\n"); 5547e939de1SThierry Reding return -ENXIO; 5557e939de1SThierry Reding } 5567e939de1SThierry Reding } 5577e939de1SThierry Reding 5584bdc0d67SChristoph Hellwig fuse->base = ioremap(regs.start, resource_size(®s)); 5597e939de1SThierry Reding if (!fuse->base) { 5607e939de1SThierry Reding pr_err("failed to map FUSE registers\n"); 5617e939de1SThierry Reding return -ENXIO; 5627e939de1SThierry Reding } 5637e939de1SThierry Reding 5647e939de1SThierry Reding fuse->soc->init(fuse); 565783c8f4cSPeter De Schrijver 56603b3f4c8SThierry Reding pr_info("Tegra Revision: %s SKU: %d CPU Process: %d SoC Process: %d\n", 567783c8f4cSPeter De Schrijver tegra_revision_name[tegra_sku_info.revision], 568783c8f4cSPeter De Schrijver tegra_sku_info.sku_id, tegra_sku_info.cpu_process_id, 56903b3f4c8SThierry Reding tegra_sku_info.soc_process_id); 57003b3f4c8SThierry Reding pr_debug("Tegra CPU Speedo ID %d, SoC Speedo ID %d\n", 571783c8f4cSPeter De Schrijver tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id); 57224fa5af8SThierry Reding 5739f94faddSThierry Reding if (fuse->soc->lookups) { 5749f94faddSThierry Reding size_t size = sizeof(*fuse->lookups) * fuse->soc->num_lookups; 5759f94faddSThierry Reding 5769f94faddSThierry Reding fuse->lookups = kmemdup(fuse->soc->lookups, size, GFP_KERNEL); 577854d128bSYang Yingliang if (fuse->lookups) 5789f94faddSThierry Reding nvmem_add_cell_lookups(fuse->lookups, fuse->soc->num_lookups); 5799f94faddSThierry Reding } 58027a0342aSThierry Reding 58124fa5af8SThierry Reding return 0; 582783c8f4cSPeter De Schrijver } 58324fa5af8SThierry Reding early_initcall(tegra_init_fuse); 58427a0342aSThierry Reding 58527a0342aSThierry Reding #ifdef CONFIG_ARM64 58627a0342aSThierry Reding static int __init tegra_init_soc(void) 58727a0342aSThierry Reding { 588226cff48SThierry Reding struct device_node *np; 58927a0342aSThierry Reding struct device *soc; 59027a0342aSThierry Reding 591226cff48SThierry Reding /* make sure we're running on Tegra */ 592226cff48SThierry Reding np = of_find_matching_node(NULL, tegra_fuse_match); 593226cff48SThierry Reding if (!np) 594226cff48SThierry Reding return 0; 595226cff48SThierry Reding 596226cff48SThierry Reding of_node_put(np); 597226cff48SThierry Reding 59827a0342aSThierry Reding soc = tegra_soc_device_register(); 59927a0342aSThierry Reding if (IS_ERR(soc)) { 60027a0342aSThierry Reding pr_err("failed to register SoC device: %ld\n", PTR_ERR(soc)); 60127a0342aSThierry Reding return PTR_ERR(soc); 60227a0342aSThierry Reding } 60327a0342aSThierry Reding 60427a0342aSThierry Reding return 0; 60527a0342aSThierry Reding } 6069261b43eSThierry Reding device_initcall(tegra_init_soc); 60727a0342aSThierry Reding #endif 608