19952f691SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2783c8f4cSPeter De Schrijver /* 3783c8f4cSPeter De Schrijver * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. 4783c8f4cSPeter De Schrijver */ 5783c8f4cSPeter De Schrijver 67e939de1SThierry Reding #include <linux/clk.h> 7783c8f4cSPeter De Schrijver #include <linux/device.h> 8783c8f4cSPeter De Schrijver #include <linux/kobject.h> 91859217bSPaul Gortmaker #include <linux/init.h> 1027a0342aSThierry Reding #include <linux/io.h> 1196ee12b2SThierry Reding #include <linux/nvmem-consumer.h> 1296ee12b2SThierry Reding #include <linux/nvmem-provider.h> 13783c8f4cSPeter De Schrijver #include <linux/of.h> 14783c8f4cSPeter De Schrijver #include <linux/of_address.h> 1527a0342aSThierry Reding #include <linux/platform_device.h> 1627a0342aSThierry Reding #include <linux/slab.h> 1727a0342aSThierry Reding #include <linux/sys_soc.h> 18783c8f4cSPeter De Schrijver 1924fa5af8SThierry Reding #include <soc/tegra/common.h> 20783c8f4cSPeter De Schrijver #include <soc/tegra/fuse.h> 21783c8f4cSPeter De Schrijver 22783c8f4cSPeter De Schrijver #include "fuse.h" 23783c8f4cSPeter De Schrijver 24783c8f4cSPeter De Schrijver struct tegra_sku_info tegra_sku_info; 25f9fc3661SVince Hsu EXPORT_SYMBOL(tegra_sku_info); 26783c8f4cSPeter De Schrijver 27783c8f4cSPeter De Schrijver static const char *tegra_revision_name[TEGRA_REVISION_MAX] = { 28783c8f4cSPeter De Schrijver [TEGRA_REVISION_UNKNOWN] = "unknown", 29783c8f4cSPeter De Schrijver [TEGRA_REVISION_A01] = "A01", 30783c8f4cSPeter De Schrijver [TEGRA_REVISION_A02] = "A02", 31783c8f4cSPeter De Schrijver [TEGRA_REVISION_A03] = "A03", 32783c8f4cSPeter De Schrijver [TEGRA_REVISION_A03p] = "A03 prime", 33783c8f4cSPeter De Schrijver [TEGRA_REVISION_A04] = "A04", 34783c8f4cSPeter De Schrijver }; 35783c8f4cSPeter De Schrijver 36783c8f4cSPeter De Schrijver static const struct of_device_id car_match[] __initconst = { 37783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra20-car", }, 38783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra30-car", }, 39783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra114-car", }, 40783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra124-car", }, 419b07eb05SThierry Reding { .compatible = "nvidia,tegra132-car", }, 420dc5a0d8SThierry Reding { .compatible = "nvidia,tegra210-car", }, 43783c8f4cSPeter De Schrijver {}, 44783c8f4cSPeter De Schrijver }; 45783c8f4cSPeter De Schrijver 467e939de1SThierry Reding static struct tegra_fuse *fuse = &(struct tegra_fuse) { 477e939de1SThierry Reding .base = NULL, 487e939de1SThierry Reding .soc = NULL, 497e939de1SThierry Reding }; 507e939de1SThierry Reding 517e939de1SThierry Reding static const struct of_device_id tegra_fuse_match[] = { 521f44febfSThierry Reding #ifdef CONFIG_ARCH_TEGRA_234_SOC 531f44febfSThierry Reding { .compatible = "nvidia,tegra234-efuse", .data = &tegra234_fuse_soc }, 541f44febfSThierry Reding #endif 553979a4c6SJC Kuo #ifdef CONFIG_ARCH_TEGRA_194_SOC 563979a4c6SJC Kuo { .compatible = "nvidia,tegra194-efuse", .data = &tegra194_fuse_soc }, 573979a4c6SJC Kuo #endif 5883468fe2STimo Alho #ifdef CONFIG_ARCH_TEGRA_186_SOC 5983468fe2STimo Alho { .compatible = "nvidia,tegra186-efuse", .data = &tegra186_fuse_soc }, 6083468fe2STimo Alho #endif 610dc5a0d8SThierry Reding #ifdef CONFIG_ARCH_TEGRA_210_SOC 620dc5a0d8SThierry Reding { .compatible = "nvidia,tegra210-efuse", .data = &tegra210_fuse_soc }, 630dc5a0d8SThierry Reding #endif 647e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_132_SOC 657e939de1SThierry Reding { .compatible = "nvidia,tegra132-efuse", .data = &tegra124_fuse_soc }, 667e939de1SThierry Reding #endif 677e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_124_SOC 687e939de1SThierry Reding { .compatible = "nvidia,tegra124-efuse", .data = &tegra124_fuse_soc }, 697e939de1SThierry Reding #endif 707e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_114_SOC 717e939de1SThierry Reding { .compatible = "nvidia,tegra114-efuse", .data = &tegra114_fuse_soc }, 727e939de1SThierry Reding #endif 737e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_3x_SOC 747e939de1SThierry Reding { .compatible = "nvidia,tegra30-efuse", .data = &tegra30_fuse_soc }, 757e939de1SThierry Reding #endif 767e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_2x_SOC 777e939de1SThierry Reding { .compatible = "nvidia,tegra20-efuse", .data = &tegra20_fuse_soc }, 787e939de1SThierry Reding #endif 797e939de1SThierry Reding { /* sentinel */ } 807e939de1SThierry Reding }; 817e939de1SThierry Reding 8296ee12b2SThierry Reding static int tegra_fuse_read(void *priv, unsigned int offset, void *value, 8396ee12b2SThierry Reding size_t bytes) 8496ee12b2SThierry Reding { 8596ee12b2SThierry Reding unsigned int count = bytes / 4, i; 8696ee12b2SThierry Reding struct tegra_fuse *fuse = priv; 8796ee12b2SThierry Reding u32 *buffer = value; 8896ee12b2SThierry Reding 8996ee12b2SThierry Reding for (i = 0; i < count; i++) 9096ee12b2SThierry Reding buffer[i] = fuse->read(fuse, offset + i * 4); 9196ee12b2SThierry Reding 9296ee12b2SThierry Reding return 0; 9396ee12b2SThierry Reding } 9496ee12b2SThierry Reding 95f4619c7fSThierry Reding static const struct nvmem_cell_info tegra_fuse_cells[] = { 96f4619c7fSThierry Reding { 97f4619c7fSThierry Reding .name = "tsensor-cpu1", 98f4619c7fSThierry Reding .offset = 0x084, 99f4619c7fSThierry Reding .bytes = 4, 100f4619c7fSThierry Reding .bit_offset = 0, 101f4619c7fSThierry Reding .nbits = 32, 102f4619c7fSThierry Reding }, { 103f4619c7fSThierry Reding .name = "tsensor-cpu2", 104f4619c7fSThierry Reding .offset = 0x088, 105f4619c7fSThierry Reding .bytes = 4, 106f4619c7fSThierry Reding .bit_offset = 0, 107f4619c7fSThierry Reding .nbits = 32, 108f4619c7fSThierry Reding }, { 109f4619c7fSThierry Reding .name = "tsensor-cpu0", 110f4619c7fSThierry Reding .offset = 0x098, 111f4619c7fSThierry Reding .bytes = 4, 112f4619c7fSThierry Reding .bit_offset = 0, 113f4619c7fSThierry Reding .nbits = 32, 114f4619c7fSThierry Reding }, { 115f4619c7fSThierry Reding .name = "xusb-pad-calibration", 116f4619c7fSThierry Reding .offset = 0x0f0, 117f4619c7fSThierry Reding .bytes = 4, 118f4619c7fSThierry Reding .bit_offset = 0, 119f4619c7fSThierry Reding .nbits = 32, 120f4619c7fSThierry Reding }, { 121f4619c7fSThierry Reding .name = "tsensor-cpu3", 122f4619c7fSThierry Reding .offset = 0x12c, 123f4619c7fSThierry Reding .bytes = 4, 124f4619c7fSThierry Reding .bit_offset = 0, 125f4619c7fSThierry Reding .nbits = 32, 126f4619c7fSThierry Reding }, { 127f4619c7fSThierry Reding .name = "sata-calibration", 128f4619c7fSThierry Reding .offset = 0x124, 129f4619c7fSThierry Reding .bytes = 1, 130f4619c7fSThierry Reding .bit_offset = 0, 131f4619c7fSThierry Reding .nbits = 2, 132f4619c7fSThierry Reding }, { 133f4619c7fSThierry Reding .name = "tsensor-gpu", 134f4619c7fSThierry Reding .offset = 0x154, 135f4619c7fSThierry Reding .bytes = 4, 136f4619c7fSThierry Reding .bit_offset = 0, 137f4619c7fSThierry Reding .nbits = 32, 138f4619c7fSThierry Reding }, { 139f4619c7fSThierry Reding .name = "tsensor-mem0", 140f4619c7fSThierry Reding .offset = 0x158, 141f4619c7fSThierry Reding .bytes = 4, 142f4619c7fSThierry Reding .bit_offset = 0, 143f4619c7fSThierry Reding .nbits = 32, 144f4619c7fSThierry Reding }, { 145f4619c7fSThierry Reding .name = "tsensor-mem1", 146f4619c7fSThierry Reding .offset = 0x15c, 147f4619c7fSThierry Reding .bytes = 4, 148f4619c7fSThierry Reding .bit_offset = 0, 149f4619c7fSThierry Reding .nbits = 32, 150f4619c7fSThierry Reding }, { 151f4619c7fSThierry Reding .name = "tsensor-pllx", 152f4619c7fSThierry Reding .offset = 0x160, 153f4619c7fSThierry Reding .bytes = 4, 154f4619c7fSThierry Reding .bit_offset = 0, 155f4619c7fSThierry Reding .nbits = 32, 156f4619c7fSThierry Reding }, { 157f4619c7fSThierry Reding .name = "tsensor-common", 158f4619c7fSThierry Reding .offset = 0x180, 159f4619c7fSThierry Reding .bytes = 4, 160f4619c7fSThierry Reding .bit_offset = 0, 161f4619c7fSThierry Reding .nbits = 32, 162f4619c7fSThierry Reding }, { 163f4619c7fSThierry Reding .name = "tsensor-realignment", 164f4619c7fSThierry Reding .offset = 0x1fc, 165f4619c7fSThierry Reding .bytes = 4, 166f4619c7fSThierry Reding .bit_offset = 0, 167f4619c7fSThierry Reding .nbits = 32, 168f4619c7fSThierry Reding }, { 169f4619c7fSThierry Reding .name = "gpu-calibration", 170f4619c7fSThierry Reding .offset = 0x204, 171f4619c7fSThierry Reding .bytes = 4, 172f4619c7fSThierry Reding .bit_offset = 0, 173f4619c7fSThierry Reding .nbits = 32, 174f4619c7fSThierry Reding }, { 175f4619c7fSThierry Reding .name = "xusb-pad-calibration-ext", 176f4619c7fSThierry Reding .offset = 0x250, 177f4619c7fSThierry Reding .bytes = 4, 178f4619c7fSThierry Reding .bit_offset = 0, 179f4619c7fSThierry Reding .nbits = 32, 180f4619c7fSThierry Reding }, 181f4619c7fSThierry Reding }; 182f4619c7fSThierry Reding 1837e939de1SThierry Reding static int tegra_fuse_probe(struct platform_device *pdev) 1847e939de1SThierry Reding { 1857e939de1SThierry Reding void __iomem *base = fuse->base; 18696ee12b2SThierry Reding struct nvmem_config nvmem; 1877e939de1SThierry Reding struct resource *res; 1887e939de1SThierry Reding int err; 1897e939de1SThierry Reding 1907e939de1SThierry Reding /* take over the memory region from the early initialization */ 1917e939de1SThierry Reding res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 19255a042b3SDmitry Osipenko fuse->phys = res->start; 1937e939de1SThierry Reding fuse->base = devm_ioremap_resource(&pdev->dev, res); 19451294bf6STimo Alho if (IS_ERR(fuse->base)) { 19551294bf6STimo Alho err = PTR_ERR(fuse->base); 19651294bf6STimo Alho fuse->base = base; 19751294bf6STimo Alho return err; 19851294bf6STimo Alho } 1997e939de1SThierry Reding 2007e939de1SThierry Reding fuse->clk = devm_clk_get(&pdev->dev, "fuse"); 2017e939de1SThierry Reding if (IS_ERR(fuse->clk)) { 202f0b2835fSThierry Reding if (PTR_ERR(fuse->clk) != -EPROBE_DEFER) 2037e939de1SThierry Reding dev_err(&pdev->dev, "failed to get FUSE clock: %ld", 2047e939de1SThierry Reding PTR_ERR(fuse->clk)); 205f0b2835fSThierry Reding 20651294bf6STimo Alho fuse->base = base; 2077e939de1SThierry Reding return PTR_ERR(fuse->clk); 2087e939de1SThierry Reding } 2097e939de1SThierry Reding 2107e939de1SThierry Reding platform_set_drvdata(pdev, fuse); 2117e939de1SThierry Reding fuse->dev = &pdev->dev; 2127e939de1SThierry Reding 2137e939de1SThierry Reding if (fuse->soc->probe) { 2147e939de1SThierry Reding err = fuse->soc->probe(fuse); 2159f1022b8SThierry Reding if (err < 0) 2169f1022b8SThierry Reding goto restore; 21751294bf6STimo Alho } 2187e939de1SThierry Reding 21996ee12b2SThierry Reding memset(&nvmem, 0, sizeof(nvmem)); 22096ee12b2SThierry Reding nvmem.dev = &pdev->dev; 22196ee12b2SThierry Reding nvmem.name = "fuse"; 22296ee12b2SThierry Reding nvmem.id = -1; 22396ee12b2SThierry Reding nvmem.owner = THIS_MODULE; 224f4619c7fSThierry Reding nvmem.cells = tegra_fuse_cells; 225f4619c7fSThierry Reding nvmem.ncells = ARRAY_SIZE(tegra_fuse_cells); 22696ee12b2SThierry Reding nvmem.type = NVMEM_TYPE_OTP; 22796ee12b2SThierry Reding nvmem.read_only = true; 22896ee12b2SThierry Reding nvmem.root_only = true; 22996ee12b2SThierry Reding nvmem.reg_read = tegra_fuse_read; 23096ee12b2SThierry Reding nvmem.size = fuse->soc->info->size; 23196ee12b2SThierry Reding nvmem.word_size = 4; 23296ee12b2SThierry Reding nvmem.stride = 4; 23396ee12b2SThierry Reding nvmem.priv = fuse; 23496ee12b2SThierry Reding 23596ee12b2SThierry Reding fuse->nvmem = devm_nvmem_register(&pdev->dev, &nvmem); 23696ee12b2SThierry Reding if (IS_ERR(fuse->nvmem)) { 23796ee12b2SThierry Reding err = PTR_ERR(fuse->nvmem); 23896ee12b2SThierry Reding dev_err(&pdev->dev, "failed to register NVMEM device: %d\n", 23996ee12b2SThierry Reding err); 2409f1022b8SThierry Reding goto restore; 2419f1022b8SThierry Reding } 2427e939de1SThierry Reding 2437e939de1SThierry Reding /* release the early I/O memory mapping */ 2447e939de1SThierry Reding iounmap(base); 2457e939de1SThierry Reding 2467e939de1SThierry Reding return 0; 2479f1022b8SThierry Reding 2489f1022b8SThierry Reding restore: 249*a65a4ea1SDmitry Osipenko fuse->clk = NULL; 2509f1022b8SThierry Reding fuse->base = base; 2519f1022b8SThierry Reding return err; 2527e939de1SThierry Reding } 2537e939de1SThierry Reding 2547e939de1SThierry Reding static struct platform_driver tegra_fuse_driver = { 2557e939de1SThierry Reding .driver = { 2567e939de1SThierry Reding .name = "tegra-fuse", 2577e939de1SThierry Reding .of_match_table = tegra_fuse_match, 2587e939de1SThierry Reding .suppress_bind_attrs = true, 2597e939de1SThierry Reding }, 2607e939de1SThierry Reding .probe = tegra_fuse_probe, 2617e939de1SThierry Reding }; 2621859217bSPaul Gortmaker builtin_platform_driver(tegra_fuse_driver); 2637e939de1SThierry Reding 2647e939de1SThierry Reding bool __init tegra_fuse_read_spare(unsigned int spare) 2657e939de1SThierry Reding { 2667e939de1SThierry Reding unsigned int offset = fuse->soc->info->spare + spare * 4; 2677e939de1SThierry Reding 2687e939de1SThierry Reding return fuse->read_early(fuse, offset) & 1; 2697e939de1SThierry Reding } 2707e939de1SThierry Reding 2717e939de1SThierry Reding u32 __init tegra_fuse_read_early(unsigned int offset) 2727e939de1SThierry Reding { 2737e939de1SThierry Reding return fuse->read_early(fuse, offset); 2747e939de1SThierry Reding } 2757e939de1SThierry Reding 2767e939de1SThierry Reding int tegra_fuse_readl(unsigned long offset, u32 *value) 2777e939de1SThierry Reding { 2780a728e0bSNagarjuna Kristam if (!fuse->read || !fuse->clk) 2797e939de1SThierry Reding return -EPROBE_DEFER; 2807e939de1SThierry Reding 2810a728e0bSNagarjuna Kristam if (IS_ERR(fuse->clk)) 2820a728e0bSNagarjuna Kristam return PTR_ERR(fuse->clk); 2830a728e0bSNagarjuna Kristam 2847e939de1SThierry Reding *value = fuse->read(fuse, offset); 2857e939de1SThierry Reding 2867e939de1SThierry Reding return 0; 2877e939de1SThierry Reding } 2887e939de1SThierry Reding EXPORT_SYMBOL(tegra_fuse_readl); 2897e939de1SThierry Reding 290783c8f4cSPeter De Schrijver static void tegra_enable_fuse_clk(void __iomem *base) 291783c8f4cSPeter De Schrijver { 292783c8f4cSPeter De Schrijver u32 reg; 293783c8f4cSPeter De Schrijver 294783c8f4cSPeter De Schrijver reg = readl_relaxed(base + 0x48); 295783c8f4cSPeter De Schrijver reg |= 1 << 28; 296783c8f4cSPeter De Schrijver writel(reg, base + 0x48); 297783c8f4cSPeter De Schrijver 298783c8f4cSPeter De Schrijver /* 299783c8f4cSPeter De Schrijver * Enable FUSE clock. This needs to be hardcoded because the clock 300783c8f4cSPeter De Schrijver * subsystem is not active during early boot. 301783c8f4cSPeter De Schrijver */ 302783c8f4cSPeter De Schrijver reg = readl(base + 0x14); 303783c8f4cSPeter De Schrijver reg |= 1 << 7; 304783c8f4cSPeter De Schrijver writel(reg, base + 0x14); 305783c8f4cSPeter De Schrijver } 306783c8f4cSPeter De Schrijver 307379ac9ebSJon Hunter static ssize_t major_show(struct device *dev, struct device_attribute *attr, 308379ac9ebSJon Hunter char *buf) 309379ac9ebSJon Hunter { 310379ac9ebSJon Hunter return sprintf(buf, "%d\n", tegra_get_major_rev()); 311379ac9ebSJon Hunter } 312379ac9ebSJon Hunter 313379ac9ebSJon Hunter static DEVICE_ATTR_RO(major); 314379ac9ebSJon Hunter 315379ac9ebSJon Hunter static ssize_t minor_show(struct device *dev, struct device_attribute *attr, 316379ac9ebSJon Hunter char *buf) 317379ac9ebSJon Hunter { 318379ac9ebSJon Hunter return sprintf(buf, "%d\n", tegra_get_minor_rev()); 319379ac9ebSJon Hunter } 320379ac9ebSJon Hunter 321379ac9ebSJon Hunter static DEVICE_ATTR_RO(minor); 322379ac9ebSJon Hunter 323379ac9ebSJon Hunter static struct attribute *tegra_soc_attr[] = { 324379ac9ebSJon Hunter &dev_attr_major.attr, 325379ac9ebSJon Hunter &dev_attr_minor.attr, 326379ac9ebSJon Hunter NULL, 327379ac9ebSJon Hunter }; 328379ac9ebSJon Hunter 329379ac9ebSJon Hunter const struct attribute_group tegra_soc_attr_group = { 330379ac9ebSJon Hunter .attrs = tegra_soc_attr, 331379ac9ebSJon Hunter }; 332379ac9ebSJon Hunter 3331f44febfSThierry Reding #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \ 3341f44febfSThierry Reding IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) 335379ac9ebSJon Hunter static ssize_t platform_show(struct device *dev, struct device_attribute *attr, 336379ac9ebSJon Hunter char *buf) 337379ac9ebSJon Hunter { 338379ac9ebSJon Hunter /* 339379ac9ebSJon Hunter * Displays the value in the 'pre_si_platform' field of the HIDREV 340379ac9ebSJon Hunter * register for Tegra194 devices. A value of 0 indicates that the 341379ac9ebSJon Hunter * platform type is silicon and all other non-zero values indicate 342379ac9ebSJon Hunter * the type of simulation platform is being used. 343379ac9ebSJon Hunter */ 344775edf78SThierry Reding return sprintf(buf, "%d\n", tegra_get_platform()); 345379ac9ebSJon Hunter } 346379ac9ebSJon Hunter 347379ac9ebSJon Hunter static DEVICE_ATTR_RO(platform); 348379ac9ebSJon Hunter 349379ac9ebSJon Hunter static struct attribute *tegra194_soc_attr[] = { 350379ac9ebSJon Hunter &dev_attr_major.attr, 351379ac9ebSJon Hunter &dev_attr_minor.attr, 352379ac9ebSJon Hunter &dev_attr_platform.attr, 353379ac9ebSJon Hunter NULL, 354379ac9ebSJon Hunter }; 355379ac9ebSJon Hunter 356379ac9ebSJon Hunter const struct attribute_group tegra194_soc_attr_group = { 357379ac9ebSJon Hunter .attrs = tegra194_soc_attr, 358379ac9ebSJon Hunter }; 359379ac9ebSJon Hunter #endif 360379ac9ebSJon Hunter 36127a0342aSThierry Reding struct device * __init tegra_soc_device_register(void) 36227a0342aSThierry Reding { 36327a0342aSThierry Reding struct soc_device_attribute *attr; 36427a0342aSThierry Reding struct soc_device *dev; 36527a0342aSThierry Reding 36627a0342aSThierry Reding attr = kzalloc(sizeof(*attr), GFP_KERNEL); 36727a0342aSThierry Reding if (!attr) 36827a0342aSThierry Reding return NULL; 36927a0342aSThierry Reding 37027a0342aSThierry Reding attr->family = kasprintf(GFP_KERNEL, "Tegra"); 37137558ac8SJon Hunter attr->revision = kasprintf(GFP_KERNEL, "%s", 37237558ac8SJon Hunter tegra_revision_name[tegra_sku_info.revision]); 37327a0342aSThierry Reding attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id()); 374379ac9ebSJon Hunter attr->custom_attr_group = fuse->soc->soc_attr_group; 37527a0342aSThierry Reding 37627a0342aSThierry Reding dev = soc_device_register(attr); 37727a0342aSThierry Reding if (IS_ERR(dev)) { 37827a0342aSThierry Reding kfree(attr->soc_id); 37927a0342aSThierry Reding kfree(attr->revision); 38027a0342aSThierry Reding kfree(attr->family); 38127a0342aSThierry Reding kfree(attr); 38227a0342aSThierry Reding return ERR_CAST(dev); 38327a0342aSThierry Reding } 38427a0342aSThierry Reding 38527a0342aSThierry Reding return soc_device_to_device(dev); 38627a0342aSThierry Reding } 38727a0342aSThierry Reding 38824fa5af8SThierry Reding static int __init tegra_init_fuse(void) 389783c8f4cSPeter De Schrijver { 3907e939de1SThierry Reding const struct of_device_id *match; 391783c8f4cSPeter De Schrijver struct device_node *np; 3927e939de1SThierry Reding struct resource regs; 39324fa5af8SThierry Reding 394783c8f4cSPeter De Schrijver tegra_init_apbmisc(); 395783c8f4cSPeter De Schrijver 3967e939de1SThierry Reding np = of_find_matching_node_and_match(NULL, tegra_fuse_match, &match); 3977e939de1SThierry Reding if (!np) { 3987e939de1SThierry Reding /* 3997e939de1SThierry Reding * Fall back to legacy initialization for 32-bit ARM only. All 4007e939de1SThierry Reding * 64-bit ARM device tree files for Tegra are required to have 4017e939de1SThierry Reding * a FUSE node. 4027e939de1SThierry Reding * 4037e939de1SThierry Reding * This is for backwards-compatibility with old device trees 4047e939de1SThierry Reding * that didn't contain a FUSE node. 4057e939de1SThierry Reding */ 4067e939de1SThierry Reding if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 4077e939de1SThierry Reding u8 chip = tegra_get_chip_id(); 4087e939de1SThierry Reding 4097e939de1SThierry Reding regs.start = 0x7000f800; 4107e939de1SThierry Reding regs.end = 0x7000fbff; 4117e939de1SThierry Reding regs.flags = IORESOURCE_MEM; 4127e939de1SThierry Reding 4137e939de1SThierry Reding switch (chip) { 4147e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_2x_SOC 4157e939de1SThierry Reding case TEGRA20: 4167e939de1SThierry Reding fuse->soc = &tegra20_fuse_soc; 4177e939de1SThierry Reding break; 4187e939de1SThierry Reding #endif 4197e939de1SThierry Reding 4207e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_3x_SOC 4217e939de1SThierry Reding case TEGRA30: 4227e939de1SThierry Reding fuse->soc = &tegra30_fuse_soc; 4237e939de1SThierry Reding break; 4247e939de1SThierry Reding #endif 4257e939de1SThierry Reding 4267e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_114_SOC 4277e939de1SThierry Reding case TEGRA114: 4287e939de1SThierry Reding fuse->soc = &tegra114_fuse_soc; 4297e939de1SThierry Reding break; 4307e939de1SThierry Reding #endif 4317e939de1SThierry Reding 4327e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_124_SOC 4337e939de1SThierry Reding case TEGRA124: 4347e939de1SThierry Reding fuse->soc = &tegra124_fuse_soc; 4357e939de1SThierry Reding break; 4367e939de1SThierry Reding #endif 4377e939de1SThierry Reding 4387e939de1SThierry Reding default: 4397e939de1SThierry Reding pr_warn("Unsupported SoC: %02x\n", chip); 4407e939de1SThierry Reding break; 4417e939de1SThierry Reding } 442783c8f4cSPeter De Schrijver } else { 4437e939de1SThierry Reding /* 4447e939de1SThierry Reding * At this point we're not running on Tegra, so play 4457e939de1SThierry Reding * nice with multi-platform kernels. 4467e939de1SThierry Reding */ 4477e939de1SThierry Reding return 0; 4487e939de1SThierry Reding } 4497e939de1SThierry Reding } else { 4507e939de1SThierry Reding /* 4517e939de1SThierry Reding * Extract information from the device tree if we've found a 4527e939de1SThierry Reding * matching node. 4537e939de1SThierry Reding */ 4547e939de1SThierry Reding if (of_address_to_resource(np, 0, ®s) < 0) { 4557e939de1SThierry Reding pr_err("failed to get FUSE register\n"); 45624fa5af8SThierry Reding return -ENXIO; 457783c8f4cSPeter De Schrijver } 458783c8f4cSPeter De Schrijver 4597e939de1SThierry Reding fuse->soc = match->data; 4607e939de1SThierry Reding } 4617e939de1SThierry Reding 4627e939de1SThierry Reding np = of_find_matching_node(NULL, car_match); 4637e939de1SThierry Reding if (np) { 4647e939de1SThierry Reding void __iomem *base = of_iomap(np, 0); 4657e939de1SThierry Reding if (base) { 4667e939de1SThierry Reding tegra_enable_fuse_clk(base); 4677e939de1SThierry Reding iounmap(base); 4687e939de1SThierry Reding } else { 4697e939de1SThierry Reding pr_err("failed to map clock registers\n"); 4707e939de1SThierry Reding return -ENXIO; 4717e939de1SThierry Reding } 4727e939de1SThierry Reding } 4737e939de1SThierry Reding 4744bdc0d67SChristoph Hellwig fuse->base = ioremap(regs.start, resource_size(®s)); 4757e939de1SThierry Reding if (!fuse->base) { 4767e939de1SThierry Reding pr_err("failed to map FUSE registers\n"); 4777e939de1SThierry Reding return -ENXIO; 4787e939de1SThierry Reding } 4797e939de1SThierry Reding 4807e939de1SThierry Reding fuse->soc->init(fuse); 481783c8f4cSPeter De Schrijver 48203b3f4c8SThierry Reding pr_info("Tegra Revision: %s SKU: %d CPU Process: %d SoC Process: %d\n", 483783c8f4cSPeter De Schrijver tegra_revision_name[tegra_sku_info.revision], 484783c8f4cSPeter De Schrijver tegra_sku_info.sku_id, tegra_sku_info.cpu_process_id, 48503b3f4c8SThierry Reding tegra_sku_info.soc_process_id); 48603b3f4c8SThierry Reding pr_debug("Tegra CPU Speedo ID %d, SoC Speedo ID %d\n", 487783c8f4cSPeter De Schrijver tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id); 48824fa5af8SThierry Reding 4899f94faddSThierry Reding if (fuse->soc->lookups) { 4909f94faddSThierry Reding size_t size = sizeof(*fuse->lookups) * fuse->soc->num_lookups; 4919f94faddSThierry Reding 4929f94faddSThierry Reding fuse->lookups = kmemdup(fuse->soc->lookups, size, GFP_KERNEL); 493854d128bSYang Yingliang if (fuse->lookups) 4949f94faddSThierry Reding nvmem_add_cell_lookups(fuse->lookups, fuse->soc->num_lookups); 4959f94faddSThierry Reding } 49627a0342aSThierry Reding 49724fa5af8SThierry Reding return 0; 498783c8f4cSPeter De Schrijver } 49924fa5af8SThierry Reding early_initcall(tegra_init_fuse); 50027a0342aSThierry Reding 50127a0342aSThierry Reding #ifdef CONFIG_ARM64 50227a0342aSThierry Reding static int __init tegra_init_soc(void) 50327a0342aSThierry Reding { 504226cff48SThierry Reding struct device_node *np; 50527a0342aSThierry Reding struct device *soc; 50627a0342aSThierry Reding 507226cff48SThierry Reding /* make sure we're running on Tegra */ 508226cff48SThierry Reding np = of_find_matching_node(NULL, tegra_fuse_match); 509226cff48SThierry Reding if (!np) 510226cff48SThierry Reding return 0; 511226cff48SThierry Reding 512226cff48SThierry Reding of_node_put(np); 513226cff48SThierry Reding 51427a0342aSThierry Reding soc = tegra_soc_device_register(); 51527a0342aSThierry Reding if (IS_ERR(soc)) { 51627a0342aSThierry Reding pr_err("failed to register SoC device: %ld\n", PTR_ERR(soc)); 51727a0342aSThierry Reding return PTR_ERR(soc); 51827a0342aSThierry Reding } 51927a0342aSThierry Reding 52027a0342aSThierry Reding return 0; 52127a0342aSThierry Reding } 5229261b43eSThierry Reding device_initcall(tegra_init_soc); 52327a0342aSThierry Reding #endif 524