19952f691SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2783c8f4cSPeter De Schrijver /* 3821d96e3SKartik * Copyright (c) 2013-2023, NVIDIA CORPORATION. All rights reserved. 4783c8f4cSPeter De Schrijver */ 5783c8f4cSPeter De Schrijver 6*972167c6SKartik #include <linux/acpi.h> 77e939de1SThierry Reding #include <linux/clk.h> 8783c8f4cSPeter De Schrijver #include <linux/device.h> 9783c8f4cSPeter De Schrijver #include <linux/kobject.h> 101859217bSPaul Gortmaker #include <linux/init.h> 1127a0342aSThierry Reding #include <linux/io.h> 12*972167c6SKartik #include <linux/mod_devicetable.h> 1396ee12b2SThierry Reding #include <linux/nvmem-consumer.h> 1496ee12b2SThierry Reding #include <linux/nvmem-provider.h> 15783c8f4cSPeter De Schrijver #include <linux/of.h> 16783c8f4cSPeter De Schrijver #include <linux/of_address.h> 1727a0342aSThierry Reding #include <linux/platform_device.h> 1824a15252SDmitry Osipenko #include <linux/pm_runtime.h> 19aeecc50aSDmitry Osipenko #include <linux/reset.h> 2027a0342aSThierry Reding #include <linux/slab.h> 2127a0342aSThierry Reding #include <linux/sys_soc.h> 22783c8f4cSPeter De Schrijver 2324fa5af8SThierry Reding #include <soc/tegra/common.h> 24783c8f4cSPeter De Schrijver #include <soc/tegra/fuse.h> 25783c8f4cSPeter De Schrijver 26783c8f4cSPeter De Schrijver #include "fuse.h" 27783c8f4cSPeter De Schrijver 28783c8f4cSPeter De Schrijver struct tegra_sku_info tegra_sku_info; 29f9fc3661SVince Hsu EXPORT_SYMBOL(tegra_sku_info); 30783c8f4cSPeter De Schrijver 31783c8f4cSPeter De Schrijver static const char *tegra_revision_name[TEGRA_REVISION_MAX] = { 32783c8f4cSPeter De Schrijver [TEGRA_REVISION_UNKNOWN] = "unknown", 33783c8f4cSPeter De Schrijver [TEGRA_REVISION_A01] = "A01", 34783c8f4cSPeter De Schrijver [TEGRA_REVISION_A02] = "A02", 35783c8f4cSPeter De Schrijver [TEGRA_REVISION_A03] = "A03", 36783c8f4cSPeter De Schrijver [TEGRA_REVISION_A03p] = "A03 prime", 37783c8f4cSPeter De Schrijver [TEGRA_REVISION_A04] = "A04", 38783c8f4cSPeter De Schrijver }; 39783c8f4cSPeter De Schrijver 40bebf683bSKartik static const char *tegra_platform_name[TEGRA_PLATFORM_MAX] = { 41bebf683bSKartik [TEGRA_PLATFORM_SILICON] = "Silicon", 42bebf683bSKartik [TEGRA_PLATFORM_QT] = "QT", 43bebf683bSKartik [TEGRA_PLATFORM_SYSTEM_FPGA] = "System FPGA", 44bebf683bSKartik [TEGRA_PLATFORM_UNIT_FPGA] = "Unit FPGA", 45bebf683bSKartik [TEGRA_PLATFORM_ASIM_QT] = "Asim QT", 46bebf683bSKartik [TEGRA_PLATFORM_ASIM_LINSIM] = "Asim Linsim", 47bebf683bSKartik [TEGRA_PLATFORM_DSIM_ASIM_LINSIM] = "Dsim Asim Linsim", 48bebf683bSKartik [TEGRA_PLATFORM_VERIFICATION_SIMULATION] = "Verification Simulation", 49bebf683bSKartik [TEGRA_PLATFORM_VDK] = "VDK", 50bebf683bSKartik [TEGRA_PLATFORM_VSP] = "VSP", 51bebf683bSKartik }; 52bebf683bSKartik 53783c8f4cSPeter De Schrijver static const struct of_device_id car_match[] __initconst = { 54783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra20-car", }, 55783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra30-car", }, 56783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra114-car", }, 57783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra124-car", }, 589b07eb05SThierry Reding { .compatible = "nvidia,tegra132-car", }, 590dc5a0d8SThierry Reding { .compatible = "nvidia,tegra210-car", }, 60783c8f4cSPeter De Schrijver {}, 61783c8f4cSPeter De Schrijver }; 62783c8f4cSPeter De Schrijver 637e939de1SThierry Reding static struct tegra_fuse *fuse = &(struct tegra_fuse) { 647e939de1SThierry Reding .base = NULL, 657e939de1SThierry Reding .soc = NULL, 667e939de1SThierry Reding }; 677e939de1SThierry Reding 687e939de1SThierry Reding static const struct of_device_id tegra_fuse_match[] = { 691f44febfSThierry Reding #ifdef CONFIG_ARCH_TEGRA_234_SOC 701f44febfSThierry Reding { .compatible = "nvidia,tegra234-efuse", .data = &tegra234_fuse_soc }, 711f44febfSThierry Reding #endif 723979a4c6SJC Kuo #ifdef CONFIG_ARCH_TEGRA_194_SOC 733979a4c6SJC Kuo { .compatible = "nvidia,tegra194-efuse", .data = &tegra194_fuse_soc }, 743979a4c6SJC Kuo #endif 7583468fe2STimo Alho #ifdef CONFIG_ARCH_TEGRA_186_SOC 7683468fe2STimo Alho { .compatible = "nvidia,tegra186-efuse", .data = &tegra186_fuse_soc }, 7783468fe2STimo Alho #endif 780dc5a0d8SThierry Reding #ifdef CONFIG_ARCH_TEGRA_210_SOC 790dc5a0d8SThierry Reding { .compatible = "nvidia,tegra210-efuse", .data = &tegra210_fuse_soc }, 800dc5a0d8SThierry Reding #endif 817e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_132_SOC 827e939de1SThierry Reding { .compatible = "nvidia,tegra132-efuse", .data = &tegra124_fuse_soc }, 837e939de1SThierry Reding #endif 847e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_124_SOC 857e939de1SThierry Reding { .compatible = "nvidia,tegra124-efuse", .data = &tegra124_fuse_soc }, 867e939de1SThierry Reding #endif 877e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_114_SOC 887e939de1SThierry Reding { .compatible = "nvidia,tegra114-efuse", .data = &tegra114_fuse_soc }, 897e939de1SThierry Reding #endif 907e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_3x_SOC 917e939de1SThierry Reding { .compatible = "nvidia,tegra30-efuse", .data = &tegra30_fuse_soc }, 927e939de1SThierry Reding #endif 937e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_2x_SOC 947e939de1SThierry Reding { .compatible = "nvidia,tegra20-efuse", .data = &tegra20_fuse_soc }, 957e939de1SThierry Reding #endif 967e939de1SThierry Reding { /* sentinel */ } 977e939de1SThierry Reding }; 987e939de1SThierry Reding 9996ee12b2SThierry Reding static int tegra_fuse_read(void *priv, unsigned int offset, void *value, 10096ee12b2SThierry Reding size_t bytes) 10196ee12b2SThierry Reding { 10296ee12b2SThierry Reding unsigned int count = bytes / 4, i; 10396ee12b2SThierry Reding struct tegra_fuse *fuse = priv; 10496ee12b2SThierry Reding u32 *buffer = value; 10596ee12b2SThierry Reding 10696ee12b2SThierry Reding for (i = 0; i < count; i++) 10796ee12b2SThierry Reding buffer[i] = fuse->read(fuse, offset + i * 4); 10896ee12b2SThierry Reding 10996ee12b2SThierry Reding return 0; 11096ee12b2SThierry Reding } 11196ee12b2SThierry Reding 11288724b78SDmitry Osipenko static void tegra_fuse_restore(void *base) 11388724b78SDmitry Osipenko { 114b631c9c2SThierry Reding fuse->base = (void __iomem *)base; 11588724b78SDmitry Osipenko fuse->clk = NULL; 11688724b78SDmitry Osipenko } 11788724b78SDmitry Osipenko 11813a69354SKartik static void tegra_fuse_print_sku_info(struct tegra_sku_info *tegra_sku_info) 11913a69354SKartik { 12013a69354SKartik pr_info("Tegra Revision: %s SKU: %d CPU Process: %d SoC Process: %d\n", 12113a69354SKartik tegra_revision_name[tegra_sku_info->revision], 12213a69354SKartik tegra_sku_info->sku_id, tegra_sku_info->cpu_process_id, 12313a69354SKartik tegra_sku_info->soc_process_id); 12413a69354SKartik pr_debug("Tegra CPU Speedo ID %d, SoC Speedo ID %d\n", 12513a69354SKartik tegra_sku_info->cpu_speedo_id, tegra_sku_info->soc_speedo_id); 12613a69354SKartik } 12713a69354SKartik 12871661c1cSKartik static int tegra_fuse_add_lookups(struct tegra_fuse *fuse) 12971661c1cSKartik { 13071661c1cSKartik fuse->lookups = kmemdup_array(fuse->soc->lookups, sizeof(*fuse->lookups), 13171661c1cSKartik fuse->soc->num_lookups, GFP_KERNEL); 13271661c1cSKartik if (!fuse->lookups) 13371661c1cSKartik return -ENOMEM; 13471661c1cSKartik 13571661c1cSKartik nvmem_add_cell_lookups(fuse->lookups, fuse->soc->num_lookups); 13671661c1cSKartik 13771661c1cSKartik return 0; 13871661c1cSKartik } 13971661c1cSKartik 1407e939de1SThierry Reding static int tegra_fuse_probe(struct platform_device *pdev) 1417e939de1SThierry Reding { 1427e939de1SThierry Reding void __iomem *base = fuse->base; 14396ee12b2SThierry Reding struct nvmem_config nvmem; 1447e939de1SThierry Reding struct resource *res; 1457e939de1SThierry Reding int err; 1467e939de1SThierry Reding 147b631c9c2SThierry Reding err = devm_add_action(&pdev->dev, tegra_fuse_restore, (void __force *)base); 14888724b78SDmitry Osipenko if (err) 14988724b78SDmitry Osipenko return err; 15088724b78SDmitry Osipenko 1517e939de1SThierry Reding /* take over the memory region from the early initialization */ 1526674c980SYangtao Li fuse->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1536674c980SYangtao Li if (IS_ERR(fuse->base)) 1546674c980SYangtao Li return PTR_ERR(fuse->base); 15555a042b3SDmitry Osipenko fuse->phys = res->start; 1567e939de1SThierry Reding 157*972167c6SKartik /* Initialize the soc data and lookups if using ACPI boot. */ 158*972167c6SKartik if (is_acpi_node(dev_fwnode(&pdev->dev)) && !fuse->soc) { 159*972167c6SKartik u8 chip; 160*972167c6SKartik 161*972167c6SKartik tegra_acpi_init_apbmisc(); 162*972167c6SKartik 163*972167c6SKartik chip = tegra_get_chip_id(); 164*972167c6SKartik switch (chip) { 165*972167c6SKartik #if defined(CONFIG_ARCH_TEGRA_194_SOC) 166*972167c6SKartik case TEGRA194: 167*972167c6SKartik fuse->soc = &tegra194_fuse_soc; 168*972167c6SKartik break; 169*972167c6SKartik #endif 170*972167c6SKartik #if defined(CONFIG_ARCH_TEGRA_234_SOC) 171*972167c6SKartik case TEGRA234: 172*972167c6SKartik fuse->soc = &tegra234_fuse_soc; 173*972167c6SKartik break; 174*972167c6SKartik #endif 175*972167c6SKartik default: 176*972167c6SKartik return dev_err_probe(&pdev->dev, -EINVAL, "Unsupported SoC: %02x\n", chip); 177*972167c6SKartik } 178*972167c6SKartik 179*972167c6SKartik fuse->soc->init(fuse); 180*972167c6SKartik tegra_fuse_print_sku_info(&tegra_sku_info); 181*972167c6SKartik tegra_soc_device_register(); 182*972167c6SKartik 183*972167c6SKartik err = tegra_fuse_add_lookups(fuse); 184*972167c6SKartik if (err) 185*972167c6SKartik return dev_err_probe(&pdev->dev, err, "failed to add FUSE lookups\n"); 186*972167c6SKartik } 187*972167c6SKartik 188*972167c6SKartik fuse->clk = devm_clk_get_optional(&pdev->dev, "fuse"); 1894569e604SKartik if (IS_ERR(fuse->clk)) 1904569e604SKartik return dev_err_probe(&pdev->dev, PTR_ERR(fuse->clk), "failed to get FUSE clock\n"); 1917e939de1SThierry Reding 1927e939de1SThierry Reding platform_set_drvdata(pdev, fuse); 1937e939de1SThierry Reding fuse->dev = &pdev->dev; 1947e939de1SThierry Reding 19588724b78SDmitry Osipenko err = devm_pm_runtime_enable(&pdev->dev); 19688724b78SDmitry Osipenko if (err) 19788724b78SDmitry Osipenko return err; 19824a15252SDmitry Osipenko 1997e939de1SThierry Reding if (fuse->soc->probe) { 2007e939de1SThierry Reding err = fuse->soc->probe(fuse); 2019f1022b8SThierry Reding if (err < 0) 20288724b78SDmitry Osipenko return err; 20351294bf6STimo Alho } 2047e939de1SThierry Reding 20596ee12b2SThierry Reding memset(&nvmem, 0, sizeof(nvmem)); 20696ee12b2SThierry Reding nvmem.dev = &pdev->dev; 20796ee12b2SThierry Reding nvmem.name = "fuse"; 20896ee12b2SThierry Reding nvmem.id = -1; 20996ee12b2SThierry Reding nvmem.owner = THIS_MODULE; 210bea06d77SKartik nvmem.cells = fuse->soc->cells; 211bea06d77SKartik nvmem.ncells = fuse->soc->num_cells; 212cc5b2ad5SKartik nvmem.keepout = fuse->soc->keepouts; 213cc5b2ad5SKartik nvmem.nkeepout = fuse->soc->num_keepouts; 21496ee12b2SThierry Reding nvmem.type = NVMEM_TYPE_OTP; 21596ee12b2SThierry Reding nvmem.read_only = true; 216821d96e3SKartik nvmem.root_only = false; 21796ee12b2SThierry Reding nvmem.reg_read = tegra_fuse_read; 21896ee12b2SThierry Reding nvmem.size = fuse->soc->info->size; 21996ee12b2SThierry Reding nvmem.word_size = 4; 22096ee12b2SThierry Reding nvmem.stride = 4; 22196ee12b2SThierry Reding nvmem.priv = fuse; 22296ee12b2SThierry Reding 22396ee12b2SThierry Reding fuse->nvmem = devm_nvmem_register(&pdev->dev, &nvmem); 22496ee12b2SThierry Reding if (IS_ERR(fuse->nvmem)) { 22596ee12b2SThierry Reding err = PTR_ERR(fuse->nvmem); 22696ee12b2SThierry Reding dev_err(&pdev->dev, "failed to register NVMEM device: %d\n", 22796ee12b2SThierry Reding err); 22888724b78SDmitry Osipenko return err; 2299f1022b8SThierry Reding } 2307e939de1SThierry Reding 231aeecc50aSDmitry Osipenko fuse->rst = devm_reset_control_get_optional(&pdev->dev, "fuse"); 2324569e604SKartik if (IS_ERR(fuse->rst)) 2334569e604SKartik return dev_err_probe(&pdev->dev, PTR_ERR(fuse->rst), "failed to get FUSE reset\n"); 234aeecc50aSDmitry Osipenko 235aeecc50aSDmitry Osipenko /* 236aeecc50aSDmitry Osipenko * FUSE clock is enabled at a boot time, hence this resume/suspend 237aeecc50aSDmitry Osipenko * disables the clock besides the h/w resetting. 238aeecc50aSDmitry Osipenko */ 239aeecc50aSDmitry Osipenko err = pm_runtime_resume_and_get(&pdev->dev); 240aeecc50aSDmitry Osipenko if (err) 24188724b78SDmitry Osipenko return err; 242aeecc50aSDmitry Osipenko 243aeecc50aSDmitry Osipenko err = reset_control_reset(fuse->rst); 244aeecc50aSDmitry Osipenko pm_runtime_put(&pdev->dev); 245aeecc50aSDmitry Osipenko 246aeecc50aSDmitry Osipenko if (err < 0) { 247aeecc50aSDmitry Osipenko dev_err(&pdev->dev, "failed to reset FUSE: %d\n", err); 24888724b78SDmitry Osipenko return err; 2497e939de1SThierry Reding } 2507e939de1SThierry Reding 2517e939de1SThierry Reding /* release the early I/O memory mapping */ 2527e939de1SThierry Reding iounmap(base); 2537e939de1SThierry Reding 2547e939de1SThierry Reding return 0; 2557e939de1SThierry Reding } 2567e939de1SThierry Reding 25724a15252SDmitry Osipenko static int __maybe_unused tegra_fuse_runtime_resume(struct device *dev) 25824a15252SDmitry Osipenko { 25924a15252SDmitry Osipenko int err; 26024a15252SDmitry Osipenko 26124a15252SDmitry Osipenko err = clk_prepare_enable(fuse->clk); 26224a15252SDmitry Osipenko if (err < 0) { 26324a15252SDmitry Osipenko dev_err(dev, "failed to enable FUSE clock: %d\n", err); 26424a15252SDmitry Osipenko return err; 26524a15252SDmitry Osipenko } 26624a15252SDmitry Osipenko 26724a15252SDmitry Osipenko return 0; 26824a15252SDmitry Osipenko } 26924a15252SDmitry Osipenko 27024a15252SDmitry Osipenko static int __maybe_unused tegra_fuse_runtime_suspend(struct device *dev) 27124a15252SDmitry Osipenko { 27224a15252SDmitry Osipenko clk_disable_unprepare(fuse->clk); 27324a15252SDmitry Osipenko 27424a15252SDmitry Osipenko return 0; 27524a15252SDmitry Osipenko } 27624a15252SDmitry Osipenko 27759c6fcebSDmitry Osipenko static int __maybe_unused tegra_fuse_suspend(struct device *dev) 27859c6fcebSDmitry Osipenko { 27959c6fcebSDmitry Osipenko int ret; 28059c6fcebSDmitry Osipenko 28159c6fcebSDmitry Osipenko /* 28259c6fcebSDmitry Osipenko * Critical for RAM re-repair operation, which must occur on resume 28359c6fcebSDmitry Osipenko * from LP1 system suspend and as part of CCPLEX cluster switching. 28459c6fcebSDmitry Osipenko */ 28559c6fcebSDmitry Osipenko if (fuse->soc->clk_suspend_on) 28659c6fcebSDmitry Osipenko ret = pm_runtime_resume_and_get(dev); 28759c6fcebSDmitry Osipenko else 28859c6fcebSDmitry Osipenko ret = pm_runtime_force_suspend(dev); 28959c6fcebSDmitry Osipenko 29059c6fcebSDmitry Osipenko return ret; 29159c6fcebSDmitry Osipenko } 29259c6fcebSDmitry Osipenko 29359c6fcebSDmitry Osipenko static int __maybe_unused tegra_fuse_resume(struct device *dev) 29459c6fcebSDmitry Osipenko { 29559c6fcebSDmitry Osipenko int ret = 0; 29659c6fcebSDmitry Osipenko 29759c6fcebSDmitry Osipenko if (fuse->soc->clk_suspend_on) 29859c6fcebSDmitry Osipenko pm_runtime_put(dev); 29959c6fcebSDmitry Osipenko else 30059c6fcebSDmitry Osipenko ret = pm_runtime_force_resume(dev); 30159c6fcebSDmitry Osipenko 30259c6fcebSDmitry Osipenko return ret; 30359c6fcebSDmitry Osipenko } 30459c6fcebSDmitry Osipenko 30524a15252SDmitry Osipenko static const struct dev_pm_ops tegra_fuse_pm = { 30624a15252SDmitry Osipenko SET_RUNTIME_PM_OPS(tegra_fuse_runtime_suspend, tegra_fuse_runtime_resume, 30724a15252SDmitry Osipenko NULL) 30859c6fcebSDmitry Osipenko SET_SYSTEM_SLEEP_PM_OPS(tegra_fuse_suspend, tegra_fuse_resume) 30924a15252SDmitry Osipenko }; 31024a15252SDmitry Osipenko 311*972167c6SKartik static const struct acpi_device_id tegra_fuse_acpi_match[] = { 312*972167c6SKartik { "NVDA200F" }, 313*972167c6SKartik { /* sentinel */ } 314*972167c6SKartik }; 315*972167c6SKartik MODULE_DEVICE_TABLE(acpi, tegra_fuse_acpi_match); 316*972167c6SKartik 3177e939de1SThierry Reding static struct platform_driver tegra_fuse_driver = { 3187e939de1SThierry Reding .driver = { 3197e939de1SThierry Reding .name = "tegra-fuse", 3207e939de1SThierry Reding .of_match_table = tegra_fuse_match, 321*972167c6SKartik .acpi_match_table = tegra_fuse_acpi_match, 32224a15252SDmitry Osipenko .pm = &tegra_fuse_pm, 3237e939de1SThierry Reding .suppress_bind_attrs = true, 3247e939de1SThierry Reding }, 3257e939de1SThierry Reding .probe = tegra_fuse_probe, 3267e939de1SThierry Reding }; 3271859217bSPaul Gortmaker builtin_platform_driver(tegra_fuse_driver); 3287e939de1SThierry Reding 329a7083763SNathan Chancellor u32 __init tegra_fuse_read_spare(unsigned int spare) 3307e939de1SThierry Reding { 3317e939de1SThierry Reding unsigned int offset = fuse->soc->info->spare + spare * 4; 3327e939de1SThierry Reding 3337e939de1SThierry Reding return fuse->read_early(fuse, offset) & 1; 3347e939de1SThierry Reding } 3357e939de1SThierry Reding 3367e939de1SThierry Reding u32 __init tegra_fuse_read_early(unsigned int offset) 3377e939de1SThierry Reding { 3387e939de1SThierry Reding return fuse->read_early(fuse, offset); 3397e939de1SThierry Reding } 3407e939de1SThierry Reding 3417e939de1SThierry Reding int tegra_fuse_readl(unsigned long offset, u32 *value) 3427e939de1SThierry Reding { 343*972167c6SKartik /* 344*972167c6SKartik * Wait for fuse->clk to be initialized if device-tree boot is used. 345*972167c6SKartik */ 346*972167c6SKartik if (is_of_node(dev_fwnode(fuse->dev)) && !fuse->clk) 347*972167c6SKartik return -EPROBE_DEFER; 348*972167c6SKartik 349*972167c6SKartik if (!fuse->read) 3507e939de1SThierry Reding return -EPROBE_DEFER; 3517e939de1SThierry Reding 3520a728e0bSNagarjuna Kristam if (IS_ERR(fuse->clk)) 3530a728e0bSNagarjuna Kristam return PTR_ERR(fuse->clk); 3540a728e0bSNagarjuna Kristam 3557e939de1SThierry Reding *value = fuse->read(fuse, offset); 3567e939de1SThierry Reding 3577e939de1SThierry Reding return 0; 3587e939de1SThierry Reding } 3597e939de1SThierry Reding EXPORT_SYMBOL(tegra_fuse_readl); 3607e939de1SThierry Reding 361783c8f4cSPeter De Schrijver static void tegra_enable_fuse_clk(void __iomem *base) 362783c8f4cSPeter De Schrijver { 363783c8f4cSPeter De Schrijver u32 reg; 364783c8f4cSPeter De Schrijver 365783c8f4cSPeter De Schrijver reg = readl_relaxed(base + 0x48); 366783c8f4cSPeter De Schrijver reg |= 1 << 28; 367783c8f4cSPeter De Schrijver writel(reg, base + 0x48); 368783c8f4cSPeter De Schrijver 369783c8f4cSPeter De Schrijver /* 370783c8f4cSPeter De Schrijver * Enable FUSE clock. This needs to be hardcoded because the clock 371783c8f4cSPeter De Schrijver * subsystem is not active during early boot. 372783c8f4cSPeter De Schrijver */ 373783c8f4cSPeter De Schrijver reg = readl(base + 0x14); 374783c8f4cSPeter De Schrijver reg |= 1 << 7; 375783c8f4cSPeter De Schrijver writel(reg, base + 0x14); 376783c8f4cSPeter De Schrijver } 377783c8f4cSPeter De Schrijver 378379ac9ebSJon Hunter static ssize_t major_show(struct device *dev, struct device_attribute *attr, 379379ac9ebSJon Hunter char *buf) 380379ac9ebSJon Hunter { 381379ac9ebSJon Hunter return sprintf(buf, "%d\n", tegra_get_major_rev()); 382379ac9ebSJon Hunter } 383379ac9ebSJon Hunter 384379ac9ebSJon Hunter static DEVICE_ATTR_RO(major); 385379ac9ebSJon Hunter 386379ac9ebSJon Hunter static ssize_t minor_show(struct device *dev, struct device_attribute *attr, 387379ac9ebSJon Hunter char *buf) 388379ac9ebSJon Hunter { 389379ac9ebSJon Hunter return sprintf(buf, "%d\n", tegra_get_minor_rev()); 390379ac9ebSJon Hunter } 391379ac9ebSJon Hunter 392379ac9ebSJon Hunter static DEVICE_ATTR_RO(minor); 393379ac9ebSJon Hunter 394379ac9ebSJon Hunter static struct attribute *tegra_soc_attr[] = { 395379ac9ebSJon Hunter &dev_attr_major.attr, 396379ac9ebSJon Hunter &dev_attr_minor.attr, 397379ac9ebSJon Hunter NULL, 398379ac9ebSJon Hunter }; 399379ac9ebSJon Hunter 400379ac9ebSJon Hunter const struct attribute_group tegra_soc_attr_group = { 401379ac9ebSJon Hunter .attrs = tegra_soc_attr, 402379ac9ebSJon Hunter }; 403379ac9ebSJon Hunter 4041f44febfSThierry Reding #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \ 4051f44febfSThierry Reding IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) 406379ac9ebSJon Hunter static ssize_t platform_show(struct device *dev, struct device_attribute *attr, 407379ac9ebSJon Hunter char *buf) 408379ac9ebSJon Hunter { 409379ac9ebSJon Hunter /* 410379ac9ebSJon Hunter * Displays the value in the 'pre_si_platform' field of the HIDREV 411379ac9ebSJon Hunter * register for Tegra194 devices. A value of 0 indicates that the 412379ac9ebSJon Hunter * platform type is silicon and all other non-zero values indicate 413379ac9ebSJon Hunter * the type of simulation platform is being used. 414379ac9ebSJon Hunter */ 415775edf78SThierry Reding return sprintf(buf, "%d\n", tegra_get_platform()); 416379ac9ebSJon Hunter } 417379ac9ebSJon Hunter 418379ac9ebSJon Hunter static DEVICE_ATTR_RO(platform); 419379ac9ebSJon Hunter 420379ac9ebSJon Hunter static struct attribute *tegra194_soc_attr[] = { 421379ac9ebSJon Hunter &dev_attr_major.attr, 422379ac9ebSJon Hunter &dev_attr_minor.attr, 423379ac9ebSJon Hunter &dev_attr_platform.attr, 424379ac9ebSJon Hunter NULL, 425379ac9ebSJon Hunter }; 426379ac9ebSJon Hunter 427379ac9ebSJon Hunter const struct attribute_group tegra194_soc_attr_group = { 428379ac9ebSJon Hunter .attrs = tegra194_soc_attr, 429379ac9ebSJon Hunter }; 430379ac9ebSJon Hunter #endif 431379ac9ebSJon Hunter 432*972167c6SKartik struct device *tegra_soc_device_register(void) 43327a0342aSThierry Reding { 43427a0342aSThierry Reding struct soc_device_attribute *attr; 43527a0342aSThierry Reding struct soc_device *dev; 43627a0342aSThierry Reding 43727a0342aSThierry Reding attr = kzalloc(sizeof(*attr), GFP_KERNEL); 43827a0342aSThierry Reding if (!attr) 43927a0342aSThierry Reding return NULL; 44027a0342aSThierry Reding 44127a0342aSThierry Reding attr->family = kasprintf(GFP_KERNEL, "Tegra"); 442bebf683bSKartik if (tegra_is_silicon()) 443bebf683bSKartik attr->revision = kasprintf(GFP_KERNEL, "%s %s", 444bebf683bSKartik tegra_platform_name[tegra_sku_info.platform], 44537558ac8SJon Hunter tegra_revision_name[tegra_sku_info.revision]); 446bebf683bSKartik else 447bebf683bSKartik attr->revision = kasprintf(GFP_KERNEL, "%s", 448bebf683bSKartik tegra_platform_name[tegra_sku_info.platform]); 44927a0342aSThierry Reding attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id()); 450379ac9ebSJon Hunter attr->custom_attr_group = fuse->soc->soc_attr_group; 45127a0342aSThierry Reding 45227a0342aSThierry Reding dev = soc_device_register(attr); 45327a0342aSThierry Reding if (IS_ERR(dev)) { 45427a0342aSThierry Reding kfree(attr->soc_id); 45527a0342aSThierry Reding kfree(attr->revision); 45627a0342aSThierry Reding kfree(attr->family); 45727a0342aSThierry Reding kfree(attr); 45827a0342aSThierry Reding return ERR_CAST(dev); 45927a0342aSThierry Reding } 46027a0342aSThierry Reding 46127a0342aSThierry Reding return soc_device_to_device(dev); 46227a0342aSThierry Reding } 46327a0342aSThierry Reding 46424fa5af8SThierry Reding static int __init tegra_init_fuse(void) 465783c8f4cSPeter De Schrijver { 4667e939de1SThierry Reding const struct of_device_id *match; 467783c8f4cSPeter De Schrijver struct device_node *np; 4687e939de1SThierry Reding struct resource regs; 46971661c1cSKartik int err; 47024fa5af8SThierry Reding 471783c8f4cSPeter De Schrijver tegra_init_apbmisc(); 472783c8f4cSPeter De Schrijver 4737e939de1SThierry Reding np = of_find_matching_node_and_match(NULL, tegra_fuse_match, &match); 4747e939de1SThierry Reding if (!np) { 4757e939de1SThierry Reding /* 4767e939de1SThierry Reding * Fall back to legacy initialization for 32-bit ARM only. All 4777e939de1SThierry Reding * 64-bit ARM device tree files for Tegra are required to have 4787e939de1SThierry Reding * a FUSE node. 4797e939de1SThierry Reding * 4807e939de1SThierry Reding * This is for backwards-compatibility with old device trees 4817e939de1SThierry Reding * that didn't contain a FUSE node. 4827e939de1SThierry Reding */ 4837e939de1SThierry Reding if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 4847e939de1SThierry Reding u8 chip = tegra_get_chip_id(); 4857e939de1SThierry Reding 4867e939de1SThierry Reding regs.start = 0x7000f800; 4877e939de1SThierry Reding regs.end = 0x7000fbff; 4887e939de1SThierry Reding regs.flags = IORESOURCE_MEM; 4897e939de1SThierry Reding 4907e939de1SThierry Reding switch (chip) { 4917e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_2x_SOC 4927e939de1SThierry Reding case TEGRA20: 4937e939de1SThierry Reding fuse->soc = &tegra20_fuse_soc; 4947e939de1SThierry Reding break; 4957e939de1SThierry Reding #endif 4967e939de1SThierry Reding 4977e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_3x_SOC 4987e939de1SThierry Reding case TEGRA30: 4997e939de1SThierry Reding fuse->soc = &tegra30_fuse_soc; 5007e939de1SThierry Reding break; 5017e939de1SThierry Reding #endif 5027e939de1SThierry Reding 5037e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_114_SOC 5047e939de1SThierry Reding case TEGRA114: 5057e939de1SThierry Reding fuse->soc = &tegra114_fuse_soc; 5067e939de1SThierry Reding break; 5077e939de1SThierry Reding #endif 5087e939de1SThierry Reding 5097e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_124_SOC 5107e939de1SThierry Reding case TEGRA124: 5117e939de1SThierry Reding fuse->soc = &tegra124_fuse_soc; 5127e939de1SThierry Reding break; 5137e939de1SThierry Reding #endif 5147e939de1SThierry Reding 5157e939de1SThierry Reding default: 5167e939de1SThierry Reding pr_warn("Unsupported SoC: %02x\n", chip); 5177e939de1SThierry Reding break; 5187e939de1SThierry Reding } 519783c8f4cSPeter De Schrijver } else { 5207e939de1SThierry Reding /* 5217e939de1SThierry Reding * At this point we're not running on Tegra, so play 5227e939de1SThierry Reding * nice with multi-platform kernels. 5237e939de1SThierry Reding */ 5247e939de1SThierry Reding return 0; 5257e939de1SThierry Reding } 5267e939de1SThierry Reding } else { 5277e939de1SThierry Reding /* 5287e939de1SThierry Reding * Extract information from the device tree if we've found a 5297e939de1SThierry Reding * matching node. 5307e939de1SThierry Reding */ 5317e939de1SThierry Reding if (of_address_to_resource(np, 0, ®s) < 0) { 5327e939de1SThierry Reding pr_err("failed to get FUSE register\n"); 53324fa5af8SThierry Reding return -ENXIO; 534783c8f4cSPeter De Schrijver } 535783c8f4cSPeter De Schrijver 5367e939de1SThierry Reding fuse->soc = match->data; 5377e939de1SThierry Reding } 5387e939de1SThierry Reding 5397e939de1SThierry Reding np = of_find_matching_node(NULL, car_match); 5407e939de1SThierry Reding if (np) { 5417e939de1SThierry Reding void __iomem *base = of_iomap(np, 0); 542e941712cSLiang He of_node_put(np); 5437e939de1SThierry Reding if (base) { 5447e939de1SThierry Reding tegra_enable_fuse_clk(base); 5457e939de1SThierry Reding iounmap(base); 5467e939de1SThierry Reding } else { 5477e939de1SThierry Reding pr_err("failed to map clock registers\n"); 5487e939de1SThierry Reding return -ENXIO; 5497e939de1SThierry Reding } 5507e939de1SThierry Reding } 5517e939de1SThierry Reding 5524bdc0d67SChristoph Hellwig fuse->base = ioremap(regs.start, resource_size(®s)); 5537e939de1SThierry Reding if (!fuse->base) { 5547e939de1SThierry Reding pr_err("failed to map FUSE registers\n"); 5557e939de1SThierry Reding return -ENXIO; 5567e939de1SThierry Reding } 5577e939de1SThierry Reding 5587e939de1SThierry Reding fuse->soc->init(fuse); 559783c8f4cSPeter De Schrijver 56013a69354SKartik tegra_fuse_print_sku_info(&tegra_sku_info); 56124fa5af8SThierry Reding 56271661c1cSKartik err = tegra_fuse_add_lookups(fuse); 56371661c1cSKartik if (err) 56471661c1cSKartik pr_err("failed to add FUSE lookups\n"); 5659f94faddSThierry Reding 56671661c1cSKartik return err; 567783c8f4cSPeter De Schrijver } 56824fa5af8SThierry Reding early_initcall(tegra_init_fuse); 56927a0342aSThierry Reding 57027a0342aSThierry Reding #ifdef CONFIG_ARM64 57127a0342aSThierry Reding static int __init tegra_init_soc(void) 57227a0342aSThierry Reding { 573226cff48SThierry Reding struct device_node *np; 57427a0342aSThierry Reding struct device *soc; 57527a0342aSThierry Reding 576226cff48SThierry Reding /* make sure we're running on Tegra */ 577226cff48SThierry Reding np = of_find_matching_node(NULL, tegra_fuse_match); 578226cff48SThierry Reding if (!np) 579226cff48SThierry Reding return 0; 580226cff48SThierry Reding 581226cff48SThierry Reding of_node_put(np); 582226cff48SThierry Reding 58327a0342aSThierry Reding soc = tegra_soc_device_register(); 58427a0342aSThierry Reding if (IS_ERR(soc)) { 58527a0342aSThierry Reding pr_err("failed to register SoC device: %ld\n", PTR_ERR(soc)); 58627a0342aSThierry Reding return PTR_ERR(soc); 58727a0342aSThierry Reding } 58827a0342aSThierry Reding 58927a0342aSThierry Reding return 0; 59027a0342aSThierry Reding } 5919261b43eSThierry Reding device_initcall(tegra_init_soc); 59227a0342aSThierry Reding #endif 593