19952f691SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2783c8f4cSPeter De Schrijver /* 3783c8f4cSPeter De Schrijver * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. 4783c8f4cSPeter De Schrijver */ 5783c8f4cSPeter De Schrijver 67e939de1SThierry Reding #include <linux/clk.h> 7783c8f4cSPeter De Schrijver #include <linux/device.h> 8783c8f4cSPeter De Schrijver #include <linux/kobject.h> 91859217bSPaul Gortmaker #include <linux/init.h> 1027a0342aSThierry Reding #include <linux/io.h> 11*96ee12b2SThierry Reding #include <linux/nvmem-consumer.h> 12*96ee12b2SThierry Reding #include <linux/nvmem-provider.h> 13783c8f4cSPeter De Schrijver #include <linux/of.h> 14783c8f4cSPeter De Schrijver #include <linux/of_address.h> 1527a0342aSThierry Reding #include <linux/platform_device.h> 1627a0342aSThierry Reding #include <linux/slab.h> 1727a0342aSThierry Reding #include <linux/sys_soc.h> 18783c8f4cSPeter De Schrijver 1924fa5af8SThierry Reding #include <soc/tegra/common.h> 20783c8f4cSPeter De Schrijver #include <soc/tegra/fuse.h> 21783c8f4cSPeter De Schrijver 22783c8f4cSPeter De Schrijver #include "fuse.h" 23783c8f4cSPeter De Schrijver 24783c8f4cSPeter De Schrijver struct tegra_sku_info tegra_sku_info; 25f9fc3661SVince Hsu EXPORT_SYMBOL(tegra_sku_info); 26783c8f4cSPeter De Schrijver 27783c8f4cSPeter De Schrijver static const char *tegra_revision_name[TEGRA_REVISION_MAX] = { 28783c8f4cSPeter De Schrijver [TEGRA_REVISION_UNKNOWN] = "unknown", 29783c8f4cSPeter De Schrijver [TEGRA_REVISION_A01] = "A01", 30783c8f4cSPeter De Schrijver [TEGRA_REVISION_A02] = "A02", 31783c8f4cSPeter De Schrijver [TEGRA_REVISION_A03] = "A03", 32783c8f4cSPeter De Schrijver [TEGRA_REVISION_A03p] = "A03 prime", 33783c8f4cSPeter De Schrijver [TEGRA_REVISION_A04] = "A04", 34783c8f4cSPeter De Schrijver }; 35783c8f4cSPeter De Schrijver 36783c8f4cSPeter De Schrijver static const struct of_device_id car_match[] __initconst = { 37783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra20-car", }, 38783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra30-car", }, 39783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra114-car", }, 40783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra124-car", }, 419b07eb05SThierry Reding { .compatible = "nvidia,tegra132-car", }, 420dc5a0d8SThierry Reding { .compatible = "nvidia,tegra210-car", }, 43783c8f4cSPeter De Schrijver {}, 44783c8f4cSPeter De Schrijver }; 45783c8f4cSPeter De Schrijver 467e939de1SThierry Reding static struct tegra_fuse *fuse = &(struct tegra_fuse) { 477e939de1SThierry Reding .base = NULL, 487e939de1SThierry Reding .soc = NULL, 497e939de1SThierry Reding }; 507e939de1SThierry Reding 517e939de1SThierry Reding static const struct of_device_id tegra_fuse_match[] = { 5283468fe2STimo Alho #ifdef CONFIG_ARCH_TEGRA_186_SOC 5383468fe2STimo Alho { .compatible = "nvidia,tegra186-efuse", .data = &tegra186_fuse_soc }, 5483468fe2STimo Alho #endif 550dc5a0d8SThierry Reding #ifdef CONFIG_ARCH_TEGRA_210_SOC 560dc5a0d8SThierry Reding { .compatible = "nvidia,tegra210-efuse", .data = &tegra210_fuse_soc }, 570dc5a0d8SThierry Reding #endif 587e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_132_SOC 597e939de1SThierry Reding { .compatible = "nvidia,tegra132-efuse", .data = &tegra124_fuse_soc }, 607e939de1SThierry Reding #endif 617e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_124_SOC 627e939de1SThierry Reding { .compatible = "nvidia,tegra124-efuse", .data = &tegra124_fuse_soc }, 637e939de1SThierry Reding #endif 647e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_114_SOC 657e939de1SThierry Reding { .compatible = "nvidia,tegra114-efuse", .data = &tegra114_fuse_soc }, 667e939de1SThierry Reding #endif 677e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_3x_SOC 687e939de1SThierry Reding { .compatible = "nvidia,tegra30-efuse", .data = &tegra30_fuse_soc }, 697e939de1SThierry Reding #endif 707e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_2x_SOC 717e939de1SThierry Reding { .compatible = "nvidia,tegra20-efuse", .data = &tegra20_fuse_soc }, 727e939de1SThierry Reding #endif 737e939de1SThierry Reding { /* sentinel */ } 747e939de1SThierry Reding }; 757e939de1SThierry Reding 76*96ee12b2SThierry Reding static int tegra_fuse_read(void *priv, unsigned int offset, void *value, 77*96ee12b2SThierry Reding size_t bytes) 78*96ee12b2SThierry Reding { 79*96ee12b2SThierry Reding unsigned int count = bytes / 4, i; 80*96ee12b2SThierry Reding struct tegra_fuse *fuse = priv; 81*96ee12b2SThierry Reding u32 *buffer = value; 82*96ee12b2SThierry Reding 83*96ee12b2SThierry Reding for (i = 0; i < count; i++) 84*96ee12b2SThierry Reding buffer[i] = fuse->read(fuse, offset + i * 4); 85*96ee12b2SThierry Reding 86*96ee12b2SThierry Reding return 0; 87*96ee12b2SThierry Reding } 88*96ee12b2SThierry Reding 897e939de1SThierry Reding static int tegra_fuse_probe(struct platform_device *pdev) 907e939de1SThierry Reding { 917e939de1SThierry Reding void __iomem *base = fuse->base; 92*96ee12b2SThierry Reding struct nvmem_config nvmem; 937e939de1SThierry Reding struct resource *res; 947e939de1SThierry Reding int err; 957e939de1SThierry Reding 967e939de1SThierry Reding /* take over the memory region from the early initialization */ 977e939de1SThierry Reding res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 9855a042b3SDmitry Osipenko fuse->phys = res->start; 997e939de1SThierry Reding fuse->base = devm_ioremap_resource(&pdev->dev, res); 10051294bf6STimo Alho if (IS_ERR(fuse->base)) { 10151294bf6STimo Alho err = PTR_ERR(fuse->base); 10251294bf6STimo Alho fuse->base = base; 10351294bf6STimo Alho return err; 10451294bf6STimo Alho } 1057e939de1SThierry Reding 1067e939de1SThierry Reding fuse->clk = devm_clk_get(&pdev->dev, "fuse"); 1077e939de1SThierry Reding if (IS_ERR(fuse->clk)) { 108f0b2835fSThierry Reding if (PTR_ERR(fuse->clk) != -EPROBE_DEFER) 1097e939de1SThierry Reding dev_err(&pdev->dev, "failed to get FUSE clock: %ld", 1107e939de1SThierry Reding PTR_ERR(fuse->clk)); 111f0b2835fSThierry Reding 11251294bf6STimo Alho fuse->base = base; 1137e939de1SThierry Reding return PTR_ERR(fuse->clk); 1147e939de1SThierry Reding } 1157e939de1SThierry Reding 1167e939de1SThierry Reding platform_set_drvdata(pdev, fuse); 1177e939de1SThierry Reding fuse->dev = &pdev->dev; 1187e939de1SThierry Reding 1197e939de1SThierry Reding if (fuse->soc->probe) { 1207e939de1SThierry Reding err = fuse->soc->probe(fuse); 1219f1022b8SThierry Reding if (err < 0) 1229f1022b8SThierry Reding goto restore; 12351294bf6STimo Alho } 1247e939de1SThierry Reding 125*96ee12b2SThierry Reding memset(&nvmem, 0, sizeof(nvmem)); 126*96ee12b2SThierry Reding nvmem.dev = &pdev->dev; 127*96ee12b2SThierry Reding nvmem.name = "fuse"; 128*96ee12b2SThierry Reding nvmem.id = -1; 129*96ee12b2SThierry Reding nvmem.owner = THIS_MODULE; 130*96ee12b2SThierry Reding nvmem.type = NVMEM_TYPE_OTP; 131*96ee12b2SThierry Reding nvmem.read_only = true; 132*96ee12b2SThierry Reding nvmem.root_only = true; 133*96ee12b2SThierry Reding nvmem.reg_read = tegra_fuse_read; 134*96ee12b2SThierry Reding nvmem.size = fuse->soc->info->size; 135*96ee12b2SThierry Reding nvmem.word_size = 4; 136*96ee12b2SThierry Reding nvmem.stride = 4; 137*96ee12b2SThierry Reding nvmem.priv = fuse; 138*96ee12b2SThierry Reding 139*96ee12b2SThierry Reding fuse->nvmem = devm_nvmem_register(&pdev->dev, &nvmem); 140*96ee12b2SThierry Reding if (IS_ERR(fuse->nvmem)) { 141*96ee12b2SThierry Reding err = PTR_ERR(fuse->nvmem); 142*96ee12b2SThierry Reding dev_err(&pdev->dev, "failed to register NVMEM device: %d\n", 143*96ee12b2SThierry Reding err); 1449f1022b8SThierry Reding goto restore; 1459f1022b8SThierry Reding } 1467e939de1SThierry Reding 1477e939de1SThierry Reding /* release the early I/O memory mapping */ 1487e939de1SThierry Reding iounmap(base); 1497e939de1SThierry Reding 1507e939de1SThierry Reding return 0; 1519f1022b8SThierry Reding 1529f1022b8SThierry Reding restore: 1539f1022b8SThierry Reding fuse->base = base; 1549f1022b8SThierry Reding return err; 1557e939de1SThierry Reding } 1567e939de1SThierry Reding 1577e939de1SThierry Reding static struct platform_driver tegra_fuse_driver = { 1587e939de1SThierry Reding .driver = { 1597e939de1SThierry Reding .name = "tegra-fuse", 1607e939de1SThierry Reding .of_match_table = tegra_fuse_match, 1617e939de1SThierry Reding .suppress_bind_attrs = true, 1627e939de1SThierry Reding }, 1637e939de1SThierry Reding .probe = tegra_fuse_probe, 1647e939de1SThierry Reding }; 1651859217bSPaul Gortmaker builtin_platform_driver(tegra_fuse_driver); 1667e939de1SThierry Reding 1677e939de1SThierry Reding bool __init tegra_fuse_read_spare(unsigned int spare) 1687e939de1SThierry Reding { 1697e939de1SThierry Reding unsigned int offset = fuse->soc->info->spare + spare * 4; 1707e939de1SThierry Reding 1717e939de1SThierry Reding return fuse->read_early(fuse, offset) & 1; 1727e939de1SThierry Reding } 1737e939de1SThierry Reding 1747e939de1SThierry Reding u32 __init tegra_fuse_read_early(unsigned int offset) 1757e939de1SThierry Reding { 1767e939de1SThierry Reding return fuse->read_early(fuse, offset); 1777e939de1SThierry Reding } 1787e939de1SThierry Reding 1797e939de1SThierry Reding int tegra_fuse_readl(unsigned long offset, u32 *value) 1807e939de1SThierry Reding { 1810a728e0bSNagarjuna Kristam if (!fuse->read || !fuse->clk) 1827e939de1SThierry Reding return -EPROBE_DEFER; 1837e939de1SThierry Reding 1840a728e0bSNagarjuna Kristam if (IS_ERR(fuse->clk)) 1850a728e0bSNagarjuna Kristam return PTR_ERR(fuse->clk); 1860a728e0bSNagarjuna Kristam 1877e939de1SThierry Reding *value = fuse->read(fuse, offset); 1887e939de1SThierry Reding 1897e939de1SThierry Reding return 0; 1907e939de1SThierry Reding } 1917e939de1SThierry Reding EXPORT_SYMBOL(tegra_fuse_readl); 1927e939de1SThierry Reding 193783c8f4cSPeter De Schrijver static void tegra_enable_fuse_clk(void __iomem *base) 194783c8f4cSPeter De Schrijver { 195783c8f4cSPeter De Schrijver u32 reg; 196783c8f4cSPeter De Schrijver 197783c8f4cSPeter De Schrijver reg = readl_relaxed(base + 0x48); 198783c8f4cSPeter De Schrijver reg |= 1 << 28; 199783c8f4cSPeter De Schrijver writel(reg, base + 0x48); 200783c8f4cSPeter De Schrijver 201783c8f4cSPeter De Schrijver /* 202783c8f4cSPeter De Schrijver * Enable FUSE clock. This needs to be hardcoded because the clock 203783c8f4cSPeter De Schrijver * subsystem is not active during early boot. 204783c8f4cSPeter De Schrijver */ 205783c8f4cSPeter De Schrijver reg = readl(base + 0x14); 206783c8f4cSPeter De Schrijver reg |= 1 << 7; 207783c8f4cSPeter De Schrijver writel(reg, base + 0x14); 208783c8f4cSPeter De Schrijver } 209783c8f4cSPeter De Schrijver 21027a0342aSThierry Reding struct device * __init tegra_soc_device_register(void) 21127a0342aSThierry Reding { 21227a0342aSThierry Reding struct soc_device_attribute *attr; 21327a0342aSThierry Reding struct soc_device *dev; 21427a0342aSThierry Reding 21527a0342aSThierry Reding attr = kzalloc(sizeof(*attr), GFP_KERNEL); 21627a0342aSThierry Reding if (!attr) 21727a0342aSThierry Reding return NULL; 21827a0342aSThierry Reding 21927a0342aSThierry Reding attr->family = kasprintf(GFP_KERNEL, "Tegra"); 22027a0342aSThierry Reding attr->revision = kasprintf(GFP_KERNEL, "%d", tegra_sku_info.revision); 22127a0342aSThierry Reding attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id()); 22227a0342aSThierry Reding 22327a0342aSThierry Reding dev = soc_device_register(attr); 22427a0342aSThierry Reding if (IS_ERR(dev)) { 22527a0342aSThierry Reding kfree(attr->soc_id); 22627a0342aSThierry Reding kfree(attr->revision); 22727a0342aSThierry Reding kfree(attr->family); 22827a0342aSThierry Reding kfree(attr); 22927a0342aSThierry Reding return ERR_CAST(dev); 23027a0342aSThierry Reding } 23127a0342aSThierry Reding 23227a0342aSThierry Reding return soc_device_to_device(dev); 23327a0342aSThierry Reding } 23427a0342aSThierry Reding 23524fa5af8SThierry Reding static int __init tegra_init_fuse(void) 236783c8f4cSPeter De Schrijver { 2377e939de1SThierry Reding const struct of_device_id *match; 238783c8f4cSPeter De Schrijver struct device_node *np; 2397e939de1SThierry Reding struct resource regs; 24024fa5af8SThierry Reding 241783c8f4cSPeter De Schrijver tegra_init_apbmisc(); 242783c8f4cSPeter De Schrijver 2437e939de1SThierry Reding np = of_find_matching_node_and_match(NULL, tegra_fuse_match, &match); 2447e939de1SThierry Reding if (!np) { 2457e939de1SThierry Reding /* 2467e939de1SThierry Reding * Fall back to legacy initialization for 32-bit ARM only. All 2477e939de1SThierry Reding * 64-bit ARM device tree files for Tegra are required to have 2487e939de1SThierry Reding * a FUSE node. 2497e939de1SThierry Reding * 2507e939de1SThierry Reding * This is for backwards-compatibility with old device trees 2517e939de1SThierry Reding * that didn't contain a FUSE node. 2527e939de1SThierry Reding */ 2537e939de1SThierry Reding if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 2547e939de1SThierry Reding u8 chip = tegra_get_chip_id(); 2557e939de1SThierry Reding 2567e939de1SThierry Reding regs.start = 0x7000f800; 2577e939de1SThierry Reding regs.end = 0x7000fbff; 2587e939de1SThierry Reding regs.flags = IORESOURCE_MEM; 2597e939de1SThierry Reding 2607e939de1SThierry Reding switch (chip) { 2617e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_2x_SOC 2627e939de1SThierry Reding case TEGRA20: 2637e939de1SThierry Reding fuse->soc = &tegra20_fuse_soc; 2647e939de1SThierry Reding break; 2657e939de1SThierry Reding #endif 2667e939de1SThierry Reding 2677e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_3x_SOC 2687e939de1SThierry Reding case TEGRA30: 2697e939de1SThierry Reding fuse->soc = &tegra30_fuse_soc; 2707e939de1SThierry Reding break; 2717e939de1SThierry Reding #endif 2727e939de1SThierry Reding 2737e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_114_SOC 2747e939de1SThierry Reding case TEGRA114: 2757e939de1SThierry Reding fuse->soc = &tegra114_fuse_soc; 2767e939de1SThierry Reding break; 2777e939de1SThierry Reding #endif 2787e939de1SThierry Reding 2797e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_124_SOC 2807e939de1SThierry Reding case TEGRA124: 2817e939de1SThierry Reding fuse->soc = &tegra124_fuse_soc; 2827e939de1SThierry Reding break; 2837e939de1SThierry Reding #endif 2847e939de1SThierry Reding 2857e939de1SThierry Reding default: 2867e939de1SThierry Reding pr_warn("Unsupported SoC: %02x\n", chip); 2877e939de1SThierry Reding break; 2887e939de1SThierry Reding } 289783c8f4cSPeter De Schrijver } else { 2907e939de1SThierry Reding /* 2917e939de1SThierry Reding * At this point we're not running on Tegra, so play 2927e939de1SThierry Reding * nice with multi-platform kernels. 2937e939de1SThierry Reding */ 2947e939de1SThierry Reding return 0; 2957e939de1SThierry Reding } 2967e939de1SThierry Reding } else { 2977e939de1SThierry Reding /* 2987e939de1SThierry Reding * Extract information from the device tree if we've found a 2997e939de1SThierry Reding * matching node. 3007e939de1SThierry Reding */ 3017e939de1SThierry Reding if (of_address_to_resource(np, 0, ®s) < 0) { 3027e939de1SThierry Reding pr_err("failed to get FUSE register\n"); 30324fa5af8SThierry Reding return -ENXIO; 304783c8f4cSPeter De Schrijver } 305783c8f4cSPeter De Schrijver 3067e939de1SThierry Reding fuse->soc = match->data; 3077e939de1SThierry Reding } 3087e939de1SThierry Reding 3097e939de1SThierry Reding np = of_find_matching_node(NULL, car_match); 3107e939de1SThierry Reding if (np) { 3117e939de1SThierry Reding void __iomem *base = of_iomap(np, 0); 3127e939de1SThierry Reding if (base) { 3137e939de1SThierry Reding tegra_enable_fuse_clk(base); 3147e939de1SThierry Reding iounmap(base); 3157e939de1SThierry Reding } else { 3167e939de1SThierry Reding pr_err("failed to map clock registers\n"); 3177e939de1SThierry Reding return -ENXIO; 3187e939de1SThierry Reding } 3197e939de1SThierry Reding } 3207e939de1SThierry Reding 3217e939de1SThierry Reding fuse->base = ioremap_nocache(regs.start, resource_size(®s)); 3227e939de1SThierry Reding if (!fuse->base) { 3237e939de1SThierry Reding pr_err("failed to map FUSE registers\n"); 3247e939de1SThierry Reding return -ENXIO; 3257e939de1SThierry Reding } 3267e939de1SThierry Reding 3277e939de1SThierry Reding fuse->soc->init(fuse); 328783c8f4cSPeter De Schrijver 32903b3f4c8SThierry Reding pr_info("Tegra Revision: %s SKU: %d CPU Process: %d SoC Process: %d\n", 330783c8f4cSPeter De Schrijver tegra_revision_name[tegra_sku_info.revision], 331783c8f4cSPeter De Schrijver tegra_sku_info.sku_id, tegra_sku_info.cpu_process_id, 33203b3f4c8SThierry Reding tegra_sku_info.soc_process_id); 33303b3f4c8SThierry Reding pr_debug("Tegra CPU Speedo ID %d, SoC Speedo ID %d\n", 334783c8f4cSPeter De Schrijver tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id); 33524fa5af8SThierry Reding 33627a0342aSThierry Reding 33724fa5af8SThierry Reding return 0; 338783c8f4cSPeter De Schrijver } 33924fa5af8SThierry Reding early_initcall(tegra_init_fuse); 34027a0342aSThierry Reding 34127a0342aSThierry Reding #ifdef CONFIG_ARM64 34227a0342aSThierry Reding static int __init tegra_init_soc(void) 34327a0342aSThierry Reding { 344226cff48SThierry Reding struct device_node *np; 34527a0342aSThierry Reding struct device *soc; 34627a0342aSThierry Reding 347226cff48SThierry Reding /* make sure we're running on Tegra */ 348226cff48SThierry Reding np = of_find_matching_node(NULL, tegra_fuse_match); 349226cff48SThierry Reding if (!np) 350226cff48SThierry Reding return 0; 351226cff48SThierry Reding 352226cff48SThierry Reding of_node_put(np); 353226cff48SThierry Reding 35427a0342aSThierry Reding soc = tegra_soc_device_register(); 35527a0342aSThierry Reding if (IS_ERR(soc)) { 35627a0342aSThierry Reding pr_err("failed to register SoC device: %ld\n", PTR_ERR(soc)); 35727a0342aSThierry Reding return PTR_ERR(soc); 35827a0342aSThierry Reding } 35927a0342aSThierry Reding 36027a0342aSThierry Reding return 0; 36127a0342aSThierry Reding } 3629261b43eSThierry Reding device_initcall(tegra_init_soc); 36327a0342aSThierry Reding #endif 364