19952f691SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2783c8f4cSPeter De Schrijver /* 3821d96e3SKartik * Copyright (c) 2013-2023, NVIDIA CORPORATION. All rights reserved. 4783c8f4cSPeter De Schrijver */ 5783c8f4cSPeter De Schrijver 67e939de1SThierry Reding #include <linux/clk.h> 7783c8f4cSPeter De Schrijver #include <linux/device.h> 8783c8f4cSPeter De Schrijver #include <linux/kobject.h> 91859217bSPaul Gortmaker #include <linux/init.h> 1027a0342aSThierry Reding #include <linux/io.h> 1196ee12b2SThierry Reding #include <linux/nvmem-consumer.h> 1296ee12b2SThierry Reding #include <linux/nvmem-provider.h> 13783c8f4cSPeter De Schrijver #include <linux/of.h> 14783c8f4cSPeter De Schrijver #include <linux/of_address.h> 1527a0342aSThierry Reding #include <linux/platform_device.h> 1624a15252SDmitry Osipenko #include <linux/pm_runtime.h> 17aeecc50aSDmitry Osipenko #include <linux/reset.h> 1827a0342aSThierry Reding #include <linux/slab.h> 1927a0342aSThierry Reding #include <linux/sys_soc.h> 20783c8f4cSPeter De Schrijver 2124fa5af8SThierry Reding #include <soc/tegra/common.h> 22783c8f4cSPeter De Schrijver #include <soc/tegra/fuse.h> 23783c8f4cSPeter De Schrijver 24783c8f4cSPeter De Schrijver #include "fuse.h" 25783c8f4cSPeter De Schrijver 26783c8f4cSPeter De Schrijver struct tegra_sku_info tegra_sku_info; 27f9fc3661SVince Hsu EXPORT_SYMBOL(tegra_sku_info); 28783c8f4cSPeter De Schrijver 29783c8f4cSPeter De Schrijver static const char *tegra_revision_name[TEGRA_REVISION_MAX] = { 30783c8f4cSPeter De Schrijver [TEGRA_REVISION_UNKNOWN] = "unknown", 31783c8f4cSPeter De Schrijver [TEGRA_REVISION_A01] = "A01", 32783c8f4cSPeter De Schrijver [TEGRA_REVISION_A02] = "A02", 33783c8f4cSPeter De Schrijver [TEGRA_REVISION_A03] = "A03", 34783c8f4cSPeter De Schrijver [TEGRA_REVISION_A03p] = "A03 prime", 35783c8f4cSPeter De Schrijver [TEGRA_REVISION_A04] = "A04", 36783c8f4cSPeter De Schrijver }; 37783c8f4cSPeter De Schrijver 38bebf683bSKartik static const char *tegra_platform_name[TEGRA_PLATFORM_MAX] = { 39bebf683bSKartik [TEGRA_PLATFORM_SILICON] = "Silicon", 40bebf683bSKartik [TEGRA_PLATFORM_QT] = "QT", 41bebf683bSKartik [TEGRA_PLATFORM_SYSTEM_FPGA] = "System FPGA", 42bebf683bSKartik [TEGRA_PLATFORM_UNIT_FPGA] = "Unit FPGA", 43bebf683bSKartik [TEGRA_PLATFORM_ASIM_QT] = "Asim QT", 44bebf683bSKartik [TEGRA_PLATFORM_ASIM_LINSIM] = "Asim Linsim", 45bebf683bSKartik [TEGRA_PLATFORM_DSIM_ASIM_LINSIM] = "Dsim Asim Linsim", 46bebf683bSKartik [TEGRA_PLATFORM_VERIFICATION_SIMULATION] = "Verification Simulation", 47bebf683bSKartik [TEGRA_PLATFORM_VDK] = "VDK", 48bebf683bSKartik [TEGRA_PLATFORM_VSP] = "VSP", 49bebf683bSKartik }; 50bebf683bSKartik 51783c8f4cSPeter De Schrijver static const struct of_device_id car_match[] __initconst = { 52783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra20-car", }, 53783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra30-car", }, 54783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra114-car", }, 55783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra124-car", }, 569b07eb05SThierry Reding { .compatible = "nvidia,tegra132-car", }, 570dc5a0d8SThierry Reding { .compatible = "nvidia,tegra210-car", }, 58783c8f4cSPeter De Schrijver {}, 59783c8f4cSPeter De Schrijver }; 60783c8f4cSPeter De Schrijver 617e939de1SThierry Reding static struct tegra_fuse *fuse = &(struct tegra_fuse) { 627e939de1SThierry Reding .base = NULL, 637e939de1SThierry Reding .soc = NULL, 647e939de1SThierry Reding }; 657e939de1SThierry Reding 667e939de1SThierry Reding static const struct of_device_id tegra_fuse_match[] = { 671f44febfSThierry Reding #ifdef CONFIG_ARCH_TEGRA_234_SOC 681f44febfSThierry Reding { .compatible = "nvidia,tegra234-efuse", .data = &tegra234_fuse_soc }, 691f44febfSThierry Reding #endif 703979a4c6SJC Kuo #ifdef CONFIG_ARCH_TEGRA_194_SOC 713979a4c6SJC Kuo { .compatible = "nvidia,tegra194-efuse", .data = &tegra194_fuse_soc }, 723979a4c6SJC Kuo #endif 7383468fe2STimo Alho #ifdef CONFIG_ARCH_TEGRA_186_SOC 7483468fe2STimo Alho { .compatible = "nvidia,tegra186-efuse", .data = &tegra186_fuse_soc }, 7583468fe2STimo Alho #endif 760dc5a0d8SThierry Reding #ifdef CONFIG_ARCH_TEGRA_210_SOC 770dc5a0d8SThierry Reding { .compatible = "nvidia,tegra210-efuse", .data = &tegra210_fuse_soc }, 780dc5a0d8SThierry Reding #endif 797e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_132_SOC 807e939de1SThierry Reding { .compatible = "nvidia,tegra132-efuse", .data = &tegra124_fuse_soc }, 817e939de1SThierry Reding #endif 827e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_124_SOC 837e939de1SThierry Reding { .compatible = "nvidia,tegra124-efuse", .data = &tegra124_fuse_soc }, 847e939de1SThierry Reding #endif 857e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_114_SOC 867e939de1SThierry Reding { .compatible = "nvidia,tegra114-efuse", .data = &tegra114_fuse_soc }, 877e939de1SThierry Reding #endif 887e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_3x_SOC 897e939de1SThierry Reding { .compatible = "nvidia,tegra30-efuse", .data = &tegra30_fuse_soc }, 907e939de1SThierry Reding #endif 917e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_2x_SOC 927e939de1SThierry Reding { .compatible = "nvidia,tegra20-efuse", .data = &tegra20_fuse_soc }, 937e939de1SThierry Reding #endif 947e939de1SThierry Reding { /* sentinel */ } 957e939de1SThierry Reding }; 967e939de1SThierry Reding 9796ee12b2SThierry Reding static int tegra_fuse_read(void *priv, unsigned int offset, void *value, 9896ee12b2SThierry Reding size_t bytes) 9996ee12b2SThierry Reding { 10096ee12b2SThierry Reding unsigned int count = bytes / 4, i; 10196ee12b2SThierry Reding struct tegra_fuse *fuse = priv; 10296ee12b2SThierry Reding u32 *buffer = value; 10396ee12b2SThierry Reding 10496ee12b2SThierry Reding for (i = 0; i < count; i++) 10596ee12b2SThierry Reding buffer[i] = fuse->read(fuse, offset + i * 4); 10696ee12b2SThierry Reding 10796ee12b2SThierry Reding return 0; 10896ee12b2SThierry Reding } 10996ee12b2SThierry Reding 11088724b78SDmitry Osipenko static void tegra_fuse_restore(void *base) 11188724b78SDmitry Osipenko { 112b631c9c2SThierry Reding fuse->base = (void __iomem *)base; 11388724b78SDmitry Osipenko fuse->clk = NULL; 11488724b78SDmitry Osipenko } 11588724b78SDmitry Osipenko 1167e939de1SThierry Reding static int tegra_fuse_probe(struct platform_device *pdev) 1177e939de1SThierry Reding { 1187e939de1SThierry Reding void __iomem *base = fuse->base; 11996ee12b2SThierry Reding struct nvmem_config nvmem; 1207e939de1SThierry Reding struct resource *res; 1217e939de1SThierry Reding int err; 1227e939de1SThierry Reding 123b631c9c2SThierry Reding err = devm_add_action(&pdev->dev, tegra_fuse_restore, (void __force *)base); 12488724b78SDmitry Osipenko if (err) 12588724b78SDmitry Osipenko return err; 12688724b78SDmitry Osipenko 1277e939de1SThierry Reding /* take over the memory region from the early initialization */ 1286674c980SYangtao Li fuse->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1296674c980SYangtao Li if (IS_ERR(fuse->base)) 1306674c980SYangtao Li return PTR_ERR(fuse->base); 13155a042b3SDmitry Osipenko fuse->phys = res->start; 1327e939de1SThierry Reding 1337e939de1SThierry Reding fuse->clk = devm_clk_get(&pdev->dev, "fuse"); 134*4569e604SKartik if (IS_ERR(fuse->clk)) 135*4569e604SKartik return dev_err_probe(&pdev->dev, PTR_ERR(fuse->clk), "failed to get FUSE clock\n"); 1367e939de1SThierry Reding 1377e939de1SThierry Reding platform_set_drvdata(pdev, fuse); 1387e939de1SThierry Reding fuse->dev = &pdev->dev; 1397e939de1SThierry Reding 14088724b78SDmitry Osipenko err = devm_pm_runtime_enable(&pdev->dev); 14188724b78SDmitry Osipenko if (err) 14288724b78SDmitry Osipenko return err; 14324a15252SDmitry Osipenko 1447e939de1SThierry Reding if (fuse->soc->probe) { 1457e939de1SThierry Reding err = fuse->soc->probe(fuse); 1469f1022b8SThierry Reding if (err < 0) 14788724b78SDmitry Osipenko return err; 14851294bf6STimo Alho } 1497e939de1SThierry Reding 15096ee12b2SThierry Reding memset(&nvmem, 0, sizeof(nvmem)); 15196ee12b2SThierry Reding nvmem.dev = &pdev->dev; 15296ee12b2SThierry Reding nvmem.name = "fuse"; 15396ee12b2SThierry Reding nvmem.id = -1; 15496ee12b2SThierry Reding nvmem.owner = THIS_MODULE; 155bea06d77SKartik nvmem.cells = fuse->soc->cells; 156bea06d77SKartik nvmem.ncells = fuse->soc->num_cells; 157cc5b2ad5SKartik nvmem.keepout = fuse->soc->keepouts; 158cc5b2ad5SKartik nvmem.nkeepout = fuse->soc->num_keepouts; 15996ee12b2SThierry Reding nvmem.type = NVMEM_TYPE_OTP; 16096ee12b2SThierry Reding nvmem.read_only = true; 161821d96e3SKartik nvmem.root_only = false; 16296ee12b2SThierry Reding nvmem.reg_read = tegra_fuse_read; 16396ee12b2SThierry Reding nvmem.size = fuse->soc->info->size; 16496ee12b2SThierry Reding nvmem.word_size = 4; 16596ee12b2SThierry Reding nvmem.stride = 4; 16696ee12b2SThierry Reding nvmem.priv = fuse; 16796ee12b2SThierry Reding 16896ee12b2SThierry Reding fuse->nvmem = devm_nvmem_register(&pdev->dev, &nvmem); 16996ee12b2SThierry Reding if (IS_ERR(fuse->nvmem)) { 17096ee12b2SThierry Reding err = PTR_ERR(fuse->nvmem); 17196ee12b2SThierry Reding dev_err(&pdev->dev, "failed to register NVMEM device: %d\n", 17296ee12b2SThierry Reding err); 17388724b78SDmitry Osipenko return err; 1749f1022b8SThierry Reding } 1757e939de1SThierry Reding 176aeecc50aSDmitry Osipenko fuse->rst = devm_reset_control_get_optional(&pdev->dev, "fuse"); 177*4569e604SKartik if (IS_ERR(fuse->rst)) 178*4569e604SKartik return dev_err_probe(&pdev->dev, PTR_ERR(fuse->rst), "failed to get FUSE reset\n"); 179aeecc50aSDmitry Osipenko 180aeecc50aSDmitry Osipenko /* 181aeecc50aSDmitry Osipenko * FUSE clock is enabled at a boot time, hence this resume/suspend 182aeecc50aSDmitry Osipenko * disables the clock besides the h/w resetting. 183aeecc50aSDmitry Osipenko */ 184aeecc50aSDmitry Osipenko err = pm_runtime_resume_and_get(&pdev->dev); 185aeecc50aSDmitry Osipenko if (err) 18688724b78SDmitry Osipenko return err; 187aeecc50aSDmitry Osipenko 188aeecc50aSDmitry Osipenko err = reset_control_reset(fuse->rst); 189aeecc50aSDmitry Osipenko pm_runtime_put(&pdev->dev); 190aeecc50aSDmitry Osipenko 191aeecc50aSDmitry Osipenko if (err < 0) { 192aeecc50aSDmitry Osipenko dev_err(&pdev->dev, "failed to reset FUSE: %d\n", err); 19388724b78SDmitry Osipenko return err; 1947e939de1SThierry Reding } 1957e939de1SThierry Reding 1967e939de1SThierry Reding /* release the early I/O memory mapping */ 1977e939de1SThierry Reding iounmap(base); 1987e939de1SThierry Reding 1997e939de1SThierry Reding return 0; 2007e939de1SThierry Reding } 2017e939de1SThierry Reding 20224a15252SDmitry Osipenko static int __maybe_unused tegra_fuse_runtime_resume(struct device *dev) 20324a15252SDmitry Osipenko { 20424a15252SDmitry Osipenko int err; 20524a15252SDmitry Osipenko 20624a15252SDmitry Osipenko err = clk_prepare_enable(fuse->clk); 20724a15252SDmitry Osipenko if (err < 0) { 20824a15252SDmitry Osipenko dev_err(dev, "failed to enable FUSE clock: %d\n", err); 20924a15252SDmitry Osipenko return err; 21024a15252SDmitry Osipenko } 21124a15252SDmitry Osipenko 21224a15252SDmitry Osipenko return 0; 21324a15252SDmitry Osipenko } 21424a15252SDmitry Osipenko 21524a15252SDmitry Osipenko static int __maybe_unused tegra_fuse_runtime_suspend(struct device *dev) 21624a15252SDmitry Osipenko { 21724a15252SDmitry Osipenko clk_disable_unprepare(fuse->clk); 21824a15252SDmitry Osipenko 21924a15252SDmitry Osipenko return 0; 22024a15252SDmitry Osipenko } 22124a15252SDmitry Osipenko 22259c6fcebSDmitry Osipenko static int __maybe_unused tegra_fuse_suspend(struct device *dev) 22359c6fcebSDmitry Osipenko { 22459c6fcebSDmitry Osipenko int ret; 22559c6fcebSDmitry Osipenko 22659c6fcebSDmitry Osipenko /* 22759c6fcebSDmitry Osipenko * Critical for RAM re-repair operation, which must occur on resume 22859c6fcebSDmitry Osipenko * from LP1 system suspend and as part of CCPLEX cluster switching. 22959c6fcebSDmitry Osipenko */ 23059c6fcebSDmitry Osipenko if (fuse->soc->clk_suspend_on) 23159c6fcebSDmitry Osipenko ret = pm_runtime_resume_and_get(dev); 23259c6fcebSDmitry Osipenko else 23359c6fcebSDmitry Osipenko ret = pm_runtime_force_suspend(dev); 23459c6fcebSDmitry Osipenko 23559c6fcebSDmitry Osipenko return ret; 23659c6fcebSDmitry Osipenko } 23759c6fcebSDmitry Osipenko 23859c6fcebSDmitry Osipenko static int __maybe_unused tegra_fuse_resume(struct device *dev) 23959c6fcebSDmitry Osipenko { 24059c6fcebSDmitry Osipenko int ret = 0; 24159c6fcebSDmitry Osipenko 24259c6fcebSDmitry Osipenko if (fuse->soc->clk_suspend_on) 24359c6fcebSDmitry Osipenko pm_runtime_put(dev); 24459c6fcebSDmitry Osipenko else 24559c6fcebSDmitry Osipenko ret = pm_runtime_force_resume(dev); 24659c6fcebSDmitry Osipenko 24759c6fcebSDmitry Osipenko return ret; 24859c6fcebSDmitry Osipenko } 24959c6fcebSDmitry Osipenko 25024a15252SDmitry Osipenko static const struct dev_pm_ops tegra_fuse_pm = { 25124a15252SDmitry Osipenko SET_RUNTIME_PM_OPS(tegra_fuse_runtime_suspend, tegra_fuse_runtime_resume, 25224a15252SDmitry Osipenko NULL) 25359c6fcebSDmitry Osipenko SET_SYSTEM_SLEEP_PM_OPS(tegra_fuse_suspend, tegra_fuse_resume) 25424a15252SDmitry Osipenko }; 25524a15252SDmitry Osipenko 2567e939de1SThierry Reding static struct platform_driver tegra_fuse_driver = { 2577e939de1SThierry Reding .driver = { 2587e939de1SThierry Reding .name = "tegra-fuse", 2597e939de1SThierry Reding .of_match_table = tegra_fuse_match, 26024a15252SDmitry Osipenko .pm = &tegra_fuse_pm, 2617e939de1SThierry Reding .suppress_bind_attrs = true, 2627e939de1SThierry Reding }, 2637e939de1SThierry Reding .probe = tegra_fuse_probe, 2647e939de1SThierry Reding }; 2651859217bSPaul Gortmaker builtin_platform_driver(tegra_fuse_driver); 2667e939de1SThierry Reding 267a7083763SNathan Chancellor u32 __init tegra_fuse_read_spare(unsigned int spare) 2687e939de1SThierry Reding { 2697e939de1SThierry Reding unsigned int offset = fuse->soc->info->spare + spare * 4; 2707e939de1SThierry Reding 2717e939de1SThierry Reding return fuse->read_early(fuse, offset) & 1; 2727e939de1SThierry Reding } 2737e939de1SThierry Reding 2747e939de1SThierry Reding u32 __init tegra_fuse_read_early(unsigned int offset) 2757e939de1SThierry Reding { 2767e939de1SThierry Reding return fuse->read_early(fuse, offset); 2777e939de1SThierry Reding } 2787e939de1SThierry Reding 2797e939de1SThierry Reding int tegra_fuse_readl(unsigned long offset, u32 *value) 2807e939de1SThierry Reding { 2810a728e0bSNagarjuna Kristam if (!fuse->read || !fuse->clk) 2827e939de1SThierry Reding return -EPROBE_DEFER; 2837e939de1SThierry Reding 2840a728e0bSNagarjuna Kristam if (IS_ERR(fuse->clk)) 2850a728e0bSNagarjuna Kristam return PTR_ERR(fuse->clk); 2860a728e0bSNagarjuna Kristam 2877e939de1SThierry Reding *value = fuse->read(fuse, offset); 2887e939de1SThierry Reding 2897e939de1SThierry Reding return 0; 2907e939de1SThierry Reding } 2917e939de1SThierry Reding EXPORT_SYMBOL(tegra_fuse_readl); 2927e939de1SThierry Reding 293783c8f4cSPeter De Schrijver static void tegra_enable_fuse_clk(void __iomem *base) 294783c8f4cSPeter De Schrijver { 295783c8f4cSPeter De Schrijver u32 reg; 296783c8f4cSPeter De Schrijver 297783c8f4cSPeter De Schrijver reg = readl_relaxed(base + 0x48); 298783c8f4cSPeter De Schrijver reg |= 1 << 28; 299783c8f4cSPeter De Schrijver writel(reg, base + 0x48); 300783c8f4cSPeter De Schrijver 301783c8f4cSPeter De Schrijver /* 302783c8f4cSPeter De Schrijver * Enable FUSE clock. This needs to be hardcoded because the clock 303783c8f4cSPeter De Schrijver * subsystem is not active during early boot. 304783c8f4cSPeter De Schrijver */ 305783c8f4cSPeter De Schrijver reg = readl(base + 0x14); 306783c8f4cSPeter De Schrijver reg |= 1 << 7; 307783c8f4cSPeter De Schrijver writel(reg, base + 0x14); 308783c8f4cSPeter De Schrijver } 309783c8f4cSPeter De Schrijver 310379ac9ebSJon Hunter static ssize_t major_show(struct device *dev, struct device_attribute *attr, 311379ac9ebSJon Hunter char *buf) 312379ac9ebSJon Hunter { 313379ac9ebSJon Hunter return sprintf(buf, "%d\n", tegra_get_major_rev()); 314379ac9ebSJon Hunter } 315379ac9ebSJon Hunter 316379ac9ebSJon Hunter static DEVICE_ATTR_RO(major); 317379ac9ebSJon Hunter 318379ac9ebSJon Hunter static ssize_t minor_show(struct device *dev, struct device_attribute *attr, 319379ac9ebSJon Hunter char *buf) 320379ac9ebSJon Hunter { 321379ac9ebSJon Hunter return sprintf(buf, "%d\n", tegra_get_minor_rev()); 322379ac9ebSJon Hunter } 323379ac9ebSJon Hunter 324379ac9ebSJon Hunter static DEVICE_ATTR_RO(minor); 325379ac9ebSJon Hunter 326379ac9ebSJon Hunter static struct attribute *tegra_soc_attr[] = { 327379ac9ebSJon Hunter &dev_attr_major.attr, 328379ac9ebSJon Hunter &dev_attr_minor.attr, 329379ac9ebSJon Hunter NULL, 330379ac9ebSJon Hunter }; 331379ac9ebSJon Hunter 332379ac9ebSJon Hunter const struct attribute_group tegra_soc_attr_group = { 333379ac9ebSJon Hunter .attrs = tegra_soc_attr, 334379ac9ebSJon Hunter }; 335379ac9ebSJon Hunter 3361f44febfSThierry Reding #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \ 3371f44febfSThierry Reding IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) 338379ac9ebSJon Hunter static ssize_t platform_show(struct device *dev, struct device_attribute *attr, 339379ac9ebSJon Hunter char *buf) 340379ac9ebSJon Hunter { 341379ac9ebSJon Hunter /* 342379ac9ebSJon Hunter * Displays the value in the 'pre_si_platform' field of the HIDREV 343379ac9ebSJon Hunter * register for Tegra194 devices. A value of 0 indicates that the 344379ac9ebSJon Hunter * platform type is silicon and all other non-zero values indicate 345379ac9ebSJon Hunter * the type of simulation platform is being used. 346379ac9ebSJon Hunter */ 347775edf78SThierry Reding return sprintf(buf, "%d\n", tegra_get_platform()); 348379ac9ebSJon Hunter } 349379ac9ebSJon Hunter 350379ac9ebSJon Hunter static DEVICE_ATTR_RO(platform); 351379ac9ebSJon Hunter 352379ac9ebSJon Hunter static struct attribute *tegra194_soc_attr[] = { 353379ac9ebSJon Hunter &dev_attr_major.attr, 354379ac9ebSJon Hunter &dev_attr_minor.attr, 355379ac9ebSJon Hunter &dev_attr_platform.attr, 356379ac9ebSJon Hunter NULL, 357379ac9ebSJon Hunter }; 358379ac9ebSJon Hunter 359379ac9ebSJon Hunter const struct attribute_group tegra194_soc_attr_group = { 360379ac9ebSJon Hunter .attrs = tegra194_soc_attr, 361379ac9ebSJon Hunter }; 362379ac9ebSJon Hunter #endif 363379ac9ebSJon Hunter 36427a0342aSThierry Reding struct device * __init tegra_soc_device_register(void) 36527a0342aSThierry Reding { 36627a0342aSThierry Reding struct soc_device_attribute *attr; 36727a0342aSThierry Reding struct soc_device *dev; 36827a0342aSThierry Reding 36927a0342aSThierry Reding attr = kzalloc(sizeof(*attr), GFP_KERNEL); 37027a0342aSThierry Reding if (!attr) 37127a0342aSThierry Reding return NULL; 37227a0342aSThierry Reding 37327a0342aSThierry Reding attr->family = kasprintf(GFP_KERNEL, "Tegra"); 374bebf683bSKartik if (tegra_is_silicon()) 375bebf683bSKartik attr->revision = kasprintf(GFP_KERNEL, "%s %s", 376bebf683bSKartik tegra_platform_name[tegra_sku_info.platform], 37737558ac8SJon Hunter tegra_revision_name[tegra_sku_info.revision]); 378bebf683bSKartik else 379bebf683bSKartik attr->revision = kasprintf(GFP_KERNEL, "%s", 380bebf683bSKartik tegra_platform_name[tegra_sku_info.platform]); 38127a0342aSThierry Reding attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id()); 382379ac9ebSJon Hunter attr->custom_attr_group = fuse->soc->soc_attr_group; 38327a0342aSThierry Reding 38427a0342aSThierry Reding dev = soc_device_register(attr); 38527a0342aSThierry Reding if (IS_ERR(dev)) { 38627a0342aSThierry Reding kfree(attr->soc_id); 38727a0342aSThierry Reding kfree(attr->revision); 38827a0342aSThierry Reding kfree(attr->family); 38927a0342aSThierry Reding kfree(attr); 39027a0342aSThierry Reding return ERR_CAST(dev); 39127a0342aSThierry Reding } 39227a0342aSThierry Reding 39327a0342aSThierry Reding return soc_device_to_device(dev); 39427a0342aSThierry Reding } 39527a0342aSThierry Reding 39624fa5af8SThierry Reding static int __init tegra_init_fuse(void) 397783c8f4cSPeter De Schrijver { 3987e939de1SThierry Reding const struct of_device_id *match; 399783c8f4cSPeter De Schrijver struct device_node *np; 4007e939de1SThierry Reding struct resource regs; 40124fa5af8SThierry Reding 402783c8f4cSPeter De Schrijver tegra_init_apbmisc(); 403783c8f4cSPeter De Schrijver 4047e939de1SThierry Reding np = of_find_matching_node_and_match(NULL, tegra_fuse_match, &match); 4057e939de1SThierry Reding if (!np) { 4067e939de1SThierry Reding /* 4077e939de1SThierry Reding * Fall back to legacy initialization for 32-bit ARM only. All 4087e939de1SThierry Reding * 64-bit ARM device tree files for Tegra are required to have 4097e939de1SThierry Reding * a FUSE node. 4107e939de1SThierry Reding * 4117e939de1SThierry Reding * This is for backwards-compatibility with old device trees 4127e939de1SThierry Reding * that didn't contain a FUSE node. 4137e939de1SThierry Reding */ 4147e939de1SThierry Reding if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 4157e939de1SThierry Reding u8 chip = tegra_get_chip_id(); 4167e939de1SThierry Reding 4177e939de1SThierry Reding regs.start = 0x7000f800; 4187e939de1SThierry Reding regs.end = 0x7000fbff; 4197e939de1SThierry Reding regs.flags = IORESOURCE_MEM; 4207e939de1SThierry Reding 4217e939de1SThierry Reding switch (chip) { 4227e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_2x_SOC 4237e939de1SThierry Reding case TEGRA20: 4247e939de1SThierry Reding fuse->soc = &tegra20_fuse_soc; 4257e939de1SThierry Reding break; 4267e939de1SThierry Reding #endif 4277e939de1SThierry Reding 4287e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_3x_SOC 4297e939de1SThierry Reding case TEGRA30: 4307e939de1SThierry Reding fuse->soc = &tegra30_fuse_soc; 4317e939de1SThierry Reding break; 4327e939de1SThierry Reding #endif 4337e939de1SThierry Reding 4347e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_114_SOC 4357e939de1SThierry Reding case TEGRA114: 4367e939de1SThierry Reding fuse->soc = &tegra114_fuse_soc; 4377e939de1SThierry Reding break; 4387e939de1SThierry Reding #endif 4397e939de1SThierry Reding 4407e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_124_SOC 4417e939de1SThierry Reding case TEGRA124: 4427e939de1SThierry Reding fuse->soc = &tegra124_fuse_soc; 4437e939de1SThierry Reding break; 4447e939de1SThierry Reding #endif 4457e939de1SThierry Reding 4467e939de1SThierry Reding default: 4477e939de1SThierry Reding pr_warn("Unsupported SoC: %02x\n", chip); 4487e939de1SThierry Reding break; 4497e939de1SThierry Reding } 450783c8f4cSPeter De Schrijver } else { 4517e939de1SThierry Reding /* 4527e939de1SThierry Reding * At this point we're not running on Tegra, so play 4537e939de1SThierry Reding * nice with multi-platform kernels. 4547e939de1SThierry Reding */ 4557e939de1SThierry Reding return 0; 4567e939de1SThierry Reding } 4577e939de1SThierry Reding } else { 4587e939de1SThierry Reding /* 4597e939de1SThierry Reding * Extract information from the device tree if we've found a 4607e939de1SThierry Reding * matching node. 4617e939de1SThierry Reding */ 4627e939de1SThierry Reding if (of_address_to_resource(np, 0, ®s) < 0) { 4637e939de1SThierry Reding pr_err("failed to get FUSE register\n"); 46424fa5af8SThierry Reding return -ENXIO; 465783c8f4cSPeter De Schrijver } 466783c8f4cSPeter De Schrijver 4677e939de1SThierry Reding fuse->soc = match->data; 4687e939de1SThierry Reding } 4697e939de1SThierry Reding 4707e939de1SThierry Reding np = of_find_matching_node(NULL, car_match); 4717e939de1SThierry Reding if (np) { 4727e939de1SThierry Reding void __iomem *base = of_iomap(np, 0); 473e941712cSLiang He of_node_put(np); 4747e939de1SThierry Reding if (base) { 4757e939de1SThierry Reding tegra_enable_fuse_clk(base); 4767e939de1SThierry Reding iounmap(base); 4777e939de1SThierry Reding } else { 4787e939de1SThierry Reding pr_err("failed to map clock registers\n"); 4797e939de1SThierry Reding return -ENXIO; 4807e939de1SThierry Reding } 4817e939de1SThierry Reding } 4827e939de1SThierry Reding 4834bdc0d67SChristoph Hellwig fuse->base = ioremap(regs.start, resource_size(®s)); 4847e939de1SThierry Reding if (!fuse->base) { 4857e939de1SThierry Reding pr_err("failed to map FUSE registers\n"); 4867e939de1SThierry Reding return -ENXIO; 4877e939de1SThierry Reding } 4887e939de1SThierry Reding 4897e939de1SThierry Reding fuse->soc->init(fuse); 490783c8f4cSPeter De Schrijver 49103b3f4c8SThierry Reding pr_info("Tegra Revision: %s SKU: %d CPU Process: %d SoC Process: %d\n", 492783c8f4cSPeter De Schrijver tegra_revision_name[tegra_sku_info.revision], 493783c8f4cSPeter De Schrijver tegra_sku_info.sku_id, tegra_sku_info.cpu_process_id, 49403b3f4c8SThierry Reding tegra_sku_info.soc_process_id); 49503b3f4c8SThierry Reding pr_debug("Tegra CPU Speedo ID %d, SoC Speedo ID %d\n", 496783c8f4cSPeter De Schrijver tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id); 49724fa5af8SThierry Reding 4989f94faddSThierry Reding if (fuse->soc->lookups) { 4999f94faddSThierry Reding size_t size = sizeof(*fuse->lookups) * fuse->soc->num_lookups; 5009f94faddSThierry Reding 5019f94faddSThierry Reding fuse->lookups = kmemdup(fuse->soc->lookups, size, GFP_KERNEL); 502854d128bSYang Yingliang if (fuse->lookups) 5039f94faddSThierry Reding nvmem_add_cell_lookups(fuse->lookups, fuse->soc->num_lookups); 5049f94faddSThierry Reding } 50527a0342aSThierry Reding 50624fa5af8SThierry Reding return 0; 507783c8f4cSPeter De Schrijver } 50824fa5af8SThierry Reding early_initcall(tegra_init_fuse); 50927a0342aSThierry Reding 51027a0342aSThierry Reding #ifdef CONFIG_ARM64 51127a0342aSThierry Reding static int __init tegra_init_soc(void) 51227a0342aSThierry Reding { 513226cff48SThierry Reding struct device_node *np; 51427a0342aSThierry Reding struct device *soc; 51527a0342aSThierry Reding 516226cff48SThierry Reding /* make sure we're running on Tegra */ 517226cff48SThierry Reding np = of_find_matching_node(NULL, tegra_fuse_match); 518226cff48SThierry Reding if (!np) 519226cff48SThierry Reding return 0; 520226cff48SThierry Reding 521226cff48SThierry Reding of_node_put(np); 522226cff48SThierry Reding 52327a0342aSThierry Reding soc = tegra_soc_device_register(); 52427a0342aSThierry Reding if (IS_ERR(soc)) { 52527a0342aSThierry Reding pr_err("failed to register SoC device: %ld\n", PTR_ERR(soc)); 52627a0342aSThierry Reding return PTR_ERR(soc); 52727a0342aSThierry Reding } 52827a0342aSThierry Reding 52927a0342aSThierry Reding return 0; 53027a0342aSThierry Reding } 5319261b43eSThierry Reding device_initcall(tegra_init_soc); 53227a0342aSThierry Reding #endif 533