19952f691SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2783c8f4cSPeter De Schrijver /* 3783c8f4cSPeter De Schrijver * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. 4783c8f4cSPeter De Schrijver */ 5783c8f4cSPeter De Schrijver 67e939de1SThierry Reding #include <linux/clk.h> 7783c8f4cSPeter De Schrijver #include <linux/device.h> 8783c8f4cSPeter De Schrijver #include <linux/kobject.h> 91859217bSPaul Gortmaker #include <linux/init.h> 1027a0342aSThierry Reding #include <linux/io.h> 1196ee12b2SThierry Reding #include <linux/nvmem-consumer.h> 1296ee12b2SThierry Reding #include <linux/nvmem-provider.h> 13783c8f4cSPeter De Schrijver #include <linux/of.h> 14783c8f4cSPeter De Schrijver #include <linux/of_address.h> 1527a0342aSThierry Reding #include <linux/platform_device.h> 16*24a15252SDmitry Osipenko #include <linux/pm_runtime.h> 1727a0342aSThierry Reding #include <linux/slab.h> 1827a0342aSThierry Reding #include <linux/sys_soc.h> 19783c8f4cSPeter De Schrijver 2024fa5af8SThierry Reding #include <soc/tegra/common.h> 21783c8f4cSPeter De Schrijver #include <soc/tegra/fuse.h> 22783c8f4cSPeter De Schrijver 23783c8f4cSPeter De Schrijver #include "fuse.h" 24783c8f4cSPeter De Schrijver 25783c8f4cSPeter De Schrijver struct tegra_sku_info tegra_sku_info; 26f9fc3661SVince Hsu EXPORT_SYMBOL(tegra_sku_info); 27783c8f4cSPeter De Schrijver 28783c8f4cSPeter De Schrijver static const char *tegra_revision_name[TEGRA_REVISION_MAX] = { 29783c8f4cSPeter De Schrijver [TEGRA_REVISION_UNKNOWN] = "unknown", 30783c8f4cSPeter De Schrijver [TEGRA_REVISION_A01] = "A01", 31783c8f4cSPeter De Schrijver [TEGRA_REVISION_A02] = "A02", 32783c8f4cSPeter De Schrijver [TEGRA_REVISION_A03] = "A03", 33783c8f4cSPeter De Schrijver [TEGRA_REVISION_A03p] = "A03 prime", 34783c8f4cSPeter De Schrijver [TEGRA_REVISION_A04] = "A04", 35783c8f4cSPeter De Schrijver }; 36783c8f4cSPeter De Schrijver 37783c8f4cSPeter De Schrijver static const struct of_device_id car_match[] __initconst = { 38783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra20-car", }, 39783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra30-car", }, 40783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra114-car", }, 41783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra124-car", }, 429b07eb05SThierry Reding { .compatible = "nvidia,tegra132-car", }, 430dc5a0d8SThierry Reding { .compatible = "nvidia,tegra210-car", }, 44783c8f4cSPeter De Schrijver {}, 45783c8f4cSPeter De Schrijver }; 46783c8f4cSPeter De Schrijver 477e939de1SThierry Reding static struct tegra_fuse *fuse = &(struct tegra_fuse) { 487e939de1SThierry Reding .base = NULL, 497e939de1SThierry Reding .soc = NULL, 507e939de1SThierry Reding }; 517e939de1SThierry Reding 527e939de1SThierry Reding static const struct of_device_id tegra_fuse_match[] = { 531f44febfSThierry Reding #ifdef CONFIG_ARCH_TEGRA_234_SOC 541f44febfSThierry Reding { .compatible = "nvidia,tegra234-efuse", .data = &tegra234_fuse_soc }, 551f44febfSThierry Reding #endif 563979a4c6SJC Kuo #ifdef CONFIG_ARCH_TEGRA_194_SOC 573979a4c6SJC Kuo { .compatible = "nvidia,tegra194-efuse", .data = &tegra194_fuse_soc }, 583979a4c6SJC Kuo #endif 5983468fe2STimo Alho #ifdef CONFIG_ARCH_TEGRA_186_SOC 6083468fe2STimo Alho { .compatible = "nvidia,tegra186-efuse", .data = &tegra186_fuse_soc }, 6183468fe2STimo Alho #endif 620dc5a0d8SThierry Reding #ifdef CONFIG_ARCH_TEGRA_210_SOC 630dc5a0d8SThierry Reding { .compatible = "nvidia,tegra210-efuse", .data = &tegra210_fuse_soc }, 640dc5a0d8SThierry Reding #endif 657e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_132_SOC 667e939de1SThierry Reding { .compatible = "nvidia,tegra132-efuse", .data = &tegra124_fuse_soc }, 677e939de1SThierry Reding #endif 687e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_124_SOC 697e939de1SThierry Reding { .compatible = "nvidia,tegra124-efuse", .data = &tegra124_fuse_soc }, 707e939de1SThierry Reding #endif 717e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_114_SOC 727e939de1SThierry Reding { .compatible = "nvidia,tegra114-efuse", .data = &tegra114_fuse_soc }, 737e939de1SThierry Reding #endif 747e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_3x_SOC 757e939de1SThierry Reding { .compatible = "nvidia,tegra30-efuse", .data = &tegra30_fuse_soc }, 767e939de1SThierry Reding #endif 777e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_2x_SOC 787e939de1SThierry Reding { .compatible = "nvidia,tegra20-efuse", .data = &tegra20_fuse_soc }, 797e939de1SThierry Reding #endif 807e939de1SThierry Reding { /* sentinel */ } 817e939de1SThierry Reding }; 827e939de1SThierry Reding 8396ee12b2SThierry Reding static int tegra_fuse_read(void *priv, unsigned int offset, void *value, 8496ee12b2SThierry Reding size_t bytes) 8596ee12b2SThierry Reding { 8696ee12b2SThierry Reding unsigned int count = bytes / 4, i; 8796ee12b2SThierry Reding struct tegra_fuse *fuse = priv; 8896ee12b2SThierry Reding u32 *buffer = value; 8996ee12b2SThierry Reding 9096ee12b2SThierry Reding for (i = 0; i < count; i++) 9196ee12b2SThierry Reding buffer[i] = fuse->read(fuse, offset + i * 4); 9296ee12b2SThierry Reding 9396ee12b2SThierry Reding return 0; 9496ee12b2SThierry Reding } 9596ee12b2SThierry Reding 96f4619c7fSThierry Reding static const struct nvmem_cell_info tegra_fuse_cells[] = { 97f4619c7fSThierry Reding { 98f4619c7fSThierry Reding .name = "tsensor-cpu1", 99f4619c7fSThierry Reding .offset = 0x084, 100f4619c7fSThierry Reding .bytes = 4, 101f4619c7fSThierry Reding .bit_offset = 0, 102f4619c7fSThierry Reding .nbits = 32, 103f4619c7fSThierry Reding }, { 104f4619c7fSThierry Reding .name = "tsensor-cpu2", 105f4619c7fSThierry Reding .offset = 0x088, 106f4619c7fSThierry Reding .bytes = 4, 107f4619c7fSThierry Reding .bit_offset = 0, 108f4619c7fSThierry Reding .nbits = 32, 109f4619c7fSThierry Reding }, { 110f4619c7fSThierry Reding .name = "tsensor-cpu0", 111f4619c7fSThierry Reding .offset = 0x098, 112f4619c7fSThierry Reding .bytes = 4, 113f4619c7fSThierry Reding .bit_offset = 0, 114f4619c7fSThierry Reding .nbits = 32, 115f4619c7fSThierry Reding }, { 116f4619c7fSThierry Reding .name = "xusb-pad-calibration", 117f4619c7fSThierry Reding .offset = 0x0f0, 118f4619c7fSThierry Reding .bytes = 4, 119f4619c7fSThierry Reding .bit_offset = 0, 120f4619c7fSThierry Reding .nbits = 32, 121f4619c7fSThierry Reding }, { 122f4619c7fSThierry Reding .name = "tsensor-cpu3", 123f4619c7fSThierry Reding .offset = 0x12c, 124f4619c7fSThierry Reding .bytes = 4, 125f4619c7fSThierry Reding .bit_offset = 0, 126f4619c7fSThierry Reding .nbits = 32, 127f4619c7fSThierry Reding }, { 128f4619c7fSThierry Reding .name = "sata-calibration", 129f4619c7fSThierry Reding .offset = 0x124, 130f4619c7fSThierry Reding .bytes = 1, 131f4619c7fSThierry Reding .bit_offset = 0, 132f4619c7fSThierry Reding .nbits = 2, 133f4619c7fSThierry Reding }, { 134f4619c7fSThierry Reding .name = "tsensor-gpu", 135f4619c7fSThierry Reding .offset = 0x154, 136f4619c7fSThierry Reding .bytes = 4, 137f4619c7fSThierry Reding .bit_offset = 0, 138f4619c7fSThierry Reding .nbits = 32, 139f4619c7fSThierry Reding }, { 140f4619c7fSThierry Reding .name = "tsensor-mem0", 141f4619c7fSThierry Reding .offset = 0x158, 142f4619c7fSThierry Reding .bytes = 4, 143f4619c7fSThierry Reding .bit_offset = 0, 144f4619c7fSThierry Reding .nbits = 32, 145f4619c7fSThierry Reding }, { 146f4619c7fSThierry Reding .name = "tsensor-mem1", 147f4619c7fSThierry Reding .offset = 0x15c, 148f4619c7fSThierry Reding .bytes = 4, 149f4619c7fSThierry Reding .bit_offset = 0, 150f4619c7fSThierry Reding .nbits = 32, 151f4619c7fSThierry Reding }, { 152f4619c7fSThierry Reding .name = "tsensor-pllx", 153f4619c7fSThierry Reding .offset = 0x160, 154f4619c7fSThierry Reding .bytes = 4, 155f4619c7fSThierry Reding .bit_offset = 0, 156f4619c7fSThierry Reding .nbits = 32, 157f4619c7fSThierry Reding }, { 158f4619c7fSThierry Reding .name = "tsensor-common", 159f4619c7fSThierry Reding .offset = 0x180, 160f4619c7fSThierry Reding .bytes = 4, 161f4619c7fSThierry Reding .bit_offset = 0, 162f4619c7fSThierry Reding .nbits = 32, 163f4619c7fSThierry Reding }, { 164f4619c7fSThierry Reding .name = "tsensor-realignment", 165f4619c7fSThierry Reding .offset = 0x1fc, 166f4619c7fSThierry Reding .bytes = 4, 167f4619c7fSThierry Reding .bit_offset = 0, 168f4619c7fSThierry Reding .nbits = 32, 169f4619c7fSThierry Reding }, { 170f4619c7fSThierry Reding .name = "gpu-calibration", 171f4619c7fSThierry Reding .offset = 0x204, 172f4619c7fSThierry Reding .bytes = 4, 173f4619c7fSThierry Reding .bit_offset = 0, 174f4619c7fSThierry Reding .nbits = 32, 175f4619c7fSThierry Reding }, { 176f4619c7fSThierry Reding .name = "xusb-pad-calibration-ext", 177f4619c7fSThierry Reding .offset = 0x250, 178f4619c7fSThierry Reding .bytes = 4, 179f4619c7fSThierry Reding .bit_offset = 0, 180f4619c7fSThierry Reding .nbits = 32, 181f4619c7fSThierry Reding }, 182f4619c7fSThierry Reding }; 183f4619c7fSThierry Reding 1847e939de1SThierry Reding static int tegra_fuse_probe(struct platform_device *pdev) 1857e939de1SThierry Reding { 1867e939de1SThierry Reding void __iomem *base = fuse->base; 18796ee12b2SThierry Reding struct nvmem_config nvmem; 1887e939de1SThierry Reding struct resource *res; 1897e939de1SThierry Reding int err; 1907e939de1SThierry Reding 1917e939de1SThierry Reding /* take over the memory region from the early initialization */ 1927e939de1SThierry Reding res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 19355a042b3SDmitry Osipenko fuse->phys = res->start; 1947e939de1SThierry Reding fuse->base = devm_ioremap_resource(&pdev->dev, res); 19551294bf6STimo Alho if (IS_ERR(fuse->base)) { 19651294bf6STimo Alho err = PTR_ERR(fuse->base); 19751294bf6STimo Alho fuse->base = base; 19851294bf6STimo Alho return err; 19951294bf6STimo Alho } 2007e939de1SThierry Reding 2017e939de1SThierry Reding fuse->clk = devm_clk_get(&pdev->dev, "fuse"); 2027e939de1SThierry Reding if (IS_ERR(fuse->clk)) { 203f0b2835fSThierry Reding if (PTR_ERR(fuse->clk) != -EPROBE_DEFER) 2047e939de1SThierry Reding dev_err(&pdev->dev, "failed to get FUSE clock: %ld", 2057e939de1SThierry Reding PTR_ERR(fuse->clk)); 206f0b2835fSThierry Reding 20751294bf6STimo Alho fuse->base = base; 2087e939de1SThierry Reding return PTR_ERR(fuse->clk); 2097e939de1SThierry Reding } 2107e939de1SThierry Reding 2117e939de1SThierry Reding platform_set_drvdata(pdev, fuse); 2127e939de1SThierry Reding fuse->dev = &pdev->dev; 2137e939de1SThierry Reding 214*24a15252SDmitry Osipenko pm_runtime_enable(&pdev->dev); 215*24a15252SDmitry Osipenko 2167e939de1SThierry Reding if (fuse->soc->probe) { 2177e939de1SThierry Reding err = fuse->soc->probe(fuse); 2189f1022b8SThierry Reding if (err < 0) 2199f1022b8SThierry Reding goto restore; 22051294bf6STimo Alho } 2217e939de1SThierry Reding 22296ee12b2SThierry Reding memset(&nvmem, 0, sizeof(nvmem)); 22396ee12b2SThierry Reding nvmem.dev = &pdev->dev; 22496ee12b2SThierry Reding nvmem.name = "fuse"; 22596ee12b2SThierry Reding nvmem.id = -1; 22696ee12b2SThierry Reding nvmem.owner = THIS_MODULE; 227f4619c7fSThierry Reding nvmem.cells = tegra_fuse_cells; 228f4619c7fSThierry Reding nvmem.ncells = ARRAY_SIZE(tegra_fuse_cells); 22996ee12b2SThierry Reding nvmem.type = NVMEM_TYPE_OTP; 23096ee12b2SThierry Reding nvmem.read_only = true; 23196ee12b2SThierry Reding nvmem.root_only = true; 23296ee12b2SThierry Reding nvmem.reg_read = tegra_fuse_read; 23396ee12b2SThierry Reding nvmem.size = fuse->soc->info->size; 23496ee12b2SThierry Reding nvmem.word_size = 4; 23596ee12b2SThierry Reding nvmem.stride = 4; 23696ee12b2SThierry Reding nvmem.priv = fuse; 23796ee12b2SThierry Reding 23896ee12b2SThierry Reding fuse->nvmem = devm_nvmem_register(&pdev->dev, &nvmem); 23996ee12b2SThierry Reding if (IS_ERR(fuse->nvmem)) { 24096ee12b2SThierry Reding err = PTR_ERR(fuse->nvmem); 24196ee12b2SThierry Reding dev_err(&pdev->dev, "failed to register NVMEM device: %d\n", 24296ee12b2SThierry Reding err); 2439f1022b8SThierry Reding goto restore; 2449f1022b8SThierry Reding } 2457e939de1SThierry Reding 2467e939de1SThierry Reding /* release the early I/O memory mapping */ 2477e939de1SThierry Reding iounmap(base); 2487e939de1SThierry Reding 2497e939de1SThierry Reding return 0; 2509f1022b8SThierry Reding 2519f1022b8SThierry Reding restore: 252a65a4ea1SDmitry Osipenko fuse->clk = NULL; 2539f1022b8SThierry Reding fuse->base = base; 254*24a15252SDmitry Osipenko pm_runtime_disable(&pdev->dev); 2559f1022b8SThierry Reding return err; 2567e939de1SThierry Reding } 2577e939de1SThierry Reding 258*24a15252SDmitry Osipenko static int __maybe_unused tegra_fuse_runtime_resume(struct device *dev) 259*24a15252SDmitry Osipenko { 260*24a15252SDmitry Osipenko int err; 261*24a15252SDmitry Osipenko 262*24a15252SDmitry Osipenko err = clk_prepare_enable(fuse->clk); 263*24a15252SDmitry Osipenko if (err < 0) { 264*24a15252SDmitry Osipenko dev_err(dev, "failed to enable FUSE clock: %d\n", err); 265*24a15252SDmitry Osipenko return err; 266*24a15252SDmitry Osipenko } 267*24a15252SDmitry Osipenko 268*24a15252SDmitry Osipenko return 0; 269*24a15252SDmitry Osipenko } 270*24a15252SDmitry Osipenko 271*24a15252SDmitry Osipenko static int __maybe_unused tegra_fuse_runtime_suspend(struct device *dev) 272*24a15252SDmitry Osipenko { 273*24a15252SDmitry Osipenko clk_disable_unprepare(fuse->clk); 274*24a15252SDmitry Osipenko 275*24a15252SDmitry Osipenko return 0; 276*24a15252SDmitry Osipenko } 277*24a15252SDmitry Osipenko 278*24a15252SDmitry Osipenko static const struct dev_pm_ops tegra_fuse_pm = { 279*24a15252SDmitry Osipenko SET_RUNTIME_PM_OPS(tegra_fuse_runtime_suspend, tegra_fuse_runtime_resume, 280*24a15252SDmitry Osipenko NULL) 281*24a15252SDmitry Osipenko }; 282*24a15252SDmitry Osipenko 2837e939de1SThierry Reding static struct platform_driver tegra_fuse_driver = { 2847e939de1SThierry Reding .driver = { 2857e939de1SThierry Reding .name = "tegra-fuse", 2867e939de1SThierry Reding .of_match_table = tegra_fuse_match, 287*24a15252SDmitry Osipenko .pm = &tegra_fuse_pm, 2887e939de1SThierry Reding .suppress_bind_attrs = true, 2897e939de1SThierry Reding }, 2907e939de1SThierry Reding .probe = tegra_fuse_probe, 2917e939de1SThierry Reding }; 2921859217bSPaul Gortmaker builtin_platform_driver(tegra_fuse_driver); 2937e939de1SThierry Reding 2947e939de1SThierry Reding bool __init tegra_fuse_read_spare(unsigned int spare) 2957e939de1SThierry Reding { 2967e939de1SThierry Reding unsigned int offset = fuse->soc->info->spare + spare * 4; 2977e939de1SThierry Reding 2987e939de1SThierry Reding return fuse->read_early(fuse, offset) & 1; 2997e939de1SThierry Reding } 3007e939de1SThierry Reding 3017e939de1SThierry Reding u32 __init tegra_fuse_read_early(unsigned int offset) 3027e939de1SThierry Reding { 3037e939de1SThierry Reding return fuse->read_early(fuse, offset); 3047e939de1SThierry Reding } 3057e939de1SThierry Reding 3067e939de1SThierry Reding int tegra_fuse_readl(unsigned long offset, u32 *value) 3077e939de1SThierry Reding { 3080a728e0bSNagarjuna Kristam if (!fuse->read || !fuse->clk) 3097e939de1SThierry Reding return -EPROBE_DEFER; 3107e939de1SThierry Reding 3110a728e0bSNagarjuna Kristam if (IS_ERR(fuse->clk)) 3120a728e0bSNagarjuna Kristam return PTR_ERR(fuse->clk); 3130a728e0bSNagarjuna Kristam 3147e939de1SThierry Reding *value = fuse->read(fuse, offset); 3157e939de1SThierry Reding 3167e939de1SThierry Reding return 0; 3177e939de1SThierry Reding } 3187e939de1SThierry Reding EXPORT_SYMBOL(tegra_fuse_readl); 3197e939de1SThierry Reding 320783c8f4cSPeter De Schrijver static void tegra_enable_fuse_clk(void __iomem *base) 321783c8f4cSPeter De Schrijver { 322783c8f4cSPeter De Schrijver u32 reg; 323783c8f4cSPeter De Schrijver 324783c8f4cSPeter De Schrijver reg = readl_relaxed(base + 0x48); 325783c8f4cSPeter De Schrijver reg |= 1 << 28; 326783c8f4cSPeter De Schrijver writel(reg, base + 0x48); 327783c8f4cSPeter De Schrijver 328783c8f4cSPeter De Schrijver /* 329783c8f4cSPeter De Schrijver * Enable FUSE clock. This needs to be hardcoded because the clock 330783c8f4cSPeter De Schrijver * subsystem is not active during early boot. 331783c8f4cSPeter De Schrijver */ 332783c8f4cSPeter De Schrijver reg = readl(base + 0x14); 333783c8f4cSPeter De Schrijver reg |= 1 << 7; 334783c8f4cSPeter De Schrijver writel(reg, base + 0x14); 335783c8f4cSPeter De Schrijver } 336783c8f4cSPeter De Schrijver 337379ac9ebSJon Hunter static ssize_t major_show(struct device *dev, struct device_attribute *attr, 338379ac9ebSJon Hunter char *buf) 339379ac9ebSJon Hunter { 340379ac9ebSJon Hunter return sprintf(buf, "%d\n", tegra_get_major_rev()); 341379ac9ebSJon Hunter } 342379ac9ebSJon Hunter 343379ac9ebSJon Hunter static DEVICE_ATTR_RO(major); 344379ac9ebSJon Hunter 345379ac9ebSJon Hunter static ssize_t minor_show(struct device *dev, struct device_attribute *attr, 346379ac9ebSJon Hunter char *buf) 347379ac9ebSJon Hunter { 348379ac9ebSJon Hunter return sprintf(buf, "%d\n", tegra_get_minor_rev()); 349379ac9ebSJon Hunter } 350379ac9ebSJon Hunter 351379ac9ebSJon Hunter static DEVICE_ATTR_RO(minor); 352379ac9ebSJon Hunter 353379ac9ebSJon Hunter static struct attribute *tegra_soc_attr[] = { 354379ac9ebSJon Hunter &dev_attr_major.attr, 355379ac9ebSJon Hunter &dev_attr_minor.attr, 356379ac9ebSJon Hunter NULL, 357379ac9ebSJon Hunter }; 358379ac9ebSJon Hunter 359379ac9ebSJon Hunter const struct attribute_group tegra_soc_attr_group = { 360379ac9ebSJon Hunter .attrs = tegra_soc_attr, 361379ac9ebSJon Hunter }; 362379ac9ebSJon Hunter 3631f44febfSThierry Reding #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \ 3641f44febfSThierry Reding IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) 365379ac9ebSJon Hunter static ssize_t platform_show(struct device *dev, struct device_attribute *attr, 366379ac9ebSJon Hunter char *buf) 367379ac9ebSJon Hunter { 368379ac9ebSJon Hunter /* 369379ac9ebSJon Hunter * Displays the value in the 'pre_si_platform' field of the HIDREV 370379ac9ebSJon Hunter * register for Tegra194 devices. A value of 0 indicates that the 371379ac9ebSJon Hunter * platform type is silicon and all other non-zero values indicate 372379ac9ebSJon Hunter * the type of simulation platform is being used. 373379ac9ebSJon Hunter */ 374775edf78SThierry Reding return sprintf(buf, "%d\n", tegra_get_platform()); 375379ac9ebSJon Hunter } 376379ac9ebSJon Hunter 377379ac9ebSJon Hunter static DEVICE_ATTR_RO(platform); 378379ac9ebSJon Hunter 379379ac9ebSJon Hunter static struct attribute *tegra194_soc_attr[] = { 380379ac9ebSJon Hunter &dev_attr_major.attr, 381379ac9ebSJon Hunter &dev_attr_minor.attr, 382379ac9ebSJon Hunter &dev_attr_platform.attr, 383379ac9ebSJon Hunter NULL, 384379ac9ebSJon Hunter }; 385379ac9ebSJon Hunter 386379ac9ebSJon Hunter const struct attribute_group tegra194_soc_attr_group = { 387379ac9ebSJon Hunter .attrs = tegra194_soc_attr, 388379ac9ebSJon Hunter }; 389379ac9ebSJon Hunter #endif 390379ac9ebSJon Hunter 39127a0342aSThierry Reding struct device * __init tegra_soc_device_register(void) 39227a0342aSThierry Reding { 39327a0342aSThierry Reding struct soc_device_attribute *attr; 39427a0342aSThierry Reding struct soc_device *dev; 39527a0342aSThierry Reding 39627a0342aSThierry Reding attr = kzalloc(sizeof(*attr), GFP_KERNEL); 39727a0342aSThierry Reding if (!attr) 39827a0342aSThierry Reding return NULL; 39927a0342aSThierry Reding 40027a0342aSThierry Reding attr->family = kasprintf(GFP_KERNEL, "Tegra"); 40137558ac8SJon Hunter attr->revision = kasprintf(GFP_KERNEL, "%s", 40237558ac8SJon Hunter tegra_revision_name[tegra_sku_info.revision]); 40327a0342aSThierry Reding attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id()); 404379ac9ebSJon Hunter attr->custom_attr_group = fuse->soc->soc_attr_group; 40527a0342aSThierry Reding 40627a0342aSThierry Reding dev = soc_device_register(attr); 40727a0342aSThierry Reding if (IS_ERR(dev)) { 40827a0342aSThierry Reding kfree(attr->soc_id); 40927a0342aSThierry Reding kfree(attr->revision); 41027a0342aSThierry Reding kfree(attr->family); 41127a0342aSThierry Reding kfree(attr); 41227a0342aSThierry Reding return ERR_CAST(dev); 41327a0342aSThierry Reding } 41427a0342aSThierry Reding 41527a0342aSThierry Reding return soc_device_to_device(dev); 41627a0342aSThierry Reding } 41727a0342aSThierry Reding 41824fa5af8SThierry Reding static int __init tegra_init_fuse(void) 419783c8f4cSPeter De Schrijver { 4207e939de1SThierry Reding const struct of_device_id *match; 421783c8f4cSPeter De Schrijver struct device_node *np; 4227e939de1SThierry Reding struct resource regs; 42324fa5af8SThierry Reding 424783c8f4cSPeter De Schrijver tegra_init_apbmisc(); 425783c8f4cSPeter De Schrijver 4267e939de1SThierry Reding np = of_find_matching_node_and_match(NULL, tegra_fuse_match, &match); 4277e939de1SThierry Reding if (!np) { 4287e939de1SThierry Reding /* 4297e939de1SThierry Reding * Fall back to legacy initialization for 32-bit ARM only. All 4307e939de1SThierry Reding * 64-bit ARM device tree files for Tegra are required to have 4317e939de1SThierry Reding * a FUSE node. 4327e939de1SThierry Reding * 4337e939de1SThierry Reding * This is for backwards-compatibility with old device trees 4347e939de1SThierry Reding * that didn't contain a FUSE node. 4357e939de1SThierry Reding */ 4367e939de1SThierry Reding if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 4377e939de1SThierry Reding u8 chip = tegra_get_chip_id(); 4387e939de1SThierry Reding 4397e939de1SThierry Reding regs.start = 0x7000f800; 4407e939de1SThierry Reding regs.end = 0x7000fbff; 4417e939de1SThierry Reding regs.flags = IORESOURCE_MEM; 4427e939de1SThierry Reding 4437e939de1SThierry Reding switch (chip) { 4447e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_2x_SOC 4457e939de1SThierry Reding case TEGRA20: 4467e939de1SThierry Reding fuse->soc = &tegra20_fuse_soc; 4477e939de1SThierry Reding break; 4487e939de1SThierry Reding #endif 4497e939de1SThierry Reding 4507e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_3x_SOC 4517e939de1SThierry Reding case TEGRA30: 4527e939de1SThierry Reding fuse->soc = &tegra30_fuse_soc; 4537e939de1SThierry Reding break; 4547e939de1SThierry Reding #endif 4557e939de1SThierry Reding 4567e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_114_SOC 4577e939de1SThierry Reding case TEGRA114: 4587e939de1SThierry Reding fuse->soc = &tegra114_fuse_soc; 4597e939de1SThierry Reding break; 4607e939de1SThierry Reding #endif 4617e939de1SThierry Reding 4627e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_124_SOC 4637e939de1SThierry Reding case TEGRA124: 4647e939de1SThierry Reding fuse->soc = &tegra124_fuse_soc; 4657e939de1SThierry Reding break; 4667e939de1SThierry Reding #endif 4677e939de1SThierry Reding 4687e939de1SThierry Reding default: 4697e939de1SThierry Reding pr_warn("Unsupported SoC: %02x\n", chip); 4707e939de1SThierry Reding break; 4717e939de1SThierry Reding } 472783c8f4cSPeter De Schrijver } else { 4737e939de1SThierry Reding /* 4747e939de1SThierry Reding * At this point we're not running on Tegra, so play 4757e939de1SThierry Reding * nice with multi-platform kernels. 4767e939de1SThierry Reding */ 4777e939de1SThierry Reding return 0; 4787e939de1SThierry Reding } 4797e939de1SThierry Reding } else { 4807e939de1SThierry Reding /* 4817e939de1SThierry Reding * Extract information from the device tree if we've found a 4827e939de1SThierry Reding * matching node. 4837e939de1SThierry Reding */ 4847e939de1SThierry Reding if (of_address_to_resource(np, 0, ®s) < 0) { 4857e939de1SThierry Reding pr_err("failed to get FUSE register\n"); 48624fa5af8SThierry Reding return -ENXIO; 487783c8f4cSPeter De Schrijver } 488783c8f4cSPeter De Schrijver 4897e939de1SThierry Reding fuse->soc = match->data; 4907e939de1SThierry Reding } 4917e939de1SThierry Reding 4927e939de1SThierry Reding np = of_find_matching_node(NULL, car_match); 4937e939de1SThierry Reding if (np) { 4947e939de1SThierry Reding void __iomem *base = of_iomap(np, 0); 4957e939de1SThierry Reding if (base) { 4967e939de1SThierry Reding tegra_enable_fuse_clk(base); 4977e939de1SThierry Reding iounmap(base); 4987e939de1SThierry Reding } else { 4997e939de1SThierry Reding pr_err("failed to map clock registers\n"); 5007e939de1SThierry Reding return -ENXIO; 5017e939de1SThierry Reding } 5027e939de1SThierry Reding } 5037e939de1SThierry Reding 5044bdc0d67SChristoph Hellwig fuse->base = ioremap(regs.start, resource_size(®s)); 5057e939de1SThierry Reding if (!fuse->base) { 5067e939de1SThierry Reding pr_err("failed to map FUSE registers\n"); 5077e939de1SThierry Reding return -ENXIO; 5087e939de1SThierry Reding } 5097e939de1SThierry Reding 5107e939de1SThierry Reding fuse->soc->init(fuse); 511783c8f4cSPeter De Schrijver 51203b3f4c8SThierry Reding pr_info("Tegra Revision: %s SKU: %d CPU Process: %d SoC Process: %d\n", 513783c8f4cSPeter De Schrijver tegra_revision_name[tegra_sku_info.revision], 514783c8f4cSPeter De Schrijver tegra_sku_info.sku_id, tegra_sku_info.cpu_process_id, 51503b3f4c8SThierry Reding tegra_sku_info.soc_process_id); 51603b3f4c8SThierry Reding pr_debug("Tegra CPU Speedo ID %d, SoC Speedo ID %d\n", 517783c8f4cSPeter De Schrijver tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id); 51824fa5af8SThierry Reding 5199f94faddSThierry Reding if (fuse->soc->lookups) { 5209f94faddSThierry Reding size_t size = sizeof(*fuse->lookups) * fuse->soc->num_lookups; 5219f94faddSThierry Reding 5229f94faddSThierry Reding fuse->lookups = kmemdup(fuse->soc->lookups, size, GFP_KERNEL); 523854d128bSYang Yingliang if (fuse->lookups) 5249f94faddSThierry Reding nvmem_add_cell_lookups(fuse->lookups, fuse->soc->num_lookups); 5259f94faddSThierry Reding } 52627a0342aSThierry Reding 52724fa5af8SThierry Reding return 0; 528783c8f4cSPeter De Schrijver } 52924fa5af8SThierry Reding early_initcall(tegra_init_fuse); 53027a0342aSThierry Reding 53127a0342aSThierry Reding #ifdef CONFIG_ARM64 53227a0342aSThierry Reding static int __init tegra_init_soc(void) 53327a0342aSThierry Reding { 534226cff48SThierry Reding struct device_node *np; 53527a0342aSThierry Reding struct device *soc; 53627a0342aSThierry Reding 537226cff48SThierry Reding /* make sure we're running on Tegra */ 538226cff48SThierry Reding np = of_find_matching_node(NULL, tegra_fuse_match); 539226cff48SThierry Reding if (!np) 540226cff48SThierry Reding return 0; 541226cff48SThierry Reding 542226cff48SThierry Reding of_node_put(np); 543226cff48SThierry Reding 54427a0342aSThierry Reding soc = tegra_soc_device_register(); 54527a0342aSThierry Reding if (IS_ERR(soc)) { 54627a0342aSThierry Reding pr_err("failed to register SoC device: %ld\n", PTR_ERR(soc)); 54727a0342aSThierry Reding return PTR_ERR(soc); 54827a0342aSThierry Reding } 54927a0342aSThierry Reding 55027a0342aSThierry Reding return 0; 55127a0342aSThierry Reding } 5529261b43eSThierry Reding device_initcall(tegra_init_soc); 55327a0342aSThierry Reding #endif 554