19952f691SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2783c8f4cSPeter De Schrijver /* 3783c8f4cSPeter De Schrijver * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. 4783c8f4cSPeter De Schrijver */ 5783c8f4cSPeter De Schrijver 67e939de1SThierry Reding #include <linux/clk.h> 7783c8f4cSPeter De Schrijver #include <linux/device.h> 8783c8f4cSPeter De Schrijver #include <linux/kobject.h> 91859217bSPaul Gortmaker #include <linux/init.h> 1027a0342aSThierry Reding #include <linux/io.h> 11783c8f4cSPeter De Schrijver #include <linux/of.h> 12783c8f4cSPeter De Schrijver #include <linux/of_address.h> 1327a0342aSThierry Reding #include <linux/platform_device.h> 1427a0342aSThierry Reding #include <linux/slab.h> 1527a0342aSThierry Reding #include <linux/sys_soc.h> 16783c8f4cSPeter De Schrijver 1724fa5af8SThierry Reding #include <soc/tegra/common.h> 18783c8f4cSPeter De Schrijver #include <soc/tegra/fuse.h> 19783c8f4cSPeter De Schrijver 20783c8f4cSPeter De Schrijver #include "fuse.h" 21783c8f4cSPeter De Schrijver 22783c8f4cSPeter De Schrijver struct tegra_sku_info tegra_sku_info; 23f9fc3661SVince Hsu EXPORT_SYMBOL(tegra_sku_info); 24783c8f4cSPeter De Schrijver 25783c8f4cSPeter De Schrijver static const char *tegra_revision_name[TEGRA_REVISION_MAX] = { 26783c8f4cSPeter De Schrijver [TEGRA_REVISION_UNKNOWN] = "unknown", 27783c8f4cSPeter De Schrijver [TEGRA_REVISION_A01] = "A01", 28783c8f4cSPeter De Schrijver [TEGRA_REVISION_A02] = "A02", 29783c8f4cSPeter De Schrijver [TEGRA_REVISION_A03] = "A03", 30783c8f4cSPeter De Schrijver [TEGRA_REVISION_A03p] = "A03 prime", 31783c8f4cSPeter De Schrijver [TEGRA_REVISION_A04] = "A04", 32783c8f4cSPeter De Schrijver }; 33783c8f4cSPeter De Schrijver 347e939de1SThierry Reding static u8 fuse_readb(struct tegra_fuse *fuse, unsigned int offset) 35783c8f4cSPeter De Schrijver { 36783c8f4cSPeter De Schrijver u32 val; 37783c8f4cSPeter De Schrijver 387e939de1SThierry Reding val = fuse->read(fuse, round_down(offset, 4)); 39783c8f4cSPeter De Schrijver val >>= (offset % 4) * 8; 40783c8f4cSPeter De Schrijver val &= 0xff; 41783c8f4cSPeter De Schrijver 42783c8f4cSPeter De Schrijver return val; 43783c8f4cSPeter De Schrijver } 44783c8f4cSPeter De Schrijver 45783c8f4cSPeter De Schrijver static ssize_t fuse_read(struct file *fd, struct kobject *kobj, 46783c8f4cSPeter De Schrijver struct bin_attribute *attr, char *buf, 47783c8f4cSPeter De Schrijver loff_t pos, size_t size) 48783c8f4cSPeter De Schrijver { 497e939de1SThierry Reding struct device *dev = kobj_to_dev(kobj); 507e939de1SThierry Reding struct tegra_fuse *fuse = dev_get_drvdata(dev); 51783c8f4cSPeter De Schrijver int i; 52783c8f4cSPeter De Schrijver 537e939de1SThierry Reding if (pos < 0 || pos >= attr->size) 54783c8f4cSPeter De Schrijver return 0; 55783c8f4cSPeter De Schrijver 567e939de1SThierry Reding if (size > attr->size - pos) 577e939de1SThierry Reding size = attr->size - pos; 58783c8f4cSPeter De Schrijver 59783c8f4cSPeter De Schrijver for (i = 0; i < size; i++) 607e939de1SThierry Reding buf[i] = fuse_readb(fuse, pos + i); 61783c8f4cSPeter De Schrijver 62783c8f4cSPeter De Schrijver return i; 63783c8f4cSPeter De Schrijver } 64783c8f4cSPeter De Schrijver 65783c8f4cSPeter De Schrijver static struct bin_attribute fuse_bin_attr = { 66783c8f4cSPeter De Schrijver .attr = { .name = "fuse", .mode = S_IRUGO, }, 67783c8f4cSPeter De Schrijver .read = fuse_read, 68783c8f4cSPeter De Schrijver }; 69783c8f4cSPeter De Schrijver 707e939de1SThierry Reding static int tegra_fuse_create_sysfs(struct device *dev, unsigned int size, 717e939de1SThierry Reding const struct tegra_fuse_info *info) 727e939de1SThierry Reding { 737e939de1SThierry Reding fuse_bin_attr.size = size; 747e939de1SThierry Reding 757e939de1SThierry Reding return device_create_bin_file(dev, &fuse_bin_attr); 767e939de1SThierry Reding } 777e939de1SThierry Reding 78783c8f4cSPeter De Schrijver static const struct of_device_id car_match[] __initconst = { 79783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra20-car", }, 80783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra30-car", }, 81783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra114-car", }, 82783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra124-car", }, 839b07eb05SThierry Reding { .compatible = "nvidia,tegra132-car", }, 840dc5a0d8SThierry Reding { .compatible = "nvidia,tegra210-car", }, 85783c8f4cSPeter De Schrijver {}, 86783c8f4cSPeter De Schrijver }; 87783c8f4cSPeter De Schrijver 887e939de1SThierry Reding static struct tegra_fuse *fuse = &(struct tegra_fuse) { 897e939de1SThierry Reding .base = NULL, 907e939de1SThierry Reding .soc = NULL, 917e939de1SThierry Reding }; 927e939de1SThierry Reding 937e939de1SThierry Reding static const struct of_device_id tegra_fuse_match[] = { 9483468fe2STimo Alho #ifdef CONFIG_ARCH_TEGRA_186_SOC 9583468fe2STimo Alho { .compatible = "nvidia,tegra186-efuse", .data = &tegra186_fuse_soc }, 9683468fe2STimo Alho #endif 970dc5a0d8SThierry Reding #ifdef CONFIG_ARCH_TEGRA_210_SOC 980dc5a0d8SThierry Reding { .compatible = "nvidia,tegra210-efuse", .data = &tegra210_fuse_soc }, 990dc5a0d8SThierry Reding #endif 1007e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_132_SOC 1017e939de1SThierry Reding { .compatible = "nvidia,tegra132-efuse", .data = &tegra124_fuse_soc }, 1027e939de1SThierry Reding #endif 1037e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_124_SOC 1047e939de1SThierry Reding { .compatible = "nvidia,tegra124-efuse", .data = &tegra124_fuse_soc }, 1057e939de1SThierry Reding #endif 1067e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_114_SOC 1077e939de1SThierry Reding { .compatible = "nvidia,tegra114-efuse", .data = &tegra114_fuse_soc }, 1087e939de1SThierry Reding #endif 1097e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_3x_SOC 1107e939de1SThierry Reding { .compatible = "nvidia,tegra30-efuse", .data = &tegra30_fuse_soc }, 1117e939de1SThierry Reding #endif 1127e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_2x_SOC 1137e939de1SThierry Reding { .compatible = "nvidia,tegra20-efuse", .data = &tegra20_fuse_soc }, 1147e939de1SThierry Reding #endif 1157e939de1SThierry Reding { /* sentinel */ } 1167e939de1SThierry Reding }; 1177e939de1SThierry Reding 1187e939de1SThierry Reding static int tegra_fuse_probe(struct platform_device *pdev) 1197e939de1SThierry Reding { 1207e939de1SThierry Reding void __iomem *base = fuse->base; 1217e939de1SThierry Reding struct resource *res; 1227e939de1SThierry Reding int err; 1237e939de1SThierry Reding 1247e939de1SThierry Reding /* take over the memory region from the early initialization */ 1257e939de1SThierry Reding res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 12655a042b3SDmitry Osipenko fuse->phys = res->start; 1277e939de1SThierry Reding fuse->base = devm_ioremap_resource(&pdev->dev, res); 12851294bf6STimo Alho if (IS_ERR(fuse->base)) { 12951294bf6STimo Alho err = PTR_ERR(fuse->base); 13051294bf6STimo Alho fuse->base = base; 13151294bf6STimo Alho return err; 13251294bf6STimo Alho } 1337e939de1SThierry Reding 1347e939de1SThierry Reding fuse->clk = devm_clk_get(&pdev->dev, "fuse"); 1357e939de1SThierry Reding if (IS_ERR(fuse->clk)) { 136f0b2835fSThierry Reding if (PTR_ERR(fuse->clk) != -EPROBE_DEFER) 1377e939de1SThierry Reding dev_err(&pdev->dev, "failed to get FUSE clock: %ld", 1387e939de1SThierry Reding PTR_ERR(fuse->clk)); 139f0b2835fSThierry Reding 14051294bf6STimo Alho fuse->base = base; 1417e939de1SThierry Reding return PTR_ERR(fuse->clk); 1427e939de1SThierry Reding } 1437e939de1SThierry Reding 1447e939de1SThierry Reding platform_set_drvdata(pdev, fuse); 1457e939de1SThierry Reding fuse->dev = &pdev->dev; 1467e939de1SThierry Reding 1477e939de1SThierry Reding if (fuse->soc->probe) { 1487e939de1SThierry Reding err = fuse->soc->probe(fuse); 14951294bf6STimo Alho if (err < 0) { 15051294bf6STimo Alho fuse->base = base; 1517e939de1SThierry Reding return err; 1527e939de1SThierry Reding } 15351294bf6STimo Alho } 1547e939de1SThierry Reding 1557e939de1SThierry Reding if (tegra_fuse_create_sysfs(&pdev->dev, fuse->soc->info->size, 1567e939de1SThierry Reding fuse->soc->info)) 1577e939de1SThierry Reding return -ENODEV; 1587e939de1SThierry Reding 1597e939de1SThierry Reding /* release the early I/O memory mapping */ 1607e939de1SThierry Reding iounmap(base); 1617e939de1SThierry Reding 1627e939de1SThierry Reding return 0; 1637e939de1SThierry Reding } 1647e939de1SThierry Reding 1657e939de1SThierry Reding static struct platform_driver tegra_fuse_driver = { 1667e939de1SThierry Reding .driver = { 1677e939de1SThierry Reding .name = "tegra-fuse", 1687e939de1SThierry Reding .of_match_table = tegra_fuse_match, 1697e939de1SThierry Reding .suppress_bind_attrs = true, 1707e939de1SThierry Reding }, 1717e939de1SThierry Reding .probe = tegra_fuse_probe, 1727e939de1SThierry Reding }; 1731859217bSPaul Gortmaker builtin_platform_driver(tegra_fuse_driver); 1747e939de1SThierry Reding 1757e939de1SThierry Reding bool __init tegra_fuse_read_spare(unsigned int spare) 1767e939de1SThierry Reding { 1777e939de1SThierry Reding unsigned int offset = fuse->soc->info->spare + spare * 4; 1787e939de1SThierry Reding 1797e939de1SThierry Reding return fuse->read_early(fuse, offset) & 1; 1807e939de1SThierry Reding } 1817e939de1SThierry Reding 1827e939de1SThierry Reding u32 __init tegra_fuse_read_early(unsigned int offset) 1837e939de1SThierry Reding { 1847e939de1SThierry Reding return fuse->read_early(fuse, offset); 1857e939de1SThierry Reding } 1867e939de1SThierry Reding 1877e939de1SThierry Reding int tegra_fuse_readl(unsigned long offset, u32 *value) 1887e939de1SThierry Reding { 189*0a728e0bSNagarjuna Kristam if (!fuse->read || !fuse->clk) 1907e939de1SThierry Reding return -EPROBE_DEFER; 1917e939de1SThierry Reding 192*0a728e0bSNagarjuna Kristam if (IS_ERR(fuse->clk)) 193*0a728e0bSNagarjuna Kristam return PTR_ERR(fuse->clk); 194*0a728e0bSNagarjuna Kristam 1957e939de1SThierry Reding *value = fuse->read(fuse, offset); 1967e939de1SThierry Reding 1977e939de1SThierry Reding return 0; 1987e939de1SThierry Reding } 1997e939de1SThierry Reding EXPORT_SYMBOL(tegra_fuse_readl); 2007e939de1SThierry Reding 201783c8f4cSPeter De Schrijver static void tegra_enable_fuse_clk(void __iomem *base) 202783c8f4cSPeter De Schrijver { 203783c8f4cSPeter De Schrijver u32 reg; 204783c8f4cSPeter De Schrijver 205783c8f4cSPeter De Schrijver reg = readl_relaxed(base + 0x48); 206783c8f4cSPeter De Schrijver reg |= 1 << 28; 207783c8f4cSPeter De Schrijver writel(reg, base + 0x48); 208783c8f4cSPeter De Schrijver 209783c8f4cSPeter De Schrijver /* 210783c8f4cSPeter De Schrijver * Enable FUSE clock. This needs to be hardcoded because the clock 211783c8f4cSPeter De Schrijver * subsystem is not active during early boot. 212783c8f4cSPeter De Schrijver */ 213783c8f4cSPeter De Schrijver reg = readl(base + 0x14); 214783c8f4cSPeter De Schrijver reg |= 1 << 7; 215783c8f4cSPeter De Schrijver writel(reg, base + 0x14); 216783c8f4cSPeter De Schrijver } 217783c8f4cSPeter De Schrijver 21827a0342aSThierry Reding struct device * __init tegra_soc_device_register(void) 21927a0342aSThierry Reding { 22027a0342aSThierry Reding struct soc_device_attribute *attr; 22127a0342aSThierry Reding struct soc_device *dev; 22227a0342aSThierry Reding 22327a0342aSThierry Reding attr = kzalloc(sizeof(*attr), GFP_KERNEL); 22427a0342aSThierry Reding if (!attr) 22527a0342aSThierry Reding return NULL; 22627a0342aSThierry Reding 22727a0342aSThierry Reding attr->family = kasprintf(GFP_KERNEL, "Tegra"); 22827a0342aSThierry Reding attr->revision = kasprintf(GFP_KERNEL, "%d", tegra_sku_info.revision); 22927a0342aSThierry Reding attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id()); 23027a0342aSThierry Reding 23127a0342aSThierry Reding dev = soc_device_register(attr); 23227a0342aSThierry Reding if (IS_ERR(dev)) { 23327a0342aSThierry Reding kfree(attr->soc_id); 23427a0342aSThierry Reding kfree(attr->revision); 23527a0342aSThierry Reding kfree(attr->family); 23627a0342aSThierry Reding kfree(attr); 23727a0342aSThierry Reding return ERR_CAST(dev); 23827a0342aSThierry Reding } 23927a0342aSThierry Reding 24027a0342aSThierry Reding return soc_device_to_device(dev); 24127a0342aSThierry Reding } 24227a0342aSThierry Reding 24324fa5af8SThierry Reding static int __init tegra_init_fuse(void) 244783c8f4cSPeter De Schrijver { 2457e939de1SThierry Reding const struct of_device_id *match; 246783c8f4cSPeter De Schrijver struct device_node *np; 2477e939de1SThierry Reding struct resource regs; 24824fa5af8SThierry Reding 249783c8f4cSPeter De Schrijver tegra_init_apbmisc(); 250783c8f4cSPeter De Schrijver 2517e939de1SThierry Reding np = of_find_matching_node_and_match(NULL, tegra_fuse_match, &match); 2527e939de1SThierry Reding if (!np) { 2537e939de1SThierry Reding /* 2547e939de1SThierry Reding * Fall back to legacy initialization for 32-bit ARM only. All 2557e939de1SThierry Reding * 64-bit ARM device tree files for Tegra are required to have 2567e939de1SThierry Reding * a FUSE node. 2577e939de1SThierry Reding * 2587e939de1SThierry Reding * This is for backwards-compatibility with old device trees 2597e939de1SThierry Reding * that didn't contain a FUSE node. 2607e939de1SThierry Reding */ 2617e939de1SThierry Reding if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 2627e939de1SThierry Reding u8 chip = tegra_get_chip_id(); 2637e939de1SThierry Reding 2647e939de1SThierry Reding regs.start = 0x7000f800; 2657e939de1SThierry Reding regs.end = 0x7000fbff; 2667e939de1SThierry Reding regs.flags = IORESOURCE_MEM; 2677e939de1SThierry Reding 2687e939de1SThierry Reding switch (chip) { 2697e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_2x_SOC 2707e939de1SThierry Reding case TEGRA20: 2717e939de1SThierry Reding fuse->soc = &tegra20_fuse_soc; 2727e939de1SThierry Reding break; 2737e939de1SThierry Reding #endif 2747e939de1SThierry Reding 2757e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_3x_SOC 2767e939de1SThierry Reding case TEGRA30: 2777e939de1SThierry Reding fuse->soc = &tegra30_fuse_soc; 2787e939de1SThierry Reding break; 2797e939de1SThierry Reding #endif 2807e939de1SThierry Reding 2817e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_114_SOC 2827e939de1SThierry Reding case TEGRA114: 2837e939de1SThierry Reding fuse->soc = &tegra114_fuse_soc; 2847e939de1SThierry Reding break; 2857e939de1SThierry Reding #endif 2867e939de1SThierry Reding 2877e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_124_SOC 2887e939de1SThierry Reding case TEGRA124: 2897e939de1SThierry Reding fuse->soc = &tegra124_fuse_soc; 2907e939de1SThierry Reding break; 2917e939de1SThierry Reding #endif 2927e939de1SThierry Reding 2937e939de1SThierry Reding default: 2947e939de1SThierry Reding pr_warn("Unsupported SoC: %02x\n", chip); 2957e939de1SThierry Reding break; 2967e939de1SThierry Reding } 297783c8f4cSPeter De Schrijver } else { 2987e939de1SThierry Reding /* 2997e939de1SThierry Reding * At this point we're not running on Tegra, so play 3007e939de1SThierry Reding * nice with multi-platform kernels. 3017e939de1SThierry Reding */ 3027e939de1SThierry Reding return 0; 3037e939de1SThierry Reding } 3047e939de1SThierry Reding } else { 3057e939de1SThierry Reding /* 3067e939de1SThierry Reding * Extract information from the device tree if we've found a 3077e939de1SThierry Reding * matching node. 3087e939de1SThierry Reding */ 3097e939de1SThierry Reding if (of_address_to_resource(np, 0, ®s) < 0) { 3107e939de1SThierry Reding pr_err("failed to get FUSE register\n"); 31124fa5af8SThierry Reding return -ENXIO; 312783c8f4cSPeter De Schrijver } 313783c8f4cSPeter De Schrijver 3147e939de1SThierry Reding fuse->soc = match->data; 3157e939de1SThierry Reding } 3167e939de1SThierry Reding 3177e939de1SThierry Reding np = of_find_matching_node(NULL, car_match); 3187e939de1SThierry Reding if (np) { 3197e939de1SThierry Reding void __iomem *base = of_iomap(np, 0); 3207e939de1SThierry Reding if (base) { 3217e939de1SThierry Reding tegra_enable_fuse_clk(base); 3227e939de1SThierry Reding iounmap(base); 3237e939de1SThierry Reding } else { 3247e939de1SThierry Reding pr_err("failed to map clock registers\n"); 3257e939de1SThierry Reding return -ENXIO; 3267e939de1SThierry Reding } 3277e939de1SThierry Reding } 3287e939de1SThierry Reding 3297e939de1SThierry Reding fuse->base = ioremap_nocache(regs.start, resource_size(®s)); 3307e939de1SThierry Reding if (!fuse->base) { 3317e939de1SThierry Reding pr_err("failed to map FUSE registers\n"); 3327e939de1SThierry Reding return -ENXIO; 3337e939de1SThierry Reding } 3347e939de1SThierry Reding 3357e939de1SThierry Reding fuse->soc->init(fuse); 336783c8f4cSPeter De Schrijver 33703b3f4c8SThierry Reding pr_info("Tegra Revision: %s SKU: %d CPU Process: %d SoC Process: %d\n", 338783c8f4cSPeter De Schrijver tegra_revision_name[tegra_sku_info.revision], 339783c8f4cSPeter De Schrijver tegra_sku_info.sku_id, tegra_sku_info.cpu_process_id, 34003b3f4c8SThierry Reding tegra_sku_info.soc_process_id); 34103b3f4c8SThierry Reding pr_debug("Tegra CPU Speedo ID %d, SoC Speedo ID %d\n", 342783c8f4cSPeter De Schrijver tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id); 34324fa5af8SThierry Reding 34427a0342aSThierry Reding 34524fa5af8SThierry Reding return 0; 346783c8f4cSPeter De Schrijver } 34724fa5af8SThierry Reding early_initcall(tegra_init_fuse); 34827a0342aSThierry Reding 34927a0342aSThierry Reding #ifdef CONFIG_ARM64 35027a0342aSThierry Reding static int __init tegra_init_soc(void) 35127a0342aSThierry Reding { 352226cff48SThierry Reding struct device_node *np; 35327a0342aSThierry Reding struct device *soc; 35427a0342aSThierry Reding 355226cff48SThierry Reding /* make sure we're running on Tegra */ 356226cff48SThierry Reding np = of_find_matching_node(NULL, tegra_fuse_match); 357226cff48SThierry Reding if (!np) 358226cff48SThierry Reding return 0; 359226cff48SThierry Reding 360226cff48SThierry Reding of_node_put(np); 361226cff48SThierry Reding 36227a0342aSThierry Reding soc = tegra_soc_device_register(); 36327a0342aSThierry Reding if (IS_ERR(soc)) { 36427a0342aSThierry Reding pr_err("failed to register SoC device: %ld\n", PTR_ERR(soc)); 36527a0342aSThierry Reding return PTR_ERR(soc); 36627a0342aSThierry Reding } 36727a0342aSThierry Reding 36827a0342aSThierry Reding return 0; 36927a0342aSThierry Reding } 3709261b43eSThierry Reding device_initcall(tegra_init_soc); 37127a0342aSThierry Reding #endif 372