1783c8f4cSPeter De Schrijver /* 2783c8f4cSPeter De Schrijver * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. 3783c8f4cSPeter De Schrijver * 4783c8f4cSPeter De Schrijver * This program is free software; you can redistribute it and/or modify it 5783c8f4cSPeter De Schrijver * under the terms and conditions of the GNU General Public License, 6783c8f4cSPeter De Schrijver * version 2, as published by the Free Software Foundation. 7783c8f4cSPeter De Schrijver * 8783c8f4cSPeter De Schrijver * This program is distributed in the hope it will be useful, but WITHOUT 9783c8f4cSPeter De Schrijver * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10783c8f4cSPeter De Schrijver * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11783c8f4cSPeter De Schrijver * more details. 12783c8f4cSPeter De Schrijver * 13783c8f4cSPeter De Schrijver * You should have received a copy of the GNU General Public License 14783c8f4cSPeter De Schrijver * along with this program. If not, see <http://www.gnu.org/licenses/>. 15783c8f4cSPeter De Schrijver * 16783c8f4cSPeter De Schrijver */ 17783c8f4cSPeter De Schrijver 187e939de1SThierry Reding #include <linux/clk.h> 19783c8f4cSPeter De Schrijver #include <linux/device.h> 20783c8f4cSPeter De Schrijver #include <linux/kobject.h> 217e939de1SThierry Reding #include <linux/module.h> 22783c8f4cSPeter De Schrijver #include <linux/platform_device.h> 23783c8f4cSPeter De Schrijver #include <linux/of.h> 24783c8f4cSPeter De Schrijver #include <linux/of_address.h> 25783c8f4cSPeter De Schrijver #include <linux/io.h> 26783c8f4cSPeter De Schrijver 2724fa5af8SThierry Reding #include <soc/tegra/common.h> 28783c8f4cSPeter De Schrijver #include <soc/tegra/fuse.h> 29783c8f4cSPeter De Schrijver 30783c8f4cSPeter De Schrijver #include "fuse.h" 31783c8f4cSPeter De Schrijver 32783c8f4cSPeter De Schrijver struct tegra_sku_info tegra_sku_info; 33f9fc3661SVince Hsu EXPORT_SYMBOL(tegra_sku_info); 34783c8f4cSPeter De Schrijver 35783c8f4cSPeter De Schrijver static const char *tegra_revision_name[TEGRA_REVISION_MAX] = { 36783c8f4cSPeter De Schrijver [TEGRA_REVISION_UNKNOWN] = "unknown", 37783c8f4cSPeter De Schrijver [TEGRA_REVISION_A01] = "A01", 38783c8f4cSPeter De Schrijver [TEGRA_REVISION_A02] = "A02", 39783c8f4cSPeter De Schrijver [TEGRA_REVISION_A03] = "A03", 40783c8f4cSPeter De Schrijver [TEGRA_REVISION_A03p] = "A03 prime", 41783c8f4cSPeter De Schrijver [TEGRA_REVISION_A04] = "A04", 42783c8f4cSPeter De Schrijver }; 43783c8f4cSPeter De Schrijver 447e939de1SThierry Reding static u8 fuse_readb(struct tegra_fuse *fuse, unsigned int offset) 45783c8f4cSPeter De Schrijver { 46783c8f4cSPeter De Schrijver u32 val; 47783c8f4cSPeter De Schrijver 487e939de1SThierry Reding val = fuse->read(fuse, round_down(offset, 4)); 49783c8f4cSPeter De Schrijver val >>= (offset % 4) * 8; 50783c8f4cSPeter De Schrijver val &= 0xff; 51783c8f4cSPeter De Schrijver 52783c8f4cSPeter De Schrijver return val; 53783c8f4cSPeter De Schrijver } 54783c8f4cSPeter De Schrijver 55783c8f4cSPeter De Schrijver static ssize_t fuse_read(struct file *fd, struct kobject *kobj, 56783c8f4cSPeter De Schrijver struct bin_attribute *attr, char *buf, 57783c8f4cSPeter De Schrijver loff_t pos, size_t size) 58783c8f4cSPeter De Schrijver { 597e939de1SThierry Reding struct device *dev = kobj_to_dev(kobj); 607e939de1SThierry Reding struct tegra_fuse *fuse = dev_get_drvdata(dev); 61783c8f4cSPeter De Schrijver int i; 62783c8f4cSPeter De Schrijver 637e939de1SThierry Reding if (pos < 0 || pos >= attr->size) 64783c8f4cSPeter De Schrijver return 0; 65783c8f4cSPeter De Schrijver 667e939de1SThierry Reding if (size > attr->size - pos) 677e939de1SThierry Reding size = attr->size - pos; 68783c8f4cSPeter De Schrijver 69783c8f4cSPeter De Schrijver for (i = 0; i < size; i++) 707e939de1SThierry Reding buf[i] = fuse_readb(fuse, pos + i); 71783c8f4cSPeter De Schrijver 72783c8f4cSPeter De Schrijver return i; 73783c8f4cSPeter De Schrijver } 74783c8f4cSPeter De Schrijver 75783c8f4cSPeter De Schrijver static struct bin_attribute fuse_bin_attr = { 76783c8f4cSPeter De Schrijver .attr = { .name = "fuse", .mode = S_IRUGO, }, 77783c8f4cSPeter De Schrijver .read = fuse_read, 78783c8f4cSPeter De Schrijver }; 79783c8f4cSPeter De Schrijver 807e939de1SThierry Reding static int tegra_fuse_create_sysfs(struct device *dev, unsigned int size, 817e939de1SThierry Reding const struct tegra_fuse_info *info) 827e939de1SThierry Reding { 837e939de1SThierry Reding fuse_bin_attr.size = size; 847e939de1SThierry Reding 857e939de1SThierry Reding return device_create_bin_file(dev, &fuse_bin_attr); 867e939de1SThierry Reding } 877e939de1SThierry Reding 88783c8f4cSPeter De Schrijver static const struct of_device_id car_match[] __initconst = { 89783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra20-car", }, 90783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra30-car", }, 91783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra114-car", }, 92783c8f4cSPeter De Schrijver { .compatible = "nvidia,tegra124-car", }, 939b07eb05SThierry Reding { .compatible = "nvidia,tegra132-car", }, 940dc5a0d8SThierry Reding { .compatible = "nvidia,tegra210-car", }, 95783c8f4cSPeter De Schrijver {}, 96783c8f4cSPeter De Schrijver }; 97783c8f4cSPeter De Schrijver 987e939de1SThierry Reding static struct tegra_fuse *fuse = &(struct tegra_fuse) { 997e939de1SThierry Reding .base = NULL, 1007e939de1SThierry Reding .soc = NULL, 1017e939de1SThierry Reding }; 1027e939de1SThierry Reding 1037e939de1SThierry Reding static const struct of_device_id tegra_fuse_match[] = { 1040dc5a0d8SThierry Reding #ifdef CONFIG_ARCH_TEGRA_210_SOC 1050dc5a0d8SThierry Reding { .compatible = "nvidia,tegra210-efuse", .data = &tegra210_fuse_soc }, 1060dc5a0d8SThierry Reding #endif 1077e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_132_SOC 1087e939de1SThierry Reding { .compatible = "nvidia,tegra132-efuse", .data = &tegra124_fuse_soc }, 1097e939de1SThierry Reding #endif 1107e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_124_SOC 1117e939de1SThierry Reding { .compatible = "nvidia,tegra124-efuse", .data = &tegra124_fuse_soc }, 1127e939de1SThierry Reding #endif 1137e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_114_SOC 1147e939de1SThierry Reding { .compatible = "nvidia,tegra114-efuse", .data = &tegra114_fuse_soc }, 1157e939de1SThierry Reding #endif 1167e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_3x_SOC 1177e939de1SThierry Reding { .compatible = "nvidia,tegra30-efuse", .data = &tegra30_fuse_soc }, 1187e939de1SThierry Reding #endif 1197e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_2x_SOC 1207e939de1SThierry Reding { .compatible = "nvidia,tegra20-efuse", .data = &tegra20_fuse_soc }, 1217e939de1SThierry Reding #endif 1227e939de1SThierry Reding { /* sentinel */ } 1237e939de1SThierry Reding }; 1247e939de1SThierry Reding 1257e939de1SThierry Reding static int tegra_fuse_probe(struct platform_device *pdev) 1267e939de1SThierry Reding { 1277e939de1SThierry Reding void __iomem *base = fuse->base; 1287e939de1SThierry Reding struct resource *res; 1297e939de1SThierry Reding int err; 1307e939de1SThierry Reding 1317e939de1SThierry Reding /* take over the memory region from the early initialization */ 1327e939de1SThierry Reding res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1337e939de1SThierry Reding fuse->base = devm_ioremap_resource(&pdev->dev, res); 1347e939de1SThierry Reding if (IS_ERR(fuse->base)) 1357e939de1SThierry Reding return PTR_ERR(fuse->base); 1367e939de1SThierry Reding 1377e939de1SThierry Reding fuse->clk = devm_clk_get(&pdev->dev, "fuse"); 1387e939de1SThierry Reding if (IS_ERR(fuse->clk)) { 1397e939de1SThierry Reding dev_err(&pdev->dev, "failed to get FUSE clock: %ld", 1407e939de1SThierry Reding PTR_ERR(fuse->clk)); 1417e939de1SThierry Reding return PTR_ERR(fuse->clk); 1427e939de1SThierry Reding } 1437e939de1SThierry Reding 1447e939de1SThierry Reding platform_set_drvdata(pdev, fuse); 1457e939de1SThierry Reding fuse->dev = &pdev->dev; 1467e939de1SThierry Reding 1477e939de1SThierry Reding if (fuse->soc->probe) { 1487e939de1SThierry Reding err = fuse->soc->probe(fuse); 1497e939de1SThierry Reding if (err < 0) 1507e939de1SThierry Reding return err; 1517e939de1SThierry Reding } 1527e939de1SThierry Reding 1537e939de1SThierry Reding if (tegra_fuse_create_sysfs(&pdev->dev, fuse->soc->info->size, 1547e939de1SThierry Reding fuse->soc->info)) 1557e939de1SThierry Reding return -ENODEV; 1567e939de1SThierry Reding 1577e939de1SThierry Reding /* release the early I/O memory mapping */ 1587e939de1SThierry Reding iounmap(base); 1597e939de1SThierry Reding 1607e939de1SThierry Reding return 0; 1617e939de1SThierry Reding } 1627e939de1SThierry Reding 1637e939de1SThierry Reding static struct platform_driver tegra_fuse_driver = { 1647e939de1SThierry Reding .driver = { 1657e939de1SThierry Reding .name = "tegra-fuse", 1667e939de1SThierry Reding .of_match_table = tegra_fuse_match, 1677e939de1SThierry Reding .suppress_bind_attrs = true, 1687e939de1SThierry Reding }, 1697e939de1SThierry Reding .probe = tegra_fuse_probe, 1707e939de1SThierry Reding }; 1717e939de1SThierry Reding module_platform_driver(tegra_fuse_driver); 1727e939de1SThierry Reding 1737e939de1SThierry Reding bool __init tegra_fuse_read_spare(unsigned int spare) 1747e939de1SThierry Reding { 1757e939de1SThierry Reding unsigned int offset = fuse->soc->info->spare + spare * 4; 1767e939de1SThierry Reding 1777e939de1SThierry Reding return fuse->read_early(fuse, offset) & 1; 1787e939de1SThierry Reding } 1797e939de1SThierry Reding 1807e939de1SThierry Reding u32 __init tegra_fuse_read_early(unsigned int offset) 1817e939de1SThierry Reding { 1827e939de1SThierry Reding return fuse->read_early(fuse, offset); 1837e939de1SThierry Reding } 1847e939de1SThierry Reding 1857e939de1SThierry Reding int tegra_fuse_readl(unsigned long offset, u32 *value) 1867e939de1SThierry Reding { 1877e939de1SThierry Reding if (!fuse->read) 1887e939de1SThierry Reding return -EPROBE_DEFER; 1897e939de1SThierry Reding 1907e939de1SThierry Reding *value = fuse->read(fuse, offset); 1917e939de1SThierry Reding 1927e939de1SThierry Reding return 0; 1937e939de1SThierry Reding } 1947e939de1SThierry Reding EXPORT_SYMBOL(tegra_fuse_readl); 1957e939de1SThierry Reding 196783c8f4cSPeter De Schrijver static void tegra_enable_fuse_clk(void __iomem *base) 197783c8f4cSPeter De Schrijver { 198783c8f4cSPeter De Schrijver u32 reg; 199783c8f4cSPeter De Schrijver 200783c8f4cSPeter De Schrijver reg = readl_relaxed(base + 0x48); 201783c8f4cSPeter De Schrijver reg |= 1 << 28; 202783c8f4cSPeter De Schrijver writel(reg, base + 0x48); 203783c8f4cSPeter De Schrijver 204783c8f4cSPeter De Schrijver /* 205783c8f4cSPeter De Schrijver * Enable FUSE clock. This needs to be hardcoded because the clock 206783c8f4cSPeter De Schrijver * subsystem is not active during early boot. 207783c8f4cSPeter De Schrijver */ 208783c8f4cSPeter De Schrijver reg = readl(base + 0x14); 209783c8f4cSPeter De Schrijver reg |= 1 << 7; 210783c8f4cSPeter De Schrijver writel(reg, base + 0x14); 211783c8f4cSPeter De Schrijver } 212783c8f4cSPeter De Schrijver 21324fa5af8SThierry Reding static int __init tegra_init_fuse(void) 214783c8f4cSPeter De Schrijver { 2157e939de1SThierry Reding const struct of_device_id *match; 216783c8f4cSPeter De Schrijver struct device_node *np; 2177e939de1SThierry Reding struct resource regs; 21824fa5af8SThierry Reding 219783c8f4cSPeter De Schrijver tegra_init_apbmisc(); 220783c8f4cSPeter De Schrijver 2217e939de1SThierry Reding np = of_find_matching_node_and_match(NULL, tegra_fuse_match, &match); 2227e939de1SThierry Reding if (!np) { 2237e939de1SThierry Reding /* 2247e939de1SThierry Reding * Fall back to legacy initialization for 32-bit ARM only. All 2257e939de1SThierry Reding * 64-bit ARM device tree files for Tegra are required to have 2267e939de1SThierry Reding * a FUSE node. 2277e939de1SThierry Reding * 2287e939de1SThierry Reding * This is for backwards-compatibility with old device trees 2297e939de1SThierry Reding * that didn't contain a FUSE node. 2307e939de1SThierry Reding */ 2317e939de1SThierry Reding if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 2327e939de1SThierry Reding u8 chip = tegra_get_chip_id(); 2337e939de1SThierry Reding 2347e939de1SThierry Reding regs.start = 0x7000f800; 2357e939de1SThierry Reding regs.end = 0x7000fbff; 2367e939de1SThierry Reding regs.flags = IORESOURCE_MEM; 2377e939de1SThierry Reding 2387e939de1SThierry Reding switch (chip) { 2397e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_2x_SOC 2407e939de1SThierry Reding case TEGRA20: 2417e939de1SThierry Reding fuse->soc = &tegra20_fuse_soc; 2427e939de1SThierry Reding break; 2437e939de1SThierry Reding #endif 2447e939de1SThierry Reding 2457e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_3x_SOC 2467e939de1SThierry Reding case TEGRA30: 2477e939de1SThierry Reding fuse->soc = &tegra30_fuse_soc; 2487e939de1SThierry Reding break; 2497e939de1SThierry Reding #endif 2507e939de1SThierry Reding 2517e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_114_SOC 2527e939de1SThierry Reding case TEGRA114: 2537e939de1SThierry Reding fuse->soc = &tegra114_fuse_soc; 2547e939de1SThierry Reding break; 2557e939de1SThierry Reding #endif 2567e939de1SThierry Reding 2577e939de1SThierry Reding #ifdef CONFIG_ARCH_TEGRA_124_SOC 2587e939de1SThierry Reding case TEGRA124: 2597e939de1SThierry Reding fuse->soc = &tegra124_fuse_soc; 2607e939de1SThierry Reding break; 2617e939de1SThierry Reding #endif 2627e939de1SThierry Reding 2637e939de1SThierry Reding default: 2647e939de1SThierry Reding pr_warn("Unsupported SoC: %02x\n", chip); 2657e939de1SThierry Reding break; 2667e939de1SThierry Reding } 267783c8f4cSPeter De Schrijver } else { 2687e939de1SThierry Reding /* 2697e939de1SThierry Reding * At this point we're not running on Tegra, so play 2707e939de1SThierry Reding * nice with multi-platform kernels. 2717e939de1SThierry Reding */ 2727e939de1SThierry Reding return 0; 2737e939de1SThierry Reding } 2747e939de1SThierry Reding } else { 2757e939de1SThierry Reding /* 2767e939de1SThierry Reding * Extract information from the device tree if we've found a 2777e939de1SThierry Reding * matching node. 2787e939de1SThierry Reding */ 2797e939de1SThierry Reding if (of_address_to_resource(np, 0, ®s) < 0) { 2807e939de1SThierry Reding pr_err("failed to get FUSE register\n"); 28124fa5af8SThierry Reding return -ENXIO; 282783c8f4cSPeter De Schrijver } 283783c8f4cSPeter De Schrijver 2847e939de1SThierry Reding fuse->soc = match->data; 2857e939de1SThierry Reding } 2867e939de1SThierry Reding 2877e939de1SThierry Reding np = of_find_matching_node(NULL, car_match); 2887e939de1SThierry Reding if (np) { 2897e939de1SThierry Reding void __iomem *base = of_iomap(np, 0); 2907e939de1SThierry Reding if (base) { 2917e939de1SThierry Reding tegra_enable_fuse_clk(base); 2927e939de1SThierry Reding iounmap(base); 2937e939de1SThierry Reding } else { 2947e939de1SThierry Reding pr_err("failed to map clock registers\n"); 2957e939de1SThierry Reding return -ENXIO; 2967e939de1SThierry Reding } 2977e939de1SThierry Reding } 2987e939de1SThierry Reding 2997e939de1SThierry Reding fuse->base = ioremap_nocache(regs.start, resource_size(®s)); 3007e939de1SThierry Reding if (!fuse->base) { 3017e939de1SThierry Reding pr_err("failed to map FUSE registers\n"); 3027e939de1SThierry Reding return -ENXIO; 3037e939de1SThierry Reding } 3047e939de1SThierry Reding 3057e939de1SThierry Reding fuse->soc->init(fuse); 306783c8f4cSPeter De Schrijver 307*03b3f4c8SThierry Reding pr_info("Tegra Revision: %s SKU: %d CPU Process: %d SoC Process: %d\n", 308783c8f4cSPeter De Schrijver tegra_revision_name[tegra_sku_info.revision], 309783c8f4cSPeter De Schrijver tegra_sku_info.sku_id, tegra_sku_info.cpu_process_id, 310*03b3f4c8SThierry Reding tegra_sku_info.soc_process_id); 311*03b3f4c8SThierry Reding pr_debug("Tegra CPU Speedo ID %d, SoC Speedo ID %d\n", 312783c8f4cSPeter De Schrijver tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id); 31324fa5af8SThierry Reding 31424fa5af8SThierry Reding return 0; 315783c8f4cSPeter De Schrijver } 31624fa5af8SThierry Reding early_initcall(tegra_init_fuse); 317