1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/arm-smccc.h> 7 #include <linux/kernel.h> 8 #include <linux/of.h> 9 #include <linux/panic_notifier.h> 10 11 #define SMC_SIP_INVOKE_MCE 0xc2ffff00 12 #define MCE_SMC_READ_MCA 12 13 14 #define MCA_ARI_CMD_RD_SERR 1 15 16 #define MCA_ARI_RW_SUBIDX_STAT 1 17 #define SERR_STATUS_VAL BIT_ULL(63) 18 19 #define MCA_ARI_RW_SUBIDX_ADDR 2 20 #define MCA_ARI_RW_SUBIDX_MSC1 3 21 #define MCA_ARI_RW_SUBIDX_MSC2 4 22 23 static const char * const bank_names[] = { 24 "SYS:DPMU", "ROC:IOB", "ROC:MCB", "ROC:CCE", "ROC:CQX", "ROC:CTU", 25 }; 26 27 static void read_uncore_mca(u8 cmd, u8 idx, u8 subidx, u8 inst, u64 *data) 28 { 29 struct arm_smccc_res res; 30 31 arm_smccc_smc(SMC_SIP_INVOKE_MCE | MCE_SMC_READ_MCA, 32 ((u64)inst << 24) | ((u64)idx << 16) | 33 ((u64)subidx << 8) | ((u64)cmd << 0), 34 0, 0, 0, 0, 0, 0, &res); 35 36 *data = res.a2; 37 } 38 39 static int tegra186_ari_panic_handler(struct notifier_block *nb, 40 unsigned long code, void *unused) 41 { 42 u64 status; 43 int i; 44 45 for (i = 0; i < ARRAY_SIZE(bank_names); i++) { 46 read_uncore_mca(MCA_ARI_CMD_RD_SERR, i, MCA_ARI_RW_SUBIDX_STAT, 47 0, &status); 48 49 if (status & SERR_STATUS_VAL) { 50 u64 addr, misc1, misc2; 51 52 read_uncore_mca(MCA_ARI_CMD_RD_SERR, i, 53 MCA_ARI_RW_SUBIDX_ADDR, 0, &addr); 54 read_uncore_mca(MCA_ARI_CMD_RD_SERR, i, 55 MCA_ARI_RW_SUBIDX_MSC1, 0, &misc1); 56 read_uncore_mca(MCA_ARI_CMD_RD_SERR, i, 57 MCA_ARI_RW_SUBIDX_MSC2, 0, &misc2); 58 59 pr_crit("Machine Check Error in %s\n" 60 " status=0x%llx addr=0x%llx\n" 61 " msc1=0x%llx msc2=0x%llx\n", 62 bank_names[i], status, addr, misc1, misc2); 63 } 64 } 65 66 return NOTIFY_DONE; 67 } 68 69 static struct notifier_block tegra186_ari_panic_nb = { 70 .notifier_call = tegra186_ari_panic_handler, 71 }; 72 73 static int __init tegra186_ari_init(void) 74 { 75 if (of_machine_is_compatible("nvidia,tegra186")) 76 atomic_notifier_chain_register(&panic_notifier_list, &tegra186_ari_panic_nb); 77 78 return 0; 79 } 80 early_initcall(tegra186_ari_init); 81