1# SPDX-License-Identifier: GPL-2.0-only 2if ARCH_TEGRA 3 4# 32-bit ARM SoCs 5if ARM 6 7config ARCH_TEGRA_2x_SOC 8 bool "Enable support for Tegra20 family" 9 default ARCH_TEGRA 10 select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP 11 select ARM_ERRATA_720789 12 select ARM_ERRATA_754327 if SMP 13 select ARM_ERRATA_764369 if SMP 14 select PINCTRL_TEGRA20 15 select PL310_ERRATA_727915 if CACHE_L2X0 16 select PL310_ERRATA_769419 if CACHE_L2X0 17 select SOC_TEGRA_FLOWCTRL 18 select SOC_TEGRA_PMC 19 select SOC_TEGRA20_VOLTAGE_COUPLER if REGULATOR 20 select TEGRA_TIMER 21 help 22 Support for NVIDIA Tegra AP20 and T20 processors, based on the 23 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller 24 25config ARCH_TEGRA_3x_SOC 26 bool "Enable support for Tegra30 family" 27 default ARCH_TEGRA 28 select ARM_ERRATA_754322 29 select ARM_ERRATA_764369 if SMP 30 select PINCTRL_TEGRA30 31 select PL310_ERRATA_769419 if CACHE_L2X0 32 select SOC_TEGRA_FLOWCTRL 33 select SOC_TEGRA_PMC 34 select SOC_TEGRA30_VOLTAGE_COUPLER if REGULATOR 35 select TEGRA_TIMER 36 help 37 Support for NVIDIA Tegra T30 processor family, based on the 38 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller 39 40config ARCH_TEGRA_114_SOC 41 bool "Enable support for Tegra114 family" 42 default ARCH_TEGRA 43 select ARM_ERRATA_798181 if SMP 44 select HAVE_ARM_ARCH_TIMER 45 select PINCTRL_TEGRA114 46 select SOC_TEGRA_FLOWCTRL 47 select SOC_TEGRA_PMC 48 select TEGRA_TIMER 49 help 50 Support for NVIDIA Tegra T114 processor family, based on the 51 ARM CortexA15MP CPU 52 53config ARCH_TEGRA_124_SOC 54 bool "Enable support for Tegra124 family" 55 default ARCH_TEGRA 56 select HAVE_ARM_ARCH_TIMER 57 select PINCTRL_TEGRA124 58 select SOC_TEGRA_FLOWCTRL 59 select SOC_TEGRA_PMC 60 select TEGRA_TIMER 61 help 62 Support for NVIDIA Tegra T124 processor family, based on the 63 ARM CortexA15MP CPU 64 65endif 66 67# 64-bit ARM SoCs 68if ARM64 69 70config ARCH_TEGRA_132_SOC 71 bool "NVIDIA Tegra132 SoC" 72 default ARCH_TEGRA 73 select PINCTRL_TEGRA124 74 select SOC_TEGRA_FLOWCTRL 75 select SOC_TEGRA_PMC 76 help 77 Enable support for NVIDIA Tegra132 SoC, based on the Denver 78 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC, 79 but contains an NVIDIA Denver CPU complex in place of 80 Tegra124's "4+1" Cortex-A15 CPU complex. 81 82config ARCH_TEGRA_210_SOC 83 bool "NVIDIA Tegra210 SoC" 84 default ARCH_TEGRA 85 select PINCTRL_TEGRA210 86 select SOC_TEGRA_FLOWCTRL 87 select SOC_TEGRA_PMC 88 select TEGRA_TIMER 89 help 90 Enable support for the NVIDIA Tegra210 SoC. Also known as Tegra X1, 91 the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 92 cores in a switched configuration. It features a GPU of the Maxwell 93 architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 94 and providing 256 CUDA cores. It supports hardware-accelerated en- 95 and decoding of various video standards including H.265, H.264 and 96 VP8 at 4K resolution and up to 60 fps. 97 98 Besides the multimedia features it also comes with a variety of I/O 99 controllers, such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to 100 name only a few. 101 102config ARCH_TEGRA_186_SOC 103 bool "NVIDIA Tegra186 SoC" 104 default ARCH_TEGRA 105 select PINCTRL_TEGRA186 106 select MAILBOX 107 select SOC_TEGRA_PMC 108 help 109 Enable support for the NVIDIA Tegar186 SoC. The Tegra186 features a 110 combination of Denver and Cortex-A57 CPU cores and a GPU based on 111 the Pascal architecture. It contains an ADSP with a Cortex-A9 CPU 112 used for audio processing, hardware video encoders/decoders with 113 multi-format support, ISP for image capture processing and BPMP for 114 power management. 115 116config ARCH_TEGRA_194_SOC 117 bool "NVIDIA Tegra194 SoC" 118 default ARCH_TEGRA 119 select MAILBOX 120 select PINCTRL_TEGRA194 121 select SOC_TEGRA_PMC 122 help 123 Enable support for the NVIDIA Tegra194 SoC. 124 125config ARCH_TEGRA_234_SOC 126 bool "NVIDIA Tegra234 SoC" 127 default ARCH_TEGRA 128 select MAILBOX 129 select PINCTRL_TEGRA234 130 select SOC_TEGRA_PMC 131 help 132 Enable support for the NVIDIA Tegra234 SoC. 133 134config ARCH_TEGRA_238_SOC 135 bool "NVIDIA Tegra238 SoC" 136 default ARCH_TEGRA 137 select MAILBOX 138 select SOC_TEGRA_PMC 139 help 140 Enable support for the NVIDIA Tegra238 SoC. 141 142config ARCH_TEGRA_241_SOC 143 bool "NVIDIA Tegra241 SoC" 144 default ARCH_TEGRA 145 help 146 Enable support for the NVIDIA Tegra241 SoC. 147 148config ARCH_TEGRA_264_SOC 149 bool "NVIDIA Tegra264 SoC" 150 default ARCH_TEGRA 151 select MAILBOX 152 select SOC_TEGRA_PMC 153 help 154 Enable support for the NVIDIA Tegra264 SoC. 155 156endif 157endif 158 159config SOC_TEGRA_FUSE 160 def_bool y 161 depends on ARCH_TEGRA 162 select SOC_BUS 163 164config SOC_TEGRA_FLOWCTRL 165 bool 166 167config SOC_TEGRA_PMC 168 bool 169 depends on PM 170 select GENERIC_PINCONF 171 select IRQ_DOMAIN_HIERARCHY 172 select PM_OPP 173 select PM_GENERIC_DOMAINS 174 select REGMAP 175 176config SOC_TEGRA20_VOLTAGE_COUPLER 177 bool "Voltage scaling support for Tegra20 SoCs" 178 depends on ARCH_TEGRA_2x_SOC || COMPILE_TEST 179 depends on REGULATOR 180 181config SOC_TEGRA30_VOLTAGE_COUPLER 182 bool "Voltage scaling support for Tegra30 SoCs" 183 depends on ARCH_TEGRA_3x_SOC || COMPILE_TEST 184 depends on REGULATOR 185 186config SOC_TEGRA_CBB 187 tristate "Tegra driver to handle error from CBB" 188 depends on ARCH_TEGRA_194_SOC || ARCH_TEGRA_234_SOC 189 default y 190 help 191 Support for handling error from Tegra Control Backbone(CBB). 192 This driver handles the errors from CBB and prints debug 193 information about the failed transactions. 194