1 /* 2 * Allwinner SoCs SRAM Controller Driver 3 * 4 * Copyright (C) 2015 Maxime Ripard 5 * 6 * Author: Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13 #include <linux/debugfs.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/of_platform.h> 19 #include <linux/platform_device.h> 20 #include <linux/regmap.h> 21 22 #include <linux/soc/sunxi/sunxi_sram.h> 23 24 struct sunxi_sram_func { 25 char *func; 26 u8 val; 27 u32 reg_val; 28 }; 29 30 struct sunxi_sram_data { 31 char *name; 32 u8 reg; 33 u8 offset; 34 u8 width; 35 struct sunxi_sram_func *func; 36 }; 37 38 struct sunxi_sram_desc { 39 struct sunxi_sram_data data; 40 bool claimed; 41 }; 42 43 #define SUNXI_SRAM_MAP(_reg_val, _val, _func) \ 44 { \ 45 .func = _func, \ 46 .val = _val, \ 47 .reg_val = _reg_val, \ 48 } 49 50 #define SUNXI_SRAM_DATA(_name, _reg, _off, _width, ...) \ 51 { \ 52 .name = _name, \ 53 .reg = _reg, \ 54 .offset = _off, \ 55 .width = _width, \ 56 .func = (struct sunxi_sram_func[]){ \ 57 __VA_ARGS__, { } }, \ 58 } 59 60 static struct sunxi_sram_desc sun4i_a10_sram_a3_a4 = { 61 .data = SUNXI_SRAM_DATA("A3-A4", 0x4, 0x4, 2, 62 SUNXI_SRAM_MAP(0, 0, "cpu"), 63 SUNXI_SRAM_MAP(1, 1, "emac")), 64 }; 65 66 static struct sunxi_sram_desc sun4i_a10_sram_c1 = { 67 .data = SUNXI_SRAM_DATA("C1", 0x0, 0x0, 31, 68 SUNXI_SRAM_MAP(0, 0, "cpu"), 69 SUNXI_SRAM_MAP(0x7fffffff, 1, "ve")), 70 }; 71 72 static struct sunxi_sram_desc sun4i_a10_sram_d = { 73 .data = SUNXI_SRAM_DATA("D", 0x4, 0x0, 1, 74 SUNXI_SRAM_MAP(0, 0, "cpu"), 75 SUNXI_SRAM_MAP(1, 1, "usb-otg")), 76 }; 77 78 static struct sunxi_sram_desc sun50i_a64_sram_c = { 79 .data = SUNXI_SRAM_DATA("C", 0x4, 24, 1, 80 SUNXI_SRAM_MAP(1, 0, "cpu"), 81 SUNXI_SRAM_MAP(0, 1, "de2")), 82 }; 83 84 static const struct of_device_id sunxi_sram_dt_ids[] = { 85 { 86 .compatible = "allwinner,sun4i-a10-sram-a3-a4", 87 .data = &sun4i_a10_sram_a3_a4.data, 88 }, 89 { 90 .compatible = "allwinner,sun4i-a10-sram-c1", 91 .data = &sun4i_a10_sram_c1.data, 92 }, 93 { 94 .compatible = "allwinner,sun4i-a10-sram-d", 95 .data = &sun4i_a10_sram_d.data, 96 }, 97 { 98 .compatible = "allwinner,sun50i-a64-sram-c", 99 .data = &sun50i_a64_sram_c.data, 100 }, 101 {} 102 }; 103 104 static struct device *sram_dev; 105 static DEFINE_SPINLOCK(sram_lock); 106 static void __iomem *base; 107 108 static int sunxi_sram_show(struct seq_file *s, void *data) 109 { 110 struct device_node *sram_node, *section_node; 111 const struct sunxi_sram_data *sram_data; 112 const struct of_device_id *match; 113 struct sunxi_sram_func *func; 114 const __be32 *sram_addr_p, *section_addr_p; 115 u32 val; 116 117 seq_puts(s, "Allwinner sunXi SRAM\n"); 118 seq_puts(s, "--------------------\n\n"); 119 120 for_each_child_of_node(sram_dev->of_node, sram_node) { 121 if (!of_device_is_compatible(sram_node, "mmio-sram")) 122 continue; 123 124 sram_addr_p = of_get_address(sram_node, 0, NULL, NULL); 125 126 seq_printf(s, "sram@%08x\n", 127 be32_to_cpu(*sram_addr_p)); 128 129 for_each_child_of_node(sram_node, section_node) { 130 match = of_match_node(sunxi_sram_dt_ids, section_node); 131 if (!match) 132 continue; 133 sram_data = match->data; 134 135 section_addr_p = of_get_address(section_node, 0, 136 NULL, NULL); 137 138 seq_printf(s, "\tsection@%04x\t(%s)\n", 139 be32_to_cpu(*section_addr_p), 140 sram_data->name); 141 142 val = readl(base + sram_data->reg); 143 val >>= sram_data->offset; 144 val &= GENMASK(sram_data->width - 1, 0); 145 146 for (func = sram_data->func; func->func; func++) { 147 seq_printf(s, "\t\t%s%c\n", func->func, 148 func->reg_val == val ? 149 '*' : ' '); 150 } 151 } 152 153 seq_puts(s, "\n"); 154 } 155 156 return 0; 157 } 158 159 DEFINE_SHOW_ATTRIBUTE(sunxi_sram); 160 161 static inline struct sunxi_sram_desc *to_sram_desc(const struct sunxi_sram_data *data) 162 { 163 return container_of(data, struct sunxi_sram_desc, data); 164 } 165 166 static const struct sunxi_sram_data *sunxi_sram_of_parse(struct device_node *node, 167 unsigned int *reg_value) 168 { 169 const struct of_device_id *match; 170 const struct sunxi_sram_data *data; 171 struct sunxi_sram_func *func; 172 struct of_phandle_args args; 173 u8 val; 174 int ret; 175 176 ret = of_parse_phandle_with_fixed_args(node, "allwinner,sram", 1, 0, 177 &args); 178 if (ret) 179 return ERR_PTR(ret); 180 181 if (!of_device_is_available(args.np)) { 182 ret = -EBUSY; 183 goto err; 184 } 185 186 val = args.args[0]; 187 188 match = of_match_node(sunxi_sram_dt_ids, args.np); 189 if (!match) { 190 ret = -EINVAL; 191 goto err; 192 } 193 194 data = match->data; 195 if (!data) { 196 ret = -EINVAL; 197 goto err; 198 } 199 200 for (func = data->func; func->func; func++) { 201 if (val == func->val) { 202 if (reg_value) 203 *reg_value = func->reg_val; 204 205 break; 206 } 207 } 208 209 if (!func->func) { 210 ret = -EINVAL; 211 goto err; 212 } 213 214 of_node_put(args.np); 215 return match->data; 216 217 err: 218 of_node_put(args.np); 219 return ERR_PTR(ret); 220 } 221 222 int sunxi_sram_claim(struct device *dev) 223 { 224 const struct sunxi_sram_data *sram_data; 225 struct sunxi_sram_desc *sram_desc; 226 unsigned int device; 227 u32 val, mask; 228 229 if (IS_ERR(base)) 230 return PTR_ERR(base); 231 232 if (!base) 233 return -EPROBE_DEFER; 234 235 if (!dev || !dev->of_node) 236 return -EINVAL; 237 238 sram_data = sunxi_sram_of_parse(dev->of_node, &device); 239 if (IS_ERR(sram_data)) 240 return PTR_ERR(sram_data); 241 242 sram_desc = to_sram_desc(sram_data); 243 244 spin_lock(&sram_lock); 245 246 if (sram_desc->claimed) { 247 spin_unlock(&sram_lock); 248 return -EBUSY; 249 } 250 251 mask = GENMASK(sram_data->offset + sram_data->width - 1, 252 sram_data->offset); 253 val = readl(base + sram_data->reg); 254 val &= ~mask; 255 writel(val | ((device << sram_data->offset) & mask), 256 base + sram_data->reg); 257 258 sram_desc->claimed = true; 259 spin_unlock(&sram_lock); 260 261 return 0; 262 } 263 EXPORT_SYMBOL(sunxi_sram_claim); 264 265 void sunxi_sram_release(struct device *dev) 266 { 267 const struct sunxi_sram_data *sram_data; 268 struct sunxi_sram_desc *sram_desc; 269 270 if (!dev || !dev->of_node) 271 return; 272 273 sram_data = sunxi_sram_of_parse(dev->of_node, NULL); 274 if (IS_ERR(sram_data)) 275 return; 276 277 sram_desc = to_sram_desc(sram_data); 278 279 spin_lock(&sram_lock); 280 sram_desc->claimed = false; 281 spin_unlock(&sram_lock); 282 } 283 EXPORT_SYMBOL(sunxi_sram_release); 284 285 struct sunxi_sramc_variant { 286 int num_emac_clocks; 287 bool has_ldo_ctrl; 288 bool has_ths_offset; 289 }; 290 291 static const struct sunxi_sramc_variant sun4i_a10_sramc_variant = { 292 /* Nothing special */ 293 }; 294 295 static const struct sunxi_sramc_variant sun8i_h3_sramc_variant = { 296 .num_emac_clocks = 1, 297 }; 298 299 static const struct sunxi_sramc_variant sun20i_d1_sramc_variant = { 300 .num_emac_clocks = 1, 301 .has_ldo_ctrl = true, 302 }; 303 304 static const struct sunxi_sramc_variant sun50i_a64_sramc_variant = { 305 .num_emac_clocks = 1, 306 }; 307 308 static const struct sunxi_sramc_variant sun50i_h616_sramc_variant = { 309 .num_emac_clocks = 2, 310 .has_ths_offset = true, 311 }; 312 313 #define SUNXI_SRAM_THS_OFFSET_REG 0x0 314 #define SUNXI_SRAM_EMAC_CLOCK_REG 0x30 315 #define SUNXI_SYS_LDO_CTRL_REG 0x150 316 317 static bool sunxi_sram_regmap_accessible_reg(struct device *dev, 318 unsigned int reg) 319 { 320 const struct sunxi_sramc_variant *variant = dev_get_drvdata(dev); 321 322 if (reg == SUNXI_SRAM_THS_OFFSET_REG && variant->has_ths_offset) 323 return true; 324 if (reg >= SUNXI_SRAM_EMAC_CLOCK_REG && 325 reg < SUNXI_SRAM_EMAC_CLOCK_REG + variant->num_emac_clocks * 4) 326 return true; 327 if (reg == SUNXI_SYS_LDO_CTRL_REG && variant->has_ldo_ctrl) 328 return true; 329 330 return false; 331 } 332 333 static void sunxi_sram_lock(void *_lock) 334 { 335 spinlock_t *lock = _lock; 336 337 spin_lock(lock); 338 } 339 340 static void sunxi_sram_unlock(void *_lock) 341 { 342 spinlock_t *lock = _lock; 343 344 spin_unlock(lock); 345 } 346 347 static const struct regmap_config sunxi_sram_regmap_config = { 348 .reg_bits = 32, 349 .val_bits = 32, 350 .reg_stride = 4, 351 /* last defined register */ 352 .max_register = SUNXI_SYS_LDO_CTRL_REG, 353 /* other devices have no business accessing other registers */ 354 .readable_reg = sunxi_sram_regmap_accessible_reg, 355 .writeable_reg = sunxi_sram_regmap_accessible_reg, 356 .lock = sunxi_sram_lock, 357 .unlock = sunxi_sram_unlock, 358 .lock_arg = &sram_lock, 359 }; 360 361 static int __init sunxi_sram_probe(struct platform_device *pdev) 362 { 363 const struct sunxi_sramc_variant *variant; 364 struct device *dev = &pdev->dev; 365 struct regmap *regmap; 366 367 sram_dev = &pdev->dev; 368 369 variant = of_device_get_match_data(&pdev->dev); 370 if (!variant) 371 return -EINVAL; 372 373 dev_set_drvdata(dev, (struct sunxi_sramc_variant *)variant); 374 375 base = devm_platform_ioremap_resource(pdev, 0); 376 if (IS_ERR(base)) 377 return PTR_ERR(base); 378 379 if (variant->num_emac_clocks || variant->has_ldo_ctrl) { 380 regmap = devm_regmap_init_mmio(dev, base, &sunxi_sram_regmap_config); 381 if (IS_ERR(regmap)) 382 return PTR_ERR(regmap); 383 } 384 385 of_platform_populate(dev->of_node, NULL, NULL, dev); 386 387 debugfs_create_file("sram", 0444, NULL, NULL, &sunxi_sram_fops); 388 389 return 0; 390 } 391 392 static const struct of_device_id sunxi_sram_dt_match[] = { 393 { 394 .compatible = "allwinner,sun4i-a10-sram-controller", 395 .data = &sun4i_a10_sramc_variant, 396 }, 397 { 398 .compatible = "allwinner,sun4i-a10-system-control", 399 .data = &sun4i_a10_sramc_variant, 400 }, 401 { 402 .compatible = "allwinner,sun5i-a13-system-control", 403 .data = &sun4i_a10_sramc_variant, 404 }, 405 { 406 .compatible = "allwinner,sun8i-a23-system-control", 407 .data = &sun4i_a10_sramc_variant, 408 }, 409 { 410 .compatible = "allwinner,sun8i-h3-system-control", 411 .data = &sun8i_h3_sramc_variant, 412 }, 413 { 414 .compatible = "allwinner,sun20i-d1-system-control", 415 .data = &sun20i_d1_sramc_variant, 416 }, 417 { 418 .compatible = "allwinner,sun50i-a64-sram-controller", 419 .data = &sun50i_a64_sramc_variant, 420 }, 421 { 422 .compatible = "allwinner,sun50i-a64-system-control", 423 .data = &sun50i_a64_sramc_variant, 424 }, 425 { 426 .compatible = "allwinner,sun50i-h5-system-control", 427 .data = &sun50i_a64_sramc_variant, 428 }, 429 { 430 .compatible = "allwinner,sun50i-h616-system-control", 431 .data = &sun50i_h616_sramc_variant, 432 }, 433 { }, 434 }; 435 MODULE_DEVICE_TABLE(of, sunxi_sram_dt_match); 436 437 static struct platform_driver sunxi_sram_driver = { 438 .driver = { 439 .name = "sunxi-sram", 440 .of_match_table = sunxi_sram_dt_match, 441 }, 442 }; 443 builtin_platform_driver_probe(sunxi_sram_driver, sunxi_sram_probe); 444 445 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 446 MODULE_DESCRIPTION("Allwinner sunXi SRAM Controller Driver"); 447