1*bfce552dSPankaj Dubey /* 2*bfce552dSPankaj Dubey * Copyright (c) 2011-2015 Samsung Electronics Co., Ltd. 3*bfce552dSPankaj Dubey * http://www.samsung.com/ 4*bfce552dSPankaj Dubey * 5*bfce552dSPankaj Dubey * EXYNOS5250 - CPU PMU (Power Management Unit) support 6*bfce552dSPankaj Dubey * 7*bfce552dSPankaj Dubey * This program is free software; you can redistribute it and/or modify 8*bfce552dSPankaj Dubey * it under the terms of the GNU General Public License version 2 as 9*bfce552dSPankaj Dubey * published by the Free Software Foundation. 10*bfce552dSPankaj Dubey */ 11*bfce552dSPankaj Dubey 12*bfce552dSPankaj Dubey #include <linux/soc/samsung/exynos-regs-pmu.h> 13*bfce552dSPankaj Dubey #include <linux/soc/samsung/exynos-pmu.h> 14*bfce552dSPankaj Dubey 15*bfce552dSPankaj Dubey #include "exynos-pmu.h" 16*bfce552dSPankaj Dubey 17*bfce552dSPankaj Dubey static const struct exynos_pmu_conf exynos5250_pmu_config[] = { 18*bfce552dSPankaj Dubey /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */ 19*bfce552dSPankaj Dubey { EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, 20*bfce552dSPankaj Dubey { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, 21*bfce552dSPankaj Dubey { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, 22*bfce552dSPankaj Dubey { EXYNOS5_ARM_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, 23*bfce552dSPankaj Dubey { EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, 24*bfce552dSPankaj Dubey { EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, 25*bfce552dSPankaj Dubey { EXYNOS5_FSYS_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 26*bfce552dSPankaj Dubey { EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, 27*bfce552dSPankaj Dubey { EXYNOS5_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 28*bfce552dSPankaj Dubey { EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, 29*bfce552dSPankaj Dubey { EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, 30*bfce552dSPankaj Dubey { EXYNOS5_ARM_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, 31*bfce552dSPankaj Dubey { EXYNOS5_ARM_L2_SYS_PWR_REG, { 0x3, 0x3, 0x3} }, 32*bfce552dSPankaj Dubey { EXYNOS5_ARM_L2_OPTION, { 0x10, 0x10, 0x0 } }, 33*bfce552dSPankaj Dubey { EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, 34*bfce552dSPankaj Dubey { EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, 35*bfce552dSPankaj Dubey { EXYNOS5_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, 36*bfce552dSPankaj Dubey { EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, 37*bfce552dSPankaj Dubey { EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, 38*bfce552dSPankaj Dubey { EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, 39*bfce552dSPankaj Dubey { EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, 40*bfce552dSPankaj Dubey { EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, 41*bfce552dSPankaj Dubey { EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, 42*bfce552dSPankaj Dubey { EXYNOS5_APLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 43*bfce552dSPankaj Dubey { EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 44*bfce552dSPankaj Dubey { EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 45*bfce552dSPankaj Dubey { EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, 46*bfce552dSPankaj Dubey { EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 47*bfce552dSPankaj Dubey { EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 48*bfce552dSPankaj Dubey { EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 49*bfce552dSPankaj Dubey { EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 50*bfce552dSPankaj Dubey { EXYNOS5_TOP_BUS_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, 51*bfce552dSPankaj Dubey { EXYNOS5_TOP_RETENTION_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, 52*bfce552dSPankaj Dubey { EXYNOS5_TOP_PWR_SYS_PWR_REG, { 0x3, 0x0, 0x3} }, 53*bfce552dSPankaj Dubey { EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, 54*bfce552dSPankaj Dubey { EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, 55*bfce552dSPankaj Dubey { EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x3} }, 56*bfce552dSPankaj Dubey { EXYNOS5_LOGIC_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, 57*bfce552dSPankaj Dubey { EXYNOS5_OSCCLK_GATE_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, 58*bfce552dSPankaj Dubey { EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, 59*bfce552dSPankaj Dubey { EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, 60*bfce552dSPankaj Dubey { EXYNOS5_USBOTG_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, 61*bfce552dSPankaj Dubey { EXYNOS5_G2D_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, 62*bfce552dSPankaj Dubey { EXYNOS5_USBDRD_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, 63*bfce552dSPankaj Dubey { EXYNOS5_SDMMC_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, 64*bfce552dSPankaj Dubey { EXYNOS5_CSSYS_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, 65*bfce552dSPankaj Dubey { EXYNOS5_SECSS_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, 66*bfce552dSPankaj Dubey { EXYNOS5_ROTATOR_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, 67*bfce552dSPankaj Dubey { EXYNOS5_INTRAM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, 68*bfce552dSPankaj Dubey { EXYNOS5_INTROM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, 69*bfce552dSPankaj Dubey { EXYNOS5_JPEG_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, 70*bfce552dSPankaj Dubey { EXYNOS5_JPEG_MEM_OPTION, { 0x10, 0x10, 0x0} }, 71*bfce552dSPankaj Dubey { EXYNOS5_HSI_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, 72*bfce552dSPankaj Dubey { EXYNOS5_MCUIOP_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, 73*bfce552dSPankaj Dubey { EXYNOS5_SATA_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, 74*bfce552dSPankaj Dubey { EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 75*bfce552dSPankaj Dubey { EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, 76*bfce552dSPankaj Dubey { EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 77*bfce552dSPankaj Dubey { EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 78*bfce552dSPankaj Dubey { EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 79*bfce552dSPankaj Dubey { EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 80*bfce552dSPankaj Dubey { EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 81*bfce552dSPankaj Dubey { EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 82*bfce552dSPankaj Dubey { EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 83*bfce552dSPankaj Dubey { EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 84*bfce552dSPankaj Dubey { EXYNOS5_PAD_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 85*bfce552dSPankaj Dubey { EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 86*bfce552dSPankaj Dubey { EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 87*bfce552dSPankaj Dubey { EXYNOS5_XUSBXTI_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, 88*bfce552dSPankaj Dubey { EXYNOS5_XXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, 89*bfce552dSPankaj Dubey { EXYNOS5_EXT_REGULATOR_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, 90*bfce552dSPankaj Dubey { EXYNOS5_GPIO_MODE_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 91*bfce552dSPankaj Dubey { EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 92*bfce552dSPankaj Dubey { EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, 93*bfce552dSPankaj Dubey { EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, 94*bfce552dSPankaj Dubey { EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, 95*bfce552dSPankaj Dubey { EXYNOS5_GSCL_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, 96*bfce552dSPankaj Dubey { EXYNOS5_ISP_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, 97*bfce552dSPankaj Dubey { EXYNOS5_MFC_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, 98*bfce552dSPankaj Dubey { EXYNOS5_G3D_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, 99*bfce552dSPankaj Dubey { EXYNOS5_DISP1_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, 100*bfce552dSPankaj Dubey { EXYNOS5_MAU_SYS_PWR_REG, { 0x7, 0x7, 0x0} }, 101*bfce552dSPankaj Dubey { EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 102*bfce552dSPankaj Dubey { EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 103*bfce552dSPankaj Dubey { EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 104*bfce552dSPankaj Dubey { EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 105*bfce552dSPankaj Dubey { EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 106*bfce552dSPankaj Dubey { EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, 107*bfce552dSPankaj Dubey { EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 108*bfce552dSPankaj Dubey { EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 109*bfce552dSPankaj Dubey { EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 110*bfce552dSPankaj Dubey { EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 111*bfce552dSPankaj Dubey { EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 112*bfce552dSPankaj Dubey { EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, 113*bfce552dSPankaj Dubey { EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 114*bfce552dSPankaj Dubey { EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 115*bfce552dSPankaj Dubey { EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 116*bfce552dSPankaj Dubey { EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 117*bfce552dSPankaj Dubey { EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 118*bfce552dSPankaj Dubey { EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, 119*bfce552dSPankaj Dubey { PMU_TABLE_END,}, 120*bfce552dSPankaj Dubey }; 121*bfce552dSPankaj Dubey 122*bfce552dSPankaj Dubey static unsigned int const exynos5_list_both_cnt_feed[] = { 123*bfce552dSPankaj Dubey EXYNOS5_ARM_CORE0_OPTION, 124*bfce552dSPankaj Dubey EXYNOS5_ARM_CORE1_OPTION, 125*bfce552dSPankaj Dubey EXYNOS5_ARM_COMMON_OPTION, 126*bfce552dSPankaj Dubey EXYNOS5_GSCL_OPTION, 127*bfce552dSPankaj Dubey EXYNOS5_ISP_OPTION, 128*bfce552dSPankaj Dubey EXYNOS5_MFC_OPTION, 129*bfce552dSPankaj Dubey EXYNOS5_G3D_OPTION, 130*bfce552dSPankaj Dubey EXYNOS5_DISP1_OPTION, 131*bfce552dSPankaj Dubey EXYNOS5_MAU_OPTION, 132*bfce552dSPankaj Dubey EXYNOS5_TOP_PWR_OPTION, 133*bfce552dSPankaj Dubey EXYNOS5_TOP_PWR_SYSMEM_OPTION, 134*bfce552dSPankaj Dubey }; 135*bfce552dSPankaj Dubey 136*bfce552dSPankaj Dubey static unsigned int const exynos5_list_disable_wfi_wfe[] = { 137*bfce552dSPankaj Dubey EXYNOS5_ARM_CORE1_OPTION, 138*bfce552dSPankaj Dubey EXYNOS5_FSYS_ARM_OPTION, 139*bfce552dSPankaj Dubey EXYNOS5_ISP_ARM_OPTION, 140*bfce552dSPankaj Dubey }; 141*bfce552dSPankaj Dubey 142*bfce552dSPankaj Dubey static void exynos5250_pmu_init(void) 143*bfce552dSPankaj Dubey { 144*bfce552dSPankaj Dubey unsigned int value; 145*bfce552dSPankaj Dubey /* 146*bfce552dSPankaj Dubey * When SYS_WDTRESET is set, watchdog timer reset request 147*bfce552dSPankaj Dubey * is ignored by power management unit. 148*bfce552dSPankaj Dubey */ 149*bfce552dSPankaj Dubey value = pmu_raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE); 150*bfce552dSPankaj Dubey value &= ~EXYNOS5_SYS_WDTRESET; 151*bfce552dSPankaj Dubey pmu_raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE); 152*bfce552dSPankaj Dubey 153*bfce552dSPankaj Dubey value = pmu_raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST); 154*bfce552dSPankaj Dubey value &= ~EXYNOS5_SYS_WDTRESET; 155*bfce552dSPankaj Dubey pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST); 156*bfce552dSPankaj Dubey } 157*bfce552dSPankaj Dubey 158*bfce552dSPankaj Dubey static void exynos5_powerdown_conf(enum sys_powerdown mode) 159*bfce552dSPankaj Dubey { 160*bfce552dSPankaj Dubey unsigned int i; 161*bfce552dSPankaj Dubey unsigned int tmp; 162*bfce552dSPankaj Dubey 163*bfce552dSPankaj Dubey /* 164*bfce552dSPankaj Dubey * Enable both SC_FEEDBACK and SC_COUNTER 165*bfce552dSPankaj Dubey */ 166*bfce552dSPankaj Dubey for (i = 0; i < ARRAY_SIZE(exynos5_list_both_cnt_feed); i++) { 167*bfce552dSPankaj Dubey tmp = pmu_raw_readl(exynos5_list_both_cnt_feed[i]); 168*bfce552dSPankaj Dubey tmp |= (EXYNOS5_USE_SC_FEEDBACK | 169*bfce552dSPankaj Dubey EXYNOS5_USE_SC_COUNTER); 170*bfce552dSPankaj Dubey pmu_raw_writel(tmp, exynos5_list_both_cnt_feed[i]); 171*bfce552dSPankaj Dubey } 172*bfce552dSPankaj Dubey 173*bfce552dSPankaj Dubey /* 174*bfce552dSPankaj Dubey * SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable 175*bfce552dSPankaj Dubey */ 176*bfce552dSPankaj Dubey tmp = pmu_raw_readl(EXYNOS5_ARM_COMMON_OPTION); 177*bfce552dSPankaj Dubey tmp |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN; 178*bfce552dSPankaj Dubey pmu_raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION); 179*bfce552dSPankaj Dubey 180*bfce552dSPankaj Dubey /* 181*bfce552dSPankaj Dubey * Disable WFI/WFE on XXX_OPTION 182*bfce552dSPankaj Dubey */ 183*bfce552dSPankaj Dubey for (i = 0; i < ARRAY_SIZE(exynos5_list_disable_wfi_wfe); i++) { 184*bfce552dSPankaj Dubey tmp = pmu_raw_readl(exynos5_list_disable_wfi_wfe[i]); 185*bfce552dSPankaj Dubey tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE | 186*bfce552dSPankaj Dubey EXYNOS5_OPTION_USE_STANDBYWFI); 187*bfce552dSPankaj Dubey pmu_raw_writel(tmp, exynos5_list_disable_wfi_wfe[i]); 188*bfce552dSPankaj Dubey } 189*bfce552dSPankaj Dubey } 190*bfce552dSPankaj Dubey 191*bfce552dSPankaj Dubey const struct exynos_pmu_data exynos5250_pmu_data = { 192*bfce552dSPankaj Dubey .pmu_config = exynos5250_pmu_config, 193*bfce552dSPankaj Dubey .pmu_init = exynos5250_pmu_init, 194*bfce552dSPankaj Dubey .powerdown_conf = exynos5_powerdown_conf, 195*bfce552dSPankaj Dubey }; 196