106512c53SKrzysztof Kozlowski // SPDX-License-Identifier: GPL-2.0 206512c53SKrzysztof Kozlowski // 306512c53SKrzysztof Kozlowski // Copyright (c) 2011-2015 Samsung Electronics Co., Ltd. 406512c53SKrzysztof Kozlowski // http://www.samsung.com/ 506512c53SKrzysztof Kozlowski // 6*94500540SKrzysztof Kozlowski // Exynos5250 - CPU PMU (Power Management Unit) support 7bfce552dSPankaj Dubey 8bfce552dSPankaj Dubey #include <linux/soc/samsung/exynos-regs-pmu.h> 9bfce552dSPankaj Dubey #include <linux/soc/samsung/exynos-pmu.h> 10bfce552dSPankaj Dubey 11bfce552dSPankaj Dubey #include "exynos-pmu.h" 12bfce552dSPankaj Dubey 13bfce552dSPankaj Dubey static const struct exynos_pmu_conf exynos5250_pmu_config[] = { 14bfce552dSPankaj Dubey /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */ 15bfce552dSPankaj Dubey { EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, 16bfce552dSPankaj Dubey { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, 17bfce552dSPankaj Dubey { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, 18bfce552dSPankaj Dubey { EXYNOS5_ARM_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, 19bfce552dSPankaj Dubey { EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, 20bfce552dSPankaj Dubey { EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, 21bfce552dSPankaj Dubey { EXYNOS5_FSYS_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 22bfce552dSPankaj Dubey { EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, 23bfce552dSPankaj Dubey { EXYNOS5_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 24bfce552dSPankaj Dubey { EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, 25bfce552dSPankaj Dubey { EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, 26bfce552dSPankaj Dubey { EXYNOS5_ARM_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, 27bfce552dSPankaj Dubey { EXYNOS5_ARM_L2_SYS_PWR_REG, { 0x3, 0x3, 0x3} }, 28ee55ae61SKrzysztof Kozlowski { EXYNOS_L2_OPTION(0), { 0x10, 0x10, 0x0 } }, 29bfce552dSPankaj Dubey { EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, 30bfce552dSPankaj Dubey { EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, 31bfce552dSPankaj Dubey { EXYNOS5_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, 32bfce552dSPankaj Dubey { EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, 33bfce552dSPankaj Dubey { EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, 34bfce552dSPankaj Dubey { EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, 35bfce552dSPankaj Dubey { EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, 36bfce552dSPankaj Dubey { EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, 37bfce552dSPankaj Dubey { EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, 38bfce552dSPankaj Dubey { EXYNOS5_APLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 39bfce552dSPankaj Dubey { EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 40bfce552dSPankaj Dubey { EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 41bfce552dSPankaj Dubey { EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, 42bfce552dSPankaj Dubey { EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 43bfce552dSPankaj Dubey { EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 44bfce552dSPankaj Dubey { EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 45bfce552dSPankaj Dubey { EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 46bfce552dSPankaj Dubey { EXYNOS5_TOP_BUS_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, 47bfce552dSPankaj Dubey { EXYNOS5_TOP_RETENTION_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, 48bfce552dSPankaj Dubey { EXYNOS5_TOP_PWR_SYS_PWR_REG, { 0x3, 0x0, 0x3} }, 49bfce552dSPankaj Dubey { EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, 50bfce552dSPankaj Dubey { EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, 51bfce552dSPankaj Dubey { EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x3} }, 52bfce552dSPankaj Dubey { EXYNOS5_LOGIC_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, 53bfce552dSPankaj Dubey { EXYNOS5_OSCCLK_GATE_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, 54bfce552dSPankaj Dubey { EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, 55bfce552dSPankaj Dubey { EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, 56bfce552dSPankaj Dubey { EXYNOS5_USBOTG_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, 57bfce552dSPankaj Dubey { EXYNOS5_G2D_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, 58bfce552dSPankaj Dubey { EXYNOS5_USBDRD_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, 59bfce552dSPankaj Dubey { EXYNOS5_SDMMC_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, 60bfce552dSPankaj Dubey { EXYNOS5_CSSYS_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, 61bfce552dSPankaj Dubey { EXYNOS5_SECSS_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, 62bfce552dSPankaj Dubey { EXYNOS5_ROTATOR_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, 63bfce552dSPankaj Dubey { EXYNOS5_INTRAM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, 64bfce552dSPankaj Dubey { EXYNOS5_INTROM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, 65bfce552dSPankaj Dubey { EXYNOS5_JPEG_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, 66bfce552dSPankaj Dubey { EXYNOS5_JPEG_MEM_OPTION, { 0x10, 0x10, 0x0} }, 67bfce552dSPankaj Dubey { EXYNOS5_HSI_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, 68bfce552dSPankaj Dubey { EXYNOS5_MCUIOP_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, 69bfce552dSPankaj Dubey { EXYNOS5_SATA_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, 70bfce552dSPankaj Dubey { EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 71bfce552dSPankaj Dubey { EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, 72bfce552dSPankaj Dubey { EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 73bfce552dSPankaj Dubey { EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 74bfce552dSPankaj Dubey { EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 75bfce552dSPankaj Dubey { EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 76bfce552dSPankaj Dubey { EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 77bfce552dSPankaj Dubey { EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 78bfce552dSPankaj Dubey { EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 79bfce552dSPankaj Dubey { EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 80bfce552dSPankaj Dubey { EXYNOS5_PAD_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 81bfce552dSPankaj Dubey { EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 82bfce552dSPankaj Dubey { EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 83bfce552dSPankaj Dubey { EXYNOS5_XUSBXTI_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, 84bfce552dSPankaj Dubey { EXYNOS5_XXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, 85bfce552dSPankaj Dubey { EXYNOS5_EXT_REGULATOR_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, 86bfce552dSPankaj Dubey { EXYNOS5_GPIO_MODE_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 87bfce552dSPankaj Dubey { EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 88bfce552dSPankaj Dubey { EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, 89bfce552dSPankaj Dubey { EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, 90bfce552dSPankaj Dubey { EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, 91bfce552dSPankaj Dubey { EXYNOS5_GSCL_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, 92bfce552dSPankaj Dubey { EXYNOS5_ISP_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, 93bfce552dSPankaj Dubey { EXYNOS5_MFC_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, 94bfce552dSPankaj Dubey { EXYNOS5_G3D_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, 95bfce552dSPankaj Dubey { EXYNOS5_DISP1_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, 96bfce552dSPankaj Dubey { EXYNOS5_MAU_SYS_PWR_REG, { 0x7, 0x7, 0x0} }, 97bfce552dSPankaj Dubey { EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 98bfce552dSPankaj Dubey { EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 99bfce552dSPankaj Dubey { EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 100bfce552dSPankaj Dubey { EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 101bfce552dSPankaj Dubey { EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 102bfce552dSPankaj Dubey { EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, 103bfce552dSPankaj Dubey { EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 104bfce552dSPankaj Dubey { EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 105bfce552dSPankaj Dubey { EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 106bfce552dSPankaj Dubey { EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 107bfce552dSPankaj Dubey { EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 108bfce552dSPankaj Dubey { EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, 109bfce552dSPankaj Dubey { EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 110bfce552dSPankaj Dubey { EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 111bfce552dSPankaj Dubey { EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 112bfce552dSPankaj Dubey { EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 113bfce552dSPankaj Dubey { EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 114bfce552dSPankaj Dubey { EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, 115bfce552dSPankaj Dubey { PMU_TABLE_END,}, 116bfce552dSPankaj Dubey }; 117bfce552dSPankaj Dubey 118bfce552dSPankaj Dubey static unsigned int const exynos5_list_both_cnt_feed[] = { 119bfce552dSPankaj Dubey EXYNOS5_ARM_CORE0_OPTION, 120bfce552dSPankaj Dubey EXYNOS5_ARM_CORE1_OPTION, 121bfce552dSPankaj Dubey EXYNOS5_ARM_COMMON_OPTION, 122bfce552dSPankaj Dubey EXYNOS5_GSCL_OPTION, 123bfce552dSPankaj Dubey EXYNOS5_ISP_OPTION, 124bfce552dSPankaj Dubey EXYNOS5_MFC_OPTION, 125bfce552dSPankaj Dubey EXYNOS5_G3D_OPTION, 126bfce552dSPankaj Dubey EXYNOS5_DISP1_OPTION, 127bfce552dSPankaj Dubey EXYNOS5_MAU_OPTION, 128bfce552dSPankaj Dubey EXYNOS5_TOP_PWR_OPTION, 129bfce552dSPankaj Dubey EXYNOS5_TOP_PWR_SYSMEM_OPTION, 130bfce552dSPankaj Dubey }; 131bfce552dSPankaj Dubey 132bfce552dSPankaj Dubey static unsigned int const exynos5_list_disable_wfi_wfe[] = { 133bfce552dSPankaj Dubey EXYNOS5_ARM_CORE1_OPTION, 134bfce552dSPankaj Dubey EXYNOS5_FSYS_ARM_OPTION, 135bfce552dSPankaj Dubey EXYNOS5_ISP_ARM_OPTION, 136bfce552dSPankaj Dubey }; 137bfce552dSPankaj Dubey 138bfce552dSPankaj Dubey static void exynos5250_pmu_init(void) 139bfce552dSPankaj Dubey { 140bfce552dSPankaj Dubey unsigned int value; 141bfce552dSPankaj Dubey /* 142bfce552dSPankaj Dubey * When SYS_WDTRESET is set, watchdog timer reset request 143bfce552dSPankaj Dubey * is ignored by power management unit. 144bfce552dSPankaj Dubey */ 145bfce552dSPankaj Dubey value = pmu_raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE); 146bfce552dSPankaj Dubey value &= ~EXYNOS5_SYS_WDTRESET; 147bfce552dSPankaj Dubey pmu_raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE); 148bfce552dSPankaj Dubey 149bfce552dSPankaj Dubey value = pmu_raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST); 150bfce552dSPankaj Dubey value &= ~EXYNOS5_SYS_WDTRESET; 151bfce552dSPankaj Dubey pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST); 152bfce552dSPankaj Dubey } 153bfce552dSPankaj Dubey 154bfce552dSPankaj Dubey static void exynos5_powerdown_conf(enum sys_powerdown mode) 155bfce552dSPankaj Dubey { 156bfce552dSPankaj Dubey unsigned int i; 157bfce552dSPankaj Dubey unsigned int tmp; 158bfce552dSPankaj Dubey 159bfce552dSPankaj Dubey /* 160bfce552dSPankaj Dubey * Enable both SC_FEEDBACK and SC_COUNTER 161bfce552dSPankaj Dubey */ 162bfce552dSPankaj Dubey for (i = 0; i < ARRAY_SIZE(exynos5_list_both_cnt_feed); i++) { 163bfce552dSPankaj Dubey tmp = pmu_raw_readl(exynos5_list_both_cnt_feed[i]); 164bfce552dSPankaj Dubey tmp |= (EXYNOS5_USE_SC_FEEDBACK | 165bfce552dSPankaj Dubey EXYNOS5_USE_SC_COUNTER); 166bfce552dSPankaj Dubey pmu_raw_writel(tmp, exynos5_list_both_cnt_feed[i]); 167bfce552dSPankaj Dubey } 168bfce552dSPankaj Dubey 169bfce552dSPankaj Dubey /* 170bfce552dSPankaj Dubey * SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable 171bfce552dSPankaj Dubey */ 172bfce552dSPankaj Dubey tmp = pmu_raw_readl(EXYNOS5_ARM_COMMON_OPTION); 173bfce552dSPankaj Dubey tmp |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN; 174bfce552dSPankaj Dubey pmu_raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION); 175bfce552dSPankaj Dubey 176bfce552dSPankaj Dubey /* 177bfce552dSPankaj Dubey * Disable WFI/WFE on XXX_OPTION 178bfce552dSPankaj Dubey */ 179bfce552dSPankaj Dubey for (i = 0; i < ARRAY_SIZE(exynos5_list_disable_wfi_wfe); i++) { 180bfce552dSPankaj Dubey tmp = pmu_raw_readl(exynos5_list_disable_wfi_wfe[i]); 181bfce552dSPankaj Dubey tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE | 182bfce552dSPankaj Dubey EXYNOS5_OPTION_USE_STANDBYWFI); 183bfce552dSPankaj Dubey pmu_raw_writel(tmp, exynos5_list_disable_wfi_wfe[i]); 184bfce552dSPankaj Dubey } 185bfce552dSPankaj Dubey } 186bfce552dSPankaj Dubey 187bfce552dSPankaj Dubey const struct exynos_pmu_data exynos5250_pmu_data = { 188bfce552dSPankaj Dubey .pmu_config = exynos5250_pmu_config, 189bfce552dSPankaj Dubey .pmu_init = exynos5250_pmu_init, 190bfce552dSPankaj Dubey .powerdown_conf = exynos5_powerdown_conf, 191bfce552dSPankaj Dubey }; 192