1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Rockchip Generic Register Files setup 4 * 5 * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de> 6 */ 7 8 #include <linux/err.h> 9 #include <linux/hw_bitfield.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 15 16 struct rockchip_grf_value { 17 const char *desc; 18 u32 reg; 19 u32 val; 20 }; 21 22 struct rockchip_grf_info { 23 const struct rockchip_grf_value *values; 24 int num_values; 25 }; 26 27 #define RK3036_GRF_SOC_CON0 0x140 28 29 static const struct rockchip_grf_value rk3036_defaults[] __initconst = { 30 /* 31 * Disable auto jtag/sdmmc switching that causes issues with the 32 * clock-framework and the mmc controllers making them unreliable. 33 */ 34 { "jtag switching", RK3036_GRF_SOC_CON0, FIELD_PREP_WM16_CONST(BIT(11), 0) }, 35 }; 36 37 static const struct rockchip_grf_info rk3036_grf __initconst = { 38 .values = rk3036_defaults, 39 .num_values = ARRAY_SIZE(rk3036_defaults), 40 }; 41 42 #define RK3128_GRF_SOC_CON0 0x140 43 #define RK3128_GRF_SOC_CON1 0x144 44 45 static const struct rockchip_grf_value rk3128_defaults[] __initconst = { 46 { "jtag switching", RK3128_GRF_SOC_CON0, FIELD_PREP_WM16_CONST(BIT(8), 0) }, 47 { "vpu main clock", RK3128_GRF_SOC_CON1, FIELD_PREP_WM16_CONST(BIT(10), 0) }, 48 }; 49 50 static const struct rockchip_grf_info rk3128_grf __initconst = { 51 .values = rk3128_defaults, 52 .num_values = ARRAY_SIZE(rk3128_defaults), 53 }; 54 55 #define RK3228_GRF_SOC_CON6 0x418 56 57 static const struct rockchip_grf_value rk3228_defaults[] __initconst = { 58 { "jtag switching", RK3228_GRF_SOC_CON6, FIELD_PREP_WM16_CONST(BIT(8), 0) }, 59 }; 60 61 static const struct rockchip_grf_info rk3228_grf __initconst = { 62 .values = rk3228_defaults, 63 .num_values = ARRAY_SIZE(rk3228_defaults), 64 }; 65 66 #define RK3288_GRF_SOC_CON0 0x244 67 #define RK3288_GRF_SOC_CON2 0x24c 68 69 static const struct rockchip_grf_value rk3288_defaults[] __initconst = { 70 { "jtag switching", RK3288_GRF_SOC_CON0, FIELD_PREP_WM16_CONST(BIT(12), 0) }, 71 { "pwm select", RK3288_GRF_SOC_CON2, FIELD_PREP_WM16_CONST(BIT(0), 1) }, 72 }; 73 74 static const struct rockchip_grf_info rk3288_grf __initconst = { 75 .values = rk3288_defaults, 76 .num_values = ARRAY_SIZE(rk3288_defaults), 77 }; 78 79 #define RK3328_GRF_SOC_CON4 0x410 80 81 static const struct rockchip_grf_value rk3328_defaults[] __initconst = { 82 { "jtag switching", RK3328_GRF_SOC_CON4, FIELD_PREP_WM16_CONST(BIT(12), 0) }, 83 }; 84 85 static const struct rockchip_grf_info rk3328_grf __initconst = { 86 .values = rk3328_defaults, 87 .num_values = ARRAY_SIZE(rk3328_defaults), 88 }; 89 90 #define RK3368_GRF_SOC_CON15 0x43c 91 92 static const struct rockchip_grf_value rk3368_defaults[] __initconst = { 93 { "jtag switching", RK3368_GRF_SOC_CON15, FIELD_PREP_WM16_CONST(BIT(13), 0) }, 94 }; 95 96 static const struct rockchip_grf_info rk3368_grf __initconst = { 97 .values = rk3368_defaults, 98 .num_values = ARRAY_SIZE(rk3368_defaults), 99 }; 100 101 #define RK3399_GRF_SOC_CON7 0xe21c 102 103 static const struct rockchip_grf_value rk3399_defaults[] __initconst = { 104 { "jtag switching", RK3399_GRF_SOC_CON7, FIELD_PREP_WM16_CONST(BIT(12), 0) }, 105 }; 106 107 static const struct rockchip_grf_info rk3399_grf __initconst = { 108 .values = rk3399_defaults, 109 .num_values = ARRAY_SIZE(rk3399_defaults), 110 }; 111 112 #define RK3566_GRF_USB3OTG0_CON1 0x0104 113 114 static const struct rockchip_grf_value rk3566_defaults[] __initconst = { 115 { "usb3otg port switch", RK3566_GRF_USB3OTG0_CON1, FIELD_PREP_WM16_CONST(BIT(12), 0) }, 116 { "usb3otg clock switch", RK3566_GRF_USB3OTG0_CON1, FIELD_PREP_WM16_CONST(BIT(7), 1) }, 117 { "usb3otg disable usb3", RK3566_GRF_USB3OTG0_CON1, FIELD_PREP_WM16_CONST(BIT(0), 1) }, 118 }; 119 120 static const struct rockchip_grf_info rk3566_pipegrf __initconst = { 121 .values = rk3566_defaults, 122 .num_values = ARRAY_SIZE(rk3566_defaults), 123 }; 124 125 #define RK3576_SYSGRF_SOC_CON1 0x0004 126 127 static const struct rockchip_grf_value rk3576_defaults_sys_grf[] __initconst = { 128 { "i3c0 weakpull", RK3576_SYSGRF_SOC_CON1, FIELD_PREP_WM16_CONST(GENMASK(7, 6), 3) }, 129 { "i3c1 weakpull", RK3576_SYSGRF_SOC_CON1, FIELD_PREP_WM16_CONST(GENMASK(9, 8), 3) }, 130 }; 131 132 static const struct rockchip_grf_info rk3576_sysgrf __initconst = { 133 .values = rk3576_defaults_sys_grf, 134 .num_values = ARRAY_SIZE(rk3576_defaults_sys_grf), 135 }; 136 137 #define RK3576_IOCGRF_MISC_CON 0x04F0 138 139 static const struct rockchip_grf_value rk3576_defaults_ioc_grf[] __initconst = { 140 { "jtag switching", RK3576_IOCGRF_MISC_CON, FIELD_PREP_WM16_CONST(BIT(1), 0) }, 141 }; 142 143 static const struct rockchip_grf_info rk3576_iocgrf __initconst = { 144 .values = rk3576_defaults_ioc_grf, 145 .num_values = ARRAY_SIZE(rk3576_defaults_ioc_grf), 146 }; 147 148 #define RK3588_GRF_SOC_CON6 0x0318 149 150 static const struct rockchip_grf_value rk3588_defaults[] __initconst = { 151 { "jtag switching", RK3588_GRF_SOC_CON6, FIELD_PREP_WM16_CONST(BIT(14), 0) }, 152 }; 153 154 static const struct rockchip_grf_info rk3588_sysgrf __initconst = { 155 .values = rk3588_defaults, 156 .num_values = ARRAY_SIZE(rk3588_defaults), 157 }; 158 159 static const struct of_device_id rockchip_grf_dt_match[] __initconst = { 160 { 161 .compatible = "rockchip,rk3036-grf", 162 .data = (void *)&rk3036_grf, 163 }, { 164 .compatible = "rockchip,rk3128-grf", 165 .data = (void *)&rk3128_grf, 166 }, { 167 .compatible = "rockchip,rk3228-grf", 168 .data = (void *)&rk3228_grf, 169 }, { 170 .compatible = "rockchip,rk3288-grf", 171 .data = (void *)&rk3288_grf, 172 }, { 173 .compatible = "rockchip,rk3328-grf", 174 .data = (void *)&rk3328_grf, 175 }, { 176 .compatible = "rockchip,rk3368-grf", 177 .data = (void *)&rk3368_grf, 178 }, { 179 .compatible = "rockchip,rk3399-grf", 180 .data = (void *)&rk3399_grf, 181 }, { 182 .compatible = "rockchip,rk3566-pipe-grf", 183 .data = (void *)&rk3566_pipegrf, 184 }, { 185 .compatible = "rockchip,rk3576-sys-grf", 186 .data = (void *)&rk3576_sysgrf, 187 }, { 188 .compatible = "rockchip,rk3576-ioc-grf", 189 .data = (void *)&rk3576_iocgrf, 190 }, { 191 .compatible = "rockchip,rk3588-sys-grf", 192 .data = (void *)&rk3588_sysgrf, 193 }, 194 { /* sentinel */ }, 195 }; 196 197 static int __init rockchip_grf_init(void) 198 { 199 const struct rockchip_grf_info *grf_info; 200 const struct of_device_id *match; 201 struct device_node *np; 202 struct regmap *grf; 203 int ret, i; 204 205 np = of_find_matching_node_and_match(NULL, rockchip_grf_dt_match, 206 &match); 207 if (!np) 208 return -ENODEV; 209 if (!match || !match->data) { 210 pr_err("%s: missing grf data\n", __func__); 211 of_node_put(np); 212 return -EINVAL; 213 } 214 215 grf_info = match->data; 216 217 grf = syscon_node_to_regmap(np); 218 of_node_put(np); 219 if (IS_ERR(grf)) { 220 pr_err("%s: could not get grf syscon\n", __func__); 221 return PTR_ERR(grf); 222 } 223 224 for (i = 0; i < grf_info->num_values; i++) { 225 const struct rockchip_grf_value *val = &grf_info->values[i]; 226 227 pr_debug("%s: adjusting %s in %#6x to %#10x\n", __func__, 228 val->desc, val->reg, val->val); 229 ret = regmap_write(grf, val->reg, val->val); 230 if (ret < 0) 231 pr_err("%s: write to %#6x failed with %d\n", 232 __func__, val->reg, ret); 233 } 234 235 return 0; 236 } 237 postcore_initcall(rockchip_grf_init); 238