1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * RZ/G3E System controller (SYS) driver 4 * 5 * Copyright (C) 2025 Renesas Electronics Corp. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bits.h> 10 #include <linux/device.h> 11 #include <linux/init.h> 12 #include <linux/io.h> 13 14 #include "rz-sysc.h" 15 16 /* Register Offsets */ 17 #define SYS_LSI_MODE 0x300 18 /* 19 * BOOTPLLCA[1:0] 20 * [0,0] => 1.1GHZ 21 * [0,1] => 1.5GHZ 22 * [1,0] => 1.6GHZ 23 * [1,1] => 1.7GHZ 24 */ 25 #define SYS_LSI_MODE_STAT_BOOTPLLCA55 GENMASK(12, 11) 26 #define SYS_LSI_MODE_CA55_1_7GHZ 0x3 27 28 #define SYS_LSI_PRR 0x308 29 #define SYS_LSI_PRR_CA55_DIS BIT(8) 30 #define SYS_LSI_PRR_NPU_DIS BIT(1) 31 32 #define SYS_LSI_OTPTSU1TRMVAL0 0x330 33 #define SYS_LSI_OTPTSU1TRMVAL1 0x334 34 #define SYS_SPI_STAADDCS0 0x900 35 #define SYS_SPI_ENDADDCS0 0x904 36 #define SYS_SPI_STAADDCS1 0x908 37 #define SYS_SPI_ENDADDCS1 0x90c 38 #define SYS_VSP_CLK 0xe00 39 #define SYS_GBETH0_CFG 0xf00 40 #define SYS_GBETH1_CFG 0xf04 41 #define SYS_PCIE_INTX_CH0 0x1000 42 #define SYS_PCIE_MSI1_CH0 0x1004 43 #define SYS_PCIE_MSI2_CH0 0x1008 44 #define SYS_PCIE_MSI3_CH0 0x100c 45 #define SYS_PCIE_MSI4_CH0 0x1010 46 #define SYS_PCIE_MSI5_CH0 0x1014 47 #define SYS_PCIE_PME_CH0 0x1018 48 #define SYS_PCIE_ACK_CH0 0x101c 49 #define SYS_PCIE_MISC_CH0 0x1020 50 #define SYS_PCIE_MODE_CH0 0x1024 51 #define SYS_ADC_CFG 0x1600 52 53 static void rzg3e_sys_print_id(struct device *dev, 54 void __iomem *sysc_base, 55 struct soc_device_attribute *soc_dev_attr) 56 { 57 bool is_quad_core, npu_enabled; 58 u32 prr_val, mode_val; 59 60 prr_val = readl(sysc_base + SYS_LSI_PRR); 61 mode_val = readl(sysc_base + SYS_LSI_MODE); 62 63 /* Check CPU and NPU configuration */ 64 is_quad_core = !(prr_val & SYS_LSI_PRR_CA55_DIS); 65 npu_enabled = !(prr_val & SYS_LSI_PRR_NPU_DIS); 66 67 dev_info(dev, "Detected Renesas %s Core %s %s Rev %s%s\n", 68 is_quad_core ? "Quad" : "Dual", soc_dev_attr->family, 69 soc_dev_attr->soc_id, soc_dev_attr->revision, 70 npu_enabled ? " with Ethos-U55" : ""); 71 72 /* Check CA55 PLL configuration */ 73 if (FIELD_GET(SYS_LSI_MODE_STAT_BOOTPLLCA55, mode_val) != SYS_LSI_MODE_CA55_1_7GHZ) 74 dev_warn(dev, "CA55 PLL is not set to 1.7GHz\n"); 75 } 76 77 static const struct rz_sysc_soc_id_init_data rzg3e_sys_soc_id_init_data __initconst = { 78 .family = "RZ/G3E", 79 .id = 0x8679447, 80 .devid_offset = 0x304, 81 .revision_mask = GENMASK(31, 28), 82 .specific_id_mask = GENMASK(27, 0), 83 .print_id = rzg3e_sys_print_id, 84 }; 85 86 static bool rzg3e_regmap_readable_reg(struct device *dev, unsigned int reg) 87 { 88 switch (reg) { 89 case SYS_LSI_OTPTSU1TRMVAL0: 90 case SYS_LSI_OTPTSU1TRMVAL1: 91 case SYS_SPI_STAADDCS0: 92 case SYS_SPI_ENDADDCS0: 93 case SYS_SPI_STAADDCS1: 94 case SYS_SPI_ENDADDCS1: 95 case SYS_VSP_CLK: 96 case SYS_GBETH0_CFG: 97 case SYS_GBETH1_CFG: 98 case SYS_PCIE_INTX_CH0: 99 case SYS_PCIE_MSI1_CH0: 100 case SYS_PCIE_MSI2_CH0: 101 case SYS_PCIE_MSI3_CH0: 102 case SYS_PCIE_MSI4_CH0: 103 case SYS_PCIE_MSI5_CH0: 104 case SYS_PCIE_PME_CH0: 105 case SYS_PCIE_ACK_CH0: 106 case SYS_PCIE_MISC_CH0: 107 case SYS_PCIE_MODE_CH0: 108 case SYS_ADC_CFG: 109 return true; 110 default: 111 return false; 112 } 113 } 114 115 static bool rzg3e_regmap_writeable_reg(struct device *dev, unsigned int reg) 116 { 117 switch (reg) { 118 case SYS_SPI_STAADDCS0: 119 case SYS_SPI_ENDADDCS0: 120 case SYS_SPI_STAADDCS1: 121 case SYS_SPI_ENDADDCS1: 122 case SYS_VSP_CLK: 123 case SYS_GBETH0_CFG: 124 case SYS_GBETH1_CFG: 125 case SYS_PCIE_INTX_CH0: 126 case SYS_PCIE_MSI1_CH0: 127 case SYS_PCIE_MSI2_CH0: 128 case SYS_PCIE_MSI3_CH0: 129 case SYS_PCIE_MSI4_CH0: 130 case SYS_PCIE_MSI5_CH0: 131 case SYS_PCIE_PME_CH0: 132 case SYS_PCIE_ACK_CH0: 133 case SYS_PCIE_MISC_CH0: 134 case SYS_PCIE_MODE_CH0: 135 case SYS_ADC_CFG: 136 return true; 137 default: 138 return false; 139 } 140 } 141 142 const struct rz_sysc_init_data rzg3e_sys_init_data = { 143 .soc_id_init_data = &rzg3e_sys_soc_id_init_data, 144 .readable_reg = rzg3e_regmap_readable_reg, 145 .writeable_reg = rzg3e_regmap_writeable_reg, 146 .max_register = 0x170c, 147 }; 148