1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * RZ/G3S System controller driver 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8 #include <linux/bits.h> 9 #include <linux/device.h> 10 #include <linux/init.h> 11 12 #include "rz-sysc.h" 13 14 #define SYS_XSPI_MAP_STAADD_CS0 0x348 15 #define SYS_XSPI_MAP_ENDADD_CS0 0x34c 16 #define SYS_XSPI_MAP_STAADD_CS1 0x350 17 #define SYS_XSPI_MAP_ENDADD_CS1 0x354 18 #define SYS_GETH0_CFG 0x380 19 #define SYS_GETH1_CFG 0x390 20 #define SYS_PCIE_CFG 0x3a0 21 #define SYS_PCIE_MON 0x3a4 22 #define SYS_PCIE_ERR_MON 0x3ac 23 #define SYS_PCIE_PHY 0x3b4 24 #define SYS_I2C0_CFG 0x400 25 #define SYS_I2C1_CFG 0x410 26 #define SYS_I2C2_CFG 0x420 27 #define SYS_I2C3_CFG 0x430 28 #define SYS_I3C_CFG 0x440 29 #define SYS_USB_PWRRDY 0xd70 30 #define SYS_PCIE_RST_RSM_B 0xd74 31 32 static const struct rz_sysc_soc_id_init_data rzg3s_sysc_soc_id_init_data __initconst = { 33 .family = "RZ/G3S", 34 .id = 0x85e0447, 35 .devid_offset = 0xa04, 36 .revision_mask = GENMASK(31, 28), 37 .specific_id_mask = GENMASK(27, 0), 38 }; 39 40 static bool rzg3s_regmap_readable_reg(struct device *dev, unsigned int reg) 41 { 42 switch (reg) { 43 case SYS_XSPI_MAP_STAADD_CS0: 44 case SYS_XSPI_MAP_ENDADD_CS0: 45 case SYS_XSPI_MAP_STAADD_CS1: 46 case SYS_XSPI_MAP_ENDADD_CS1: 47 case SYS_GETH0_CFG: 48 case SYS_GETH1_CFG: 49 case SYS_PCIE_CFG: 50 case SYS_PCIE_MON: 51 case SYS_PCIE_ERR_MON: 52 case SYS_PCIE_PHY: 53 case SYS_I2C0_CFG: 54 case SYS_I2C1_CFG: 55 case SYS_I2C2_CFG: 56 case SYS_I2C3_CFG: 57 case SYS_I3C_CFG: 58 case SYS_USB_PWRRDY: 59 case SYS_PCIE_RST_RSM_B: 60 return true; 61 default: 62 return false; 63 } 64 } 65 66 static bool rzg3s_regmap_writeable_reg(struct device *dev, unsigned int reg) 67 { 68 switch (reg) { 69 case SYS_XSPI_MAP_STAADD_CS0: 70 case SYS_XSPI_MAP_ENDADD_CS0: 71 case SYS_XSPI_MAP_STAADD_CS1: 72 case SYS_XSPI_MAP_ENDADD_CS1: 73 case SYS_PCIE_CFG: 74 case SYS_PCIE_PHY: 75 case SYS_I2C0_CFG: 76 case SYS_I2C1_CFG: 77 case SYS_I2C2_CFG: 78 case SYS_I2C3_CFG: 79 case SYS_I3C_CFG: 80 case SYS_USB_PWRRDY: 81 case SYS_PCIE_RST_RSM_B: 82 return true; 83 default: 84 return false; 85 } 86 } 87 88 const struct rz_sysc_init_data rzg3s_sysc_init_data __initconst = { 89 .soc_id_init_data = &rzg3s_sysc_soc_id_init_data, 90 .readable_reg = rzg3s_regmap_readable_reg, 91 .writeable_reg = rzg3s_regmap_writeable_reg, 92 .max_register = 0xe20, 93 }; 94