1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/debugfs.h> 7 #include <linux/io.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/of_address.h> 11 #include <linux/platform_device.h> 12 13 #include <linux/soc/qcom/ubwc.h> 14 15 static const struct qcom_ubwc_cfg_data no_ubwc_data = { 16 /* no UBWC, no HBB */ 17 }; 18 19 static const struct qcom_ubwc_cfg_data msm8937_data = { 20 .ubwc_enc_version = UBWC_1_0, 21 .ubwc_dec_version = UBWC_1_0, 22 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 | 23 UBWC_SWIZZLE_ENABLE_LVL2 | 24 UBWC_SWIZZLE_ENABLE_LVL3, 25 .highest_bank_bit = 14, 26 }; 27 28 static const struct qcom_ubwc_cfg_data msm8998_data = { 29 .ubwc_enc_version = UBWC_1_0, 30 .ubwc_dec_version = UBWC_1_0, 31 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 | 32 UBWC_SWIZZLE_ENABLE_LVL2 | 33 UBWC_SWIZZLE_ENABLE_LVL3, 34 .highest_bank_bit = 15, 35 }; 36 37 static const struct qcom_ubwc_cfg_data qcm2290_data = { 38 /* no UBWC */ 39 .highest_bank_bit = 15, 40 }; 41 42 static const struct qcom_ubwc_cfg_data sa8775p_data = { 43 .ubwc_enc_version = UBWC_4_0, 44 .ubwc_dec_version = UBWC_4_0, 45 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL3, 46 .ubwc_bank_spread = true, 47 .highest_bank_bit = 13, 48 .macrotile_mode = true, 49 }; 50 51 static const struct qcom_ubwc_cfg_data sar2130p_data = { 52 .ubwc_enc_version = UBWC_3_0, /* 4.0.2 in hw */ 53 .ubwc_dec_version = UBWC_4_3, 54 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | 55 UBWC_SWIZZLE_ENABLE_LVL3, 56 .ubwc_bank_spread = true, 57 .highest_bank_bit = 13, 58 .macrotile_mode = true, 59 }; 60 61 static const struct qcom_ubwc_cfg_data sc7180_data = { 62 .ubwc_enc_version = UBWC_2_0, 63 .ubwc_dec_version = UBWC_2_0, 64 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | 65 UBWC_SWIZZLE_ENABLE_LVL3, 66 .ubwc_bank_spread = true, 67 .highest_bank_bit = 14, 68 }; 69 70 static const struct qcom_ubwc_cfg_data sc7280_data = { 71 .ubwc_enc_version = UBWC_3_0, 72 .ubwc_dec_version = UBWC_4_0, 73 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | 74 UBWC_SWIZZLE_ENABLE_LVL3, 75 .ubwc_bank_spread = true, 76 .highest_bank_bit = 14, 77 .macrotile_mode = true, 78 }; 79 80 static const struct qcom_ubwc_cfg_data sc8180x_data = { 81 .ubwc_enc_version = UBWC_3_0, 82 .ubwc_dec_version = UBWC_3_0, 83 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | 84 UBWC_SWIZZLE_ENABLE_LVL3, 85 .highest_bank_bit = 16, 86 .macrotile_mode = true, 87 }; 88 89 static const struct qcom_ubwc_cfg_data sc8280xp_data = { 90 .ubwc_enc_version = UBWC_4_0, 91 .ubwc_dec_version = UBWC_4_0, 92 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | 93 UBWC_SWIZZLE_ENABLE_LVL3, 94 .ubwc_bank_spread = true, 95 .highest_bank_bit = 16, 96 .macrotile_mode = true, 97 }; 98 99 static const struct qcom_ubwc_cfg_data sdm670_data = { 100 .ubwc_enc_version = UBWC_2_0, 101 .ubwc_dec_version = UBWC_2_0, 102 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | 103 UBWC_SWIZZLE_ENABLE_LVL3, 104 .highest_bank_bit = 14, 105 }; 106 107 static const struct qcom_ubwc_cfg_data sdm845_data = { 108 .ubwc_enc_version = UBWC_2_0, 109 .ubwc_dec_version = UBWC_2_0, 110 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | 111 UBWC_SWIZZLE_ENABLE_LVL3, 112 .highest_bank_bit = 15, 113 }; 114 115 static const struct qcom_ubwc_cfg_data sm6115_data = { 116 .ubwc_enc_version = UBWC_1_0, 117 .ubwc_dec_version = UBWC_2_0, 118 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 | 119 UBWC_SWIZZLE_ENABLE_LVL2 | 120 UBWC_SWIZZLE_ENABLE_LVL3, 121 .ubwc_bank_spread = true, 122 .highest_bank_bit = 14, 123 }; 124 125 static const struct qcom_ubwc_cfg_data sm6125_data = { 126 .ubwc_enc_version = UBWC_1_0, 127 .ubwc_dec_version = UBWC_3_0, 128 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 | 129 UBWC_SWIZZLE_ENABLE_LVL2 | 130 UBWC_SWIZZLE_ENABLE_LVL3, 131 .highest_bank_bit = 14, 132 }; 133 134 static const struct qcom_ubwc_cfg_data sm6150_data = { 135 .ubwc_enc_version = UBWC_2_0, 136 .ubwc_dec_version = UBWC_2_0, 137 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | 138 UBWC_SWIZZLE_ENABLE_LVL3, 139 .highest_bank_bit = 14, 140 }; 141 142 static const struct qcom_ubwc_cfg_data sm6350_data = { 143 .ubwc_enc_version = UBWC_2_0, 144 .ubwc_dec_version = UBWC_2_0, 145 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | 146 UBWC_SWIZZLE_ENABLE_LVL3, 147 .ubwc_bank_spread = true, 148 .highest_bank_bit = 14, 149 }; 150 151 static const struct qcom_ubwc_cfg_data sm7150_data = { 152 .ubwc_enc_version = UBWC_2_0, 153 .ubwc_dec_version = UBWC_2_0, 154 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | 155 UBWC_SWIZZLE_ENABLE_LVL3, 156 .highest_bank_bit = 14, 157 }; 158 159 static const struct qcom_ubwc_cfg_data sm8150_data = { 160 .ubwc_enc_version = UBWC_3_0, 161 .ubwc_dec_version = UBWC_3_0, 162 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | 163 UBWC_SWIZZLE_ENABLE_LVL3, 164 .highest_bank_bit = 15, 165 }; 166 167 static const struct qcom_ubwc_cfg_data sm8250_data = { 168 .ubwc_enc_version = UBWC_4_0, 169 .ubwc_dec_version = UBWC_4_0, 170 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | 171 UBWC_SWIZZLE_ENABLE_LVL3, 172 .ubwc_bank_spread = true, 173 /* TODO: highest_bank_bit = 15 for LP_DDR4 */ 174 .highest_bank_bit = 16, 175 .macrotile_mode = true, 176 }; 177 178 static const struct qcom_ubwc_cfg_data sm8350_data = { 179 .ubwc_enc_version = UBWC_4_0, 180 .ubwc_dec_version = UBWC_4_0, 181 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | 182 UBWC_SWIZZLE_ENABLE_LVL3, 183 .ubwc_bank_spread = true, 184 /* TODO: highest_bank_bit = 15 for LP_DDR4 */ 185 .highest_bank_bit = 16, 186 .macrotile_mode = true, 187 }; 188 189 static const struct qcom_ubwc_cfg_data sm8550_data = { 190 .ubwc_enc_version = UBWC_4_0, 191 .ubwc_dec_version = UBWC_4_3, 192 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | 193 UBWC_SWIZZLE_ENABLE_LVL3, 194 .ubwc_bank_spread = true, 195 /* TODO: highest_bank_bit = 15 for LP_DDR4 */ 196 .highest_bank_bit = 16, 197 .macrotile_mode = true, 198 }; 199 200 static const struct qcom_ubwc_cfg_data sm8750_data = { 201 .ubwc_enc_version = UBWC_5_0, 202 .ubwc_dec_version = UBWC_5_0, 203 .ubwc_swizzle = 6, 204 .ubwc_bank_spread = true, 205 /* TODO: highest_bank_bit = 15 for LP_DDR4 */ 206 .highest_bank_bit = 16, 207 .macrotile_mode = true, 208 }; 209 210 static const struct qcom_ubwc_cfg_data x1e80100_data = { 211 .ubwc_enc_version = UBWC_4_0, 212 .ubwc_dec_version = UBWC_4_3, 213 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | 214 UBWC_SWIZZLE_ENABLE_LVL3, 215 .ubwc_bank_spread = true, 216 /* TODO: highest_bank_bit = 15 for LP_DDR4 */ 217 .highest_bank_bit = 16, 218 .macrotile_mode = true, 219 }; 220 221 static const struct of_device_id qcom_ubwc_configs[] __maybe_unused = { 222 { .compatible = "qcom,apq8016", .data = &no_ubwc_data }, 223 { .compatible = "qcom,apq8026", .data = &no_ubwc_data }, 224 { .compatible = "qcom,apq8074", .data = &no_ubwc_data }, 225 { .compatible = "qcom,apq8096", .data = &msm8998_data }, 226 { .compatible = "qcom,msm8226", .data = &no_ubwc_data }, 227 { .compatible = "qcom,msm8916", .data = &no_ubwc_data }, 228 { .compatible = "qcom,msm8917", .data = &no_ubwc_data }, 229 { .compatible = "qcom,msm8937", .data = &msm8937_data }, 230 { .compatible = "qcom,msm8929", .data = &no_ubwc_data }, 231 { .compatible = "qcom,msm8939", .data = &no_ubwc_data }, 232 { .compatible = "qcom,msm8953", .data = &msm8937_data }, 233 { .compatible = "qcom,msm8956", .data = &no_ubwc_data }, 234 { .compatible = "qcom,msm8974", .data = &no_ubwc_data }, 235 { .compatible = "qcom,msm8976", .data = &no_ubwc_data }, 236 { .compatible = "qcom,msm8996", .data = &msm8998_data }, 237 { .compatible = "qcom,msm8998", .data = &msm8998_data }, 238 { .compatible = "qcom,qcm2290", .data = &qcm2290_data, }, 239 { .compatible = "qcom,qcm6490", .data = &sc7280_data, }, 240 { .compatible = "qcom,sa8155p", .data = &sm8150_data, }, 241 { .compatible = "qcom,sa8540p", .data = &sc8280xp_data, }, 242 { .compatible = "qcom,sa8775p", .data = &sa8775p_data, }, 243 { .compatible = "qcom,sar2130p", .data = &sar2130p_data }, 244 { .compatible = "qcom,sc7180", .data = &sc7180_data }, 245 { .compatible = "qcom,sc7280", .data = &sc7280_data, }, 246 { .compatible = "qcom,sc8180x", .data = &sc8180x_data, }, 247 { .compatible = "qcom,sc8280xp", .data = &sc8280xp_data, }, 248 { .compatible = "qcom,sda660", .data = &msm8937_data }, 249 { .compatible = "qcom,sdm450", .data = &msm8937_data }, 250 { .compatible = "qcom,sdm630", .data = &msm8937_data }, 251 { .compatible = "qcom,sdm632", .data = &msm8937_data }, 252 { .compatible = "qcom,sdm636", .data = &msm8937_data }, 253 { .compatible = "qcom,sdm660", .data = &msm8937_data }, 254 { .compatible = "qcom,sdm670", .data = &sdm670_data, }, 255 { .compatible = "qcom,sdm845", .data = &sdm845_data, }, 256 { .compatible = "qcom,sm4250", .data = &sm6115_data, }, 257 { .compatible = "qcom,sm6115", .data = &sm6115_data, }, 258 { .compatible = "qcom,sm6125", .data = &sm6125_data, }, 259 { .compatible = "qcom,sm6150", .data = &sm6150_data, }, 260 { .compatible = "qcom,sm6350", .data = &sm6350_data, }, 261 { .compatible = "qcom,sm6375", .data = &sm6350_data, }, 262 { .compatible = "qcom,sm7125", .data = &sc7180_data }, 263 { .compatible = "qcom,sm7150", .data = &sm7150_data, }, 264 { .compatible = "qcom,sm7225", .data = &sm6350_data, }, 265 { .compatible = "qcom,sm7325", .data = &sc7280_data, }, 266 { .compatible = "qcom,sm8150", .data = &sm8150_data, }, 267 { .compatible = "qcom,sm8250", .data = &sm8250_data, }, 268 { .compatible = "qcom,sm8350", .data = &sm8350_data, }, 269 { .compatible = "qcom,sm8450", .data = &sm8350_data, }, 270 { .compatible = "qcom,sm8550", .data = &sm8550_data, }, 271 { .compatible = "qcom,sm8650", .data = &sm8550_data, }, 272 { .compatible = "qcom,sm8750", .data = &sm8750_data, }, 273 { .compatible = "qcom,x1e80100", .data = &x1e80100_data, }, 274 { .compatible = "qcom,x1p42100", .data = &x1e80100_data, }, 275 { } 276 }; 277 278 const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void) 279 { 280 const struct of_device_id *match; 281 struct device_node *root; 282 283 root = of_find_node_by_path("/"); 284 if (!root) 285 return ERR_PTR(-ENODEV); 286 287 match = of_match_node(qcom_ubwc_configs, root); 288 of_node_put(root); 289 if (!match) { 290 pr_err("Couldn't find UBWC config data for this platform!\n"); 291 return ERR_PTR(-EINVAL); 292 } 293 294 return match->data; 295 } 296 EXPORT_SYMBOL_GPL(qcom_ubwc_config_get_data); 297 298 MODULE_LICENSE("GPL"); 299 MODULE_DESCRIPTION("UBWC config database for QTI SoCs"); 300