1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2011-2014, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2014,2015, Linaro Ltd. 5 * 6 * SAW power controller driver 7 */ 8 9 #include <linux/kernel.h> 10 #include <linux/init.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/slab.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/of_device.h> 17 #include <linux/err.h> 18 #include <linux/platform_device.h> 19 #include <soc/qcom/spm.h> 20 21 #define SPM_CTL_INDEX 0x7f 22 #define SPM_CTL_INDEX_SHIFT 4 23 #define SPM_CTL_EN BIT(0) 24 25 enum spm_reg { 26 SPM_REG_CFG, 27 SPM_REG_SPM_CTL, 28 SPM_REG_DLY, 29 SPM_REG_PMIC_DLY, 30 SPM_REG_PMIC_DATA_0, 31 SPM_REG_PMIC_DATA_1, 32 SPM_REG_VCTL, 33 SPM_REG_SEQ_ENTRY, 34 SPM_REG_SPM_STS, 35 SPM_REG_PMIC_STS, 36 SPM_REG_NR, 37 }; 38 39 static const u8 spm_reg_offset_v2_1[SPM_REG_NR] = { 40 [SPM_REG_CFG] = 0x08, 41 [SPM_REG_SPM_CTL] = 0x30, 42 [SPM_REG_DLY] = 0x34, 43 [SPM_REG_SEQ_ENTRY] = 0x80, 44 }; 45 46 /* SPM register data for 8974, 8084 */ 47 static const struct spm_reg_data spm_reg_8974_8084_cpu = { 48 .reg_offset = spm_reg_offset_v2_1, 49 .spm_cfg = 0x1, 50 .spm_dly = 0x3C102800, 51 .seq = { 0x03, 0x0B, 0x0F, 0x00, 0x20, 0x80, 0x10, 0xE8, 0x5B, 0x03, 52 0x3B, 0xE8, 0x5B, 0x82, 0x10, 0x0B, 0x30, 0x06, 0x26, 0x30, 53 0x0F }, 54 .start_index[PM_SLEEP_MODE_STBY] = 0, 55 .start_index[PM_SLEEP_MODE_SPC] = 3, 56 }; 57 58 /* SPM register data for 8226 */ 59 static const struct spm_reg_data spm_reg_8226_cpu = { 60 .reg_offset = spm_reg_offset_v2_1, 61 .spm_cfg = 0x0, 62 .spm_dly = 0x3C102800, 63 .seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x10, 0x80, 0x30, 0x90, 64 0x5B, 0x60, 0x03, 0x60, 0x3B, 0x76, 0x76, 0x0B, 0x94, 0x5B, 65 0x80, 0x10, 0x26, 0x30, 0x0F }, 66 .start_index[PM_SLEEP_MODE_STBY] = 0, 67 .start_index[PM_SLEEP_MODE_SPC] = 5, 68 }; 69 70 static const u8 spm_reg_offset_v1_1[SPM_REG_NR] = { 71 [SPM_REG_CFG] = 0x08, 72 [SPM_REG_SPM_CTL] = 0x20, 73 [SPM_REG_PMIC_DLY] = 0x24, 74 [SPM_REG_PMIC_DATA_0] = 0x28, 75 [SPM_REG_PMIC_DATA_1] = 0x2C, 76 [SPM_REG_SEQ_ENTRY] = 0x80, 77 }; 78 79 /* SPM register data for 8064 */ 80 static const struct spm_reg_data spm_reg_8064_cpu = { 81 .reg_offset = spm_reg_offset_v1_1, 82 .spm_cfg = 0x1F, 83 .pmic_dly = 0x02020004, 84 .pmic_data[0] = 0x0084009C, 85 .pmic_data[1] = 0x00A4001C, 86 .seq = { 0x03, 0x0F, 0x00, 0x24, 0x54, 0x10, 0x09, 0x03, 0x01, 87 0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F }, 88 .start_index[PM_SLEEP_MODE_STBY] = 0, 89 .start_index[PM_SLEEP_MODE_SPC] = 2, 90 }; 91 92 static inline void spm_register_write(struct spm_driver_data *drv, 93 enum spm_reg reg, u32 val) 94 { 95 if (drv->reg_data->reg_offset[reg]) 96 writel_relaxed(val, drv->reg_base + 97 drv->reg_data->reg_offset[reg]); 98 } 99 100 /* Ensure a guaranteed write, before return */ 101 static inline void spm_register_write_sync(struct spm_driver_data *drv, 102 enum spm_reg reg, u32 val) 103 { 104 u32 ret; 105 106 if (!drv->reg_data->reg_offset[reg]) 107 return; 108 109 do { 110 writel_relaxed(val, drv->reg_base + 111 drv->reg_data->reg_offset[reg]); 112 ret = readl_relaxed(drv->reg_base + 113 drv->reg_data->reg_offset[reg]); 114 if (ret == val) 115 break; 116 cpu_relax(); 117 } while (1); 118 } 119 120 static inline u32 spm_register_read(struct spm_driver_data *drv, 121 enum spm_reg reg) 122 { 123 return readl_relaxed(drv->reg_base + drv->reg_data->reg_offset[reg]); 124 } 125 126 void spm_set_low_power_mode(struct spm_driver_data *drv, 127 enum pm_sleep_mode mode) 128 { 129 u32 start_index; 130 u32 ctl_val; 131 132 start_index = drv->reg_data->start_index[mode]; 133 134 ctl_val = spm_register_read(drv, SPM_REG_SPM_CTL); 135 ctl_val &= ~(SPM_CTL_INDEX << SPM_CTL_INDEX_SHIFT); 136 ctl_val |= start_index << SPM_CTL_INDEX_SHIFT; 137 ctl_val |= SPM_CTL_EN; 138 spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val); 139 } 140 141 static const struct of_device_id spm_match_table[] = { 142 { .compatible = "qcom,msm8226-saw2-v2.1-cpu", 143 .data = &spm_reg_8226_cpu }, 144 { .compatible = "qcom,msm8974-saw2-v2.1-cpu", 145 .data = &spm_reg_8974_8084_cpu }, 146 { .compatible = "qcom,apq8084-saw2-v2.1-cpu", 147 .data = &spm_reg_8974_8084_cpu }, 148 { .compatible = "qcom,apq8064-saw2-v1.1-cpu", 149 .data = &spm_reg_8064_cpu }, 150 { }, 151 }; 152 MODULE_DEVICE_TABLE(of, spm_match_table); 153 154 static int spm_dev_probe(struct platform_device *pdev) 155 { 156 const struct of_device_id *match_id; 157 struct spm_driver_data *drv; 158 struct resource *res; 159 void __iomem *addr; 160 161 drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL); 162 if (!drv) 163 return -ENOMEM; 164 165 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 166 drv->reg_base = devm_ioremap_resource(&pdev->dev, res); 167 if (IS_ERR(drv->reg_base)) 168 return PTR_ERR(drv->reg_base); 169 170 match_id = of_match_node(spm_match_table, pdev->dev.of_node); 171 if (!match_id) 172 return -ENODEV; 173 174 drv->reg_data = match_id->data; 175 platform_set_drvdata(pdev, drv); 176 177 /* Write the SPM sequences first.. */ 178 addr = drv->reg_base + drv->reg_data->reg_offset[SPM_REG_SEQ_ENTRY]; 179 __iowrite32_copy(addr, drv->reg_data->seq, 180 ARRAY_SIZE(drv->reg_data->seq) / 4); 181 182 /* 183 * ..and then the control registers. 184 * On some SoC if the control registers are written first and if the 185 * CPU was held in reset, the reset signal could trigger the SPM state 186 * machine, before the sequences are completely written. 187 */ 188 spm_register_write(drv, SPM_REG_CFG, drv->reg_data->spm_cfg); 189 spm_register_write(drv, SPM_REG_DLY, drv->reg_data->spm_dly); 190 spm_register_write(drv, SPM_REG_PMIC_DLY, drv->reg_data->pmic_dly); 191 spm_register_write(drv, SPM_REG_PMIC_DATA_0, 192 drv->reg_data->pmic_data[0]); 193 spm_register_write(drv, SPM_REG_PMIC_DATA_1, 194 drv->reg_data->pmic_data[1]); 195 196 /* Set up Standby as the default low power mode */ 197 spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY); 198 199 return 0; 200 } 201 202 static struct platform_driver spm_driver = { 203 .probe = spm_dev_probe, 204 .driver = { 205 .name = "qcom_spm", 206 .of_match_table = spm_match_table, 207 }, 208 }; 209 210 static int __init qcom_spm_init(void) 211 { 212 return platform_driver_register(&spm_driver); 213 } 214 arch_initcall(qcom_spm_init); 215 216 MODULE_LICENSE("GPL v2"); 217