1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2009-2017, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2017-2019, Linaro Ltd. 5 */ 6 7 #include <linux/debugfs.h> 8 #include <linux/err.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <linux/random.h> 12 #include <linux/slab.h> 13 #include <linux/soc/qcom/smem.h> 14 #include <linux/string.h> 15 #include <linux/stringify.h> 16 #include <linux/sys_soc.h> 17 #include <linux/types.h> 18 19 #include <asm/unaligned.h> 20 21 #include <dt-bindings/arm/qcom,ids.h> 22 23 /* 24 * SoC version type with major number in the upper 16 bits and minor 25 * number in the lower 16 bits. 26 */ 27 #define SOCINFO_MAJOR(ver) (((ver) >> 16) & 0xffff) 28 #define SOCINFO_MINOR(ver) ((ver) & 0xffff) 29 #define SOCINFO_VERSION(maj, min) ((((maj) & 0xffff) << 16)|((min) & 0xffff)) 30 31 /* Helper macros to create soc_id table */ 32 #define qcom_board_id(id) QCOM_ID_ ## id, __stringify(id) 33 #define qcom_board_id_named(id, name) QCOM_ID_ ## id, (name) 34 35 #define SMEM_SOCINFO_BUILD_ID_LENGTH 32 36 #define SMEM_SOCINFO_CHIP_ID_LENGTH 32 37 38 /* 39 * SMEM item id, used to acquire handles to respective 40 * SMEM region. 41 */ 42 #define SMEM_HW_SW_BUILD_ID 137 43 44 #ifdef CONFIG_DEBUG_FS 45 #define SMEM_IMAGE_VERSION_BLOCKS_COUNT 32 46 #define SMEM_IMAGE_VERSION_SIZE 4096 47 #define SMEM_IMAGE_VERSION_NAME_SIZE 75 48 #define SMEM_IMAGE_VERSION_VARIANT_SIZE 20 49 #define SMEM_IMAGE_VERSION_OEM_SIZE 32 50 51 /* 52 * SMEM Image table indices 53 */ 54 #define SMEM_IMAGE_TABLE_BOOT_INDEX 0 55 #define SMEM_IMAGE_TABLE_TZ_INDEX 1 56 #define SMEM_IMAGE_TABLE_RPM_INDEX 3 57 #define SMEM_IMAGE_TABLE_APPS_INDEX 10 58 #define SMEM_IMAGE_TABLE_MPSS_INDEX 11 59 #define SMEM_IMAGE_TABLE_ADSP_INDEX 12 60 #define SMEM_IMAGE_TABLE_CNSS_INDEX 13 61 #define SMEM_IMAGE_TABLE_VIDEO_INDEX 14 62 #define SMEM_IMAGE_VERSION_TABLE 469 63 64 /* 65 * SMEM Image table names 66 */ 67 static const char *const socinfo_image_names[] = { 68 [SMEM_IMAGE_TABLE_ADSP_INDEX] = "adsp", 69 [SMEM_IMAGE_TABLE_APPS_INDEX] = "apps", 70 [SMEM_IMAGE_TABLE_BOOT_INDEX] = "boot", 71 [SMEM_IMAGE_TABLE_CNSS_INDEX] = "cnss", 72 [SMEM_IMAGE_TABLE_MPSS_INDEX] = "mpss", 73 [SMEM_IMAGE_TABLE_RPM_INDEX] = "rpm", 74 [SMEM_IMAGE_TABLE_TZ_INDEX] = "tz", 75 [SMEM_IMAGE_TABLE_VIDEO_INDEX] = "video", 76 }; 77 78 static const char *const pmic_models[] = { 79 [0] = "Unknown PMIC model", 80 [1] = "PM8941", 81 [2] = "PM8841", 82 [3] = "PM8019", 83 [4] = "PM8226", 84 [5] = "PM8110", 85 [6] = "PMA8084", 86 [7] = "PMI8962", 87 [8] = "PMD9635", 88 [9] = "PM8994", 89 [10] = "PMI8994", 90 [11] = "PM8916", 91 [12] = "PM8004", 92 [13] = "PM8909/PM8058", 93 [14] = "PM8028", 94 [15] = "PM8901", 95 [16] = "PM8950/PM8027", 96 [17] = "PMI8950/ISL9519", 97 [18] = "PMK8001/PM8921", 98 [19] = "PMI8996/PM8018", 99 [20] = "PM8998/PM8015", 100 [21] = "PMI8998/PM8014", 101 [22] = "PM8821", 102 [23] = "PM8038", 103 [24] = "PM8005/PM8922", 104 [25] = "PM8917", 105 [26] = "PM660L", 106 [27] = "PM660", 107 [30] = "PM8150", 108 [31] = "PM8150L", 109 [32] = "PM8150B", 110 [33] = "PMK8002", 111 [36] = "PM8009", 112 [38] = "PM8150C", 113 [41] = "SMB2351", 114 [45] = "PM6125", 115 [47] = "PMK8350", 116 [48] = "PM8350", 117 [49] = "PM8350C", 118 [50] = "PM8350B", 119 [51] = "PMR735A", 120 [52] = "PMR735B", 121 [58] = "PM8450", 122 [65] = "PM8010", 123 }; 124 #endif /* CONFIG_DEBUG_FS */ 125 126 /* Socinfo SMEM item structure */ 127 struct socinfo { 128 __le32 fmt; 129 __le32 id; 130 __le32 ver; 131 char build_id[SMEM_SOCINFO_BUILD_ID_LENGTH]; 132 /* Version 2 */ 133 __le32 raw_id; 134 __le32 raw_ver; 135 /* Version 3 */ 136 __le32 hw_plat; 137 /* Version 4 */ 138 __le32 plat_ver; 139 /* Version 5 */ 140 __le32 accessory_chip; 141 /* Version 6 */ 142 __le32 hw_plat_subtype; 143 /* Version 7 */ 144 __le32 pmic_model; 145 __le32 pmic_die_rev; 146 /* Version 8 */ 147 __le32 pmic_model_1; 148 __le32 pmic_die_rev_1; 149 __le32 pmic_model_2; 150 __le32 pmic_die_rev_2; 151 /* Version 9 */ 152 __le32 foundry_id; 153 /* Version 10 */ 154 __le32 serial_num; 155 /* Version 11 */ 156 __le32 num_pmics; 157 __le32 pmic_array_offset; 158 /* Version 12 */ 159 __le32 chip_family; 160 __le32 raw_device_family; 161 __le32 raw_device_num; 162 /* Version 13 */ 163 __le32 nproduct_id; 164 char chip_id[SMEM_SOCINFO_CHIP_ID_LENGTH]; 165 /* Version 14 */ 166 __le32 num_clusters; 167 __le32 ncluster_array_offset; 168 __le32 num_defective_parts; 169 __le32 ndefective_parts_array_offset; 170 /* Version 15 */ 171 __le32 nmodem_supported; 172 }; 173 174 #ifdef CONFIG_DEBUG_FS 175 struct socinfo_params { 176 u32 raw_device_family; 177 u32 hw_plat_subtype; 178 u32 accessory_chip; 179 u32 raw_device_num; 180 u32 chip_family; 181 u32 foundry_id; 182 u32 plat_ver; 183 u32 raw_ver; 184 u32 hw_plat; 185 u32 fmt; 186 u32 nproduct_id; 187 u32 num_clusters; 188 u32 ncluster_array_offset; 189 u32 num_defective_parts; 190 u32 ndefective_parts_array_offset; 191 u32 nmodem_supported; 192 }; 193 194 struct smem_image_version { 195 char name[SMEM_IMAGE_VERSION_NAME_SIZE]; 196 char variant[SMEM_IMAGE_VERSION_VARIANT_SIZE]; 197 char pad; 198 char oem[SMEM_IMAGE_VERSION_OEM_SIZE]; 199 }; 200 #endif /* CONFIG_DEBUG_FS */ 201 202 struct qcom_socinfo { 203 struct soc_device *soc_dev; 204 struct soc_device_attribute attr; 205 #ifdef CONFIG_DEBUG_FS 206 struct dentry *dbg_root; 207 struct socinfo_params info; 208 #endif /* CONFIG_DEBUG_FS */ 209 }; 210 211 struct soc_id { 212 unsigned int id; 213 const char *name; 214 }; 215 216 static const struct soc_id soc_id[] = { 217 { qcom_board_id(MSM8960) }, 218 { qcom_board_id(APQ8064) }, 219 { qcom_board_id(MSM8660A) }, 220 { qcom_board_id(MSM8260A) }, 221 { qcom_board_id(APQ8060A) }, 222 { qcom_board_id(MSM8974) }, 223 { qcom_board_id(MPQ8064) }, 224 { qcom_board_id(MSM8960AB) }, 225 { qcom_board_id(APQ8060AB) }, 226 { qcom_board_id(MSM8260AB) }, 227 { qcom_board_id(MSM8660AB) }, 228 { qcom_board_id(MSM8626) }, 229 { qcom_board_id(MSM8610) }, 230 { qcom_board_id(APQ8064AB) }, 231 { qcom_board_id(MSM8226) }, 232 { qcom_board_id(MSM8526) }, 233 { qcom_board_id(MSM8110) }, 234 { qcom_board_id(MSM8210) }, 235 { qcom_board_id(MSM8810) }, 236 { qcom_board_id(MSM8212) }, 237 { qcom_board_id(MSM8612) }, 238 { qcom_board_id(MSM8112) }, 239 { qcom_board_id(MSM8225Q) }, 240 { qcom_board_id(MSM8625Q) }, 241 { qcom_board_id(MSM8125Q) }, 242 { qcom_board_id(APQ8064AA) }, 243 { qcom_board_id(APQ8084) }, 244 { qcom_board_id(APQ8074) }, 245 { qcom_board_id(MSM8274) }, 246 { qcom_board_id(MSM8674) }, 247 { qcom_board_id_named(MSM8974PRO_AC, "MSM8974PRO-AC") }, 248 { qcom_board_id(MSM8126) }, 249 { qcom_board_id(APQ8026) }, 250 { qcom_board_id(MSM8926) }, 251 { qcom_board_id(MSM8326) }, 252 { qcom_board_id(MSM8916) }, 253 { qcom_board_id(MSM8994) }, 254 { qcom_board_id_named(APQ8074PRO_AA, "APQ8074PRO-AA") }, 255 { qcom_board_id_named(APQ8074PRO_AB, "APQ8074PRO-AB") }, 256 { qcom_board_id_named(APQ8074PRO_AC, "APQ8074PRO-AC") }, 257 { qcom_board_id_named(MSM8274PRO_AA, "MSM8274PRO-AA") }, 258 { qcom_board_id_named(MSM8274PRO_AB, "MSM8274PRO-AB") }, 259 { qcom_board_id_named(MSM8274PRO_AC, "MSM8274PRO-AC") }, 260 { qcom_board_id_named(MSM8674PRO_AA, "MSM8674PRO-AA") }, 261 { qcom_board_id_named(MSM8674PRO_AB, "MSM8674PRO-AB") }, 262 { qcom_board_id_named(MSM8674PRO_AC, "MSM8674PRO-AC") }, 263 { qcom_board_id_named(MSM8974PRO_AA, "MSM8974PRO-AA") }, 264 { qcom_board_id_named(MSM8974PRO_AB, "MSM8974PRO-AB") }, 265 { qcom_board_id(APQ8028) }, 266 { qcom_board_id(MSM8128) }, 267 { qcom_board_id(MSM8228) }, 268 { qcom_board_id(MSM8528) }, 269 { qcom_board_id(MSM8628) }, 270 { qcom_board_id(MSM8928) }, 271 { qcom_board_id(MSM8510) }, 272 { qcom_board_id(MSM8512) }, 273 { qcom_board_id(MSM8936) }, 274 { qcom_board_id(MSM8939) }, 275 { qcom_board_id(APQ8036) }, 276 { qcom_board_id(APQ8039) }, 277 { qcom_board_id(MSM8996) }, 278 { qcom_board_id(APQ8016) }, 279 { qcom_board_id(MSM8216) }, 280 { qcom_board_id(MSM8116) }, 281 { qcom_board_id(MSM8616) }, 282 { qcom_board_id(MSM8992) }, 283 { qcom_board_id(APQ8094) }, 284 { qcom_board_id(MDM9607) }, 285 { qcom_board_id(APQ8096) }, 286 { qcom_board_id(MSM8998) }, 287 { qcom_board_id(MSM8953) }, 288 { qcom_board_id(MDM8207) }, 289 { qcom_board_id(MDM9207) }, 290 { qcom_board_id(MDM9307) }, 291 { qcom_board_id(MDM9628) }, 292 { qcom_board_id(APQ8053) }, 293 { qcom_board_id(MSM8996SG) }, 294 { qcom_board_id(MSM8996AU) }, 295 { qcom_board_id(APQ8096AU) }, 296 { qcom_board_id(APQ8096SG) }, 297 { qcom_board_id(SDM660) }, 298 { qcom_board_id(SDM630) }, 299 { qcom_board_id(APQ8098) }, 300 { qcom_board_id(SDM845) }, 301 { qcom_board_id(MDM9206) }, 302 { qcom_board_id(IPQ8074) }, 303 { qcom_board_id(SDA660) }, 304 { qcom_board_id(SDM658) }, 305 { qcom_board_id(SDA658) }, 306 { qcom_board_id(SDA630) }, 307 { qcom_board_id(SDM450) }, 308 { qcom_board_id(SDA845) }, 309 { qcom_board_id(IPQ8072) }, 310 { qcom_board_id(IPQ8076) }, 311 { qcom_board_id(IPQ8078) }, 312 { qcom_board_id(SDM636) }, 313 { qcom_board_id(SDA636) }, 314 { qcom_board_id(SDM632) }, 315 { qcom_board_id(SDA632) }, 316 { qcom_board_id(SDA450) }, 317 { qcom_board_id(SM8250) }, 318 { qcom_board_id(IPQ8070) }, 319 { qcom_board_id(IPQ8071) }, 320 { qcom_board_id(IPQ8072A) }, 321 { qcom_board_id(IPQ8074A) }, 322 { qcom_board_id(IPQ8076A) }, 323 { qcom_board_id(IPQ8078A) }, 324 { qcom_board_id(SM6125) }, 325 { qcom_board_id(IPQ8070A) }, 326 { qcom_board_id(IPQ8071A) }, 327 { qcom_board_id(IPQ6018) }, 328 { qcom_board_id(IPQ6028) }, 329 { qcom_board_id(IPQ6000) }, 330 { qcom_board_id(IPQ6010) }, 331 { qcom_board_id(SC7180) }, 332 { qcom_board_id(SM6350) }, 333 { qcom_board_id(SM8350) }, 334 { qcom_board_id(SC8280XP) }, 335 { qcom_board_id(IPQ6005) }, 336 { qcom_board_id(QRB5165) }, 337 { qcom_board_id(SM8450) }, 338 { qcom_board_id(SM7225) }, 339 { qcom_board_id(SA8295P) }, 340 { qcom_board_id(SA8540P) }, 341 { qcom_board_id_named(SM8450_2, "SM8450") }, 342 { qcom_board_id_named(SM8450_3, "SM8450") }, 343 { qcom_board_id(SC7280) }, 344 { qcom_board_id(SC7180P) }, 345 { qcom_board_id(SM6375) }, 346 }; 347 348 static const char *socinfo_machine(struct device *dev, unsigned int id) 349 { 350 int idx; 351 352 for (idx = 0; idx < ARRAY_SIZE(soc_id); idx++) { 353 if (soc_id[idx].id == id) 354 return soc_id[idx].name; 355 } 356 357 return NULL; 358 } 359 360 #ifdef CONFIG_DEBUG_FS 361 362 #define QCOM_OPEN(name, _func) \ 363 static int qcom_open_##name(struct inode *inode, struct file *file) \ 364 { \ 365 return single_open(file, _func, inode->i_private); \ 366 } \ 367 \ 368 static const struct file_operations qcom_ ##name## _ops = { \ 369 .open = qcom_open_##name, \ 370 .read = seq_read, \ 371 .llseek = seq_lseek, \ 372 .release = single_release, \ 373 } 374 375 #define DEBUGFS_ADD(info, name) \ 376 debugfs_create_file(__stringify(name), 0444, \ 377 qcom_socinfo->dbg_root, \ 378 info, &qcom_ ##name## _ops) 379 380 381 static int qcom_show_build_id(struct seq_file *seq, void *p) 382 { 383 struct socinfo *socinfo = seq->private; 384 385 seq_printf(seq, "%s\n", socinfo->build_id); 386 387 return 0; 388 } 389 390 static int qcom_show_pmic_model(struct seq_file *seq, void *p) 391 { 392 struct socinfo *socinfo = seq->private; 393 int model = SOCINFO_MINOR(le32_to_cpu(socinfo->pmic_model)); 394 395 if (model < 0) 396 return -EINVAL; 397 398 if (model < ARRAY_SIZE(pmic_models) && pmic_models[model]) 399 seq_printf(seq, "%s\n", pmic_models[model]); 400 else 401 seq_printf(seq, "unknown (%d)\n", model); 402 403 return 0; 404 } 405 406 static int qcom_show_pmic_model_array(struct seq_file *seq, void *p) 407 { 408 struct socinfo *socinfo = seq->private; 409 unsigned int num_pmics = le32_to_cpu(socinfo->num_pmics); 410 unsigned int pmic_array_offset = le32_to_cpu(socinfo->pmic_array_offset); 411 int i; 412 void *ptr = socinfo; 413 414 ptr += pmic_array_offset; 415 416 /* No need for bounds checking, it happened at socinfo_debugfs_init */ 417 for (i = 0; i < num_pmics; i++) { 418 unsigned int model = SOCINFO_MINOR(get_unaligned_le32(ptr + 2 * i * sizeof(u32))); 419 unsigned int die_rev = get_unaligned_le32(ptr + (2 * i + 1) * sizeof(u32)); 420 421 if (model < ARRAY_SIZE(pmic_models) && pmic_models[model]) 422 seq_printf(seq, "%s %u.%u\n", pmic_models[model], 423 SOCINFO_MAJOR(die_rev), 424 SOCINFO_MINOR(die_rev)); 425 else 426 seq_printf(seq, "unknown (%d)\n", model); 427 } 428 429 return 0; 430 } 431 432 static int qcom_show_pmic_die_revision(struct seq_file *seq, void *p) 433 { 434 struct socinfo *socinfo = seq->private; 435 436 seq_printf(seq, "%u.%u\n", 437 SOCINFO_MAJOR(le32_to_cpu(socinfo->pmic_die_rev)), 438 SOCINFO_MINOR(le32_to_cpu(socinfo->pmic_die_rev))); 439 440 return 0; 441 } 442 443 static int qcom_show_chip_id(struct seq_file *seq, void *p) 444 { 445 struct socinfo *socinfo = seq->private; 446 447 seq_printf(seq, "%s\n", socinfo->chip_id); 448 449 return 0; 450 } 451 452 QCOM_OPEN(build_id, qcom_show_build_id); 453 QCOM_OPEN(pmic_model, qcom_show_pmic_model); 454 QCOM_OPEN(pmic_model_array, qcom_show_pmic_model_array); 455 QCOM_OPEN(pmic_die_rev, qcom_show_pmic_die_revision); 456 QCOM_OPEN(chip_id, qcom_show_chip_id); 457 458 #define DEFINE_IMAGE_OPS(type) \ 459 static int show_image_##type(struct seq_file *seq, void *p) \ 460 { \ 461 struct smem_image_version *image_version = seq->private; \ 462 if (image_version->type[0] != '\0') \ 463 seq_printf(seq, "%s\n", image_version->type); \ 464 return 0; \ 465 } \ 466 static int open_image_##type(struct inode *inode, struct file *file) \ 467 { \ 468 return single_open(file, show_image_##type, inode->i_private); \ 469 } \ 470 \ 471 static const struct file_operations qcom_image_##type##_ops = { \ 472 .open = open_image_##type, \ 473 .read = seq_read, \ 474 .llseek = seq_lseek, \ 475 .release = single_release, \ 476 } 477 478 DEFINE_IMAGE_OPS(name); 479 DEFINE_IMAGE_OPS(variant); 480 DEFINE_IMAGE_OPS(oem); 481 482 static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo, 483 struct socinfo *info, size_t info_size) 484 { 485 struct smem_image_version *versions; 486 struct dentry *dentry; 487 size_t size; 488 int i; 489 unsigned int num_pmics; 490 unsigned int pmic_array_offset; 491 492 qcom_socinfo->dbg_root = debugfs_create_dir("qcom_socinfo", NULL); 493 494 qcom_socinfo->info.fmt = __le32_to_cpu(info->fmt); 495 496 debugfs_create_x32("info_fmt", 0444, qcom_socinfo->dbg_root, 497 &qcom_socinfo->info.fmt); 498 499 switch (qcom_socinfo->info.fmt) { 500 case SOCINFO_VERSION(0, 15): 501 qcom_socinfo->info.nmodem_supported = __le32_to_cpu(info->nmodem_supported); 502 503 debugfs_create_u32("nmodem_supported", 0444, qcom_socinfo->dbg_root, 504 &qcom_socinfo->info.nmodem_supported); 505 fallthrough; 506 case SOCINFO_VERSION(0, 14): 507 qcom_socinfo->info.num_clusters = __le32_to_cpu(info->num_clusters); 508 qcom_socinfo->info.ncluster_array_offset = __le32_to_cpu(info->ncluster_array_offset); 509 qcom_socinfo->info.num_defective_parts = __le32_to_cpu(info->num_defective_parts); 510 qcom_socinfo->info.ndefective_parts_array_offset = __le32_to_cpu(info->ndefective_parts_array_offset); 511 512 debugfs_create_u32("num_clusters", 0444, qcom_socinfo->dbg_root, 513 &qcom_socinfo->info.num_clusters); 514 debugfs_create_u32("ncluster_array_offset", 0444, qcom_socinfo->dbg_root, 515 &qcom_socinfo->info.ncluster_array_offset); 516 debugfs_create_u32("num_defective_parts", 0444, qcom_socinfo->dbg_root, 517 &qcom_socinfo->info.num_defective_parts); 518 debugfs_create_u32("ndefective_parts_array_offset", 0444, qcom_socinfo->dbg_root, 519 &qcom_socinfo->info.ndefective_parts_array_offset); 520 fallthrough; 521 case SOCINFO_VERSION(0, 13): 522 qcom_socinfo->info.nproduct_id = __le32_to_cpu(info->nproduct_id); 523 524 debugfs_create_u32("nproduct_id", 0444, qcom_socinfo->dbg_root, 525 &qcom_socinfo->info.nproduct_id); 526 DEBUGFS_ADD(info, chip_id); 527 fallthrough; 528 case SOCINFO_VERSION(0, 12): 529 qcom_socinfo->info.chip_family = 530 __le32_to_cpu(info->chip_family); 531 qcom_socinfo->info.raw_device_family = 532 __le32_to_cpu(info->raw_device_family); 533 qcom_socinfo->info.raw_device_num = 534 __le32_to_cpu(info->raw_device_num); 535 536 debugfs_create_x32("chip_family", 0444, qcom_socinfo->dbg_root, 537 &qcom_socinfo->info.chip_family); 538 debugfs_create_x32("raw_device_family", 0444, 539 qcom_socinfo->dbg_root, 540 &qcom_socinfo->info.raw_device_family); 541 debugfs_create_x32("raw_device_number", 0444, 542 qcom_socinfo->dbg_root, 543 &qcom_socinfo->info.raw_device_num); 544 fallthrough; 545 case SOCINFO_VERSION(0, 11): 546 num_pmics = le32_to_cpu(info->num_pmics); 547 pmic_array_offset = le32_to_cpu(info->pmic_array_offset); 548 if (pmic_array_offset + 2 * num_pmics * sizeof(u32) <= info_size) 549 DEBUGFS_ADD(info, pmic_model_array); 550 fallthrough; 551 case SOCINFO_VERSION(0, 10): 552 case SOCINFO_VERSION(0, 9): 553 qcom_socinfo->info.foundry_id = __le32_to_cpu(info->foundry_id); 554 555 debugfs_create_u32("foundry_id", 0444, qcom_socinfo->dbg_root, 556 &qcom_socinfo->info.foundry_id); 557 fallthrough; 558 case SOCINFO_VERSION(0, 8): 559 case SOCINFO_VERSION(0, 7): 560 DEBUGFS_ADD(info, pmic_model); 561 DEBUGFS_ADD(info, pmic_die_rev); 562 fallthrough; 563 case SOCINFO_VERSION(0, 6): 564 qcom_socinfo->info.hw_plat_subtype = 565 __le32_to_cpu(info->hw_plat_subtype); 566 567 debugfs_create_u32("hardware_platform_subtype", 0444, 568 qcom_socinfo->dbg_root, 569 &qcom_socinfo->info.hw_plat_subtype); 570 fallthrough; 571 case SOCINFO_VERSION(0, 5): 572 qcom_socinfo->info.accessory_chip = 573 __le32_to_cpu(info->accessory_chip); 574 575 debugfs_create_u32("accessory_chip", 0444, 576 qcom_socinfo->dbg_root, 577 &qcom_socinfo->info.accessory_chip); 578 fallthrough; 579 case SOCINFO_VERSION(0, 4): 580 qcom_socinfo->info.plat_ver = __le32_to_cpu(info->plat_ver); 581 582 debugfs_create_u32("platform_version", 0444, 583 qcom_socinfo->dbg_root, 584 &qcom_socinfo->info.plat_ver); 585 fallthrough; 586 case SOCINFO_VERSION(0, 3): 587 qcom_socinfo->info.hw_plat = __le32_to_cpu(info->hw_plat); 588 589 debugfs_create_u32("hardware_platform", 0444, 590 qcom_socinfo->dbg_root, 591 &qcom_socinfo->info.hw_plat); 592 fallthrough; 593 case SOCINFO_VERSION(0, 2): 594 qcom_socinfo->info.raw_ver = __le32_to_cpu(info->raw_ver); 595 596 debugfs_create_u32("raw_version", 0444, qcom_socinfo->dbg_root, 597 &qcom_socinfo->info.raw_ver); 598 fallthrough; 599 case SOCINFO_VERSION(0, 1): 600 DEBUGFS_ADD(info, build_id); 601 break; 602 } 603 604 versions = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_IMAGE_VERSION_TABLE, 605 &size); 606 607 for (i = 0; i < ARRAY_SIZE(socinfo_image_names); i++) { 608 if (!socinfo_image_names[i]) 609 continue; 610 611 dentry = debugfs_create_dir(socinfo_image_names[i], 612 qcom_socinfo->dbg_root); 613 debugfs_create_file("name", 0444, dentry, &versions[i], 614 &qcom_image_name_ops); 615 debugfs_create_file("variant", 0444, dentry, &versions[i], 616 &qcom_image_variant_ops); 617 debugfs_create_file("oem", 0444, dentry, &versions[i], 618 &qcom_image_oem_ops); 619 } 620 } 621 622 static void socinfo_debugfs_exit(struct qcom_socinfo *qcom_socinfo) 623 { 624 debugfs_remove_recursive(qcom_socinfo->dbg_root); 625 } 626 #else 627 static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo, 628 struct socinfo *info, size_t info_size) 629 { 630 } 631 static void socinfo_debugfs_exit(struct qcom_socinfo *qcom_socinfo) { } 632 #endif /* CONFIG_DEBUG_FS */ 633 634 static int qcom_socinfo_probe(struct platform_device *pdev) 635 { 636 struct qcom_socinfo *qs; 637 struct socinfo *info; 638 size_t item_size; 639 640 info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_HW_SW_BUILD_ID, 641 &item_size); 642 if (IS_ERR(info)) { 643 dev_err(&pdev->dev, "Couldn't find socinfo\n"); 644 return PTR_ERR(info); 645 } 646 647 qs = devm_kzalloc(&pdev->dev, sizeof(*qs), GFP_KERNEL); 648 if (!qs) 649 return -ENOMEM; 650 651 qs->attr.family = "Snapdragon"; 652 qs->attr.machine = socinfo_machine(&pdev->dev, 653 le32_to_cpu(info->id)); 654 qs->attr.soc_id = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%u", 655 le32_to_cpu(info->id)); 656 qs->attr.revision = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%u.%u", 657 SOCINFO_MAJOR(le32_to_cpu(info->ver)), 658 SOCINFO_MINOR(le32_to_cpu(info->ver))); 659 if (offsetof(struct socinfo, serial_num) <= item_size) 660 qs->attr.serial_number = devm_kasprintf(&pdev->dev, GFP_KERNEL, 661 "%u", 662 le32_to_cpu(info->serial_num)); 663 664 qs->soc_dev = soc_device_register(&qs->attr); 665 if (IS_ERR(qs->soc_dev)) 666 return PTR_ERR(qs->soc_dev); 667 668 socinfo_debugfs_init(qs, info, item_size); 669 670 /* Feed the soc specific unique data into entropy pool */ 671 add_device_randomness(info, item_size); 672 673 platform_set_drvdata(pdev, qs); 674 675 return 0; 676 } 677 678 static int qcom_socinfo_remove(struct platform_device *pdev) 679 { 680 struct qcom_socinfo *qs = platform_get_drvdata(pdev); 681 682 soc_device_unregister(qs->soc_dev); 683 684 socinfo_debugfs_exit(qs); 685 686 return 0; 687 } 688 689 static struct platform_driver qcom_socinfo_driver = { 690 .probe = qcom_socinfo_probe, 691 .remove = qcom_socinfo_remove, 692 .driver = { 693 .name = "qcom-socinfo", 694 }, 695 }; 696 697 module_platform_driver(qcom_socinfo_driver); 698 699 MODULE_DESCRIPTION("Qualcomm SoCinfo driver"); 700 MODULE_LICENSE("GPL v2"); 701 MODULE_ALIAS("platform:qcom-socinfo"); 702