1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2009-2017, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2017-2019, Linaro Ltd. 5 */ 6 7 #include <linux/debugfs.h> 8 #include <linux/err.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <linux/random.h> 12 #include <linux/slab.h> 13 #include <linux/soc/qcom/smem.h> 14 #include <linux/soc/qcom/socinfo.h> 15 #include <linux/string.h> 16 #include <linux/stringify.h> 17 #include <linux/sys_soc.h> 18 #include <linux/types.h> 19 20 #include <asm/unaligned.h> 21 22 #include <dt-bindings/arm/qcom,ids.h> 23 24 /* 25 * SoC version type with major number in the upper 16 bits and minor 26 * number in the lower 16 bits. 27 */ 28 #define SOCINFO_MAJOR(ver) (((ver) >> 16) & 0xffff) 29 #define SOCINFO_MINOR(ver) ((ver) & 0xffff) 30 #define SOCINFO_VERSION(maj, min) ((((maj) & 0xffff) << 16)|((min) & 0xffff)) 31 32 /* Helper macros to create soc_id table */ 33 #define qcom_board_id(id) QCOM_ID_ ## id, __stringify(id) 34 #define qcom_board_id_named(id, name) QCOM_ID_ ## id, (name) 35 36 #ifdef CONFIG_DEBUG_FS 37 #define SMEM_IMAGE_VERSION_BLOCKS_COUNT 32 38 #define SMEM_IMAGE_VERSION_SIZE 4096 39 #define SMEM_IMAGE_VERSION_NAME_SIZE 75 40 #define SMEM_IMAGE_VERSION_VARIANT_SIZE 20 41 #define SMEM_IMAGE_VERSION_OEM_SIZE 32 42 43 /* 44 * SMEM Image table indices 45 */ 46 #define SMEM_IMAGE_TABLE_BOOT_INDEX 0 47 #define SMEM_IMAGE_TABLE_TZ_INDEX 1 48 #define SMEM_IMAGE_TABLE_RPM_INDEX 3 49 #define SMEM_IMAGE_TABLE_APPS_INDEX 10 50 #define SMEM_IMAGE_TABLE_MPSS_INDEX 11 51 #define SMEM_IMAGE_TABLE_ADSP_INDEX 12 52 #define SMEM_IMAGE_TABLE_CNSS_INDEX 13 53 #define SMEM_IMAGE_TABLE_VIDEO_INDEX 14 54 #define SMEM_IMAGE_TABLE_DSPS_INDEX 15 55 #define SMEM_IMAGE_TABLE_CDSP_INDEX 16 56 #define SMEM_IMAGE_TABLE_CDSP1_INDEX 19 57 #define SMEM_IMAGE_TABLE_GPDSP_INDEX 20 58 #define SMEM_IMAGE_TABLE_GPDSP1_INDEX 21 59 #define SMEM_IMAGE_VERSION_TABLE 469 60 61 /* 62 * SMEM Image table names 63 */ 64 static const char *const socinfo_image_names[] = { 65 [SMEM_IMAGE_TABLE_ADSP_INDEX] = "adsp", 66 [SMEM_IMAGE_TABLE_APPS_INDEX] = "apps", 67 [SMEM_IMAGE_TABLE_BOOT_INDEX] = "boot", 68 [SMEM_IMAGE_TABLE_CNSS_INDEX] = "cnss", 69 [SMEM_IMAGE_TABLE_MPSS_INDEX] = "mpss", 70 [SMEM_IMAGE_TABLE_RPM_INDEX] = "rpm", 71 [SMEM_IMAGE_TABLE_TZ_INDEX] = "tz", 72 [SMEM_IMAGE_TABLE_VIDEO_INDEX] = "video", 73 [SMEM_IMAGE_TABLE_DSPS_INDEX] = "dsps", 74 [SMEM_IMAGE_TABLE_CDSP_INDEX] = "cdsp", 75 [SMEM_IMAGE_TABLE_CDSP1_INDEX] = "cdsp1", 76 [SMEM_IMAGE_TABLE_GPDSP_INDEX] = "gpdsp", 77 [SMEM_IMAGE_TABLE_GPDSP1_INDEX] = "gpdsp1", 78 }; 79 80 static const char *const pmic_models[] = { 81 [0] = "Unknown PMIC model", 82 [1] = "PM8941", 83 [2] = "PM8841", 84 [3] = "PM8019", 85 [4] = "PM8226", 86 [5] = "PM8110", 87 [6] = "PMA8084", 88 [7] = "PMI8962", 89 [8] = "PMD9635", 90 [9] = "PM8994", 91 [10] = "PMI8994", 92 [11] = "PM8916", 93 [12] = "PM8004", 94 [13] = "PM8909/PM8058", 95 [14] = "PM8028", 96 [15] = "PM8901", 97 [16] = "PM8950/PM8027", 98 [17] = "PMI8950/ISL9519", 99 [18] = "PMK8001/PM8921", 100 [19] = "PMI8996/PM8018", 101 [20] = "PM8998/PM8015", 102 [21] = "PMI8998/PM8014", 103 [22] = "PM8821", 104 [23] = "PM8038", 105 [24] = "PM8005/PM8922", 106 [25] = "PM8917/PM8937", 107 [26] = "PM660L", 108 [27] = "PM660", 109 [30] = "PM8150", 110 [31] = "PM8150L", 111 [32] = "PM8150B", 112 [33] = "PMK8002", 113 [36] = "PM8009", 114 [37] = "PMI632", 115 [38] = "PM8150C", 116 [40] = "PM6150", 117 [41] = "SMB2351", 118 [44] = "PM8008", 119 [45] = "PM6125", 120 [46] = "PM7250B", 121 [47] = "PMK8350", 122 [48] = "PM8350", 123 [49] = "PM8350C", 124 [50] = "PM8350B", 125 [51] = "PMR735A", 126 [52] = "PMR735B", 127 [55] = "PM2250", 128 [58] = "PM8450", 129 [65] = "PM8010", 130 [69] = "PM8550VS", 131 [70] = "PM8550VE", 132 [71] = "PM8550B", 133 [72] = "PMR735D", 134 [73] = "PM8550", 135 [74] = "PMK8550", 136 }; 137 138 struct socinfo_params { 139 u32 raw_device_family; 140 u32 hw_plat_subtype; 141 u32 accessory_chip; 142 u32 raw_device_num; 143 u32 chip_family; 144 u32 foundry_id; 145 u32 plat_ver; 146 u32 raw_ver; 147 u32 hw_plat; 148 u32 fmt; 149 u32 nproduct_id; 150 u32 num_clusters; 151 u32 ncluster_array_offset; 152 u32 num_subset_parts; 153 u32 nsubset_parts_array_offset; 154 u32 nmodem_supported; 155 u32 feature_code; 156 u32 pcode; 157 u32 oem_variant; 158 u32 num_func_clusters; 159 u32 boot_cluster; 160 u32 boot_core; 161 }; 162 163 struct smem_image_version { 164 char name[SMEM_IMAGE_VERSION_NAME_SIZE]; 165 char variant[SMEM_IMAGE_VERSION_VARIANT_SIZE]; 166 char pad; 167 char oem[SMEM_IMAGE_VERSION_OEM_SIZE]; 168 }; 169 #endif /* CONFIG_DEBUG_FS */ 170 171 struct qcom_socinfo { 172 struct soc_device *soc_dev; 173 struct soc_device_attribute attr; 174 #ifdef CONFIG_DEBUG_FS 175 struct dentry *dbg_root; 176 struct socinfo_params info; 177 #endif /* CONFIG_DEBUG_FS */ 178 }; 179 180 struct soc_id { 181 unsigned int id; 182 const char *name; 183 }; 184 185 static const struct soc_id soc_id[] = { 186 { qcom_board_id(MSM8260) }, 187 { qcom_board_id(MSM8660) }, 188 { qcom_board_id(APQ8060) }, 189 { qcom_board_id(MSM8960) }, 190 { qcom_board_id(APQ8064) }, 191 { qcom_board_id(MSM8930) }, 192 { qcom_board_id(MSM8630) }, 193 { qcom_board_id(MSM8230) }, 194 { qcom_board_id(APQ8030) }, 195 { qcom_board_id(MSM8627) }, 196 { qcom_board_id(MSM8227) }, 197 { qcom_board_id(MSM8660A) }, 198 { qcom_board_id(MSM8260A) }, 199 { qcom_board_id(APQ8060A) }, 200 { qcom_board_id(MSM8974) }, 201 { qcom_board_id(MSM8225) }, 202 { qcom_board_id(MSM8625) }, 203 { qcom_board_id(MPQ8064) }, 204 { qcom_board_id(MSM8960AB) }, 205 { qcom_board_id(APQ8060AB) }, 206 { qcom_board_id(MSM8260AB) }, 207 { qcom_board_id(MSM8660AB) }, 208 { qcom_board_id(MSM8930AA) }, 209 { qcom_board_id(MSM8630AA) }, 210 { qcom_board_id(MSM8230AA) }, 211 { qcom_board_id(MSM8626) }, 212 { qcom_board_id(MSM8610) }, 213 { qcom_board_id(APQ8064AB) }, 214 { qcom_board_id(MSM8930AB) }, 215 { qcom_board_id(MSM8630AB) }, 216 { qcom_board_id(MSM8230AB) }, 217 { qcom_board_id(APQ8030AB) }, 218 { qcom_board_id(MSM8226) }, 219 { qcom_board_id(MSM8526) }, 220 { qcom_board_id(APQ8030AA) }, 221 { qcom_board_id(MSM8110) }, 222 { qcom_board_id(MSM8210) }, 223 { qcom_board_id(MSM8810) }, 224 { qcom_board_id(MSM8212) }, 225 { qcom_board_id(MSM8612) }, 226 { qcom_board_id(MSM8112) }, 227 { qcom_board_id(MSM8125) }, 228 { qcom_board_id(MSM8225Q) }, 229 { qcom_board_id(MSM8625Q) }, 230 { qcom_board_id(MSM8125Q) }, 231 { qcom_board_id(APQ8064AA) }, 232 { qcom_board_id(APQ8084) }, 233 { qcom_board_id(MSM8130) }, 234 { qcom_board_id(MSM8130AA) }, 235 { qcom_board_id(MSM8130AB) }, 236 { qcom_board_id(MSM8627AA) }, 237 { qcom_board_id(MSM8227AA) }, 238 { qcom_board_id(APQ8074) }, 239 { qcom_board_id(MSM8274) }, 240 { qcom_board_id(MSM8674) }, 241 { qcom_board_id(MDM9635) }, 242 { qcom_board_id_named(MSM8974PRO_AC, "MSM8974PRO-AC") }, 243 { qcom_board_id(MSM8126) }, 244 { qcom_board_id(APQ8026) }, 245 { qcom_board_id(MSM8926) }, 246 { qcom_board_id(IPQ8062) }, 247 { qcom_board_id(IPQ8064) }, 248 { qcom_board_id(IPQ8066) }, 249 { qcom_board_id(IPQ8068) }, 250 { qcom_board_id(MSM8326) }, 251 { qcom_board_id(MSM8916) }, 252 { qcom_board_id(MSM8994) }, 253 { qcom_board_id_named(APQ8074PRO_AA, "APQ8074PRO-AA") }, 254 { qcom_board_id_named(APQ8074PRO_AB, "APQ8074PRO-AB") }, 255 { qcom_board_id_named(APQ8074PRO_AC, "APQ8074PRO-AC") }, 256 { qcom_board_id_named(MSM8274PRO_AA, "MSM8274PRO-AA") }, 257 { qcom_board_id_named(MSM8274PRO_AB, "MSM8274PRO-AB") }, 258 { qcom_board_id_named(MSM8274PRO_AC, "MSM8274PRO-AC") }, 259 { qcom_board_id_named(MSM8674PRO_AA, "MSM8674PRO-AA") }, 260 { qcom_board_id_named(MSM8674PRO_AB, "MSM8674PRO-AB") }, 261 { qcom_board_id_named(MSM8674PRO_AC, "MSM8674PRO-AC") }, 262 { qcom_board_id_named(MSM8974PRO_AA, "MSM8974PRO-AA") }, 263 { qcom_board_id_named(MSM8974PRO_AB, "MSM8974PRO-AB") }, 264 { qcom_board_id(APQ8028) }, 265 { qcom_board_id(MSM8128) }, 266 { qcom_board_id(MSM8228) }, 267 { qcom_board_id(MSM8528) }, 268 { qcom_board_id(MSM8628) }, 269 { qcom_board_id(MSM8928) }, 270 { qcom_board_id(MSM8510) }, 271 { qcom_board_id(MSM8512) }, 272 { qcom_board_id(MSM8936) }, 273 { qcom_board_id(MDM9640) }, 274 { qcom_board_id(MSM8939) }, 275 { qcom_board_id(APQ8036) }, 276 { qcom_board_id(APQ8039) }, 277 { qcom_board_id(MSM8236) }, 278 { qcom_board_id(MSM8636) }, 279 { qcom_board_id(MSM8909) }, 280 { qcom_board_id(MSM8996) }, 281 { qcom_board_id(APQ8016) }, 282 { qcom_board_id(MSM8216) }, 283 { qcom_board_id(MSM8116) }, 284 { qcom_board_id(MSM8616) }, 285 { qcom_board_id(MSM8992) }, 286 { qcom_board_id(APQ8092) }, 287 { qcom_board_id(APQ8094) }, 288 { qcom_board_id(MSM8209) }, 289 { qcom_board_id(MSM8208) }, 290 { qcom_board_id(MDM9209) }, 291 { qcom_board_id(MDM9309) }, 292 { qcom_board_id(MDM9609) }, 293 { qcom_board_id(MSM8239) }, 294 { qcom_board_id(MSM8952) }, 295 { qcom_board_id(APQ8009) }, 296 { qcom_board_id(MSM8956) }, 297 { qcom_board_id(MSM8929) }, 298 { qcom_board_id(MSM8629) }, 299 { qcom_board_id(MSM8229) }, 300 { qcom_board_id(APQ8029) }, 301 { qcom_board_id(APQ8056) }, 302 { qcom_board_id(MSM8609) }, 303 { qcom_board_id(APQ8076) }, 304 { qcom_board_id(MSM8976) }, 305 { qcom_board_id(IPQ8065) }, 306 { qcom_board_id(IPQ8069) }, 307 { qcom_board_id(MDM9650) }, 308 { qcom_board_id(MDM9655) }, 309 { qcom_board_id(MDM9250) }, 310 { qcom_board_id(MDM9255) }, 311 { qcom_board_id(MDM9350) }, 312 { qcom_board_id(APQ8052) }, 313 { qcom_board_id(MDM9607) }, 314 { qcom_board_id(APQ8096) }, 315 { qcom_board_id(MSM8998) }, 316 { qcom_board_id(MSM8953) }, 317 { qcom_board_id(MSM8937) }, 318 { qcom_board_id(APQ8037) }, 319 { qcom_board_id(MDM8207) }, 320 { qcom_board_id(MDM9207) }, 321 { qcom_board_id(MDM9307) }, 322 { qcom_board_id(MDM9628) }, 323 { qcom_board_id(MSM8909W) }, 324 { qcom_board_id(APQ8009W) }, 325 { qcom_board_id(MSM8996L) }, 326 { qcom_board_id(MSM8917) }, 327 { qcom_board_id(APQ8053) }, 328 { qcom_board_id(MSM8996SG) }, 329 { qcom_board_id(APQ8017) }, 330 { qcom_board_id(MSM8217) }, 331 { qcom_board_id(MSM8617) }, 332 { qcom_board_id(MSM8996AU) }, 333 { qcom_board_id(APQ8096AU) }, 334 { qcom_board_id(APQ8096SG) }, 335 { qcom_board_id(MSM8940) }, 336 { qcom_board_id(SDX201) }, 337 { qcom_board_id(SDM660) }, 338 { qcom_board_id(SDM630) }, 339 { qcom_board_id(APQ8098) }, 340 { qcom_board_id(MSM8920) }, 341 { qcom_board_id(SDM845) }, 342 { qcom_board_id(MDM9206) }, 343 { qcom_board_id(IPQ8074) }, 344 { qcom_board_id(SDA660) }, 345 { qcom_board_id(SDM658) }, 346 { qcom_board_id(SDA658) }, 347 { qcom_board_id(SDA630) }, 348 { qcom_board_id(MSM8905) }, 349 { qcom_board_id(SDX202) }, 350 { qcom_board_id(SDM450) }, 351 { qcom_board_id(SM8150) }, 352 { qcom_board_id(SDA845) }, 353 { qcom_board_id(IPQ8072) }, 354 { qcom_board_id(IPQ8076) }, 355 { qcom_board_id(IPQ8078) }, 356 { qcom_board_id(SDM636) }, 357 { qcom_board_id(SDA636) }, 358 { qcom_board_id(SDM632) }, 359 { qcom_board_id(SDA632) }, 360 { qcom_board_id(SDA450) }, 361 { qcom_board_id(SDM439) }, 362 { qcom_board_id(SDM429) }, 363 { qcom_board_id(SM8250) }, 364 { qcom_board_id(SA8155) }, 365 { qcom_board_id(SDA439) }, 366 { qcom_board_id(SDA429) }, 367 { qcom_board_id(SM7150) }, 368 { qcom_board_id(SM7150P) }, 369 { qcom_board_id(IPQ8070) }, 370 { qcom_board_id(IPQ8071) }, 371 { qcom_board_id(QM215) }, 372 { qcom_board_id(IPQ8072A) }, 373 { qcom_board_id(IPQ8074A) }, 374 { qcom_board_id(IPQ8076A) }, 375 { qcom_board_id(IPQ8078A) }, 376 { qcom_board_id(SM6125) }, 377 { qcom_board_id(IPQ8070A) }, 378 { qcom_board_id(IPQ8071A) }, 379 { qcom_board_id(IPQ8172) }, 380 { qcom_board_id(IPQ8173) }, 381 { qcom_board_id(IPQ8174) }, 382 { qcom_board_id(IPQ6018) }, 383 { qcom_board_id(IPQ6028) }, 384 { qcom_board_id(SDM429W) }, 385 { qcom_board_id(SM4250) }, 386 { qcom_board_id(IPQ6000) }, 387 { qcom_board_id(IPQ6010) }, 388 { qcom_board_id(SC7180) }, 389 { qcom_board_id(SM6350) }, 390 { qcom_board_id(QCM2150) }, 391 { qcom_board_id(SDA429W) }, 392 { qcom_board_id(SM8350) }, 393 { qcom_board_id(QCM2290) }, 394 { qcom_board_id(SM7125) }, 395 { qcom_board_id(SM6115) }, 396 { qcom_board_id(IPQ5010) }, 397 { qcom_board_id(IPQ5018) }, 398 { qcom_board_id(IPQ5028) }, 399 { qcom_board_id(SC8280XP) }, 400 { qcom_board_id(IPQ6005) }, 401 { qcom_board_id(QRB5165) }, 402 { qcom_board_id(SM8450) }, 403 { qcom_board_id(SM7225) }, 404 { qcom_board_id(SA8295P) }, 405 { qcom_board_id(SA8540P) }, 406 { qcom_board_id(QCM4290) }, 407 { qcom_board_id(QCS4290) }, 408 { qcom_board_id_named(SM8450_2, "SM8450") }, 409 { qcom_board_id_named(SM8450_3, "SM8450") }, 410 { qcom_board_id(SC7280) }, 411 { qcom_board_id(SC7180P) }, 412 { qcom_board_id(QCM6490) }, 413 { qcom_board_id(IPQ5000) }, 414 { qcom_board_id(IPQ0509) }, 415 { qcom_board_id(IPQ0518) }, 416 { qcom_board_id(SM6375) }, 417 { qcom_board_id(IPQ9514) }, 418 { qcom_board_id(IPQ9550) }, 419 { qcom_board_id(IPQ9554) }, 420 { qcom_board_id(IPQ9570) }, 421 { qcom_board_id(IPQ9574) }, 422 { qcom_board_id(SM8550) }, 423 { qcom_board_id(IPQ5016) }, 424 { qcom_board_id(IPQ9510) }, 425 { qcom_board_id(QRB4210) }, 426 { qcom_board_id(QRB2210) }, 427 { qcom_board_id(SA8775P) }, 428 { qcom_board_id(QRU1000) }, 429 { qcom_board_id(QDU1000) }, 430 { qcom_board_id(SM8650) }, 431 { qcom_board_id(SM4450) }, 432 { qcom_board_id(QDU1010) }, 433 { qcom_board_id(QRU1032) }, 434 { qcom_board_id(QRU1052) }, 435 { qcom_board_id(QRU1062) }, 436 { qcom_board_id(IPQ5332) }, 437 { qcom_board_id(IPQ5322) }, 438 { qcom_board_id(IPQ5312) }, 439 { qcom_board_id(IPQ5302) }, 440 { qcom_board_id(IPQ5300) }, 441 }; 442 443 static const char *socinfo_machine(struct device *dev, unsigned int id) 444 { 445 int idx; 446 447 for (idx = 0; idx < ARRAY_SIZE(soc_id); idx++) { 448 if (soc_id[idx].id == id) 449 return soc_id[idx].name; 450 } 451 452 return NULL; 453 } 454 455 #ifdef CONFIG_DEBUG_FS 456 457 #define QCOM_OPEN(name, _func) \ 458 static int qcom_open_##name(struct inode *inode, struct file *file) \ 459 { \ 460 return single_open(file, _func, inode->i_private); \ 461 } \ 462 \ 463 static const struct file_operations qcom_ ##name## _ops = { \ 464 .open = qcom_open_##name, \ 465 .read = seq_read, \ 466 .llseek = seq_lseek, \ 467 .release = single_release, \ 468 } 469 470 #define DEBUGFS_ADD(info, name) \ 471 debugfs_create_file(__stringify(name), 0444, \ 472 qcom_socinfo->dbg_root, \ 473 info, &qcom_ ##name## _ops) 474 475 476 static int qcom_show_build_id(struct seq_file *seq, void *p) 477 { 478 struct socinfo *socinfo = seq->private; 479 480 seq_printf(seq, "%s\n", socinfo->build_id); 481 482 return 0; 483 } 484 485 static int qcom_show_pmic_model(struct seq_file *seq, void *p) 486 { 487 struct socinfo *socinfo = seq->private; 488 int model = SOCINFO_MINOR(le32_to_cpu(socinfo->pmic_model)); 489 490 if (model < 0) 491 return -EINVAL; 492 493 if (model < ARRAY_SIZE(pmic_models) && pmic_models[model]) 494 seq_printf(seq, "%s\n", pmic_models[model]); 495 else 496 seq_printf(seq, "unknown (%d)\n", model); 497 498 return 0; 499 } 500 501 static int qcom_show_pmic_model_array(struct seq_file *seq, void *p) 502 { 503 struct socinfo *socinfo = seq->private; 504 unsigned int num_pmics = le32_to_cpu(socinfo->num_pmics); 505 unsigned int pmic_array_offset = le32_to_cpu(socinfo->pmic_array_offset); 506 int i; 507 void *ptr = socinfo; 508 509 ptr += pmic_array_offset; 510 511 /* No need for bounds checking, it happened at socinfo_debugfs_init */ 512 for (i = 0; i < num_pmics; i++) { 513 unsigned int model = SOCINFO_MINOR(get_unaligned_le32(ptr + 2 * i * sizeof(u32))); 514 unsigned int die_rev = get_unaligned_le32(ptr + (2 * i + 1) * sizeof(u32)); 515 516 if (model < ARRAY_SIZE(pmic_models) && pmic_models[model]) 517 seq_printf(seq, "%s %u.%u\n", pmic_models[model], 518 SOCINFO_MAJOR(die_rev), 519 SOCINFO_MINOR(die_rev)); 520 else 521 seq_printf(seq, "unknown (%d)\n", model); 522 } 523 524 return 0; 525 } 526 527 static int qcom_show_pmic_die_revision(struct seq_file *seq, void *p) 528 { 529 struct socinfo *socinfo = seq->private; 530 531 seq_printf(seq, "%u.%u\n", 532 SOCINFO_MAJOR(le32_to_cpu(socinfo->pmic_die_rev)), 533 SOCINFO_MINOR(le32_to_cpu(socinfo->pmic_die_rev))); 534 535 return 0; 536 } 537 538 static int qcom_show_chip_id(struct seq_file *seq, void *p) 539 { 540 struct socinfo *socinfo = seq->private; 541 542 seq_printf(seq, "%s\n", socinfo->chip_id); 543 544 return 0; 545 } 546 547 QCOM_OPEN(build_id, qcom_show_build_id); 548 QCOM_OPEN(pmic_model, qcom_show_pmic_model); 549 QCOM_OPEN(pmic_model_array, qcom_show_pmic_model_array); 550 QCOM_OPEN(pmic_die_rev, qcom_show_pmic_die_revision); 551 QCOM_OPEN(chip_id, qcom_show_chip_id); 552 553 #define DEFINE_IMAGE_OPS(type) \ 554 static int show_image_##type(struct seq_file *seq, void *p) \ 555 { \ 556 struct smem_image_version *image_version = seq->private; \ 557 if (image_version->type[0] != '\0') \ 558 seq_printf(seq, "%s\n", image_version->type); \ 559 return 0; \ 560 } \ 561 static int open_image_##type(struct inode *inode, struct file *file) \ 562 { \ 563 return single_open(file, show_image_##type, inode->i_private); \ 564 } \ 565 \ 566 static const struct file_operations qcom_image_##type##_ops = { \ 567 .open = open_image_##type, \ 568 .read = seq_read, \ 569 .llseek = seq_lseek, \ 570 .release = single_release, \ 571 } 572 573 DEFINE_IMAGE_OPS(name); 574 DEFINE_IMAGE_OPS(variant); 575 DEFINE_IMAGE_OPS(oem); 576 577 static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo, 578 struct socinfo *info, size_t info_size) 579 { 580 struct smem_image_version *versions; 581 struct dentry *dentry; 582 size_t size; 583 int i; 584 unsigned int num_pmics; 585 unsigned int pmic_array_offset; 586 587 qcom_socinfo->dbg_root = debugfs_create_dir("qcom_socinfo", NULL); 588 589 qcom_socinfo->info.fmt = __le32_to_cpu(info->fmt); 590 591 debugfs_create_x32("info_fmt", 0444, qcom_socinfo->dbg_root, 592 &qcom_socinfo->info.fmt); 593 594 switch (qcom_socinfo->info.fmt) { 595 case SOCINFO_VERSION(0, 19): 596 qcom_socinfo->info.num_func_clusters = __le32_to_cpu(info->num_func_clusters); 597 qcom_socinfo->info.boot_cluster = __le32_to_cpu(info->boot_cluster); 598 qcom_socinfo->info.boot_core = __le32_to_cpu(info->boot_core); 599 600 debugfs_create_u32("num_func_clusters", 0444, qcom_socinfo->dbg_root, 601 &qcom_socinfo->info.num_func_clusters); 602 debugfs_create_u32("boot_cluster", 0444, qcom_socinfo->dbg_root, 603 &qcom_socinfo->info.boot_cluster); 604 debugfs_create_u32("boot_core", 0444, qcom_socinfo->dbg_root, 605 &qcom_socinfo->info.boot_core); 606 fallthrough; 607 case SOCINFO_VERSION(0, 18): 608 case SOCINFO_VERSION(0, 17): 609 qcom_socinfo->info.oem_variant = __le32_to_cpu(info->oem_variant); 610 debugfs_create_u32("oem_variant", 0444, qcom_socinfo->dbg_root, 611 &qcom_socinfo->info.oem_variant); 612 fallthrough; 613 case SOCINFO_VERSION(0, 16): 614 qcom_socinfo->info.feature_code = __le32_to_cpu(info->feature_code); 615 qcom_socinfo->info.pcode = __le32_to_cpu(info->pcode); 616 617 debugfs_create_u32("feature_code", 0444, qcom_socinfo->dbg_root, 618 &qcom_socinfo->info.feature_code); 619 debugfs_create_u32("pcode", 0444, qcom_socinfo->dbg_root, 620 &qcom_socinfo->info.pcode); 621 fallthrough; 622 case SOCINFO_VERSION(0, 15): 623 qcom_socinfo->info.nmodem_supported = __le32_to_cpu(info->nmodem_supported); 624 625 debugfs_create_u32("nmodem_supported", 0444, qcom_socinfo->dbg_root, 626 &qcom_socinfo->info.nmodem_supported); 627 fallthrough; 628 case SOCINFO_VERSION(0, 14): 629 qcom_socinfo->info.num_clusters = __le32_to_cpu(info->num_clusters); 630 qcom_socinfo->info.ncluster_array_offset = __le32_to_cpu(info->ncluster_array_offset); 631 qcom_socinfo->info.num_subset_parts = __le32_to_cpu(info->num_subset_parts); 632 qcom_socinfo->info.nsubset_parts_array_offset = 633 __le32_to_cpu(info->nsubset_parts_array_offset); 634 635 debugfs_create_u32("num_clusters", 0444, qcom_socinfo->dbg_root, 636 &qcom_socinfo->info.num_clusters); 637 debugfs_create_u32("ncluster_array_offset", 0444, qcom_socinfo->dbg_root, 638 &qcom_socinfo->info.ncluster_array_offset); 639 debugfs_create_u32("num_subset_parts", 0444, qcom_socinfo->dbg_root, 640 &qcom_socinfo->info.num_subset_parts); 641 debugfs_create_u32("nsubset_parts_array_offset", 0444, qcom_socinfo->dbg_root, 642 &qcom_socinfo->info.nsubset_parts_array_offset); 643 fallthrough; 644 case SOCINFO_VERSION(0, 13): 645 qcom_socinfo->info.nproduct_id = __le32_to_cpu(info->nproduct_id); 646 647 debugfs_create_u32("nproduct_id", 0444, qcom_socinfo->dbg_root, 648 &qcom_socinfo->info.nproduct_id); 649 DEBUGFS_ADD(info, chip_id); 650 fallthrough; 651 case SOCINFO_VERSION(0, 12): 652 qcom_socinfo->info.chip_family = 653 __le32_to_cpu(info->chip_family); 654 qcom_socinfo->info.raw_device_family = 655 __le32_to_cpu(info->raw_device_family); 656 qcom_socinfo->info.raw_device_num = 657 __le32_to_cpu(info->raw_device_num); 658 659 debugfs_create_x32("chip_family", 0444, qcom_socinfo->dbg_root, 660 &qcom_socinfo->info.chip_family); 661 debugfs_create_x32("raw_device_family", 0444, 662 qcom_socinfo->dbg_root, 663 &qcom_socinfo->info.raw_device_family); 664 debugfs_create_x32("raw_device_number", 0444, 665 qcom_socinfo->dbg_root, 666 &qcom_socinfo->info.raw_device_num); 667 fallthrough; 668 case SOCINFO_VERSION(0, 11): 669 num_pmics = le32_to_cpu(info->num_pmics); 670 pmic_array_offset = le32_to_cpu(info->pmic_array_offset); 671 if (pmic_array_offset + 2 * num_pmics * sizeof(u32) <= info_size) 672 DEBUGFS_ADD(info, pmic_model_array); 673 fallthrough; 674 case SOCINFO_VERSION(0, 10): 675 case SOCINFO_VERSION(0, 9): 676 qcom_socinfo->info.foundry_id = __le32_to_cpu(info->foundry_id); 677 678 debugfs_create_u32("foundry_id", 0444, qcom_socinfo->dbg_root, 679 &qcom_socinfo->info.foundry_id); 680 fallthrough; 681 case SOCINFO_VERSION(0, 8): 682 case SOCINFO_VERSION(0, 7): 683 DEBUGFS_ADD(info, pmic_model); 684 DEBUGFS_ADD(info, pmic_die_rev); 685 fallthrough; 686 case SOCINFO_VERSION(0, 6): 687 qcom_socinfo->info.hw_plat_subtype = 688 __le32_to_cpu(info->hw_plat_subtype); 689 690 debugfs_create_u32("hardware_platform_subtype", 0444, 691 qcom_socinfo->dbg_root, 692 &qcom_socinfo->info.hw_plat_subtype); 693 fallthrough; 694 case SOCINFO_VERSION(0, 5): 695 qcom_socinfo->info.accessory_chip = 696 __le32_to_cpu(info->accessory_chip); 697 698 debugfs_create_u32("accessory_chip", 0444, 699 qcom_socinfo->dbg_root, 700 &qcom_socinfo->info.accessory_chip); 701 fallthrough; 702 case SOCINFO_VERSION(0, 4): 703 qcom_socinfo->info.plat_ver = __le32_to_cpu(info->plat_ver); 704 705 debugfs_create_u32("platform_version", 0444, 706 qcom_socinfo->dbg_root, 707 &qcom_socinfo->info.plat_ver); 708 fallthrough; 709 case SOCINFO_VERSION(0, 3): 710 qcom_socinfo->info.hw_plat = __le32_to_cpu(info->hw_plat); 711 712 debugfs_create_u32("hardware_platform", 0444, 713 qcom_socinfo->dbg_root, 714 &qcom_socinfo->info.hw_plat); 715 fallthrough; 716 case SOCINFO_VERSION(0, 2): 717 qcom_socinfo->info.raw_ver = __le32_to_cpu(info->raw_ver); 718 719 debugfs_create_u32("raw_version", 0444, qcom_socinfo->dbg_root, 720 &qcom_socinfo->info.raw_ver); 721 fallthrough; 722 case SOCINFO_VERSION(0, 1): 723 DEBUGFS_ADD(info, build_id); 724 break; 725 } 726 727 versions = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_IMAGE_VERSION_TABLE, 728 &size); 729 730 for (i = 0; i < ARRAY_SIZE(socinfo_image_names); i++) { 731 if (!socinfo_image_names[i]) 732 continue; 733 734 dentry = debugfs_create_dir(socinfo_image_names[i], 735 qcom_socinfo->dbg_root); 736 debugfs_create_file("name", 0444, dentry, &versions[i], 737 &qcom_image_name_ops); 738 debugfs_create_file("variant", 0444, dentry, &versions[i], 739 &qcom_image_variant_ops); 740 debugfs_create_file("oem", 0444, dentry, &versions[i], 741 &qcom_image_oem_ops); 742 } 743 } 744 745 static void socinfo_debugfs_exit(struct qcom_socinfo *qcom_socinfo) 746 { 747 debugfs_remove_recursive(qcom_socinfo->dbg_root); 748 } 749 #else 750 static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo, 751 struct socinfo *info, size_t info_size) 752 { 753 } 754 static void socinfo_debugfs_exit(struct qcom_socinfo *qcom_socinfo) { } 755 #endif /* CONFIG_DEBUG_FS */ 756 757 static int qcom_socinfo_probe(struct platform_device *pdev) 758 { 759 struct qcom_socinfo *qs; 760 struct socinfo *info; 761 size_t item_size; 762 763 info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_HW_SW_BUILD_ID, 764 &item_size); 765 if (IS_ERR(info)) { 766 dev_err(&pdev->dev, "Couldn't find socinfo\n"); 767 return PTR_ERR(info); 768 } 769 770 qs = devm_kzalloc(&pdev->dev, sizeof(*qs), GFP_KERNEL); 771 if (!qs) 772 return -ENOMEM; 773 774 qs->attr.family = "Snapdragon"; 775 qs->attr.machine = socinfo_machine(&pdev->dev, 776 le32_to_cpu(info->id)); 777 qs->attr.soc_id = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%u", 778 le32_to_cpu(info->id)); 779 qs->attr.revision = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%u.%u", 780 SOCINFO_MAJOR(le32_to_cpu(info->ver)), 781 SOCINFO_MINOR(le32_to_cpu(info->ver))); 782 if (offsetof(struct socinfo, serial_num) <= item_size) 783 qs->attr.serial_number = devm_kasprintf(&pdev->dev, GFP_KERNEL, 784 "%u", 785 le32_to_cpu(info->serial_num)); 786 787 qs->soc_dev = soc_device_register(&qs->attr); 788 if (IS_ERR(qs->soc_dev)) 789 return PTR_ERR(qs->soc_dev); 790 791 socinfo_debugfs_init(qs, info, item_size); 792 793 /* Feed the soc specific unique data into entropy pool */ 794 add_device_randomness(info, item_size); 795 796 platform_set_drvdata(pdev, qs); 797 798 return 0; 799 } 800 801 static void qcom_socinfo_remove(struct platform_device *pdev) 802 { 803 struct qcom_socinfo *qs = platform_get_drvdata(pdev); 804 805 soc_device_unregister(qs->soc_dev); 806 807 socinfo_debugfs_exit(qs); 808 } 809 810 static struct platform_driver qcom_socinfo_driver = { 811 .probe = qcom_socinfo_probe, 812 .remove_new = qcom_socinfo_remove, 813 .driver = { 814 .name = "qcom-socinfo", 815 }, 816 }; 817 818 module_platform_driver(qcom_socinfo_driver); 819 820 MODULE_DESCRIPTION("Qualcomm SoCinfo driver"); 821 MODULE_LICENSE("GPL v2"); 822 MODULE_ALIAS("platform:qcom-socinfo"); 823