1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */ 8 #define __DISABLE_TRACE_MMIO__ 9 10 #include <linux/acpi.h> 11 #include <linux/bitfield.h> 12 #include <linux/clk.h> 13 #include <linux/firmware.h> 14 #include <linux/slab.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/io.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_platform.h> 20 #include <linux/pinctrl/consumer.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm_domain.h> 23 #include <linux/pm_opp.h> 24 #include <linux/soc/qcom/geni-se.h> 25 26 /** 27 * DOC: Overview 28 * 29 * Generic Interface (GENI) Serial Engine (SE) Wrapper driver is introduced 30 * to manage GENI firmware based Qualcomm Universal Peripheral (QUP) Wrapper 31 * controller. QUP Wrapper is designed to support various serial bus protocols 32 * like UART, SPI, I2C, I3C, etc. 33 */ 34 35 /** 36 * DOC: Hardware description 37 * 38 * GENI based QUP is a highly-flexible and programmable module for supporting 39 * a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single 40 * QUP module can provide upto 8 serial interfaces, using its internal 41 * serial engines. The actual configuration is determined by the target 42 * platform configuration. The protocol supported by each interface is 43 * determined by the firmware loaded to the serial engine. Each SE consists 44 * of a DMA Engine and GENI sub modules which enable serial engines to 45 * support FIFO and DMA modes of operation. 46 * 47 * 48 * +-----------------------------------------+ 49 * |QUP Wrapper | 50 * | +----------------------------+ | 51 * --QUP & SE Clocks--> | Serial Engine N | +-IO------> 52 * | | ... | | Interface 53 * <---Clock Perf.----+ +----+-----------------------+ | | 54 * State Interface | | Serial Engine 1 | | | 55 * | | | | | 56 * | | | | | 57 * <--------AHB-------> | | | | 58 * | | +----+ | 59 * | | | | 60 * | | | | 61 * <------SE IRQ------+ +----------------------------+ | 62 * | | 63 * +-----------------------------------------+ 64 * 65 * Figure 1: GENI based QUP Wrapper 66 * 67 * The GENI submodules include primary and secondary sequencers which are 68 * used to drive TX & RX operations. On serial interfaces that operate using 69 * master-slave model, primary sequencer drives both TX & RX operations. On 70 * serial interfaces that operate using peer-to-peer model, primary sequencer 71 * drives TX operation and secondary sequencer drives RX operation. 72 */ 73 74 /** 75 * DOC: Software description 76 * 77 * GENI SE Wrapper driver is structured into 2 parts: 78 * 79 * geni_wrapper represents QUP Wrapper controller. This part of the driver 80 * manages QUP Wrapper information such as hardware version, clock 81 * performance table that is common to all the internal serial engines. 82 * 83 * geni_se represents serial engine. This part of the driver manages serial 84 * engine information such as clocks, containing QUP Wrapper, etc. This part 85 * of driver also supports operations (eg. initialize the concerned serial 86 * engine, select between FIFO and DMA mode of operation etc.) that are 87 * common to all the serial engines and are independent of serial interfaces. 88 */ 89 90 #define MAX_CLK_PERF_LEVEL 32 91 #define MAX_CLKS 2 92 93 /** 94 * struct geni_wrapper - Data structure to represent the QUP Wrapper Core 95 * @dev: Device pointer of the QUP wrapper core 96 * @base: Base address of this instance of QUP wrapper core 97 * @clks: Handle to the primary & optional secondary AHB clocks 98 * @num_clks: Count of clocks 99 */ 100 struct geni_wrapper { 101 struct device *dev; 102 void __iomem *base; 103 struct clk_bulk_data clks[MAX_CLKS]; 104 unsigned int num_clks; 105 }; 106 107 /** 108 * struct geni_se_desc - Data structure to represent the QUP Wrapper resources 109 * @clks: Name of the primary & optional secondary AHB clocks 110 * @num_clks: Count of clock names 111 */ 112 struct geni_se_desc { 113 unsigned int num_clks; 114 const char * const *clks; 115 }; 116 117 static const char * const icc_path_names[] = {"qup-core", "qup-config", 118 "qup-memory"}; 119 120 static const char * const protocol_name[] = { "None", "SPI", "UART", "I2C", "I3C", "SPI SLAVE" }; 121 122 /** 123 * struct se_fw_hdr - Serial Engine firmware configuration header 124 * 125 * This structure defines the SE firmware header, which together with the 126 * firmware payload is stored in individual ELF segments. 127 * 128 * @magic: Set to 'SEFW'. 129 * @version: Structure version number. 130 * @core_version: QUPV3 hardware version. 131 * @serial_protocol: Encoded in GENI_FW_REVISION. 132 * @fw_version: Firmware version, from GENI_FW_REVISION. 133 * @cfg_version: Configuration version, from GENI_INIT_CFG_REVISION. 134 * @fw_size_in_items: Number of 32-bit words in GENI_FW_RAM. 135 * @fw_offset: Byte offset to GENI_FW_RAM array. 136 * @cfg_size_in_items: Number of GENI_FW_CFG index/value pairs. 137 * @cfg_idx_offset: Byte offset to GENI_FW_CFG index array. 138 * @cfg_val_offset: Byte offset to GENI_FW_CFG values array. 139 */ 140 struct se_fw_hdr { 141 __le32 magic; 142 __le32 version; 143 __le32 core_version; 144 __le16 serial_protocol; 145 __le16 fw_version; 146 __le16 cfg_version; 147 __le16 fw_size_in_items; 148 __le16 fw_offset; 149 __le16 cfg_size_in_items; 150 __le16 cfg_idx_offset; 151 __le16 cfg_val_offset; 152 }; 153 154 /*Magic numbers*/ 155 #define SE_MAGIC_NUM 0x57464553 156 157 #define MAX_GENI_CFG_RAMn_CNT 455 158 159 #define MI_PBT_NON_PAGED_SEGMENT 0x0 160 #define MI_PBT_HASH_SEGMENT 0x2 161 #define MI_PBT_NOTUSED_SEGMENT 0x3 162 #define MI_PBT_SHARED_SEGMENT 0x4 163 164 #define MI_PBT_FLAG_PAGE_MODE BIT(20) 165 #define MI_PBT_FLAG_SEGMENT_TYPE GENMASK(26, 24) 166 #define MI_PBT_FLAG_ACCESS_TYPE GENMASK(23, 21) 167 168 #define MI_PBT_PAGE_MODE_VALUE(x) FIELD_GET(MI_PBT_FLAG_PAGE_MODE, x) 169 170 #define MI_PBT_SEGMENT_TYPE_VALUE(x) FIELD_GET(MI_PBT_FLAG_SEGMENT_TYPE, x) 171 172 #define MI_PBT_ACCESS_TYPE_VALUE(x) FIELD_GET(MI_PBT_FLAG_ACCESS_TYPE, x) 173 174 #define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \ 175 M_IO_DATA_DEASSERT_EN | \ 176 M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \ 177 M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \ 178 M_TX_FIFO_WR_ERR_EN) 179 180 /* Common QUPV3 registers */ 181 #define QUPV3_HW_VER_REG 0x4 182 #define QUPV3_SE_AHB_M_CFG 0x118 183 #define QUPV3_COMMON_CFG 0x120 184 #define QUPV3_COMMON_CGC_CTRL 0x21c 185 186 /* QUPV3_COMMON_CFG fields */ 187 #define FAST_SWITCH_TO_HIGH_DISABLE BIT(0) 188 189 /* QUPV3_SE_AHB_M_CFG fields */ 190 #define AHB_M_CLK_CGC_ON BIT(0) 191 192 /* QUPV3_COMMON_CGC_CTRL fields */ 193 #define COMMON_CSR_SLV_CLK_CGC_ON BIT(0) 194 195 /* Common SE registers */ 196 #define SE_GENI_INIT_CFG_REVISION 0x0 197 #define SE_GENI_S_INIT_CFG_REVISION 0x4 198 #define SE_GENI_CGC_CTRL 0x28 199 #define SE_GENI_CLK_CTRL_RO 0x60 200 #define SE_GENI_FW_S_REVISION_RO 0x6c 201 #define SE_GENI_CFG_REG0 0x100 202 #define SE_GENI_BYTE_GRAN 0x254 203 #define SE_GENI_TX_PACKING_CFG0 0x260 204 #define SE_GENI_TX_PACKING_CFG1 0x264 205 #define SE_GENI_RX_PACKING_CFG0 0x284 206 #define SE_GENI_RX_PACKING_CFG1 0x288 207 #define SE_GENI_S_IRQ_ENABLE 0x644 208 #define SE_DMA_TX_PTR_L 0xc30 209 #define SE_DMA_TX_PTR_H 0xc34 210 #define SE_DMA_TX_ATTR 0xc38 211 #define SE_DMA_TX_LEN 0xc3c 212 #define SE_DMA_TX_IRQ_EN 0xc48 213 #define SE_DMA_TX_IRQ_EN_SET 0xc4c 214 #define SE_DMA_TX_IRQ_EN_CLR 0xc50 215 #define SE_DMA_TX_LEN_IN 0xc54 216 #define SE_DMA_TX_MAX_BURST 0xc5c 217 #define SE_DMA_RX_PTR_L 0xd30 218 #define SE_DMA_RX_PTR_H 0xd34 219 #define SE_DMA_RX_ATTR 0xd38 220 #define SE_DMA_RX_LEN 0xd3c 221 #define SE_DMA_RX_IRQ_EN 0xd48 222 #define SE_DMA_RX_IRQ_EN_SET 0xd4c 223 #define SE_DMA_RX_IRQ_EN_CLR 0xd50 224 #define SE_DMA_RX_MAX_BURST 0xd5c 225 #define SE_DMA_RX_FLUSH 0xd60 226 #define SE_GSI_EVENT_EN 0xe18 227 #define SE_IRQ_EN 0xe1c 228 #define SE_DMA_GENERAL_CFG 0xe30 229 #define SE_GENI_FW_REVISION 0x1000 230 #define SE_GENI_S_FW_REVISION 0x1004 231 #define SE_GENI_CFG_RAMN 0x1010 232 #define SE_GENI_CLK_CTRL 0x2000 233 #define SE_DMA_IF_EN 0x2004 234 #define SE_FIFO_IF_DISABLE 0x2008 235 236 /* GENI_FW_REVISION_RO fields */ 237 #define FW_REV_VERSION_MSK GENMASK(7, 0) 238 239 /* GENI_OUTPUT_CTRL fields */ 240 #define DEFAULT_IO_OUTPUT_CTRL_MSK GENMASK(6, 0) 241 242 /* GENI_CGC_CTRL fields */ 243 #define CFG_AHB_CLK_CGC_ON BIT(0) 244 #define CFG_AHB_WR_ACLK_CGC_ON BIT(1) 245 #define DATA_AHB_CLK_CGC_ON BIT(2) 246 #define SCLK_CGC_ON BIT(3) 247 #define TX_CLK_CGC_ON BIT(4) 248 #define RX_CLK_CGC_ON BIT(5) 249 #define EXT_CLK_CGC_ON BIT(6) 250 #define PROG_RAM_HCLK_OFF BIT(8) 251 #define PROG_RAM_SCLK_OFF BIT(9) 252 #define DEFAULT_CGC_EN GENMASK(6, 0) 253 254 /* SE_GSI_EVENT_EN fields */ 255 #define DMA_RX_EVENT_EN BIT(0) 256 #define DMA_TX_EVENT_EN BIT(1) 257 #define GENI_M_EVENT_EN BIT(2) 258 #define GENI_S_EVENT_EN BIT(3) 259 260 /* SE_IRQ_EN fields */ 261 #define DMA_RX_IRQ_EN BIT(0) 262 #define DMA_TX_IRQ_EN BIT(1) 263 #define GENI_M_IRQ_EN BIT(2) 264 #define GENI_S_IRQ_EN BIT(3) 265 266 /* SE_DMA_GENERAL_CFG */ 267 #define DMA_RX_CLK_CGC_ON BIT(0) 268 #define DMA_TX_CLK_CGC_ON BIT(1) 269 #define DMA_AHB_SLV_CLK_CGC_ON BIT(2) 270 #define AHB_SEC_SLV_CLK_CGC_ON BIT(3) 271 #define DUMMY_RX_NON_BUFFERABLE BIT(4) 272 #define RX_DMA_ZERO_PADDING_EN BIT(5) 273 #define RX_DMA_IRQ_DELAY_MSK GENMASK(8, 6) 274 #define RX_DMA_IRQ_DELAY_SHFT 6 275 276 /* GENI_CLK_CTRL fields */ 277 #define SER_CLK_SEL BIT(0) 278 279 /* GENI_DMA_IF_EN fields */ 280 #define DMA_IF_EN BIT(0) 281 282 #define geni_setbits32(_addr, _v) writel(readl(_addr) | (_v), _addr) 283 #define geni_clrbits32(_addr, _v) writel(readl(_addr) & ~(_v), _addr) 284 285 enum domain_idx { 286 DOMAIN_IDX_POWER, 287 DOMAIN_IDX_PERF, 288 DOMAIN_IDX_MAX 289 }; 290 291 /** 292 * geni_se_get_qup_hw_version() - Read the QUP wrapper Hardware version 293 * @se: Pointer to the corresponding serial engine. 294 * 295 * Return: Hardware Version of the wrapper. 296 */ 297 u32 geni_se_get_qup_hw_version(struct geni_se *se) 298 { 299 struct geni_wrapper *wrapper = se->wrapper; 300 301 return readl_relaxed(wrapper->base + QUPV3_HW_VER_REG); 302 } 303 EXPORT_SYMBOL_GPL(geni_se_get_qup_hw_version); 304 305 static void geni_se_io_set_mode(void __iomem *base) 306 { 307 u32 val; 308 309 val = readl_relaxed(base + SE_IRQ_EN); 310 val |= GENI_M_IRQ_EN | GENI_S_IRQ_EN; 311 val |= DMA_TX_IRQ_EN | DMA_RX_IRQ_EN; 312 writel_relaxed(val, base + SE_IRQ_EN); 313 314 val = readl_relaxed(base + SE_GENI_DMA_MODE_EN); 315 val &= ~GENI_DMA_MODE_EN; 316 writel_relaxed(val, base + SE_GENI_DMA_MODE_EN); 317 318 writel_relaxed(0, base + SE_GSI_EVENT_EN); 319 } 320 321 static void geni_se_io_init(void __iomem *base) 322 { 323 u32 val; 324 325 val = readl_relaxed(base + SE_GENI_CGC_CTRL); 326 val |= DEFAULT_CGC_EN; 327 writel_relaxed(val, base + SE_GENI_CGC_CTRL); 328 329 val = readl_relaxed(base + SE_DMA_GENERAL_CFG); 330 val |= AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CLK_CGC_ON; 331 val |= DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON; 332 writel_relaxed(val, base + SE_DMA_GENERAL_CFG); 333 334 writel_relaxed(DEFAULT_IO_OUTPUT_CTRL_MSK, base + GENI_OUTPUT_CTRL); 335 writel_relaxed(FORCE_DEFAULT, base + GENI_FORCE_DEFAULT_REG); 336 } 337 338 static void geni_se_irq_clear(struct geni_se *se) 339 { 340 writel_relaxed(0, se->base + SE_GSI_EVENT_EN); 341 writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR); 342 writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR); 343 writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR); 344 writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR); 345 writel_relaxed(0xffffffff, se->base + SE_IRQ_EN); 346 } 347 348 /** 349 * geni_se_init() - Initialize the GENI serial engine 350 * @se: Pointer to the concerned serial engine. 351 * @rx_wm: Receive watermark, in units of FIFO words. 352 * @rx_rfr: Ready-for-receive watermark, in units of FIFO words. 353 * 354 * This function is used to initialize the GENI serial engine, configure 355 * receive watermark and ready-for-receive watermarks. 356 */ 357 void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr) 358 { 359 u32 val; 360 361 geni_se_irq_clear(se); 362 geni_se_io_init(se->base); 363 geni_se_io_set_mode(se->base); 364 365 writel_relaxed(rx_wm, se->base + SE_GENI_RX_WATERMARK_REG); 366 writel_relaxed(rx_rfr, se->base + SE_GENI_RX_RFR_WATERMARK_REG); 367 368 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); 369 val |= M_COMMON_GENI_M_IRQ_EN; 370 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); 371 372 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); 373 val |= S_COMMON_GENI_S_IRQ_EN; 374 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); 375 } 376 EXPORT_SYMBOL_GPL(geni_se_init); 377 378 static void geni_se_select_fifo_mode(struct geni_se *se) 379 { 380 u32 proto = geni_se_read_proto(se); 381 u32 val, val_old; 382 383 geni_se_irq_clear(se); 384 385 /* UART driver manages enabling / disabling interrupts internally */ 386 if (proto != GENI_SE_UART) { 387 /* Non-UART use only primary sequencer so dont bother about S_IRQ */ 388 val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); 389 val |= M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN; 390 val |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; 391 if (val != val_old) 392 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); 393 } 394 395 val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); 396 val &= ~GENI_DMA_MODE_EN; 397 if (val != val_old) 398 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); 399 } 400 401 static void geni_se_select_dma_mode(struct geni_se *se) 402 { 403 u32 proto = geni_se_read_proto(se); 404 u32 val, val_old; 405 406 geni_se_irq_clear(se); 407 408 /* UART driver manages enabling / disabling interrupts internally */ 409 if (proto != GENI_SE_UART) { 410 /* Non-UART use only primary sequencer so dont bother about S_IRQ */ 411 val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); 412 val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN); 413 val &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); 414 if (val != val_old) 415 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); 416 } 417 418 val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); 419 val |= GENI_DMA_MODE_EN; 420 if (val != val_old) 421 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); 422 } 423 424 static void geni_se_select_gpi_mode(struct geni_se *se) 425 { 426 u32 val; 427 428 geni_se_irq_clear(se); 429 430 writel(0, se->base + SE_IRQ_EN); 431 432 val = readl(se->base + SE_GENI_M_IRQ_EN); 433 val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN | 434 M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); 435 writel(val, se->base + SE_GENI_M_IRQ_EN); 436 437 writel(GENI_DMA_MODE_EN, se->base + SE_GENI_DMA_MODE_EN); 438 439 val = readl(se->base + SE_GSI_EVENT_EN); 440 val |= (DMA_RX_EVENT_EN | DMA_TX_EVENT_EN | GENI_M_EVENT_EN | GENI_S_EVENT_EN); 441 writel(val, se->base + SE_GSI_EVENT_EN); 442 } 443 444 /** 445 * geni_se_select_mode() - Select the serial engine transfer mode 446 * @se: Pointer to the concerned serial engine. 447 * @mode: Transfer mode to be selected. 448 */ 449 void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode) 450 { 451 WARN_ON(mode != GENI_SE_FIFO && mode != GENI_SE_DMA && mode != GENI_GPI_DMA); 452 453 switch (mode) { 454 case GENI_SE_FIFO: 455 geni_se_select_fifo_mode(se); 456 break; 457 case GENI_SE_DMA: 458 geni_se_select_dma_mode(se); 459 break; 460 case GENI_GPI_DMA: 461 geni_se_select_gpi_mode(se); 462 break; 463 case GENI_SE_INVALID: 464 default: 465 break; 466 } 467 } 468 EXPORT_SYMBOL_GPL(geni_se_select_mode); 469 470 /** 471 * DOC: Overview 472 * 473 * GENI FIFO packing is highly configurable. TX/RX packing/unpacking consist 474 * of up to 4 operations, each operation represented by 4 configuration vectors 475 * of 10 bits programmed in GENI_TX_PACKING_CFG0 and GENI_TX_PACKING_CFG1 for 476 * TX FIFO and in GENI_RX_PACKING_CFG0 and GENI_RX_PACKING_CFG1 for RX FIFO. 477 * Refer to below examples for detailed bit-field description. 478 * 479 * Example 1: word_size = 7, packing_mode = 4 x 8, msb_to_lsb = 1 480 * 481 * +-----------+-------+-------+-------+-------+ 482 * | | vec_0 | vec_1 | vec_2 | vec_3 | 483 * +-----------+-------+-------+-------+-------+ 484 * | start | 0x6 | 0xe | 0x16 | 0x1e | 485 * | direction | 1 | 1 | 1 | 1 | 486 * | length | 6 | 6 | 6 | 6 | 487 * | stop | 0 | 0 | 0 | 1 | 488 * +-----------+-------+-------+-------+-------+ 489 * 490 * Example 2: word_size = 15, packing_mode = 2 x 16, msb_to_lsb = 0 491 * 492 * +-----------+-------+-------+-------+-------+ 493 * | | vec_0 | vec_1 | vec_2 | vec_3 | 494 * +-----------+-------+-------+-------+-------+ 495 * | start | 0x0 | 0x8 | 0x10 | 0x18 | 496 * | direction | 0 | 0 | 0 | 0 | 497 * | length | 7 | 6 | 7 | 6 | 498 * | stop | 0 | 0 | 0 | 1 | 499 * +-----------+-------+-------+-------+-------+ 500 * 501 * Example 3: word_size = 23, packing_mode = 1 x 32, msb_to_lsb = 1 502 * 503 * +-----------+-------+-------+-------+-------+ 504 * | | vec_0 | vec_1 | vec_2 | vec_3 | 505 * +-----------+-------+-------+-------+-------+ 506 * | start | 0x16 | 0xe | 0x6 | 0x0 | 507 * | direction | 1 | 1 | 1 | 1 | 508 * | length | 7 | 7 | 6 | 0 | 509 * | stop | 0 | 0 | 1 | 0 | 510 * +-----------+-------+-------+-------+-------+ 511 * 512 */ 513 514 #define NUM_PACKING_VECTORS 4 515 #define PACKING_START_SHIFT 5 516 #define PACKING_DIR_SHIFT 4 517 #define PACKING_LEN_SHIFT 1 518 #define PACKING_STOP_BIT BIT(0) 519 #define PACKING_VECTOR_SHIFT 10 520 /** 521 * geni_se_config_packing() - Packing configuration of the serial engine 522 * @se: Pointer to the concerned serial engine 523 * @bpw: Bits of data per transfer word. 524 * @pack_words: Number of words per fifo element. 525 * @msb_to_lsb: Transfer from MSB to LSB or vice-versa. 526 * @tx_cfg: Flag to configure the TX Packing. 527 * @rx_cfg: Flag to configure the RX Packing. 528 * 529 * This function is used to configure the packing rules for the current 530 * transfer. 531 */ 532 void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words, 533 bool msb_to_lsb, bool tx_cfg, bool rx_cfg) 534 { 535 u32 cfg0, cfg1, cfg[NUM_PACKING_VECTORS] = {0}; 536 int len; 537 int temp_bpw = bpw; 538 int idx_start = msb_to_lsb ? bpw - 1 : 0; 539 int idx = idx_start; 540 int idx_delta = msb_to_lsb ? -BITS_PER_BYTE : BITS_PER_BYTE; 541 int ceil_bpw = ALIGN(bpw, BITS_PER_BYTE); 542 int iter = (ceil_bpw * pack_words) / BITS_PER_BYTE; 543 int i; 544 545 if (iter <= 0 || iter > NUM_PACKING_VECTORS) 546 return; 547 548 for (i = 0; i < iter; i++) { 549 len = min_t(int, temp_bpw, BITS_PER_BYTE) - 1; 550 cfg[i] = idx << PACKING_START_SHIFT; 551 cfg[i] |= msb_to_lsb << PACKING_DIR_SHIFT; 552 cfg[i] |= len << PACKING_LEN_SHIFT; 553 554 if (temp_bpw <= BITS_PER_BYTE) { 555 idx = ((i + 1) * BITS_PER_BYTE) + idx_start; 556 temp_bpw = bpw; 557 } else { 558 idx = idx + idx_delta; 559 temp_bpw = temp_bpw - BITS_PER_BYTE; 560 } 561 } 562 cfg[iter - 1] |= PACKING_STOP_BIT; 563 cfg0 = cfg[0] | (cfg[1] << PACKING_VECTOR_SHIFT); 564 cfg1 = cfg[2] | (cfg[3] << PACKING_VECTOR_SHIFT); 565 566 if (tx_cfg) { 567 writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0); 568 writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1); 569 } 570 if (rx_cfg) { 571 writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0); 572 writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1); 573 } 574 575 /* 576 * Number of protocol words in each FIFO entry 577 * 0 - 4x8, four words in each entry, max word size of 8 bits 578 * 1 - 2x16, two words in each entry, max word size of 16 bits 579 * 2 - 1x32, one word in each entry, max word size of 32 bits 580 * 3 - undefined 581 */ 582 if (pack_words || bpw == 32) 583 writel_relaxed(bpw / 16, se->base + SE_GENI_BYTE_GRAN); 584 } 585 EXPORT_SYMBOL_GPL(geni_se_config_packing); 586 587 static void geni_se_clks_off(struct geni_se *se) 588 { 589 struct geni_wrapper *wrapper = se->wrapper; 590 591 clk_disable_unprepare(se->clk); 592 clk_bulk_disable_unprepare(wrapper->num_clks, wrapper->clks); 593 clk_disable_unprepare(se->core_clk); 594 } 595 596 /** 597 * geni_se_resources_off() - Turn off resources associated with the serial 598 * engine 599 * @se: Pointer to the concerned serial engine. 600 * 601 * Return: 0 on success, standard Linux error codes on failure/error. 602 */ 603 int geni_se_resources_off(struct geni_se *se) 604 { 605 int ret; 606 607 if (has_acpi_companion(se->dev)) 608 return 0; 609 610 ret = pinctrl_pm_select_sleep_state(se->dev); 611 if (ret) 612 return ret; 613 614 geni_se_clks_off(se); 615 return 0; 616 } 617 EXPORT_SYMBOL_GPL(geni_se_resources_off); 618 619 static int geni_se_clks_on(struct geni_se *se) 620 { 621 int ret; 622 struct geni_wrapper *wrapper = se->wrapper; 623 624 ret = clk_bulk_prepare_enable(wrapper->num_clks, wrapper->clks); 625 if (ret) 626 return ret; 627 628 ret = clk_prepare_enable(se->clk); 629 if (ret) 630 goto err_bulk_clks; 631 632 ret = clk_prepare_enable(se->core_clk); 633 if (ret) 634 goto err_se_clk; 635 636 return 0; 637 638 err_se_clk: 639 clk_disable_unprepare(se->clk); 640 err_bulk_clks: 641 clk_bulk_disable_unprepare(wrapper->num_clks, wrapper->clks); 642 return ret; 643 } 644 645 /** 646 * geni_se_resources_on() - Turn on resources associated with the serial 647 * engine 648 * @se: Pointer to the concerned serial engine. 649 * 650 * Return: 0 on success, standard Linux error codes on failure/error. 651 */ 652 int geni_se_resources_on(struct geni_se *se) 653 { 654 int ret; 655 656 if (has_acpi_companion(se->dev)) 657 return 0; 658 659 ret = geni_se_clks_on(se); 660 if (ret) 661 return ret; 662 663 ret = pinctrl_pm_select_default_state(se->dev); 664 if (ret) 665 geni_se_clks_off(se); 666 667 return ret; 668 } 669 EXPORT_SYMBOL_GPL(geni_se_resources_on); 670 671 /** 672 * geni_se_clk_tbl_get() - Get the clock table to program DFS 673 * @se: Pointer to the concerned serial engine. 674 * @tbl: Table in which the output is returned. 675 * 676 * This function is called by the protocol drivers to determine the different 677 * clock frequencies supported by serial engine core clock. The protocol 678 * drivers use the output to determine the clock frequency index to be 679 * programmed into DFS. 680 * 681 * Return: number of valid performance levels in the table on success, 682 * standard Linux error codes on failure. 683 */ 684 int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl) 685 { 686 long freq = 0; 687 int i; 688 689 if (se->clk_perf_tbl) { 690 *tbl = se->clk_perf_tbl; 691 return se->num_clk_levels; 692 } 693 694 se->clk_perf_tbl = devm_kcalloc(se->dev, MAX_CLK_PERF_LEVEL, 695 sizeof(*se->clk_perf_tbl), 696 GFP_KERNEL); 697 if (!se->clk_perf_tbl) 698 return -ENOMEM; 699 700 for (i = 0; i < MAX_CLK_PERF_LEVEL; i++) { 701 freq = clk_round_rate(se->clk, freq + 1); 702 if (freq <= 0 || 703 (i > 0 && freq == se->clk_perf_tbl[i - 1])) 704 break; 705 se->clk_perf_tbl[i] = freq; 706 } 707 se->num_clk_levels = i; 708 *tbl = se->clk_perf_tbl; 709 return se->num_clk_levels; 710 } 711 EXPORT_SYMBOL_GPL(geni_se_clk_tbl_get); 712 713 /** 714 * geni_se_clk_freq_match() - Get the matching or closest SE clock frequency 715 * @se: Pointer to the concerned serial engine. 716 * @req_freq: Requested clock frequency. 717 * @index: Index of the resultant frequency in the table. 718 * @res_freq: Resultant frequency of the source clock. 719 * @exact: Flag to indicate exact multiple requirement of the requested 720 * frequency. 721 * 722 * This function is called by the protocol drivers to determine the best match 723 * of the requested frequency as provided by the serial engine clock in order 724 * to meet the performance requirements. 725 * 726 * If we return success: 727 * - if @exact is true then @res_freq / <an_integer> == @req_freq 728 * - if @exact is false then @res_freq / <an_integer> <= @req_freq 729 * 730 * Return: 0 on success, standard Linux error codes on failure. 731 */ 732 int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq, 733 unsigned int *index, unsigned long *res_freq, 734 bool exact) 735 { 736 unsigned long *tbl; 737 int num_clk_levels; 738 int i; 739 unsigned long best_delta; 740 unsigned long new_delta; 741 unsigned int divider; 742 743 num_clk_levels = geni_se_clk_tbl_get(se, &tbl); 744 if (num_clk_levels < 0) 745 return num_clk_levels; 746 747 if (num_clk_levels == 0) 748 return -EINVAL; 749 750 best_delta = ULONG_MAX; 751 for (i = 0; i < num_clk_levels; i++) { 752 divider = DIV_ROUND_UP(tbl[i], req_freq); 753 new_delta = req_freq - tbl[i] / divider; 754 if (new_delta < best_delta) { 755 /* We have a new best! */ 756 *index = i; 757 *res_freq = tbl[i]; 758 759 /* If the new best is exact then we're done */ 760 if (new_delta == 0) 761 return 0; 762 763 /* Record how close we got */ 764 best_delta = new_delta; 765 } 766 } 767 768 if (exact) 769 return -EINVAL; 770 771 return 0; 772 } 773 EXPORT_SYMBOL_GPL(geni_se_clk_freq_match); 774 775 #define GENI_SE_DMA_DONE_EN BIT(0) 776 #define GENI_SE_DMA_EOT_EN BIT(1) 777 #define GENI_SE_DMA_AHB_ERR_EN BIT(2) 778 #define GENI_SE_DMA_RESET_DONE_EN BIT(3) 779 #define GENI_SE_DMA_FLUSH_DONE BIT(4) 780 781 #define GENI_SE_DMA_EOT_BUF BIT(0) 782 783 /** 784 * geni_se_tx_init_dma() - Initiate TX DMA transfer on the serial engine 785 * @se: Pointer to the concerned serial engine. 786 * @iova: Mapped DMA address. 787 * @len: Length of the TX buffer. 788 * 789 * This function is used to initiate DMA TX transfer. 790 */ 791 void geni_se_tx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len) 792 { 793 u32 val; 794 795 val = GENI_SE_DMA_DONE_EN; 796 val |= GENI_SE_DMA_EOT_EN; 797 val |= GENI_SE_DMA_AHB_ERR_EN; 798 writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET); 799 writel_relaxed(lower_32_bits(iova), se->base + SE_DMA_TX_PTR_L); 800 writel_relaxed(upper_32_bits(iova), se->base + SE_DMA_TX_PTR_H); 801 writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR); 802 writel(len, se->base + SE_DMA_TX_LEN); 803 } 804 EXPORT_SYMBOL_GPL(geni_se_tx_init_dma); 805 806 /** 807 * geni_se_tx_dma_prep() - Prepare the serial engine for TX DMA transfer 808 * @se: Pointer to the concerned serial engine. 809 * @buf: Pointer to the TX buffer. 810 * @len: Length of the TX buffer. 811 * @iova: Pointer to store the mapped DMA address. 812 * 813 * This function is used to prepare the buffers for DMA TX. 814 * 815 * Return: 0 on success, standard Linux error codes on failure. 816 */ 817 int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len, 818 dma_addr_t *iova) 819 { 820 struct geni_wrapper *wrapper = se->wrapper; 821 822 if (!wrapper) 823 return -EINVAL; 824 825 *iova = dma_map_single(wrapper->dev, buf, len, DMA_TO_DEVICE); 826 if (dma_mapping_error(wrapper->dev, *iova)) 827 return -EIO; 828 829 geni_se_tx_init_dma(se, *iova, len); 830 return 0; 831 } 832 EXPORT_SYMBOL_GPL(geni_se_tx_dma_prep); 833 834 /** 835 * geni_se_rx_init_dma() - Initiate RX DMA transfer on the serial engine 836 * @se: Pointer to the concerned serial engine. 837 * @iova: Mapped DMA address. 838 * @len: Length of the RX buffer. 839 * 840 * This function is used to initiate DMA RX transfer. 841 */ 842 void geni_se_rx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len) 843 { 844 u32 val; 845 846 val = GENI_SE_DMA_DONE_EN; 847 val |= GENI_SE_DMA_EOT_EN; 848 val |= GENI_SE_DMA_AHB_ERR_EN; 849 writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET); 850 writel_relaxed(lower_32_bits(iova), se->base + SE_DMA_RX_PTR_L); 851 writel_relaxed(upper_32_bits(iova), se->base + SE_DMA_RX_PTR_H); 852 /* RX does not have EOT buffer type bit. So just reset RX_ATTR */ 853 writel_relaxed(0, se->base + SE_DMA_RX_ATTR); 854 writel(len, se->base + SE_DMA_RX_LEN); 855 } 856 EXPORT_SYMBOL_GPL(geni_se_rx_init_dma); 857 858 /** 859 * geni_se_rx_dma_prep() - Prepare the serial engine for RX DMA transfer 860 * @se: Pointer to the concerned serial engine. 861 * @buf: Pointer to the RX buffer. 862 * @len: Length of the RX buffer. 863 * @iova: Pointer to store the mapped DMA address. 864 * 865 * This function is used to prepare the buffers for DMA RX. 866 * 867 * Return: 0 on success, standard Linux error codes on failure. 868 */ 869 int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len, 870 dma_addr_t *iova) 871 { 872 struct geni_wrapper *wrapper = se->wrapper; 873 874 if (!wrapper) 875 return -EINVAL; 876 877 *iova = dma_map_single(wrapper->dev, buf, len, DMA_FROM_DEVICE); 878 if (dma_mapping_error(wrapper->dev, *iova)) 879 return -EIO; 880 881 geni_se_rx_init_dma(se, *iova, len); 882 return 0; 883 } 884 EXPORT_SYMBOL_GPL(geni_se_rx_dma_prep); 885 886 /** 887 * geni_se_tx_dma_unprep() - Unprepare the serial engine after TX DMA transfer 888 * @se: Pointer to the concerned serial engine. 889 * @iova: DMA address of the TX buffer. 890 * @len: Length of the TX buffer. 891 * 892 * This function is used to unprepare the DMA buffers after DMA TX. 893 */ 894 void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len) 895 { 896 struct geni_wrapper *wrapper = se->wrapper; 897 898 if (!dma_mapping_error(wrapper->dev, iova)) 899 dma_unmap_single(wrapper->dev, iova, len, DMA_TO_DEVICE); 900 } 901 EXPORT_SYMBOL_GPL(geni_se_tx_dma_unprep); 902 903 /** 904 * geni_se_rx_dma_unprep() - Unprepare the serial engine after RX DMA transfer 905 * @se: Pointer to the concerned serial engine. 906 * @iova: DMA address of the RX buffer. 907 * @len: Length of the RX buffer. 908 * 909 * This function is used to unprepare the DMA buffers after DMA RX. 910 */ 911 void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len) 912 { 913 struct geni_wrapper *wrapper = se->wrapper; 914 915 if (!dma_mapping_error(wrapper->dev, iova)) 916 dma_unmap_single(wrapper->dev, iova, len, DMA_FROM_DEVICE); 917 } 918 EXPORT_SYMBOL_GPL(geni_se_rx_dma_unprep); 919 920 int geni_icc_get(struct geni_se *se, const char *icc_ddr) 921 { 922 struct geni_icc_path *icc_paths = se->icc_paths; 923 924 if (has_acpi_companion(se->dev)) 925 return 0; 926 927 icc_paths[GENI_TO_CORE].path = devm_of_icc_get(se->dev, "qup-core"); 928 if (IS_ERR(icc_paths[GENI_TO_CORE].path)) 929 return dev_err_probe(se->dev, PTR_ERR(icc_paths[GENI_TO_CORE].path), 930 "Failed to get 'qup-core' ICC path\n"); 931 932 icc_paths[CPU_TO_GENI].path = devm_of_icc_get(se->dev, "qup-config"); 933 if (IS_ERR(icc_paths[CPU_TO_GENI].path)) 934 return dev_err_probe(se->dev, PTR_ERR(icc_paths[CPU_TO_GENI].path), 935 "Failed to get 'qup-config' ICC path\n"); 936 937 /* The DDR path is optional, depending on protocol and hw capabilities */ 938 icc_paths[GENI_TO_DDR].path = devm_of_icc_get(se->dev, "qup-memory"); 939 if (IS_ERR(icc_paths[GENI_TO_DDR].path)) { 940 if (PTR_ERR(icc_paths[GENI_TO_DDR].path) == -ENODATA) 941 icc_paths[GENI_TO_DDR].path = NULL; 942 else 943 return dev_err_probe(se->dev, PTR_ERR(icc_paths[GENI_TO_DDR].path), 944 "Failed to get 'qup-memory' ICC path\n"); 945 } 946 947 return 0; 948 } 949 EXPORT_SYMBOL_GPL(geni_icc_get); 950 951 int geni_icc_set_bw(struct geni_se *se) 952 { 953 int i, ret; 954 955 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { 956 ret = icc_set_bw(se->icc_paths[i].path, 957 se->icc_paths[i].avg_bw, se->icc_paths[i].avg_bw); 958 if (ret) { 959 dev_err_ratelimited(se->dev, "ICC BW voting failed on path '%s': %d\n", 960 icc_path_names[i], ret); 961 return ret; 962 } 963 } 964 965 return 0; 966 } 967 EXPORT_SYMBOL_GPL(geni_icc_set_bw); 968 969 /** 970 * geni_icc_set_bw_ab() - Set average bandwidth for all ICC paths and apply 971 * @se: Pointer to the concerned serial engine. 972 * @core_ab: Average bandwidth in kBps for GENI_TO_CORE path. 973 * @cfg_ab: Average bandwidth in kBps for CPU_TO_GENI path. 974 * @ddr_ab: Average bandwidth in kBps for GENI_TO_DDR path. 975 * 976 * Sets bandwidth values for all ICC paths and applies them. DDR path is 977 * optional and only set if it exists. 978 * 979 * Return: 0 on success, negative error code on failure. 980 */ 981 int geni_icc_set_bw_ab(struct geni_se *se, u32 core_ab, u32 cfg_ab, u32 ddr_ab) 982 { 983 se->icc_paths[GENI_TO_CORE].avg_bw = core_ab; 984 se->icc_paths[CPU_TO_GENI].avg_bw = cfg_ab; 985 se->icc_paths[GENI_TO_DDR].avg_bw = ddr_ab; 986 987 return geni_icc_set_bw(se); 988 } 989 EXPORT_SYMBOL_GPL(geni_icc_set_bw_ab); 990 991 void geni_icc_set_tag(struct geni_se *se, u32 tag) 992 { 993 int i; 994 995 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) 996 icc_set_tag(se->icc_paths[i].path, tag); 997 } 998 EXPORT_SYMBOL_GPL(geni_icc_set_tag); 999 1000 /* To do: Replace this by icc_bulk_enable once it's implemented in ICC core */ 1001 int geni_icc_enable(struct geni_se *se) 1002 { 1003 int i, ret; 1004 1005 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { 1006 ret = icc_enable(se->icc_paths[i].path); 1007 if (ret) { 1008 dev_err_ratelimited(se->dev, "ICC enable failed on path '%s': %d\n", 1009 icc_path_names[i], ret); 1010 return ret; 1011 } 1012 } 1013 1014 return 0; 1015 } 1016 EXPORT_SYMBOL_GPL(geni_icc_enable); 1017 1018 int geni_icc_disable(struct geni_se *se) 1019 { 1020 int i, ret; 1021 1022 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { 1023 ret = icc_disable(se->icc_paths[i].path); 1024 if (ret) { 1025 dev_err_ratelimited(se->dev, "ICC disable failed on path '%s': %d\n", 1026 icc_path_names[i], ret); 1027 return ret; 1028 } 1029 } 1030 1031 return 0; 1032 } 1033 EXPORT_SYMBOL_GPL(geni_icc_disable); 1034 1035 /** 1036 * geni_se_resources_deactivate() - Deactivate GENI SE device resources 1037 * @se: Pointer to the geni_se structure 1038 * 1039 * Deactivates device resources for power saving: OPP rate to 0, pin control 1040 * to sleep state, turns off clocks, and disables interconnect. Skips ACPI devices. 1041 * 1042 * Return: 0 on success, negative error code on failure 1043 */ 1044 int geni_se_resources_deactivate(struct geni_se *se) 1045 { 1046 int ret; 1047 1048 if (has_acpi_companion(se->dev)) 1049 return 0; 1050 1051 if (se->has_opp) 1052 dev_pm_opp_set_rate(se->dev, 0); 1053 1054 ret = pinctrl_pm_select_sleep_state(se->dev); 1055 if (ret) 1056 return ret; 1057 1058 geni_se_clks_off(se); 1059 1060 return geni_icc_disable(se); 1061 } 1062 EXPORT_SYMBOL_GPL(geni_se_resources_deactivate); 1063 1064 /** 1065 * geni_se_resources_activate() - Activate GENI SE device resources 1066 * @se: Pointer to the geni_se structure 1067 * 1068 * Activates device resources for operation: enables interconnect, prepares clocks, 1069 * and sets pin control to default state. Includes error cleanup. Skips ACPI devices. 1070 * 1071 * Unlike geni_se_resources_deactivate(), this function doesn't alter the 1072 * connected genpds' performance states, which must be additionally handled. 1073 * 1074 * Return: 0 on success, negative error code on failure 1075 */ 1076 int geni_se_resources_activate(struct geni_se *se) 1077 { 1078 int ret; 1079 1080 if (has_acpi_companion(se->dev)) 1081 return 0; 1082 1083 ret = geni_icc_enable(se); 1084 if (ret) 1085 return ret; 1086 1087 ret = geni_se_clks_on(se); 1088 if (ret) 1089 goto out_icc_disable; 1090 1091 ret = pinctrl_pm_select_default_state(se->dev); 1092 if (ret) { 1093 geni_se_clks_off(se); 1094 goto out_icc_disable; 1095 } 1096 1097 return 0; 1098 1099 out_icc_disable: 1100 geni_icc_disable(se); 1101 return ret; 1102 } 1103 EXPORT_SYMBOL_GPL(geni_se_resources_activate); 1104 1105 /** 1106 * geni_se_set_perf_level() - Set performance level for GENI SE. 1107 * @se: Pointer to the struct geni_se instance. 1108 * @level: The desired performance level. 1109 * 1110 * Sets the performance level by directly calling dev_pm_opp_set_level 1111 * on the performance device associated with the SE. 1112 * 1113 * Return: 0 on success, or a negative error code on failure. 1114 */ 1115 int geni_se_set_perf_level(struct geni_se *se, unsigned long level) 1116 { 1117 return dev_pm_opp_set_level(se->pd_list->pd_devs[DOMAIN_IDX_PERF], level); 1118 } 1119 EXPORT_SYMBOL_GPL(geni_se_set_perf_level); 1120 1121 /** 1122 * geni_se_set_perf_opp() - Set performance OPP for GENI SE by frequency. 1123 * @se: Pointer to the struct geni_se instance. 1124 * @clk_freq: The requested clock frequency. 1125 * 1126 * Finds the nearest operating performance point (OPP) for the given 1127 * clock frequency and applies it to the SE's performance device. 1128 * 1129 * Return: 0 on success, or a negative error code on failure. 1130 */ 1131 int geni_se_set_perf_opp(struct geni_se *se, unsigned long clk_freq) 1132 { 1133 struct device *perf_dev = se->pd_list->pd_devs[DOMAIN_IDX_PERF]; 1134 struct dev_pm_opp *opp; 1135 int ret; 1136 1137 opp = dev_pm_opp_find_freq_floor(perf_dev, &clk_freq); 1138 if (IS_ERR(opp)) { 1139 dev_err(se->dev, "failed to find opp for freq %lu\n", clk_freq); 1140 return PTR_ERR(opp); 1141 } 1142 1143 ret = dev_pm_opp_set_opp(perf_dev, opp); 1144 dev_pm_opp_put(opp); 1145 return ret; 1146 } 1147 EXPORT_SYMBOL_GPL(geni_se_set_perf_opp); 1148 1149 /** 1150 * geni_se_domain_attach() - Attach power domains to a GENI SE device. 1151 * @se: Pointer to the geni_se structure representing the GENI SE device. 1152 * 1153 * This function attaches the power domains ("power" and "perf") required 1154 * in the SCMI auto-VM environment to the GENI Serial Engine device. It 1155 * initializes se->pd_list with the attached domains. 1156 * 1157 * Return: 0 on success, or a negative error code on failure. 1158 */ 1159 int geni_se_domain_attach(struct geni_se *se) 1160 { 1161 struct dev_pm_domain_attach_data pd_data = { 1162 .pd_flags = PD_FLAG_DEV_LINK_ON, 1163 .pd_names = (const char*[]) { "power", "perf" }, 1164 .num_pd_names = 2, 1165 }; 1166 int ret; 1167 1168 ret = devm_pm_domain_attach_list(se->dev, 1169 &pd_data, &se->pd_list); 1170 if (ret == 0) 1171 return -ENODEV; 1172 else if (ret < 0) 1173 return ret; 1174 1175 return 0; 1176 } 1177 EXPORT_SYMBOL_GPL(geni_se_domain_attach); 1178 1179 /** 1180 * geni_se_resources_init() - Initialize resources for a GENI SE device. 1181 * @se: Pointer to the geni_se structure representing the GENI SE device. 1182 * 1183 * This function initializes various resources required by the GENI Serial Engine 1184 * (SE) device, including clock resources (core and SE clocks), interconnect 1185 * paths for communication. 1186 * It retrieves optional and mandatory clock resources, adds an OF-based 1187 * operating performance point (OPP) table, and sets up interconnect paths 1188 * with default bandwidths. The function also sets a flag (`has_opp`) to 1189 * indicate whether OPP support is available for the device. 1190 * 1191 * Return: 0 on success, or a negative errno on failure. 1192 */ 1193 int geni_se_resources_init(struct geni_se *se) 1194 { 1195 int ret; 1196 1197 se->core_clk = devm_clk_get_optional(se->dev, "core"); 1198 if (IS_ERR(se->core_clk)) 1199 return dev_err_probe(se->dev, PTR_ERR(se->core_clk), 1200 "Failed to get optional core clk\n"); 1201 1202 se->clk = devm_clk_get(se->dev, "se"); 1203 if (IS_ERR(se->clk) && !has_acpi_companion(se->dev)) 1204 return dev_err_probe(se->dev, PTR_ERR(se->clk), 1205 "Failed to get SE clk\n"); 1206 1207 ret = devm_pm_opp_set_clkname(se->dev, "se"); 1208 if (ret) 1209 return ret; 1210 1211 ret = devm_pm_opp_of_add_table(se->dev); 1212 if (ret && ret != -ENODEV) 1213 return dev_err_probe(se->dev, ret, "Failed to add OPP table\n"); 1214 1215 se->has_opp = (ret == 0); 1216 1217 ret = geni_icc_get(se, "qup-memory"); 1218 if (ret) 1219 return ret; 1220 1221 return geni_icc_set_bw_ab(se, GENI_DEFAULT_BW, GENI_DEFAULT_BW, GENI_DEFAULT_BW); 1222 } 1223 EXPORT_SYMBOL_GPL(geni_se_resources_init); 1224 1225 /** 1226 * geni_find_protocol_fw() - Locate and validate SE firmware for a protocol. 1227 * @dev: Pointer to the device structure. 1228 * @fw: Pointer to the firmware image. 1229 * @protocol: Expected serial engine protocol type. 1230 * 1231 * Identifies the appropriate firmware image or configuration required for a 1232 * specific communication protocol instance running on a Qualcomm GENI 1233 * controller. 1234 * 1235 * Return: pointer to a valid 'struct se_fw_hdr' if found, or NULL otherwise. 1236 */ 1237 static struct se_fw_hdr *geni_find_protocol_fw(struct device *dev, const struct firmware *fw, 1238 enum geni_se_protocol_type protocol) 1239 { 1240 const struct elf32_hdr *ehdr; 1241 const struct elf32_phdr *phdrs; 1242 const struct elf32_phdr *phdr; 1243 struct se_fw_hdr *sefw; 1244 u32 fw_end, cfg_idx_end, cfg_val_end; 1245 u16 fw_size; 1246 int i; 1247 1248 if (!fw || fw->size < sizeof(struct elf32_hdr)) 1249 return NULL; 1250 1251 ehdr = (const struct elf32_hdr *)fw->data; 1252 phdrs = (const struct elf32_phdr *)(fw->data + ehdr->e_phoff); 1253 1254 /* 1255 * The firmware is expected to have at least two program headers (segments). 1256 * One for metadata and the other for the actual protocol-specific firmware. 1257 */ 1258 if (ehdr->e_phnum < 2) { 1259 dev_err(dev, "Invalid firmware: less than 2 program headers\n"); 1260 return NULL; 1261 } 1262 1263 for (i = 0; i < ehdr->e_phnum; i++) { 1264 phdr = &phdrs[i]; 1265 1266 if (fw->size < phdr->p_offset + phdr->p_filesz) { 1267 dev_err(dev, "Firmware size (%zu) < expected offset (%u) + size (%u)\n", 1268 fw->size, phdr->p_offset, phdr->p_filesz); 1269 return NULL; 1270 } 1271 1272 if (phdr->p_type != PT_LOAD || !phdr->p_memsz) 1273 continue; 1274 1275 if (MI_PBT_PAGE_MODE_VALUE(phdr->p_flags) != MI_PBT_NON_PAGED_SEGMENT || 1276 MI_PBT_SEGMENT_TYPE_VALUE(phdr->p_flags) == MI_PBT_HASH_SEGMENT || 1277 MI_PBT_ACCESS_TYPE_VALUE(phdr->p_flags) == MI_PBT_NOTUSED_SEGMENT || 1278 MI_PBT_ACCESS_TYPE_VALUE(phdr->p_flags) == MI_PBT_SHARED_SEGMENT) 1279 continue; 1280 1281 if (phdr->p_filesz < sizeof(struct se_fw_hdr)) 1282 continue; 1283 1284 sefw = (struct se_fw_hdr *)(fw->data + phdr->p_offset); 1285 fw_size = le16_to_cpu(sefw->fw_size_in_items); 1286 fw_end = le16_to_cpu(sefw->fw_offset) + fw_size * sizeof(u32); 1287 cfg_idx_end = le16_to_cpu(sefw->cfg_idx_offset) + 1288 le16_to_cpu(sefw->cfg_size_in_items) * sizeof(u8); 1289 cfg_val_end = le16_to_cpu(sefw->cfg_val_offset) + 1290 le16_to_cpu(sefw->cfg_size_in_items) * sizeof(u32); 1291 1292 if (le32_to_cpu(sefw->magic) != SE_MAGIC_NUM || le32_to_cpu(sefw->version) != 1) 1293 continue; 1294 1295 if (le32_to_cpu(sefw->serial_protocol) != protocol) 1296 continue; 1297 1298 if (fw_size % 2 != 0) { 1299 fw_size++; 1300 sefw->fw_size_in_items = cpu_to_le16(fw_size); 1301 } 1302 1303 if (fw_size >= MAX_GENI_CFG_RAMn_CNT) { 1304 dev_err(dev, 1305 "Firmware size (%u) exceeds max allowed RAMn count (%u)\n", 1306 fw_size, MAX_GENI_CFG_RAMn_CNT); 1307 continue; 1308 } 1309 1310 if (fw_end > phdr->p_filesz || cfg_idx_end > phdr->p_filesz || 1311 cfg_val_end > phdr->p_filesz) { 1312 dev_err(dev, "Truncated or corrupt SE FW segment found at index %d\n", i); 1313 continue; 1314 } 1315 1316 return sefw; 1317 } 1318 1319 dev_err(dev, "Failed to get %s protocol firmware\n", protocol_name[protocol]); 1320 return NULL; 1321 } 1322 1323 /** 1324 * geni_configure_xfer_mode() - Set the transfer mode. 1325 * @se: Pointer to the concerned serial engine. 1326 * @mode: SE data transfer mode. 1327 * 1328 * Set the transfer mode to either FIFO or DMA according to the mode specified 1329 * by the protocol driver. 1330 * 1331 * Return: 0 if successful, otherwise return an error value. 1332 */ 1333 static int geni_configure_xfer_mode(struct geni_se *se, enum geni_se_xfer_mode mode) 1334 { 1335 /* Configure SE FIFO, DMA or GSI mode. */ 1336 switch (mode) { 1337 case GENI_GPI_DMA: 1338 geni_setbits32(se->base + SE_GENI_DMA_MODE_EN, GENI_DMA_MODE_EN); 1339 writel(0x0, se->base + SE_IRQ_EN); 1340 writel(DMA_RX_EVENT_EN | DMA_TX_EVENT_EN | GENI_M_EVENT_EN | GENI_S_EVENT_EN, 1341 se->base + SE_GSI_EVENT_EN); 1342 break; 1343 1344 case GENI_SE_FIFO: 1345 geni_clrbits32(se->base + SE_GENI_DMA_MODE_EN, GENI_DMA_MODE_EN); 1346 writel(DMA_RX_IRQ_EN | DMA_TX_IRQ_EN | GENI_M_IRQ_EN | GENI_S_IRQ_EN, 1347 se->base + SE_IRQ_EN); 1348 writel(0x0, se->base + SE_GSI_EVENT_EN); 1349 break; 1350 1351 case GENI_SE_DMA: 1352 geni_setbits32(se->base + SE_GENI_DMA_MODE_EN, GENI_DMA_MODE_EN); 1353 writel(DMA_RX_IRQ_EN | DMA_TX_IRQ_EN | GENI_M_IRQ_EN | GENI_S_IRQ_EN, 1354 se->base + SE_IRQ_EN); 1355 writel(0x0, se->base + SE_GSI_EVENT_EN); 1356 break; 1357 1358 default: 1359 dev_err(se->dev, "Invalid geni-se transfer mode: %d\n", mode); 1360 return -EINVAL; 1361 } 1362 return 0; 1363 } 1364 1365 /** 1366 * geni_enable_interrupts() - Enable interrupts. 1367 * @se: Pointer to the concerned serial engine. 1368 * 1369 * Enable the required interrupts during the firmware load process. 1370 */ 1371 static void geni_enable_interrupts(struct geni_se *se) 1372 { 1373 u32 val; 1374 1375 /* Enable required interrupts. */ 1376 writel(M_COMMON_GENI_M_IRQ_EN, se->base + SE_GENI_M_IRQ_EN); 1377 1378 val = S_CMD_OVERRUN_EN | S_ILLEGAL_CMD_EN | S_CMD_CANCEL_EN | S_CMD_ABORT_EN | 1379 S_GP_IRQ_0_EN | S_GP_IRQ_1_EN | S_GP_IRQ_2_EN | S_GP_IRQ_3_EN | 1380 S_RX_FIFO_WR_ERR_EN | S_RX_FIFO_RD_ERR_EN; 1381 writel(val, se->base + SE_GENI_S_IRQ_ENABLE); 1382 1383 /* DMA mode configuration. */ 1384 val = GENI_SE_DMA_RESET_DONE_EN | GENI_SE_DMA_AHB_ERR_EN | GENI_SE_DMA_DONE_EN; 1385 writel(val, se->base + SE_DMA_TX_IRQ_EN_SET); 1386 val = GENI_SE_DMA_FLUSH_DONE | GENI_SE_DMA_RESET_DONE_EN | GENI_SE_DMA_AHB_ERR_EN | 1387 GENI_SE_DMA_DONE_EN; 1388 writel(val, se->base + SE_DMA_RX_IRQ_EN_SET); 1389 } 1390 1391 /** 1392 * geni_write_fw_revision() - Write the firmware revision. 1393 * @se: Pointer to the concerned serial engine. 1394 * @serial_protocol: serial protocol type. 1395 * @fw_version: QUP firmware version. 1396 * 1397 * Write the firmware revision and protocol into the respective register. 1398 */ 1399 static void geni_write_fw_revision(struct geni_se *se, u16 serial_protocol, u16 fw_version) 1400 { 1401 u32 reg; 1402 1403 reg = FIELD_PREP(FW_REV_PROTOCOL_MSK, serial_protocol); 1404 reg |= FIELD_PREP(FW_REV_VERSION_MSK, fw_version); 1405 1406 writel(reg, se->base + SE_GENI_FW_REVISION); 1407 writel(reg, se->base + SE_GENI_S_FW_REVISION); 1408 } 1409 1410 /** 1411 * geni_load_se_fw() - Load Serial Engine specific firmware. 1412 * @se: Pointer to the concerned serial engine. 1413 * @fw: Pointer to the firmware structure. 1414 * @mode: SE data transfer mode. 1415 * @protocol: Protocol type to be used with the SE (e.g., UART, SPI, I2C). 1416 * 1417 * Load the protocol firmware into the IRAM of the Serial Engine. 1418 * 1419 * Return: 0 if successful, otherwise return an error value. 1420 */ 1421 static int geni_load_se_fw(struct geni_se *se, const struct firmware *fw, 1422 enum geni_se_xfer_mode mode, enum geni_se_protocol_type protocol) 1423 { 1424 const u32 *fw_data, *cfg_val_arr; 1425 const u8 *cfg_idx_arr; 1426 u32 i, reg_value; 1427 int ret; 1428 struct se_fw_hdr *hdr; 1429 1430 hdr = geni_find_protocol_fw(se->dev, fw, protocol); 1431 if (!hdr) 1432 return -EINVAL; 1433 1434 fw_data = (const u32 *)((u8 *)hdr + le16_to_cpu(hdr->fw_offset)); 1435 cfg_idx_arr = (const u8 *)hdr + le16_to_cpu(hdr->cfg_idx_offset); 1436 cfg_val_arr = (const u32 *)((u8 *)hdr + le16_to_cpu(hdr->cfg_val_offset)); 1437 1438 ret = geni_icc_set_bw(se); 1439 if (ret) 1440 return ret; 1441 1442 ret = geni_icc_enable(se); 1443 if (ret) 1444 return ret; 1445 1446 ret = geni_se_resources_on(se); 1447 if (ret) 1448 goto out_icc_disable; 1449 1450 /* 1451 * Disable high-priority interrupts until all currently executing 1452 * low-priority interrupts have been fully handled. 1453 */ 1454 geni_setbits32(se->wrapper->base + QUPV3_COMMON_CFG, FAST_SWITCH_TO_HIGH_DISABLE); 1455 1456 /* Set AHB_M_CLK_CGC_ON to indicate hardware controls se-wrapper cgc clock. */ 1457 geni_setbits32(se->wrapper->base + QUPV3_SE_AHB_M_CFG, AHB_M_CLK_CGC_ON); 1458 1459 /* Let hardware to control common cgc. */ 1460 geni_setbits32(se->wrapper->base + QUPV3_COMMON_CGC_CTRL, COMMON_CSR_SLV_CLK_CGC_ON); 1461 1462 /* 1463 * Setting individual bits in GENI_OUTPUT_CTRL activates corresponding output lines, 1464 * allowing the hardware to drive data as configured. 1465 */ 1466 writel(0x0, se->base + GENI_OUTPUT_CTRL); 1467 1468 /* Set SCLK and HCLK to program RAM */ 1469 geni_setbits32(se->base + SE_GENI_CGC_CTRL, PROG_RAM_SCLK_OFF | PROG_RAM_HCLK_OFF); 1470 writel(0x0, se->base + SE_GENI_CLK_CTRL); 1471 geni_clrbits32(se->base + SE_GENI_CGC_CTRL, PROG_RAM_SCLK_OFF | PROG_RAM_HCLK_OFF); 1472 1473 /* Enable required clocks for DMA CSR, TX and RX. */ 1474 reg_value = AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CLK_CGC_ON | 1475 DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON; 1476 geni_setbits32(se->base + SE_DMA_GENERAL_CFG, reg_value); 1477 1478 /* Let hardware control CGC by default. */ 1479 writel(DEFAULT_CGC_EN, se->base + SE_GENI_CGC_CTRL); 1480 1481 /* Set version of the configuration register part of firmware. */ 1482 writel(le16_to_cpu(hdr->cfg_version), se->base + SE_GENI_INIT_CFG_REVISION); 1483 writel(le16_to_cpu(hdr->cfg_version), se->base + SE_GENI_S_INIT_CFG_REVISION); 1484 1485 /* Configure GENI primitive table. */ 1486 for (i = 0; i < le16_to_cpu(hdr->cfg_size_in_items); i++) 1487 writel(cfg_val_arr[i], 1488 se->base + SE_GENI_CFG_REG0 + (cfg_idx_arr[i] * sizeof(u32))); 1489 1490 /* Configure condition for assertion of RX_RFR_WATERMARK condition. */ 1491 reg_value = geni_se_get_rx_fifo_depth(se); 1492 writel(reg_value - 2, se->base + SE_GENI_RX_RFR_WATERMARK_REG); 1493 1494 /* Let hardware control CGC */ 1495 geni_setbits32(se->base + GENI_OUTPUT_CTRL, DEFAULT_IO_OUTPUT_CTRL_MSK); 1496 1497 ret = geni_configure_xfer_mode(se, mode); 1498 if (ret) 1499 goto out_resources_off; 1500 1501 geni_enable_interrupts(se); 1502 1503 geni_write_fw_revision(se, le16_to_cpu(hdr->serial_protocol), le16_to_cpu(hdr->fw_version)); 1504 1505 /* Program RAM address space. */ 1506 memcpy_toio(se->base + SE_GENI_CFG_RAMN, fw_data, 1507 le16_to_cpu(hdr->fw_size_in_items) * sizeof(u32)); 1508 1509 /* Put default values on GENI's output pads. */ 1510 writel_relaxed(0x1, se->base + GENI_FORCE_DEFAULT_REG); 1511 1512 /* Toggle SCLK/HCLK from high to low to finalize RAM programming and apply config. */ 1513 geni_setbits32(se->base + SE_GENI_CGC_CTRL, PROG_RAM_SCLK_OFF | PROG_RAM_HCLK_OFF); 1514 geni_setbits32(se->base + SE_GENI_CLK_CTRL, SER_CLK_SEL); 1515 geni_clrbits32(se->base + SE_GENI_CGC_CTRL, PROG_RAM_SCLK_OFF | PROG_RAM_HCLK_OFF); 1516 1517 /* Serial engine DMA interface is enabled. */ 1518 geni_setbits32(se->base + SE_DMA_IF_EN, DMA_IF_EN); 1519 1520 /* Enable or disable FIFO interface of the serial engine. */ 1521 if (mode == GENI_SE_FIFO) 1522 geni_clrbits32(se->base + SE_FIFO_IF_DISABLE, FIFO_IF_DISABLE); 1523 else 1524 geni_setbits32(se->base + SE_FIFO_IF_DISABLE, FIFO_IF_DISABLE); 1525 1526 out_resources_off: 1527 geni_se_resources_off(se); 1528 1529 out_icc_disable: 1530 geni_icc_disable(se); 1531 return ret; 1532 } 1533 1534 /** 1535 * geni_load_se_firmware() - Load firmware for SE based on protocol 1536 * @se: Pointer to the concerned serial engine. 1537 * @protocol: Protocol type to be used with the SE (e.g., UART, SPI, I2C). 1538 * 1539 * Retrieves the firmware name from device properties and sets the transfer mode 1540 * (FIFO or GSI DMA) based on device tree configuration. Enforces FIFO mode for 1541 * UART protocol due to lack of GSI DMA support. Requests the firmware and loads 1542 * it into the SE. 1543 * 1544 * Return: 0 on success, negative error code on failure. 1545 */ 1546 int geni_load_se_firmware(struct geni_se *se, enum geni_se_protocol_type protocol) 1547 { 1548 const char *fw_name; 1549 const struct firmware *fw; 1550 enum geni_se_xfer_mode mode = GENI_SE_FIFO; 1551 int ret; 1552 1553 if (protocol >= ARRAY_SIZE(protocol_name)) { 1554 dev_err(se->dev, "Invalid geni-se protocol: %d", protocol); 1555 return -EINVAL; 1556 } 1557 1558 ret = device_property_read_string(se->wrapper->dev, "firmware-name", &fw_name); 1559 if (ret) { 1560 dev_err(se->dev, "Failed to read firmware-name property: %d\n", ret); 1561 return -EINVAL; 1562 } 1563 1564 if (of_property_read_bool(se->dev->of_node, "qcom,enable-gsi-dma")) 1565 mode = GENI_GPI_DMA; 1566 1567 /* GSI mode is not supported by the UART driver; therefore, setting FIFO mode */ 1568 if (protocol == GENI_SE_UART) 1569 mode = GENI_SE_FIFO; 1570 1571 ret = request_firmware(&fw, fw_name, se->dev); 1572 if (ret) { 1573 if (ret == -ENOENT) 1574 return -EPROBE_DEFER; 1575 1576 dev_err(se->dev, "Failed to request firmware '%s' for protocol %d: ret: %d\n", 1577 fw_name, protocol, ret); 1578 return ret; 1579 } 1580 1581 ret = geni_load_se_fw(se, fw, mode, protocol); 1582 release_firmware(fw); 1583 1584 if (ret) { 1585 dev_err(se->dev, "Failed to load SE firmware for protocol %d: ret: %d\n", 1586 protocol, ret); 1587 return ret; 1588 } 1589 1590 dev_dbg(se->dev, "Firmware load for %s protocol is successful for xfer mode: %d\n", 1591 protocol_name[protocol], mode); 1592 return 0; 1593 } 1594 EXPORT_SYMBOL_GPL(geni_load_se_firmware); 1595 1596 static int geni_se_probe(struct platform_device *pdev) 1597 { 1598 struct device *dev = &pdev->dev; 1599 struct geni_wrapper *wrapper; 1600 const struct geni_se_desc *desc; 1601 int ret; 1602 1603 wrapper = devm_kzalloc(dev, sizeof(*wrapper), GFP_KERNEL); 1604 if (!wrapper) 1605 return -ENOMEM; 1606 1607 wrapper->dev = dev; 1608 wrapper->base = devm_platform_ioremap_resource(pdev, 0); 1609 if (IS_ERR(wrapper->base)) 1610 return PTR_ERR(wrapper->base); 1611 1612 desc = device_get_match_data(&pdev->dev); 1613 1614 if (!has_acpi_companion(&pdev->dev) && desc->num_clks) { 1615 int i; 1616 1617 wrapper->num_clks = min_t(unsigned int, desc->num_clks, MAX_CLKS); 1618 1619 for (i = 0; i < wrapper->num_clks; ++i) 1620 wrapper->clks[i].id = desc->clks[i]; 1621 1622 ret = of_count_phandle_with_args(dev->of_node, "clocks", "#clock-cells"); 1623 if (ret < 0) { 1624 dev_err(dev, "invalid clocks property at %pOF\n", dev->of_node); 1625 return ret; 1626 } 1627 1628 if (ret < wrapper->num_clks) { 1629 dev_err(dev, "invalid clocks count at %pOF, expected %d entries\n", 1630 dev->of_node, wrapper->num_clks); 1631 return -EINVAL; 1632 } 1633 1634 ret = devm_clk_bulk_get(dev, wrapper->num_clks, wrapper->clks); 1635 if (ret) { 1636 dev_err(dev, "Err getting clks %d\n", ret); 1637 return ret; 1638 } 1639 } 1640 1641 dev_set_drvdata(dev, wrapper); 1642 dev_dbg(dev, "GENI SE Driver probed\n"); 1643 return devm_of_platform_populate(dev); 1644 } 1645 1646 static const char * const qup_clks[] = { 1647 "m-ahb", 1648 "s-ahb", 1649 }; 1650 1651 static const struct geni_se_desc qup_desc = { 1652 .clks = qup_clks, 1653 .num_clks = ARRAY_SIZE(qup_clks), 1654 }; 1655 1656 static const struct geni_se_desc sa8255p_qup_desc = {}; 1657 1658 static const char * const i2c_master_hub_clks[] = { 1659 "s-ahb", 1660 }; 1661 1662 static const struct geni_se_desc i2c_master_hub_desc = { 1663 .clks = i2c_master_hub_clks, 1664 .num_clks = ARRAY_SIZE(i2c_master_hub_clks), 1665 }; 1666 1667 static const struct of_device_id geni_se_dt_match[] = { 1668 { .compatible = "qcom,geni-se-qup", .data = &qup_desc }, 1669 { .compatible = "qcom,geni-se-i2c-master-hub", .data = &i2c_master_hub_desc }, 1670 { .compatible = "qcom,sa8255p-geni-se-qup", .data = &sa8255p_qup_desc }, 1671 {} 1672 }; 1673 MODULE_DEVICE_TABLE(of, geni_se_dt_match); 1674 1675 static struct platform_driver geni_se_driver = { 1676 .driver = { 1677 .name = "geni_se_qup", 1678 .of_match_table = geni_se_dt_match, 1679 }, 1680 .probe = geni_se_probe, 1681 }; 1682 module_platform_driver(geni_se_driver); 1683 1684 MODULE_DESCRIPTION("GENI Serial Engine Driver"); 1685 MODULE_LICENSE("GPL v2"); 1686