xref: /linux/drivers/soc/qcom/ocmem.c (revision a3a02a52bcfcbcc4a637d4b68bf1bc391c9fad02) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * The On Chip Memory (OCMEM) allocator allows various clients to allocate
4  * memory from OCMEM based on performance, latency and power requirements.
5  * This is typically used by the GPU, camera/video, and audio components on
6  * some Snapdragon SoCs.
7  *
8  * Copyright (C) 2019 Brian Masney <masneyb@onstation.org>
9  * Copyright (C) 2015 Red Hat. Author: Rob Clark <robdclark@gmail.com>
10  */
11 
12 #include <linux/bitfield.h>
13 #include <linux/cleanup.h>
14 #include <linux/clk.h>
15 #include <linux/io.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/of.h>
19 #include <linux/of_platform.h>
20 #include <linux/platform_device.h>
21 #include <linux/firmware/qcom/qcom_scm.h>
22 #include <linux/sizes.h>
23 #include <linux/slab.h>
24 #include <linux/types.h>
25 #include <soc/qcom/ocmem.h>
26 
27 enum region_mode {
28 	WIDE_MODE = 0x0,
29 	THIN_MODE,
30 	MODE_DEFAULT = WIDE_MODE,
31 };
32 
33 enum ocmem_macro_state {
34 	PASSTHROUGH = 0,
35 	PERI_ON = 1,
36 	CORE_ON = 2,
37 	CLK_OFF = 4,
38 };
39 
40 struct ocmem_region {
41 	bool interleaved;
42 	enum region_mode mode;
43 	unsigned int num_macros;
44 	enum ocmem_macro_state macro_state[4];
45 	unsigned long macro_size;
46 	unsigned long region_size;
47 };
48 
49 struct ocmem_config {
50 	uint8_t num_regions;
51 	unsigned long macro_size;
52 };
53 
54 struct ocmem {
55 	struct device *dev;
56 	const struct ocmem_config *config;
57 	struct resource *memory;
58 	void __iomem *mmio;
59 	struct clk *core_clk;
60 	struct clk *iface_clk;
61 	unsigned int num_ports;
62 	unsigned int num_macros;
63 	bool interleaved;
64 	struct ocmem_region *regions;
65 	unsigned long active_allocations;
66 };
67 
68 #define OCMEM_MIN_ALIGN				SZ_64K
69 #define OCMEM_MIN_ALLOC				SZ_64K
70 
71 #define OCMEM_REG_HW_VERSION			0x00000000
72 #define OCMEM_REG_HW_PROFILE			0x00000004
73 
74 #define OCMEM_REG_REGION_MODE_CTL		0x00001000
75 #define OCMEM_REGION_MODE_CTL_REG0_THIN		0x00000001
76 #define OCMEM_REGION_MODE_CTL_REG1_THIN		0x00000002
77 #define OCMEM_REGION_MODE_CTL_REG2_THIN		0x00000004
78 #define OCMEM_REGION_MODE_CTL_REG3_THIN		0x00000008
79 
80 #define OCMEM_REG_GFX_MPU_START			0x00001004
81 #define OCMEM_REG_GFX_MPU_END			0x00001008
82 
83 #define OCMEM_HW_VERSION_MAJOR(val)		FIELD_GET(GENMASK(31, 28), val)
84 #define OCMEM_HW_VERSION_MINOR(val)		FIELD_GET(GENMASK(27, 16), val)
85 #define OCMEM_HW_VERSION_STEP(val)		FIELD_GET(GENMASK(15, 0), val)
86 
87 #define OCMEM_HW_PROFILE_NUM_PORTS(val)		FIELD_GET(0x0000000f, (val))
88 #define OCMEM_HW_PROFILE_NUM_MACROS(val)	FIELD_GET(0x00003f00, (val))
89 
90 #define OCMEM_HW_PROFILE_LAST_REGN_HALFSIZE	0x00010000
91 #define OCMEM_HW_PROFILE_INTERLEAVING		0x00020000
92 #define OCMEM_REG_GEN_STATUS			0x0000000c
93 
94 #define OCMEM_REG_PSGSC_STATUS			0x00000038
95 #define OCMEM_REG_PSGSC_CTL(i0)			(0x0000003c + 0x1*(i0))
96 
97 #define OCMEM_PSGSC_CTL_MACRO0_MODE(val)	FIELD_PREP(0x00000007, (val))
98 #define OCMEM_PSGSC_CTL_MACRO1_MODE(val)	FIELD_PREP(0x00000070, (val))
99 #define OCMEM_PSGSC_CTL_MACRO2_MODE(val)	FIELD_PREP(0x00000700, (val))
100 #define OCMEM_PSGSC_CTL_MACRO3_MODE(val)	FIELD_PREP(0x00007000, (val))
101 
102 static inline void ocmem_write(struct ocmem *ocmem, u32 reg, u32 data)
103 {
104 	writel(data, ocmem->mmio + reg);
105 }
106 
107 static inline u32 ocmem_read(struct ocmem *ocmem, u32 reg)
108 {
109 	return readl(ocmem->mmio + reg);
110 }
111 
112 static void update_ocmem(struct ocmem *ocmem)
113 {
114 	uint32_t region_mode_ctrl = 0x0;
115 	int i;
116 
117 	if (!qcom_scm_ocmem_lock_available()) {
118 		for (i = 0; i < ocmem->config->num_regions; i++) {
119 			struct ocmem_region *region = &ocmem->regions[i];
120 
121 			if (region->mode == THIN_MODE)
122 				region_mode_ctrl |= BIT(i);
123 		}
124 
125 		dev_dbg(ocmem->dev, "ocmem_region_mode_control %x\n",
126 			region_mode_ctrl);
127 		ocmem_write(ocmem, OCMEM_REG_REGION_MODE_CTL, region_mode_ctrl);
128 	}
129 
130 	for (i = 0; i < ocmem->config->num_regions; i++) {
131 		struct ocmem_region *region = &ocmem->regions[i];
132 		u32 data;
133 
134 		data = OCMEM_PSGSC_CTL_MACRO0_MODE(region->macro_state[0]) |
135 			OCMEM_PSGSC_CTL_MACRO1_MODE(region->macro_state[1]) |
136 			OCMEM_PSGSC_CTL_MACRO2_MODE(region->macro_state[2]) |
137 			OCMEM_PSGSC_CTL_MACRO3_MODE(region->macro_state[3]);
138 
139 		ocmem_write(ocmem, OCMEM_REG_PSGSC_CTL(i), data);
140 	}
141 }
142 
143 static unsigned long phys_to_offset(struct ocmem *ocmem,
144 				    unsigned long addr)
145 {
146 	if (addr < ocmem->memory->start || addr >= ocmem->memory->end)
147 		return 0;
148 
149 	return addr - ocmem->memory->start;
150 }
151 
152 static unsigned long device_address(struct ocmem *ocmem,
153 				    enum ocmem_client client,
154 				    unsigned long addr)
155 {
156 	WARN_ON(client != OCMEM_GRAPHICS);
157 
158 	/* TODO: gpu uses phys_to_offset, but others do not.. */
159 	return phys_to_offset(ocmem, addr);
160 }
161 
162 static void update_range(struct ocmem *ocmem, struct ocmem_buf *buf,
163 			 enum ocmem_macro_state mstate, enum region_mode rmode)
164 {
165 	unsigned long offset = 0;
166 	int i, j;
167 
168 	for (i = 0; i < ocmem->config->num_regions; i++) {
169 		struct ocmem_region *region = &ocmem->regions[i];
170 
171 		if (buf->offset <= offset && offset < buf->offset + buf->len)
172 			region->mode = rmode;
173 
174 		for (j = 0; j < region->num_macros; j++) {
175 			if (buf->offset <= offset &&
176 			    offset < buf->offset + buf->len)
177 				region->macro_state[j] = mstate;
178 
179 			offset += region->macro_size;
180 		}
181 	}
182 
183 	update_ocmem(ocmem);
184 }
185 
186 struct ocmem *of_get_ocmem(struct device *dev)
187 {
188 	struct platform_device *pdev;
189 	struct device_node *devnode;
190 	struct ocmem *ocmem;
191 
192 	devnode = of_parse_phandle(dev->of_node, "sram", 0);
193 	if (!devnode || !devnode->parent) {
194 		dev_err(dev, "Cannot look up sram phandle\n");
195 		of_node_put(devnode);
196 		return ERR_PTR(-ENODEV);
197 	}
198 
199 	pdev = of_find_device_by_node(devnode->parent);
200 	if (!pdev) {
201 		dev_err(dev, "Cannot find device node %s\n", devnode->name);
202 		of_node_put(devnode);
203 		return ERR_PTR(-EPROBE_DEFER);
204 	}
205 	of_node_put(devnode);
206 
207 	ocmem = platform_get_drvdata(pdev);
208 	if (!ocmem) {
209 		dev_err(dev, "Cannot get ocmem\n");
210 		put_device(&pdev->dev);
211 		return ERR_PTR(-ENODEV);
212 	}
213 	return ocmem;
214 }
215 EXPORT_SYMBOL_GPL(of_get_ocmem);
216 
217 struct ocmem_buf *ocmem_allocate(struct ocmem *ocmem, enum ocmem_client client,
218 				 unsigned long size)
219 {
220 	int ret;
221 
222 	/* TODO: add support for other clients... */
223 	if (WARN_ON(client != OCMEM_GRAPHICS))
224 		return ERR_PTR(-ENODEV);
225 
226 	if (size < OCMEM_MIN_ALLOC || !IS_ALIGNED(size, OCMEM_MIN_ALIGN))
227 		return ERR_PTR(-EINVAL);
228 
229 	if (test_and_set_bit_lock(BIT(client), &ocmem->active_allocations))
230 		return ERR_PTR(-EBUSY);
231 
232 	struct ocmem_buf *buf __free(kfree) = kzalloc(sizeof(*buf), GFP_KERNEL);
233 	if (!buf) {
234 		ret = -ENOMEM;
235 		goto err_unlock;
236 	}
237 
238 	buf->offset = 0;
239 	buf->addr = device_address(ocmem, client, buf->offset);
240 	buf->len = size;
241 
242 	update_range(ocmem, buf, CORE_ON, WIDE_MODE);
243 
244 	if (qcom_scm_ocmem_lock_available()) {
245 		ret = qcom_scm_ocmem_lock(QCOM_SCM_OCMEM_GRAPHICS_ID,
246 					  buf->offset, buf->len, WIDE_MODE);
247 		if (ret) {
248 			dev_err(ocmem->dev, "could not lock: %d\n", ret);
249 			ret = -EINVAL;
250 			goto err_unlock;
251 		}
252 	} else {
253 		ocmem_write(ocmem, OCMEM_REG_GFX_MPU_START, buf->offset);
254 		ocmem_write(ocmem, OCMEM_REG_GFX_MPU_END,
255 			    buf->offset + buf->len);
256 	}
257 
258 	dev_dbg(ocmem->dev, "using %ldK of OCMEM at 0x%08lx for client %d\n",
259 		size / 1024, buf->addr, client);
260 
261 	return_ptr(buf);
262 
263 err_unlock:
264 	clear_bit_unlock(BIT(client), &ocmem->active_allocations);
265 
266 	return ERR_PTR(ret);
267 }
268 EXPORT_SYMBOL_GPL(ocmem_allocate);
269 
270 void ocmem_free(struct ocmem *ocmem, enum ocmem_client client,
271 		struct ocmem_buf *buf)
272 {
273 	/* TODO: add support for other clients... */
274 	if (WARN_ON(client != OCMEM_GRAPHICS))
275 		return;
276 
277 	update_range(ocmem, buf, CLK_OFF, MODE_DEFAULT);
278 
279 	if (qcom_scm_ocmem_lock_available()) {
280 		int ret;
281 
282 		ret = qcom_scm_ocmem_unlock(QCOM_SCM_OCMEM_GRAPHICS_ID,
283 					    buf->offset, buf->len);
284 		if (ret)
285 			dev_err(ocmem->dev, "could not unlock: %d\n", ret);
286 	} else {
287 		ocmem_write(ocmem, OCMEM_REG_GFX_MPU_START, 0x0);
288 		ocmem_write(ocmem, OCMEM_REG_GFX_MPU_END, 0x0);
289 	}
290 
291 	kfree(buf);
292 
293 	clear_bit_unlock(BIT(client), &ocmem->active_allocations);
294 }
295 EXPORT_SYMBOL_GPL(ocmem_free);
296 
297 static int ocmem_dev_probe(struct platform_device *pdev)
298 {
299 	struct device *dev = &pdev->dev;
300 	unsigned long reg, region_size;
301 	int i, j, ret, num_banks;
302 	struct ocmem *ocmem;
303 
304 	if (!qcom_scm_is_available())
305 		return -EPROBE_DEFER;
306 
307 	ocmem = devm_kzalloc(dev, sizeof(*ocmem), GFP_KERNEL);
308 	if (!ocmem)
309 		return -ENOMEM;
310 
311 	ocmem->dev = dev;
312 	ocmem->config = device_get_match_data(dev);
313 
314 	ocmem->core_clk = devm_clk_get(dev, "core");
315 	if (IS_ERR(ocmem->core_clk))
316 		return dev_err_probe(dev, PTR_ERR(ocmem->core_clk),
317 				     "Unable to get core clock\n");
318 
319 	ocmem->iface_clk = devm_clk_get_optional(dev, "iface");
320 	if (IS_ERR(ocmem->iface_clk))
321 		return dev_err_probe(dev, PTR_ERR(ocmem->iface_clk),
322 				     "Unable to get iface clock\n");
323 
324 	ocmem->mmio = devm_platform_ioremap_resource_byname(pdev, "ctrl");
325 	if (IS_ERR(ocmem->mmio))
326 		return dev_err_probe(&pdev->dev, PTR_ERR(ocmem->mmio),
327 				     "Failed to ioremap ocmem_ctrl resource\n");
328 
329 	ocmem->memory = platform_get_resource_byname(pdev, IORESOURCE_MEM,
330 						     "mem");
331 	if (!ocmem->memory) {
332 		dev_err(dev, "Could not get mem region\n");
333 		return -ENXIO;
334 	}
335 
336 	/* The core clock is synchronous with graphics */
337 	WARN_ON(clk_set_rate(ocmem->core_clk, 1000) < 0);
338 
339 	ret = clk_prepare_enable(ocmem->core_clk);
340 	if (ret)
341 		return dev_err_probe(ocmem->dev, ret, "Failed to enable core clock\n");
342 
343 	ret = clk_prepare_enable(ocmem->iface_clk);
344 	if (ret) {
345 		clk_disable_unprepare(ocmem->core_clk);
346 		return dev_err_probe(ocmem->dev, ret, "Failed to enable iface clock\n");
347 	}
348 
349 	if (qcom_scm_restore_sec_cfg_available()) {
350 		dev_dbg(dev, "configuring scm\n");
351 		ret = qcom_scm_restore_sec_cfg(QCOM_SCM_OCMEM_DEV_ID, 0);
352 		if (ret) {
353 			dev_err_probe(dev, ret, "Could not enable secure configuration\n");
354 			goto err_clk_disable;
355 		}
356 	}
357 
358 	reg = ocmem_read(ocmem, OCMEM_REG_HW_VERSION);
359 	dev_dbg(dev, "OCMEM hardware version: %lu.%lu.%lu\n",
360 		OCMEM_HW_VERSION_MAJOR(reg),
361 		OCMEM_HW_VERSION_MINOR(reg),
362 		OCMEM_HW_VERSION_STEP(reg));
363 
364 	reg = ocmem_read(ocmem, OCMEM_REG_HW_PROFILE);
365 	ocmem->num_ports = OCMEM_HW_PROFILE_NUM_PORTS(reg);
366 	ocmem->num_macros = OCMEM_HW_PROFILE_NUM_MACROS(reg);
367 	ocmem->interleaved = !!(reg & OCMEM_HW_PROFILE_INTERLEAVING);
368 
369 	num_banks = ocmem->num_ports / 2;
370 	region_size = ocmem->config->macro_size * num_banks;
371 
372 	dev_info(dev, "%u ports, %u regions, %u macros, %sinterleaved\n",
373 		 ocmem->num_ports, ocmem->config->num_regions,
374 		 ocmem->num_macros, ocmem->interleaved ? "" : "not ");
375 
376 	ocmem->regions = devm_kcalloc(dev, ocmem->config->num_regions,
377 				      sizeof(struct ocmem_region), GFP_KERNEL);
378 	if (!ocmem->regions) {
379 		ret = -ENOMEM;
380 		goto err_clk_disable;
381 	}
382 
383 	for (i = 0; i < ocmem->config->num_regions; i++) {
384 		struct ocmem_region *region = &ocmem->regions[i];
385 
386 		if (WARN_ON(num_banks > ARRAY_SIZE(region->macro_state))) {
387 			ret = -EINVAL;
388 			goto err_clk_disable;
389 		}
390 
391 		region->mode = MODE_DEFAULT;
392 		region->num_macros = num_banks;
393 
394 		if (i == (ocmem->config->num_regions - 1) &&
395 		    reg & OCMEM_HW_PROFILE_LAST_REGN_HALFSIZE) {
396 			region->macro_size = ocmem->config->macro_size / 2;
397 			region->region_size = region_size / 2;
398 		} else {
399 			region->macro_size = ocmem->config->macro_size;
400 			region->region_size = region_size;
401 		}
402 
403 		for (j = 0; j < ARRAY_SIZE(region->macro_state); j++)
404 			region->macro_state[j] = CLK_OFF;
405 	}
406 
407 	platform_set_drvdata(pdev, ocmem);
408 
409 	return 0;
410 
411 err_clk_disable:
412 	clk_disable_unprepare(ocmem->core_clk);
413 	clk_disable_unprepare(ocmem->iface_clk);
414 	return ret;
415 }
416 
417 static void ocmem_dev_remove(struct platform_device *pdev)
418 {
419 	struct ocmem *ocmem = platform_get_drvdata(pdev);
420 
421 	clk_disable_unprepare(ocmem->core_clk);
422 	clk_disable_unprepare(ocmem->iface_clk);
423 }
424 
425 static const struct ocmem_config ocmem_8226_config = {
426 	.num_regions = 1,
427 	.macro_size = SZ_128K,
428 };
429 
430 static const struct ocmem_config ocmem_8974_config = {
431 	.num_regions = 3,
432 	.macro_size = SZ_128K,
433 };
434 
435 static const struct of_device_id ocmem_of_match[] = {
436 	{ .compatible = "qcom,msm8226-ocmem", .data = &ocmem_8226_config },
437 	{ .compatible = "qcom,msm8974-ocmem", .data = &ocmem_8974_config },
438 	{ }
439 };
440 
441 MODULE_DEVICE_TABLE(of, ocmem_of_match);
442 
443 static struct platform_driver ocmem_driver = {
444 	.probe = ocmem_dev_probe,
445 	.remove_new = ocmem_dev_remove,
446 	.driver = {
447 		.name = "ocmem",
448 		.of_match_table = ocmem_of_match,
449 	},
450 };
451 
452 module_platform_driver(ocmem_driver);
453 
454 MODULE_DESCRIPTION("On Chip Memory (OCMEM) allocator for some Snapdragon SoCs");
455 MODULE_LICENSE("GPL v2");
456