xref: /linux/drivers/soc/qcom/ocmem.c (revision 4359a011e259a4608afc7fb3635370c9d4ba5943) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * The On Chip Memory (OCMEM) allocator allows various clients to allocate
4  * memory from OCMEM based on performance, latency and power requirements.
5  * This is typically used by the GPU, camera/video, and audio components on
6  * some Snapdragon SoCs.
7  *
8  * Copyright (C) 2019 Brian Masney <masneyb@onstation.org>
9  * Copyright (C) 2015 Red Hat. Author: Rob Clark <robdclark@gmail.com>
10  */
11 
12 #include <linux/bitfield.h>
13 #include <linux/clk.h>
14 #include <linux/io.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/of_device.h>
18 #include <linux/platform_device.h>
19 #include <linux/qcom_scm.h>
20 #include <linux/sizes.h>
21 #include <linux/slab.h>
22 #include <linux/types.h>
23 #include <soc/qcom/ocmem.h>
24 
25 enum region_mode {
26 	WIDE_MODE = 0x0,
27 	THIN_MODE,
28 	MODE_DEFAULT = WIDE_MODE,
29 };
30 
31 enum ocmem_macro_state {
32 	PASSTHROUGH = 0,
33 	PERI_ON = 1,
34 	CORE_ON = 2,
35 	CLK_OFF = 4,
36 };
37 
38 struct ocmem_region {
39 	bool interleaved;
40 	enum region_mode mode;
41 	unsigned int num_macros;
42 	enum ocmem_macro_state macro_state[4];
43 	unsigned long macro_size;
44 	unsigned long region_size;
45 };
46 
47 struct ocmem_config {
48 	uint8_t num_regions;
49 	unsigned long macro_size;
50 };
51 
52 struct ocmem {
53 	struct device *dev;
54 	const struct ocmem_config *config;
55 	struct resource *memory;
56 	void __iomem *mmio;
57 	unsigned int num_ports;
58 	unsigned int num_macros;
59 	bool interleaved;
60 	struct ocmem_region *regions;
61 	unsigned long active_allocations;
62 };
63 
64 #define OCMEM_MIN_ALIGN				SZ_64K
65 #define OCMEM_MIN_ALLOC				SZ_64K
66 
67 #define OCMEM_REG_HW_VERSION			0x00000000
68 #define OCMEM_REG_HW_PROFILE			0x00000004
69 
70 #define OCMEM_REG_REGION_MODE_CTL		0x00001000
71 #define OCMEM_REGION_MODE_CTL_REG0_THIN		0x00000001
72 #define OCMEM_REGION_MODE_CTL_REG1_THIN		0x00000002
73 #define OCMEM_REGION_MODE_CTL_REG2_THIN		0x00000004
74 #define OCMEM_REGION_MODE_CTL_REG3_THIN		0x00000008
75 
76 #define OCMEM_REG_GFX_MPU_START			0x00001004
77 #define OCMEM_REG_GFX_MPU_END			0x00001008
78 
79 #define OCMEM_HW_PROFILE_NUM_PORTS(val)		FIELD_PREP(0x0000000f, (val))
80 #define OCMEM_HW_PROFILE_NUM_MACROS(val)	FIELD_PREP(0x00003f00, (val))
81 
82 #define OCMEM_HW_PROFILE_LAST_REGN_HALFSIZE	0x00010000
83 #define OCMEM_HW_PROFILE_INTERLEAVING		0x00020000
84 #define OCMEM_REG_GEN_STATUS			0x0000000c
85 
86 #define OCMEM_REG_PSGSC_STATUS			0x00000038
87 #define OCMEM_REG_PSGSC_CTL(i0)			(0x0000003c + 0x1*(i0))
88 
89 #define OCMEM_PSGSC_CTL_MACRO0_MODE(val)	FIELD_PREP(0x00000007, (val))
90 #define OCMEM_PSGSC_CTL_MACRO1_MODE(val)	FIELD_PREP(0x00000070, (val))
91 #define OCMEM_PSGSC_CTL_MACRO2_MODE(val)	FIELD_PREP(0x00000700, (val))
92 #define OCMEM_PSGSC_CTL_MACRO3_MODE(val)	FIELD_PREP(0x00007000, (val))
93 
94 #define OCMEM_CLK_CORE_IDX			0
95 static struct clk_bulk_data ocmem_clks[] = {
96 	{
97 		.id = "core",
98 	},
99 	{
100 		.id = "iface",
101 	},
102 };
103 
104 static inline void ocmem_write(struct ocmem *ocmem, u32 reg, u32 data)
105 {
106 	writel(data, ocmem->mmio + reg);
107 }
108 
109 static inline u32 ocmem_read(struct ocmem *ocmem, u32 reg)
110 {
111 	return readl(ocmem->mmio + reg);
112 }
113 
114 static void update_ocmem(struct ocmem *ocmem)
115 {
116 	uint32_t region_mode_ctrl = 0x0;
117 	int i;
118 
119 	if (!qcom_scm_ocmem_lock_available()) {
120 		for (i = 0; i < ocmem->config->num_regions; i++) {
121 			struct ocmem_region *region = &ocmem->regions[i];
122 
123 			if (region->mode == THIN_MODE)
124 				region_mode_ctrl |= BIT(i);
125 		}
126 
127 		dev_dbg(ocmem->dev, "ocmem_region_mode_control %x\n",
128 			region_mode_ctrl);
129 		ocmem_write(ocmem, OCMEM_REG_REGION_MODE_CTL, region_mode_ctrl);
130 	}
131 
132 	for (i = 0; i < ocmem->config->num_regions; i++) {
133 		struct ocmem_region *region = &ocmem->regions[i];
134 		u32 data;
135 
136 		data = OCMEM_PSGSC_CTL_MACRO0_MODE(region->macro_state[0]) |
137 			OCMEM_PSGSC_CTL_MACRO1_MODE(region->macro_state[1]) |
138 			OCMEM_PSGSC_CTL_MACRO2_MODE(region->macro_state[2]) |
139 			OCMEM_PSGSC_CTL_MACRO3_MODE(region->macro_state[3]);
140 
141 		ocmem_write(ocmem, OCMEM_REG_PSGSC_CTL(i), data);
142 	}
143 }
144 
145 static unsigned long phys_to_offset(struct ocmem *ocmem,
146 				    unsigned long addr)
147 {
148 	if (addr < ocmem->memory->start || addr >= ocmem->memory->end)
149 		return 0;
150 
151 	return addr - ocmem->memory->start;
152 }
153 
154 static unsigned long device_address(struct ocmem *ocmem,
155 				    enum ocmem_client client,
156 				    unsigned long addr)
157 {
158 	WARN_ON(client != OCMEM_GRAPHICS);
159 
160 	/* TODO: gpu uses phys_to_offset, but others do not.. */
161 	return phys_to_offset(ocmem, addr);
162 }
163 
164 static void update_range(struct ocmem *ocmem, struct ocmem_buf *buf,
165 			 enum ocmem_macro_state mstate, enum region_mode rmode)
166 {
167 	unsigned long offset = 0;
168 	int i, j;
169 
170 	for (i = 0; i < ocmem->config->num_regions; i++) {
171 		struct ocmem_region *region = &ocmem->regions[i];
172 
173 		if (buf->offset <= offset && offset < buf->offset + buf->len)
174 			region->mode = rmode;
175 
176 		for (j = 0; j < region->num_macros; j++) {
177 			if (buf->offset <= offset &&
178 			    offset < buf->offset + buf->len)
179 				region->macro_state[j] = mstate;
180 
181 			offset += region->macro_size;
182 		}
183 	}
184 
185 	update_ocmem(ocmem);
186 }
187 
188 struct ocmem *of_get_ocmem(struct device *dev)
189 {
190 	struct platform_device *pdev;
191 	struct device_node *devnode;
192 	struct ocmem *ocmem;
193 
194 	devnode = of_parse_phandle(dev->of_node, "sram", 0);
195 	if (!devnode || !devnode->parent) {
196 		dev_err(dev, "Cannot look up sram phandle\n");
197 		of_node_put(devnode);
198 		return ERR_PTR(-ENODEV);
199 	}
200 
201 	pdev = of_find_device_by_node(devnode->parent);
202 	if (!pdev) {
203 		dev_err(dev, "Cannot find device node %s\n", devnode->name);
204 		of_node_put(devnode);
205 		return ERR_PTR(-EPROBE_DEFER);
206 	}
207 	of_node_put(devnode);
208 
209 	ocmem = platform_get_drvdata(pdev);
210 	if (!ocmem) {
211 		dev_err(dev, "Cannot get ocmem\n");
212 		put_device(&pdev->dev);
213 		return ERR_PTR(-ENODEV);
214 	}
215 	return ocmem;
216 }
217 EXPORT_SYMBOL(of_get_ocmem);
218 
219 struct ocmem_buf *ocmem_allocate(struct ocmem *ocmem, enum ocmem_client client,
220 				 unsigned long size)
221 {
222 	struct ocmem_buf *buf;
223 	int ret;
224 
225 	/* TODO: add support for other clients... */
226 	if (WARN_ON(client != OCMEM_GRAPHICS))
227 		return ERR_PTR(-ENODEV);
228 
229 	if (size < OCMEM_MIN_ALLOC || !IS_ALIGNED(size, OCMEM_MIN_ALIGN))
230 		return ERR_PTR(-EINVAL);
231 
232 	if (test_and_set_bit_lock(BIT(client), &ocmem->active_allocations))
233 		return ERR_PTR(-EBUSY);
234 
235 	buf = kzalloc(sizeof(*buf), GFP_KERNEL);
236 	if (!buf) {
237 		ret = -ENOMEM;
238 		goto err_unlock;
239 	}
240 
241 	buf->offset = 0;
242 	buf->addr = device_address(ocmem, client, buf->offset);
243 	buf->len = size;
244 
245 	update_range(ocmem, buf, CORE_ON, WIDE_MODE);
246 
247 	if (qcom_scm_ocmem_lock_available()) {
248 		ret = qcom_scm_ocmem_lock(QCOM_SCM_OCMEM_GRAPHICS_ID,
249 					  buf->offset, buf->len, WIDE_MODE);
250 		if (ret) {
251 			dev_err(ocmem->dev, "could not lock: %d\n", ret);
252 			ret = -EINVAL;
253 			goto err_kfree;
254 		}
255 	} else {
256 		ocmem_write(ocmem, OCMEM_REG_GFX_MPU_START, buf->offset);
257 		ocmem_write(ocmem, OCMEM_REG_GFX_MPU_END,
258 			    buf->offset + buf->len);
259 	}
260 
261 	dev_dbg(ocmem->dev, "using %ldK of OCMEM at 0x%08lx for client %d\n",
262 		size / 1024, buf->addr, client);
263 
264 	return buf;
265 
266 err_kfree:
267 	kfree(buf);
268 err_unlock:
269 	clear_bit_unlock(BIT(client), &ocmem->active_allocations);
270 
271 	return ERR_PTR(ret);
272 }
273 EXPORT_SYMBOL(ocmem_allocate);
274 
275 void ocmem_free(struct ocmem *ocmem, enum ocmem_client client,
276 		struct ocmem_buf *buf)
277 {
278 	/* TODO: add support for other clients... */
279 	if (WARN_ON(client != OCMEM_GRAPHICS))
280 		return;
281 
282 	update_range(ocmem, buf, CLK_OFF, MODE_DEFAULT);
283 
284 	if (qcom_scm_ocmem_lock_available()) {
285 		int ret;
286 
287 		ret = qcom_scm_ocmem_unlock(QCOM_SCM_OCMEM_GRAPHICS_ID,
288 					    buf->offset, buf->len);
289 		if (ret)
290 			dev_err(ocmem->dev, "could not unlock: %d\n", ret);
291 	} else {
292 		ocmem_write(ocmem, OCMEM_REG_GFX_MPU_START, 0x0);
293 		ocmem_write(ocmem, OCMEM_REG_GFX_MPU_END, 0x0);
294 	}
295 
296 	kfree(buf);
297 
298 	clear_bit_unlock(BIT(client), &ocmem->active_allocations);
299 }
300 EXPORT_SYMBOL(ocmem_free);
301 
302 static int ocmem_dev_probe(struct platform_device *pdev)
303 {
304 	struct device *dev = &pdev->dev;
305 	unsigned long reg, region_size;
306 	int i, j, ret, num_banks;
307 	struct ocmem *ocmem;
308 
309 	if (!qcom_scm_is_available())
310 		return -EPROBE_DEFER;
311 
312 	ocmem = devm_kzalloc(dev, sizeof(*ocmem), GFP_KERNEL);
313 	if (!ocmem)
314 		return -ENOMEM;
315 
316 	ocmem->dev = dev;
317 	ocmem->config = device_get_match_data(dev);
318 
319 	ret = devm_clk_bulk_get(dev, ARRAY_SIZE(ocmem_clks), ocmem_clks);
320 	if (ret) {
321 		if (ret != -EPROBE_DEFER)
322 			dev_err(dev, "Unable to get clocks\n");
323 
324 		return ret;
325 	}
326 
327 	ocmem->mmio = devm_platform_ioremap_resource_byname(pdev, "ctrl");
328 	if (IS_ERR(ocmem->mmio)) {
329 		dev_err(&pdev->dev, "Failed to ioremap ocmem_ctrl resource\n");
330 		return PTR_ERR(ocmem->mmio);
331 	}
332 
333 	ocmem->memory = platform_get_resource_byname(pdev, IORESOURCE_MEM,
334 						     "mem");
335 	if (!ocmem->memory) {
336 		dev_err(dev, "Could not get mem region\n");
337 		return -ENXIO;
338 	}
339 
340 	/* The core clock is synchronous with graphics */
341 	WARN_ON(clk_set_rate(ocmem_clks[OCMEM_CLK_CORE_IDX].clk, 1000) < 0);
342 
343 	ret = clk_bulk_prepare_enable(ARRAY_SIZE(ocmem_clks), ocmem_clks);
344 	if (ret) {
345 		dev_info(ocmem->dev, "Failed to enable clocks\n");
346 		return ret;
347 	}
348 
349 	if (qcom_scm_restore_sec_cfg_available()) {
350 		dev_dbg(dev, "configuring scm\n");
351 		ret = qcom_scm_restore_sec_cfg(QCOM_SCM_OCMEM_DEV_ID, 0);
352 		if (ret) {
353 			dev_err(dev, "Could not enable secure configuration\n");
354 			goto err_clk_disable;
355 		}
356 	}
357 
358 	reg = ocmem_read(ocmem, OCMEM_REG_HW_PROFILE);
359 	ocmem->num_ports = OCMEM_HW_PROFILE_NUM_PORTS(reg);
360 	ocmem->num_macros = OCMEM_HW_PROFILE_NUM_MACROS(reg);
361 	ocmem->interleaved = !!(reg & OCMEM_HW_PROFILE_INTERLEAVING);
362 
363 	num_banks = ocmem->num_ports / 2;
364 	region_size = ocmem->config->macro_size * num_banks;
365 
366 	dev_info(dev, "%u ports, %u regions, %u macros, %sinterleaved\n",
367 		 ocmem->num_ports, ocmem->config->num_regions,
368 		 ocmem->num_macros, ocmem->interleaved ? "" : "not ");
369 
370 	ocmem->regions = devm_kcalloc(dev, ocmem->config->num_regions,
371 				      sizeof(struct ocmem_region), GFP_KERNEL);
372 	if (!ocmem->regions) {
373 		ret = -ENOMEM;
374 		goto err_clk_disable;
375 	}
376 
377 	for (i = 0; i < ocmem->config->num_regions; i++) {
378 		struct ocmem_region *region = &ocmem->regions[i];
379 
380 		if (WARN_ON(num_banks > ARRAY_SIZE(region->macro_state))) {
381 			ret = -EINVAL;
382 			goto err_clk_disable;
383 		}
384 
385 		region->mode = MODE_DEFAULT;
386 		region->num_macros = num_banks;
387 
388 		if (i == (ocmem->config->num_regions - 1) &&
389 		    reg & OCMEM_HW_PROFILE_LAST_REGN_HALFSIZE) {
390 			region->macro_size = ocmem->config->macro_size / 2;
391 			region->region_size = region_size / 2;
392 		} else {
393 			region->macro_size = ocmem->config->macro_size;
394 			region->region_size = region_size;
395 		}
396 
397 		for (j = 0; j < ARRAY_SIZE(region->macro_state); j++)
398 			region->macro_state[j] = CLK_OFF;
399 	}
400 
401 	platform_set_drvdata(pdev, ocmem);
402 
403 	return 0;
404 
405 err_clk_disable:
406 	clk_bulk_disable_unprepare(ARRAY_SIZE(ocmem_clks), ocmem_clks);
407 	return ret;
408 }
409 
410 static int ocmem_dev_remove(struct platform_device *pdev)
411 {
412 	clk_bulk_disable_unprepare(ARRAY_SIZE(ocmem_clks), ocmem_clks);
413 
414 	return 0;
415 }
416 
417 static const struct ocmem_config ocmem_8974_config = {
418 	.num_regions = 3,
419 	.macro_size = SZ_128K,
420 };
421 
422 static const struct of_device_id ocmem_of_match[] = {
423 	{ .compatible = "qcom,msm8974-ocmem", .data = &ocmem_8974_config },
424 	{ }
425 };
426 
427 MODULE_DEVICE_TABLE(of, ocmem_of_match);
428 
429 static struct platform_driver ocmem_driver = {
430 	.probe = ocmem_dev_probe,
431 	.remove = ocmem_dev_remove,
432 	.driver = {
433 		.name = "ocmem",
434 		.of_match_table = ocmem_of_match,
435 	},
436 };
437 
438 module_platform_driver(ocmem_driver);
439 
440 MODULE_DESCRIPTION("On Chip Memory (OCMEM) allocator for some Snapdragon SoCs");
441 MODULE_LICENSE("GPL v2");
442