xref: /linux/drivers/soc/qcom/llcc-qcom.c (revision 576d7fed09c7edbae7600f29a8a3ed6c1ead904f)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4  *
5  */
6 
7 #include <linux/bitfield.h>
8 #include <linux/bitmap.h>
9 #include <linux/bitops.h>
10 #include <linux/device.h>
11 #include <linux/io.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/mutex.h>
15 #include <linux/nvmem-consumer.h>
16 #include <linux/of.h>
17 #include <linux/regmap.h>
18 #include <linux/sizes.h>
19 #include <linux/slab.h>
20 #include <linux/soc/qcom/llcc-qcom.h>
21 
22 #define ACTIVATE                      BIT(0)
23 #define DEACTIVATE                    BIT(1)
24 #define ACT_CLEAR                     BIT(0)
25 #define ACT_COMPLETE                  BIT(4)
26 #define ACT_CTRL_OPCODE_ACTIVATE      BIT(0)
27 #define ACT_CTRL_OPCODE_DEACTIVATE    BIT(1)
28 #define ACT_CTRL_ACT_TRIG             BIT(0)
29 #define ACT_CTRL_OPCODE_SHIFT         0x01
30 #define ATTR1_PROBE_TARGET_WAYS_SHIFT 0x02
31 #define ATTR1_FIXED_SIZE_SHIFT        0x03
32 #define ATTR1_PRIORITY_SHIFT          0x04
33 #define ATTR1_MAX_CAP_SHIFT           0x10
34 #define ATTR0_RES_WAYS_MASK           GENMASK(15, 0)
35 #define ATTR0_BONUS_WAYS_MASK         GENMASK(31, 16)
36 #define ATTR0_BONUS_WAYS_SHIFT        0x10
37 #define LLCC_STATUS_READ_DELAY        100
38 
39 #define CACHE_LINE_SIZE_SHIFT         6
40 
41 #define LLCC_LB_CNT_MASK              GENMASK(31, 28)
42 #define LLCC_LB_CNT_SHIFT             28
43 
44 #define MAX_CAP_TO_BYTES(n)           (n * SZ_1K)
45 #define LLCC_TRP_ACT_CTRLn(n)         (n * SZ_4K)
46 #define LLCC_TRP_ACT_CLEARn(n)        (8 + n * SZ_4K)
47 #define LLCC_TRP_STATUSn(n)           (4 + n * SZ_4K)
48 #define LLCC_TRP_ATTR0_CFGn(n)        (0x21000 + SZ_8 * n)
49 #define LLCC_TRP_ATTR1_CFGn(n)        (0x21004 + SZ_8 * n)
50 #define LLCC_TRP_ATTR2_CFGn(n)        (0x21100 + SZ_8 * n)
51 
52 #define LLCC_TRP_SCID_DIS_CAP_ALLOC   0x21f00
53 #define LLCC_TRP_PCB_ACT              0x21f04
54 #define LLCC_TRP_ALGO_CFG1	      0x21f0c
55 #define LLCC_TRP_ALGO_CFG2	      0x21f10
56 #define LLCC_TRP_ALGO_CFG3	      0x21f14
57 #define LLCC_TRP_ALGO_CFG4	      0x21f18
58 #define LLCC_TRP_ALGO_CFG5	      0x21f1c
59 #define LLCC_TRP_WRSC_EN              0x21f20
60 #define LLCC_TRP_ALGO_CFG6	      0x21f24
61 #define LLCC_TRP_ALGO_CFG7	      0x21f28
62 #define LLCC_TRP_WRSC_CACHEABLE_EN    0x21f2c
63 #define LLCC_TRP_ALGO_CFG8	      0x21f30
64 
65 #define LLCC_VERSION_2_0_0_0          0x02000000
66 #define LLCC_VERSION_2_1_0_0          0x02010000
67 #define LLCC_VERSION_4_1_0_0          0x04010000
68 
69 /**
70  * struct llcc_slice_config - Data associated with the llcc slice
71  * @usecase_id: Unique id for the client's use case
72  * @slice_id: llcc slice id for each client
73  * @max_cap: The maximum capacity of the cache slice provided in KB
74  * @priority: Priority of the client used to select victim line for replacement
75  * @fixed_size: Boolean indicating if the slice has a fixed capacity
76  * @bonus_ways: Bonus ways are additional ways to be used for any slice,
77  *		if client ends up using more than reserved cache ways. Bonus
78  *		ways are allocated only if they are not reserved for some
79  *		other client.
80  * @res_ways: Reserved ways for the cache slice, the reserved ways cannot
81  *		be used by any other client than the one its assigned to.
82  * @cache_mode: Each slice operates as a cache, this controls the mode of the
83  *             slice: normal or TCM(Tightly Coupled Memory)
84  * @probe_target_ways: Determines what ways to probe for access hit. When
85  *                    configured to 1 only bonus and reserved ways are probed.
86  *                    When configured to 0 all ways in llcc are probed.
87  * @dis_cap_alloc: Disable capacity based allocation for a client
88  * @retain_on_pc: If this bit is set and client has maintained active vote
89  *               then the ways assigned to this client are not flushed on power
90  *               collapse.
91  * @activate_on_init: Activate the slice immediately after it is programmed
92  * @write_scid_en: Bit enables write cache support for a given scid.
93  * @write_scid_cacheable_en: Enables write cache cacheable support for a
94  *			     given scid (not supported on v2 or older hardware).
95  */
96 struct llcc_slice_config {
97 	u32 usecase_id;
98 	u32 slice_id;
99 	u32 max_cap;
100 	u32 priority;
101 	bool fixed_size;
102 	u32 bonus_ways;
103 	u32 res_ways;
104 	u32 cache_mode;
105 	u32 probe_target_ways;
106 	bool dis_cap_alloc;
107 	bool retain_on_pc;
108 	bool activate_on_init;
109 	bool write_scid_en;
110 	bool write_scid_cacheable_en;
111 	bool stale_en;
112 	bool stale_cap_en;
113 	bool mru_uncap_en;
114 	bool mru_rollover;
115 	bool alloc_oneway_en;
116 	bool ovcap_en;
117 	bool ovcap_prio;
118 	bool vict_prio;
119 };
120 
121 struct qcom_llcc_config {
122 	const struct llcc_slice_config *sct_data;
123 	const u32 *reg_offset;
124 	const struct llcc_edac_reg_offset *edac_reg_offset;
125 	int size;
126 	bool need_llcc_cfg;
127 	bool no_edac;
128 };
129 
130 struct qcom_sct_config {
131 	const struct qcom_llcc_config *llcc_config;
132 	int num_config;
133 };
134 
135 enum llcc_reg_offset {
136 	LLCC_COMMON_HW_INFO,
137 	LLCC_COMMON_STATUS0,
138 };
139 
140 static const struct llcc_slice_config sc7180_data[] =  {
141 	{ LLCC_CPUSS,    1,  256, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 1 },
142 	{ LLCC_MDM,      8,  128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
143 	{ LLCC_GPUHTW,   11, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
144 	{ LLCC_GPU,      12, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
145 };
146 
147 static const struct llcc_slice_config sc7280_data[] =  {
148 	{ LLCC_CPUSS,    1,  768, 1, 0, 0x3f, 0x0, 0, 0, 0, 1, 1, 0},
149 	{ LLCC_MDMHPGRW, 7,  512, 2, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
150 	{ LLCC_CMPT,     10, 768, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
151 	{ LLCC_GPUHTW,   11, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
152 	{ LLCC_GPU,      12, 512, 1, 0, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
153 	{ LLCC_MMUHWT,   13, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 0, 1, 0},
154 	{ LLCC_MDMPNG,   21, 768, 0, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
155 	{ LLCC_WLHW,     24, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
156 	{ LLCC_MODPE,    29, 64,  1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
157 };
158 
159 static const struct llcc_slice_config sc8180x_data[] = {
160 	{ LLCC_CPUSS,    1, 6144,  1, 1, 0xfff, 0x0,   0, 0, 0, 1, 1 },
161 	{ LLCC_VIDSC0,   2, 512,   2, 1, 0xfff, 0x0,   0, 0, 0, 1, 0 },
162 	{ LLCC_VIDSC1,   3, 512,   2, 1, 0xfff, 0x0,   0, 0, 0, 1, 0 },
163 	{ LLCC_AUDIO,    6, 1024,  1, 1, 0xfff, 0x0,   0, 0, 0, 1, 0 },
164 	{ LLCC_MDMHPGRW, 7, 3072,  1, 1, 0x3ff, 0xc00, 0, 0, 0, 1, 0 },
165 	{ LLCC_MDM,      8, 3072,  1, 1, 0xfff, 0x0,   0, 0, 0, 1, 0 },
166 	{ LLCC_MODHW,    9, 1024,  1, 1, 0xfff, 0x0,   0, 0, 0, 1, 0 },
167 	{ LLCC_CMPT,     10, 6144, 1, 1, 0xfff, 0x0,   0, 0, 0, 1, 0 },
168 	{ LLCC_GPUHTW,   11, 1024, 1, 1, 0xfff, 0x0,   0, 0, 0, 1, 0 },
169 	{ LLCC_GPU,      12, 5120, 1, 1, 0xfff, 0x0,   0, 0, 0, 1, 0 },
170 	{ LLCC_MMUHWT,   13, 1024, 1, 1, 0xfff, 0x0,   0, 0, 0, 0, 1 },
171 	{ LLCC_CMPTDMA,  15, 6144, 1, 1, 0xfff, 0x0,   0, 0, 0, 1, 0 },
172 	{ LLCC_DISP,     16, 6144, 1, 1, 0xfff, 0x0,   0, 0, 0, 1, 0 },
173 	{ LLCC_VIDFW,    17, 1024, 1, 1, 0xfff, 0x0,   0, 0, 0, 1, 0 },
174 	{ LLCC_MDMHPFX,  20, 1024, 2, 1, 0xfff, 0x0,   0, 0, 0, 1, 0 },
175 	{ LLCC_MDMPNG,   21, 1024, 0, 1, 0xc,   0x0,   0, 0, 0, 1, 0 },
176 	{ LLCC_AUDHW,    22, 1024, 1, 1, 0xfff, 0x0,   0, 0, 0, 1, 0 },
177 	{ LLCC_NPU,      23, 6144, 1, 1, 0xfff, 0x0,   0, 0, 0, 1, 0 },
178 	{ LLCC_WLHW,     24, 6144, 1, 1, 0xfff, 0x0,   0, 0, 0, 1, 0 },
179 	{ LLCC_MODPE,    29, 512,  1, 1, 0xc,   0x0,   0, 0, 0, 1, 0 },
180 	{ LLCC_APTCM,    30, 512,  3, 1, 0x0,   0x1,   1, 0, 0, 1, 0 },
181 	{ LLCC_WRCACHE,  31, 128,  1, 1, 0xfff, 0x0,   0, 0, 0, 0, 0 },
182 };
183 
184 static const struct llcc_slice_config sc8280xp_data[] = {
185 	{ LLCC_CPUSS,    1,  6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 },
186 	{ LLCC_VIDSC0,   2,  512,  3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
187 	{ LLCC_AUDIO,    6,  1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 },
188 	{ LLCC_CMPT,     10, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 },
189 	{ LLCC_GPUHTW,   11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
190 	{ LLCC_GPU,      12, 4096, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 1 },
191 	{ LLCC_MMUHWT,   13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
192 	{ LLCC_DISP,     16, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
193 	{ LLCC_AUDHW,    22, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
194 	{ LLCC_ECC,      26, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
195 	{ LLCC_CVP,      28, 512,  3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
196 	{ LLCC_APTCM,    30, 1024, 3, 1, 0x0,   0x1, 1, 0, 0, 1, 0, 0 },
197 	{ LLCC_WRCACHE,  31, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
198 	{ LLCC_CVPFW,    17, 512,  1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
199 	{ LLCC_CPUSS1,   3, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
200 	{ LLCC_CPUHWT,   5, 512,  1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
201 };
202 
203 static const struct llcc_slice_config sdm845_data[] =  {
204 	{ LLCC_CPUSS,    1,  2816, 1, 0, 0xffc, 0x2,   0, 0, 1, 1, 1 },
205 	{ LLCC_VIDSC0,   2,  512,  2, 1, 0x0,   0x0f0, 0, 0, 1, 1, 0 },
206 	{ LLCC_VIDSC1,   3,  512,  2, 1, 0x0,   0x0f0, 0, 0, 1, 1, 0 },
207 	{ LLCC_ROTATOR,  4,  563,  2, 1, 0x0,   0x00e, 2, 0, 1, 1, 0 },
208 	{ LLCC_VOICE,    5,  2816, 1, 0, 0xffc, 0x2,   0, 0, 1, 1, 0 },
209 	{ LLCC_AUDIO,    6,  2816, 1, 0, 0xffc, 0x2,   0, 0, 1, 1, 0 },
210 	{ LLCC_MDMHPGRW, 7,  1024, 2, 0, 0xfc,  0xf00, 0, 0, 1, 1, 0 },
211 	{ LLCC_MDM,      8,  2816, 1, 0, 0xffc, 0x2,   0, 0, 1, 1, 0 },
212 	{ LLCC_CMPT,     10, 2816, 1, 0, 0xffc, 0x2,   0, 0, 1, 1, 0 },
213 	{ LLCC_GPUHTW,   11, 512,  1, 1, 0xc,   0x0,   0, 0, 1, 1, 0 },
214 	{ LLCC_GPU,      12, 2304, 1, 0, 0xff0, 0x2,   0, 0, 1, 1, 0 },
215 	{ LLCC_MMUHWT,   13, 256,  2, 0, 0x0,   0x1,   0, 0, 1, 0, 1 },
216 	{ LLCC_CMPTDMA,  15, 2816, 1, 0, 0xffc, 0x2,   0, 0, 1, 1, 0 },
217 	{ LLCC_DISP,     16, 2816, 1, 0, 0xffc, 0x2,   0, 0, 1, 1, 0 },
218 	{ LLCC_VIDFW,    17, 2816, 1, 0, 0xffc, 0x2,   0, 0, 1, 1, 0 },
219 	{ LLCC_MDMHPFX,  20, 1024, 2, 1, 0x0,   0xf00, 0, 0, 1, 1, 0 },
220 	{ LLCC_MDMPNG,   21, 1024, 0, 1, 0x1e,  0x0,   0, 0, 1, 1, 0 },
221 	{ LLCC_AUDHW,    22, 1024, 1, 1, 0xffc, 0x2,   0, 0, 1, 1, 0 },
222 };
223 
224 static const struct llcc_slice_config sm6350_data[] =  {
225 	{ LLCC_CPUSS,    1,  768, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 1 },
226 	{ LLCC_MDM,      8,  512, 2, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 },
227 	{ LLCC_GPUHTW,   11, 256, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 },
228 	{ LLCC_GPU,      12, 512, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 },
229 	{ LLCC_MDMPNG,   21, 768, 0, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 },
230 	{ LLCC_NPU,      23, 768, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 },
231 	{ LLCC_MODPE,    29,  64, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 },
232 };
233 
234 static const struct llcc_slice_config sm7150_data[] =  {
235 	{ LLCC_CPUSS,    1,  512, 1, 0, 0xF, 0x0, 0, 0, 0, 1, 1 },
236 	{ LLCC_MDM,      8,  128, 2, 0, 0xF, 0x0, 0, 0, 0, 1, 0 },
237 	{ LLCC_GPUHTW,   11, 256, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0 },
238 	{ LLCC_GPU,      12, 256, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0 },
239 	{ LLCC_NPU,      23, 512, 1, 0, 0xF, 0x0, 0, 0, 0, 1, 0 },
240 };
241 
242 static const struct llcc_slice_config sm8150_data[] =  {
243 	{  LLCC_CPUSS,    1, 3072, 1, 1, 0xFFF, 0x0,   0, 0, 0, 1, 1 },
244 	{  LLCC_VIDSC0,   2, 512,  2, 1, 0xFFF, 0x0,   0, 0, 0, 1, 0 },
245 	{  LLCC_VIDSC1,   3, 512,  2, 1, 0xFFF, 0x0,   0, 0, 0, 1, 0 },
246 	{  LLCC_AUDIO,    6, 1024, 1, 1, 0xFFF, 0x0,   0, 0, 0, 1, 0 },
247 	{  LLCC_MDMHPGRW, 7, 3072, 1, 0, 0xFF,  0xF00, 0, 0, 0, 1, 0 },
248 	{  LLCC_MDM,      8, 3072, 1, 1, 0xFFF, 0x0,   0, 0, 0, 1, 0 },
249 	{  LLCC_MODHW,    9, 1024, 1, 1, 0xFFF, 0x0,   0, 0, 0, 1, 0 },
250 	{  LLCC_CMPT,    10, 3072, 1, 1, 0xFFF, 0x0,   0, 0, 0, 1, 0 },
251 	{  LLCC_GPUHTW , 11, 512,  1, 1, 0xFFF, 0x0,   0, 0, 0, 1, 0 },
252 	{  LLCC_GPU,     12, 2560, 1, 1, 0xFFF, 0x0,   0, 0, 0, 1, 0 },
253 	{  LLCC_MMUHWT,  13, 1024, 1, 1, 0xFFF, 0x0,   0, 0, 0, 0, 1 },
254 	{  LLCC_CMPTDMA, 15, 3072, 1, 1, 0xFFF, 0x0,   0, 0, 0, 1, 0 },
255 	{  LLCC_DISP,    16, 3072, 1, 1, 0xFFF, 0x0,   0, 0, 0, 1, 0 },
256 	{  LLCC_MDMHPFX, 20, 1024, 2, 1, 0xFFF, 0x0,   0, 0, 0, 1, 0 },
257 	{  LLCC_MDMHPFX, 21, 1024, 0, 1, 0xF,   0x0,   0, 0, 0, 1, 0 },
258 	{  LLCC_AUDHW,   22, 1024, 1, 1, 0xFFF, 0x0,   0, 0, 0, 1, 0 },
259 	{  LLCC_NPU,     23, 3072, 1, 1, 0xFFF, 0x0,   0, 0, 0, 1, 0 },
260 	{  LLCC_WLHW,    24, 3072, 1, 1, 0xFFF, 0x0,   0, 0, 0, 1, 0 },
261 	{  LLCC_MODPE,   29, 256,  1, 1, 0xF,   0x0,   0, 0, 0, 1, 0 },
262 	{  LLCC_APTCM,   30, 256,  3, 1, 0x0,   0x1,   1, 0, 0, 1, 0 },
263 	{  LLCC_WRCACHE, 31, 128,  1, 1, 0xFFF, 0x0,   0, 0, 0, 0, 0 },
264 };
265 
266 static const struct llcc_slice_config sm8250_data[] =  {
267 	{ LLCC_CPUSS,    1, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 },
268 	{ LLCC_VIDSC0,   2, 512,  3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
269 	{ LLCC_AUDIO,    6, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 },
270 	{ LLCC_CMPT,    10, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 },
271 	{ LLCC_GPUHTW,  11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
272 	{ LLCC_GPU,     12, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 1 },
273 	{ LLCC_MMUHWT,  13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
274 	{ LLCC_CMPTDMA, 15, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
275 	{ LLCC_DISP,    16, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
276 	{ LLCC_VIDFW,   17, 512,  1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
277 	{ LLCC_AUDHW,   22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
278 	{ LLCC_NPU,     23, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
279 	{ LLCC_WLHW,    24, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
280 	{ LLCC_CVP,     28, 256,  3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
281 	{ LLCC_APTCM,   30, 128,  3, 0, 0x0,   0x3, 1, 0, 0, 1, 0, 0 },
282 	{ LLCC_WRCACHE, 31, 256,  1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
283 };
284 
285 static const struct llcc_slice_config sm8350_data[] =  {
286 	{ LLCC_CPUSS,    1, 3072,  1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 1 },
287 	{ LLCC_VIDSC0,   2, 512,   3, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
288 	{ LLCC_AUDIO,    6, 1024,  1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 },
289 	{ LLCC_MDMHPGRW, 7, 1024,  3, 0, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
290 	{ LLCC_MODHW,    9, 1024,  1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
291 	{ LLCC_CMPT,     10, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
292 	{ LLCC_GPUHTW,   11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
293 	{ LLCC_GPU,      12, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 },
294 	{ LLCC_MMUHWT,   13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 },
295 	{ LLCC_DISP,     16, 3072, 2, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
296 	{ LLCC_MDMPNG,   21, 1024, 0, 1, 0xf,   0x0, 0, 0, 0, 0, 1, 0 },
297 	{ LLCC_AUDHW,    22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
298 	{ LLCC_CVP,      28, 512,  3, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
299 	{ LLCC_MODPE,    29, 256,  1, 1, 0xf,   0x0, 0, 0, 0, 0, 1, 0 },
300 	{ LLCC_APTCM,    30, 1024, 3, 1, 0x0,   0x1, 1, 0, 0, 0, 1, 0 },
301 	{ LLCC_WRCACHE,  31, 512,  1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 },
302 	{ LLCC_CVPFW,    17, 512,  1, 0, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
303 	{ LLCC_CPUSS1,   3, 1024,  1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
304 	{ LLCC_CPUHWT,   5, 512,   1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 },
305 };
306 
307 static const struct llcc_slice_config sm8450_data[] =  {
308 	{LLCC_CPUSS,     1, 3072, 1, 0, 0xFFFF, 0x0,   0, 0, 0, 1, 1, 0, 0 },
309 	{LLCC_VIDSC0,    2,  512, 3, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },
310 	{LLCC_AUDIO,     6, 1024, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0 },
311 	{LLCC_MDMHPGRW,  7, 1024, 3, 0, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },
312 	{LLCC_MODHW,     9, 1024, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },
313 	{LLCC_CMPT,     10, 4096, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },
314 	{LLCC_GPUHTW,   11,  512, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },
315 	{LLCC_GPU,      12, 2048, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 1, 0 },
316 	{LLCC_MMUHWT,   13,  768, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 0, 1, 0, 0 },
317 	{LLCC_DISP,     16, 4096, 2, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },
318 	{LLCC_MDMPNG,   21, 1024, 1, 1, 0xF000, 0x0,   0, 0, 0, 1, 0, 0, 0 },
319 	{LLCC_AUDHW,    22, 1024, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0 },
320 	{LLCC_CVP,      28,  256, 3, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },
321 	{LLCC_MODPE,    29,   64, 1, 1, 0xF000, 0x0,   0, 0, 0, 1, 0, 0, 0 },
322 	{LLCC_APTCM,    30, 1024, 3, 1, 0x0,    0xF0,  1, 0, 0, 1, 0, 0, 0 },
323 	{LLCC_WRCACHE,  31,  512, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 0, 1, 0, 0 },
324 	{LLCC_CVPFW,    17,  512, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },
325 	{LLCC_CPUSS1,    3, 1024, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },
326 	{LLCC_CAMEXP0,   4,  256, 3, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },
327 	{LLCC_CPUMTE,   23,  256, 1, 1, 0x0FFF, 0x0,   0, 0, 0, 0, 1, 0, 0 },
328 	{LLCC_CPUHWT,    5,  512, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 1, 0, 0 },
329 	{LLCC_CAMEXP1,  27,  256, 3, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },
330 	{LLCC_AENPU,     8, 2048, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0 },
331 };
332 
333 static const struct llcc_slice_config sm8550_data[] =  {
334 	{LLCC_CPUSS,     1, 5120, 1, 0, 0xFFFFFF, 0x0,   0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
335 	{LLCC_VIDSC0,    2,  512, 4, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
336 	{LLCC_AUDIO,     6, 1024, 1, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
337 	{LLCC_MDMHPGRW, 25, 1024, 4, 0, 0xFFFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
338 	{LLCC_MODHW,    26, 1024, 1, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
339 	{LLCC_CMPT,     10, 4096, 1, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
340 	{LLCC_GPUHTW,   11,  512, 1, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
341 	{LLCC_GPU,       9, 3096, 1, 0, 0xFFFFFF, 0x0,   0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, },
342 	{LLCC_MMUHWT,   18,  768, 1, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
343 	{LLCC_DISP,     16, 6144, 1, 1, 0xFFFFFF, 0x0,   2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
344 	{LLCC_MDMPNG,   27, 1024, 0, 1, 0xF00000, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
345 	{LLCC_AUDHW,    22, 1024, 1, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
346 	{LLCC_CVP,       8,  256, 4, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
347 	{LLCC_MODPE,    29,   64, 1, 1, 0xF00000, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, },
348 	{LLCC_WRCACHE,  31,  512, 1, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
349 	{LLCC_CAMEXP0,   4,  256, 4, 1,      0xF, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
350 	{LLCC_CPUHWT,    5,  512, 1, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
351 	{LLCC_CAMEXP1,   7, 3200, 3, 1, 0xFFFFF0, 0x0,   2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
352 	{LLCC_CMPTHCP,  17,  256, 4, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
353 	{LLCC_LCPDARE,  30,  128, 4, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, },
354 	{LLCC_AENPU,     3, 3072, 1, 1, 0xFE01FF, 0x0,   2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
355 	{LLCC_ISLAND1,  12, 1792, 7, 1,   0xFE00, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
356 	{LLCC_ISLAND4,  15,  256, 7, 1,  0x10000, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
357 	{LLCC_CAMEXP2,  19, 3200, 3, 1, 0xFFFFF0, 0x0,   2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
358 	{LLCC_CAMEXP3,  20, 3200, 2, 1, 0xFFFFF0, 0x0,   2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
359 	{LLCC_CAMEXP4,  21, 3200, 2, 1, 0xFFFFF0, 0x0,   2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
360 	{LLCC_DISP_WB,  23, 1024, 4, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
361 	{LLCC_DISP_1,   24, 6144, 1, 1, 0xFFFFFF, 0x0,   2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
362 	{LLCC_VIDVSP,   28,  256, 4, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
363 };
364 
365 static const struct llcc_slice_config qdu1000_data_2ch[] = {
366 	{ LLCC_MDMHPGRW, 7, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
367 	{ LLCC_MODHW,    9, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
368 	{ LLCC_MDMPNG,  21, 256, 0, 1, 0x3,   0x0, 0, 0, 0, 1, 0, 0, 0 },
369 	{ LLCC_ECC,     26, 512, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 },
370 	{ LLCC_MODPE,   29, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
371 	{ LLCC_APTCM,   30, 256, 3, 1, 0x0,   0xc, 1, 0, 0, 1, 0, 0, 0 },
372 	{ LLCC_WRCACHE, 31, 128, 1, 1, 0x3,   0x0, 0, 0, 0, 0, 1, 0, 0 },
373 };
374 
375 static const struct llcc_slice_config qdu1000_data_4ch[] = {
376 	{ LLCC_MDMHPGRW, 7, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
377 	{ LLCC_MODHW,    9, 512,  1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
378 	{ LLCC_MDMPNG,  21, 512,  0, 1, 0x3,   0x0, 0, 0, 0, 1, 0, 0, 0 },
379 	{ LLCC_ECC,     26, 1024, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 },
380 	{ LLCC_MODPE,   29, 512,  1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
381 	{ LLCC_APTCM,   30, 512,  3, 1, 0x0,   0xc, 1, 0, 0, 1, 0, 0, 0 },
382 	{ LLCC_WRCACHE, 31, 256,  1, 1, 0x3,   0x0, 0, 0, 0, 0, 1, 0, 0 },
383 };
384 
385 static const struct llcc_slice_config qdu1000_data_8ch[] = {
386 	{ LLCC_MDMHPGRW, 7, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
387 	{ LLCC_MODHW,    9, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
388 	{ LLCC_MDMPNG,  21, 1024, 0, 1, 0x3,   0x0, 0, 0, 0, 1, 0, 0, 0 },
389 	{ LLCC_ECC,     26, 2048, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 },
390 	{ LLCC_MODPE,   29, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
391 	{ LLCC_APTCM,   30, 1024, 3, 1, 0x0,   0xc, 1, 0, 0, 1, 0, 0, 0 },
392 	{ LLCC_WRCACHE, 31, 512,  1, 1, 0x3,   0x0, 0, 0, 0, 0, 1, 0, 0 },
393 };
394 
395 static const struct llcc_edac_reg_offset llcc_v1_edac_reg_offset = {
396 	.trp_ecc_error_status0 = 0x20344,
397 	.trp_ecc_error_status1 = 0x20348,
398 	.trp_ecc_sb_err_syn0 = 0x2304c,
399 	.trp_ecc_db_err_syn0 = 0x20370,
400 	.trp_ecc_error_cntr_clear = 0x20440,
401 	.trp_interrupt_0_status = 0x20480,
402 	.trp_interrupt_0_clear = 0x20484,
403 	.trp_interrupt_0_enable = 0x20488,
404 
405 	/* LLCC Common registers */
406 	.cmn_status0 = 0x3000c,
407 	.cmn_interrupt_0_enable = 0x3001c,
408 	.cmn_interrupt_2_enable = 0x3003c,
409 
410 	/* LLCC DRP registers */
411 	.drp_ecc_error_cfg = 0x40000,
412 	.drp_ecc_error_cntr_clear = 0x40004,
413 	.drp_interrupt_status = 0x41000,
414 	.drp_interrupt_clear = 0x41008,
415 	.drp_interrupt_enable = 0x4100c,
416 	.drp_ecc_error_status0 = 0x42044,
417 	.drp_ecc_error_status1 = 0x42048,
418 	.drp_ecc_sb_err_syn0 = 0x4204c,
419 	.drp_ecc_db_err_syn0 = 0x42070,
420 };
421 
422 static const struct llcc_edac_reg_offset llcc_v2_1_edac_reg_offset = {
423 	.trp_ecc_error_status0 = 0x20344,
424 	.trp_ecc_error_status1 = 0x20348,
425 	.trp_ecc_sb_err_syn0 = 0x2034c,
426 	.trp_ecc_db_err_syn0 = 0x20370,
427 	.trp_ecc_error_cntr_clear = 0x20440,
428 	.trp_interrupt_0_status = 0x20480,
429 	.trp_interrupt_0_clear = 0x20484,
430 	.trp_interrupt_0_enable = 0x20488,
431 
432 	/* LLCC Common registers */
433 	.cmn_status0 = 0x3400c,
434 	.cmn_interrupt_0_enable = 0x3401c,
435 	.cmn_interrupt_2_enable = 0x3403c,
436 
437 	/* LLCC DRP registers */
438 	.drp_ecc_error_cfg = 0x50000,
439 	.drp_ecc_error_cntr_clear = 0x50004,
440 	.drp_interrupt_status = 0x50020,
441 	.drp_interrupt_clear = 0x50028,
442 	.drp_interrupt_enable = 0x5002c,
443 	.drp_ecc_error_status0 = 0x520f4,
444 	.drp_ecc_error_status1 = 0x520f8,
445 	.drp_ecc_sb_err_syn0 = 0x520fc,
446 	.drp_ecc_db_err_syn0 = 0x52120,
447 };
448 
449 /* LLCC register offset starting from v1.0.0 */
450 static const u32 llcc_v1_reg_offset[] = {
451 	[LLCC_COMMON_HW_INFO]	= 0x00030000,
452 	[LLCC_COMMON_STATUS0]	= 0x0003000c,
453 };
454 
455 /* LLCC register offset starting from v2.0.1 */
456 static const u32 llcc_v2_1_reg_offset[] = {
457 	[LLCC_COMMON_HW_INFO]	= 0x00034000,
458 	[LLCC_COMMON_STATUS0]	= 0x0003400c,
459 };
460 
461 static const struct qcom_llcc_config qdu1000_cfg[] = {
462 	{
463 		.sct_data       = qdu1000_data_8ch,
464 		.size		= ARRAY_SIZE(qdu1000_data_8ch),
465 		.need_llcc_cfg	= true,
466 		.reg_offset	= llcc_v2_1_reg_offset,
467 		.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
468 	},
469 	{
470 		.sct_data       = qdu1000_data_4ch,
471 		.size           = ARRAY_SIZE(qdu1000_data_4ch),
472 		.need_llcc_cfg  = true,
473 		.reg_offset     = llcc_v2_1_reg_offset,
474 		.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
475 	},
476 	{
477 		.sct_data       = qdu1000_data_4ch,
478 		.size           = ARRAY_SIZE(qdu1000_data_4ch),
479 		.need_llcc_cfg  = true,
480 		.reg_offset     = llcc_v2_1_reg_offset,
481 		.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
482 	},
483 	{
484 		.sct_data       = qdu1000_data_2ch,
485 		.size           = ARRAY_SIZE(qdu1000_data_2ch),
486 		.need_llcc_cfg  = true,
487 		.reg_offset     = llcc_v2_1_reg_offset,
488 		.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
489 	},
490 };
491 
492 static const struct qcom_llcc_config sc7180_cfg[] = {
493 	{
494 		.sct_data	= sc7180_data,
495 		.size		= ARRAY_SIZE(sc7180_data),
496 		.need_llcc_cfg	= true,
497 		.reg_offset	= llcc_v1_reg_offset,
498 		.edac_reg_offset = &llcc_v1_edac_reg_offset,
499 	},
500 };
501 
502 static const struct qcom_llcc_config sc7280_cfg[] = {
503 	{
504 		.sct_data	= sc7280_data,
505 		.size		= ARRAY_SIZE(sc7280_data),
506 		.need_llcc_cfg	= true,
507 		.reg_offset	= llcc_v1_reg_offset,
508 		.edac_reg_offset = &llcc_v1_edac_reg_offset,
509 	},
510 };
511 
512 static const struct qcom_llcc_config sc8180x_cfg[] = {
513 	{
514 		.sct_data	= sc8180x_data,
515 		.size		= ARRAY_SIZE(sc8180x_data),
516 		.need_llcc_cfg	= true,
517 		.reg_offset	= llcc_v1_reg_offset,
518 		.edac_reg_offset = &llcc_v1_edac_reg_offset,
519 	},
520 };
521 
522 static const struct qcom_llcc_config sc8280xp_cfg[] = {
523 	{
524 		.sct_data	= sc8280xp_data,
525 		.size		= ARRAY_SIZE(sc8280xp_data),
526 		.need_llcc_cfg	= true,
527 		.reg_offset	= llcc_v1_reg_offset,
528 		.edac_reg_offset = &llcc_v1_edac_reg_offset,
529 	},
530 };
531 
532 static const struct qcom_llcc_config sdm845_cfg[] = {
533 	{
534 		.sct_data	= sdm845_data,
535 		.size		= ARRAY_SIZE(sdm845_data),
536 		.need_llcc_cfg	= false,
537 		.reg_offset	= llcc_v1_reg_offset,
538 		.edac_reg_offset = &llcc_v1_edac_reg_offset,
539 		.no_edac	= true,
540 	},
541 };
542 
543 static const struct qcom_llcc_config sm6350_cfg[] = {
544 	{
545 		.sct_data	= sm6350_data,
546 		.size		= ARRAY_SIZE(sm6350_data),
547 		.need_llcc_cfg	= true,
548 		.reg_offset	= llcc_v1_reg_offset,
549 		.edac_reg_offset = &llcc_v1_edac_reg_offset,
550 	},
551 };
552 
553 static const struct qcom_llcc_config sm7150_cfg[] = {
554 	{
555 		.sct_data       = sm7150_data,
556 		.size           = ARRAY_SIZE(sm7150_data),
557 		.need_llcc_cfg	= true,
558 		.reg_offset	= llcc_v1_reg_offset,
559 		.edac_reg_offset = &llcc_v1_edac_reg_offset,
560 	},
561 };
562 
563 static const struct qcom_llcc_config sm8150_cfg[] = {
564 	{
565 		.sct_data       = sm8150_data,
566 		.size           = ARRAY_SIZE(sm8150_data),
567 		.need_llcc_cfg	= true,
568 		.reg_offset	= llcc_v1_reg_offset,
569 		.edac_reg_offset = &llcc_v1_edac_reg_offset,
570 	},
571 };
572 
573 static const struct qcom_llcc_config sm8250_cfg[] = {
574 	{
575 		.sct_data       = sm8250_data,
576 		.size           = ARRAY_SIZE(sm8250_data),
577 		.need_llcc_cfg	= true,
578 		.reg_offset	= llcc_v1_reg_offset,
579 		.edac_reg_offset = &llcc_v1_edac_reg_offset,
580 	},
581 };
582 
583 static const struct qcom_llcc_config sm8350_cfg[] = {
584 	{
585 		.sct_data       = sm8350_data,
586 		.size           = ARRAY_SIZE(sm8350_data),
587 		.need_llcc_cfg	= true,
588 		.reg_offset	= llcc_v1_reg_offset,
589 		.edac_reg_offset = &llcc_v1_edac_reg_offset,
590 	},
591 };
592 
593 static const struct qcom_llcc_config sm8450_cfg[] = {
594 	{
595 		.sct_data       = sm8450_data,
596 		.size           = ARRAY_SIZE(sm8450_data),
597 		.need_llcc_cfg	= true,
598 		.reg_offset	= llcc_v2_1_reg_offset,
599 		.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
600 	},
601 };
602 
603 static const struct qcom_llcc_config sm8550_cfg[] = {
604 	{
605 		.sct_data       = sm8550_data,
606 		.size           = ARRAY_SIZE(sm8550_data),
607 		.need_llcc_cfg	= true,
608 		.reg_offset	= llcc_v2_1_reg_offset,
609 		.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
610 	},
611 };
612 
613 static const struct qcom_sct_config qdu1000_cfgs = {
614 	.llcc_config	= qdu1000_cfg,
615 	.num_config	= ARRAY_SIZE(qdu1000_cfg),
616 };
617 
618 static const struct qcom_sct_config sc7180_cfgs = {
619 	.llcc_config	= sc7180_cfg,
620 	.num_config	= ARRAY_SIZE(sc7180_cfg),
621 };
622 
623 static const struct qcom_sct_config sc7280_cfgs = {
624 	.llcc_config	= sc7280_cfg,
625 	.num_config	= ARRAY_SIZE(sc7280_cfg),
626 };
627 
628 static const struct qcom_sct_config sc8180x_cfgs = {
629 	.llcc_config	= sc8180x_cfg,
630 	.num_config	= ARRAY_SIZE(sc8180x_cfg),
631 };
632 
633 static const struct qcom_sct_config sc8280xp_cfgs = {
634 	.llcc_config	= sc8280xp_cfg,
635 	.num_config	= ARRAY_SIZE(sc8280xp_cfg),
636 };
637 
638 static const struct qcom_sct_config sdm845_cfgs = {
639 	.llcc_config	= sdm845_cfg,
640 	.num_config	= ARRAY_SIZE(sdm845_cfg),
641 };
642 
643 static const struct qcom_sct_config sm6350_cfgs = {
644 	.llcc_config	= sm6350_cfg,
645 	.num_config	= ARRAY_SIZE(sm6350_cfg),
646 };
647 
648 static const struct qcom_sct_config sm7150_cfgs = {
649 	.llcc_config	= sm7150_cfg,
650 	.num_config	= ARRAY_SIZE(sm7150_cfg),
651 };
652 
653 static const struct qcom_sct_config sm8150_cfgs = {
654 	.llcc_config	= sm8150_cfg,
655 	.num_config	= ARRAY_SIZE(sm8150_cfg),
656 };
657 
658 static const struct qcom_sct_config sm8250_cfgs = {
659 	.llcc_config	= sm8250_cfg,
660 	.num_config	= ARRAY_SIZE(sm8250_cfg),
661 };
662 
663 static const struct qcom_sct_config sm8350_cfgs = {
664 	.llcc_config	= sm8350_cfg,
665 	.num_config	= ARRAY_SIZE(sm8350_cfg),
666 };
667 
668 static const struct qcom_sct_config sm8450_cfgs = {
669 	.llcc_config	= sm8450_cfg,
670 	.num_config	= ARRAY_SIZE(sm8450_cfg),
671 };
672 
673 static const struct qcom_sct_config sm8550_cfgs = {
674 	.llcc_config	= sm8550_cfg,
675 	.num_config	= ARRAY_SIZE(sm8550_cfg),
676 };
677 
678 static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
679 
680 /**
681  * llcc_slice_getd - get llcc slice descriptor
682  * @uid: usecase_id for the client
683  *
684  * A pointer to llcc slice descriptor will be returned on success
685  * and error pointer is returned on failure
686  */
687 struct llcc_slice_desc *llcc_slice_getd(u32 uid)
688 {
689 	const struct llcc_slice_config *cfg;
690 	struct llcc_slice_desc *desc;
691 	u32 sz, count;
692 
693 	if (IS_ERR(drv_data))
694 		return ERR_CAST(drv_data);
695 
696 	cfg = drv_data->cfg;
697 	sz = drv_data->cfg_size;
698 
699 	for (count = 0; cfg && count < sz; count++, cfg++)
700 		if (cfg->usecase_id == uid)
701 			break;
702 
703 	if (count == sz || !cfg)
704 		return ERR_PTR(-ENODEV);
705 
706 	desc = kzalloc(sizeof(*desc), GFP_KERNEL);
707 	if (!desc)
708 		return ERR_PTR(-ENOMEM);
709 
710 	desc->slice_id = cfg->slice_id;
711 	desc->slice_size = cfg->max_cap;
712 
713 	return desc;
714 }
715 EXPORT_SYMBOL_GPL(llcc_slice_getd);
716 
717 /**
718  * llcc_slice_putd - llcc slice descritpor
719  * @desc: Pointer to llcc slice descriptor
720  */
721 void llcc_slice_putd(struct llcc_slice_desc *desc)
722 {
723 	if (!IS_ERR_OR_NULL(desc))
724 		kfree(desc);
725 }
726 EXPORT_SYMBOL_GPL(llcc_slice_putd);
727 
728 static int llcc_update_act_ctrl(u32 sid,
729 				u32 act_ctrl_reg_val, u32 status)
730 {
731 	u32 act_ctrl_reg;
732 	u32 act_clear_reg;
733 	u32 status_reg;
734 	u32 slice_status;
735 	int ret;
736 
737 	if (IS_ERR(drv_data))
738 		return PTR_ERR(drv_data);
739 
740 	act_ctrl_reg = LLCC_TRP_ACT_CTRLn(sid);
741 	act_clear_reg = LLCC_TRP_ACT_CLEARn(sid);
742 	status_reg = LLCC_TRP_STATUSn(sid);
743 
744 	/* Set the ACTIVE trigger */
745 	act_ctrl_reg_val |= ACT_CTRL_ACT_TRIG;
746 	ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg,
747 				act_ctrl_reg_val);
748 	if (ret)
749 		return ret;
750 
751 	/* Clear the ACTIVE trigger */
752 	act_ctrl_reg_val &= ~ACT_CTRL_ACT_TRIG;
753 	ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg,
754 				act_ctrl_reg_val);
755 	if (ret)
756 		return ret;
757 
758 	if (drv_data->version >= LLCC_VERSION_4_1_0_0) {
759 		ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg,
760 				      slice_status, (slice_status & ACT_COMPLETE),
761 				      0, LLCC_STATUS_READ_DELAY);
762 		if (ret)
763 			return ret;
764 	}
765 
766 	ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg,
767 				      slice_status, !(slice_status & status),
768 				      0, LLCC_STATUS_READ_DELAY);
769 
770 	if (drv_data->version >= LLCC_VERSION_4_1_0_0)
771 		ret = regmap_write(drv_data->bcast_regmap, act_clear_reg,
772 					ACT_CLEAR);
773 
774 	return ret;
775 }
776 
777 /**
778  * llcc_slice_activate - Activate the llcc slice
779  * @desc: Pointer to llcc slice descriptor
780  *
781  * A value of zero will be returned on success and a negative errno will
782  * be returned in error cases
783  */
784 int llcc_slice_activate(struct llcc_slice_desc *desc)
785 {
786 	int ret;
787 	u32 act_ctrl_val;
788 
789 	if (IS_ERR(drv_data))
790 		return PTR_ERR(drv_data);
791 
792 	if (IS_ERR_OR_NULL(desc))
793 		return -EINVAL;
794 
795 	mutex_lock(&drv_data->lock);
796 	if (test_bit(desc->slice_id, drv_data->bitmap)) {
797 		mutex_unlock(&drv_data->lock);
798 		return 0;
799 	}
800 
801 	act_ctrl_val = ACT_CTRL_OPCODE_ACTIVATE << ACT_CTRL_OPCODE_SHIFT;
802 
803 	ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val,
804 				  DEACTIVATE);
805 	if (ret) {
806 		mutex_unlock(&drv_data->lock);
807 		return ret;
808 	}
809 
810 	__set_bit(desc->slice_id, drv_data->bitmap);
811 	mutex_unlock(&drv_data->lock);
812 
813 	return ret;
814 }
815 EXPORT_SYMBOL_GPL(llcc_slice_activate);
816 
817 /**
818  * llcc_slice_deactivate - Deactivate the llcc slice
819  * @desc: Pointer to llcc slice descriptor
820  *
821  * A value of zero will be returned on success and a negative errno will
822  * be returned in error cases
823  */
824 int llcc_slice_deactivate(struct llcc_slice_desc *desc)
825 {
826 	u32 act_ctrl_val;
827 	int ret;
828 
829 	if (IS_ERR(drv_data))
830 		return PTR_ERR(drv_data);
831 
832 	if (IS_ERR_OR_NULL(desc))
833 		return -EINVAL;
834 
835 	mutex_lock(&drv_data->lock);
836 	if (!test_bit(desc->slice_id, drv_data->bitmap)) {
837 		mutex_unlock(&drv_data->lock);
838 		return 0;
839 	}
840 	act_ctrl_val = ACT_CTRL_OPCODE_DEACTIVATE << ACT_CTRL_OPCODE_SHIFT;
841 
842 	ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val,
843 				  ACTIVATE);
844 	if (ret) {
845 		mutex_unlock(&drv_data->lock);
846 		return ret;
847 	}
848 
849 	__clear_bit(desc->slice_id, drv_data->bitmap);
850 	mutex_unlock(&drv_data->lock);
851 
852 	return ret;
853 }
854 EXPORT_SYMBOL_GPL(llcc_slice_deactivate);
855 
856 /**
857  * llcc_get_slice_id - return the slice id
858  * @desc: Pointer to llcc slice descriptor
859  */
860 int llcc_get_slice_id(struct llcc_slice_desc *desc)
861 {
862 	if (IS_ERR_OR_NULL(desc))
863 		return -EINVAL;
864 
865 	return desc->slice_id;
866 }
867 EXPORT_SYMBOL_GPL(llcc_get_slice_id);
868 
869 /**
870  * llcc_get_slice_size - return the slice id
871  * @desc: Pointer to llcc slice descriptor
872  */
873 size_t llcc_get_slice_size(struct llcc_slice_desc *desc)
874 {
875 	if (IS_ERR_OR_NULL(desc))
876 		return 0;
877 
878 	return desc->slice_size;
879 }
880 EXPORT_SYMBOL_GPL(llcc_get_slice_size);
881 
882 static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config,
883 				  const struct qcom_llcc_config *cfg)
884 {
885 	int ret;
886 	u32 attr2_cfg;
887 	u32 attr1_cfg;
888 	u32 attr0_cfg;
889 	u32 attr2_val;
890 	u32 attr1_val;
891 	u32 attr0_val;
892 	u32 max_cap_cacheline;
893 	struct llcc_slice_desc desc;
894 
895 	attr1_val = config->cache_mode;
896 	attr1_val |= config->probe_target_ways << ATTR1_PROBE_TARGET_WAYS_SHIFT;
897 	attr1_val |= config->fixed_size << ATTR1_FIXED_SIZE_SHIFT;
898 	attr1_val |= config->priority << ATTR1_PRIORITY_SHIFT;
899 
900 	max_cap_cacheline = MAX_CAP_TO_BYTES(config->max_cap);
901 
902 	/*
903 	 * LLCC instances can vary for each target.
904 	 * The SW writes to broadcast register which gets propagated
905 	 * to each llcc instance (llcc0,.. llccN).
906 	 * Since the size of the memory is divided equally amongst the
907 	 * llcc instances, we need to configure the max cap accordingly.
908 	 */
909 	max_cap_cacheline = max_cap_cacheline / drv_data->num_banks;
910 	max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT;
911 	attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT;
912 
913 	attr1_cfg = LLCC_TRP_ATTR1_CFGn(config->slice_id);
914 
915 	ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, attr1_val);
916 	if (ret)
917 		return ret;
918 
919 	if (drv_data->version >= LLCC_VERSION_4_1_0_0) {
920 		attr2_cfg = LLCC_TRP_ATTR2_CFGn(config->slice_id);
921 		attr0_val = config->res_ways;
922 		attr2_val = config->bonus_ways;
923 	} else {
924 		attr0_val = config->res_ways & ATTR0_RES_WAYS_MASK;
925 		attr0_val |= config->bonus_ways << ATTR0_BONUS_WAYS_SHIFT;
926 	}
927 
928 	attr0_cfg = LLCC_TRP_ATTR0_CFGn(config->slice_id);
929 
930 	ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, attr0_val);
931 	if (ret)
932 		return ret;
933 
934 	if (drv_data->version >= LLCC_VERSION_4_1_0_0) {
935 		ret = regmap_write(drv_data->bcast_regmap, attr2_cfg, attr2_val);
936 		if (ret)
937 			return ret;
938 	}
939 
940 	if (cfg->need_llcc_cfg) {
941 		u32 disable_cap_alloc, retain_pc;
942 
943 		disable_cap_alloc = config->dis_cap_alloc << config->slice_id;
944 		ret = regmap_write(drv_data->bcast_regmap,
945 				LLCC_TRP_SCID_DIS_CAP_ALLOC, disable_cap_alloc);
946 		if (ret)
947 			return ret;
948 
949 		if (drv_data->version < LLCC_VERSION_4_1_0_0) {
950 			retain_pc = config->retain_on_pc << config->slice_id;
951 			ret = regmap_write(drv_data->bcast_regmap,
952 					LLCC_TRP_PCB_ACT, retain_pc);
953 			if (ret)
954 				return ret;
955 		}
956 	}
957 
958 	if (drv_data->version >= LLCC_VERSION_2_0_0_0) {
959 		u32 wren;
960 
961 		wren = config->write_scid_en << config->slice_id;
962 		ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_EN,
963 					 BIT(config->slice_id), wren);
964 		if (ret)
965 			return ret;
966 	}
967 
968 	if (drv_data->version >= LLCC_VERSION_2_1_0_0) {
969 		u32 wr_cache_en;
970 
971 		wr_cache_en = config->write_scid_cacheable_en << config->slice_id;
972 		ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_CACHEABLE_EN,
973 					 BIT(config->slice_id), wr_cache_en);
974 		if (ret)
975 			return ret;
976 	}
977 
978 	if (drv_data->version >= LLCC_VERSION_4_1_0_0) {
979 		u32 stale_en;
980 		u32 stale_cap_en;
981 		u32 mru_uncap_en;
982 		u32 mru_rollover;
983 		u32 alloc_oneway_en;
984 		u32 ovcap_en;
985 		u32 ovcap_prio;
986 		u32 vict_prio;
987 
988 		stale_en = config->stale_en << config->slice_id;
989 		ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG1,
990 					 BIT(config->slice_id), stale_en);
991 		if (ret)
992 			return ret;
993 
994 		stale_cap_en = config->stale_cap_en << config->slice_id;
995 		ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG2,
996 					 BIT(config->slice_id), stale_cap_en);
997 		if (ret)
998 			return ret;
999 
1000 		mru_uncap_en = config->mru_uncap_en << config->slice_id;
1001 		ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG3,
1002 					 BIT(config->slice_id), mru_uncap_en);
1003 		if (ret)
1004 			return ret;
1005 
1006 		mru_rollover = config->mru_rollover << config->slice_id;
1007 		ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG4,
1008 					 BIT(config->slice_id), mru_rollover);
1009 		if (ret)
1010 			return ret;
1011 
1012 		alloc_oneway_en = config->alloc_oneway_en << config->slice_id;
1013 		ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG5,
1014 					 BIT(config->slice_id), alloc_oneway_en);
1015 		if (ret)
1016 			return ret;
1017 
1018 		ovcap_en = config->ovcap_en << config->slice_id;
1019 		ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG6,
1020 					 BIT(config->slice_id), ovcap_en);
1021 		if (ret)
1022 			return ret;
1023 
1024 		ovcap_prio = config->ovcap_prio << config->slice_id;
1025 		ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG7,
1026 					 BIT(config->slice_id), ovcap_prio);
1027 		if (ret)
1028 			return ret;
1029 
1030 		vict_prio = config->vict_prio << config->slice_id;
1031 		ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG8,
1032 					 BIT(config->slice_id), vict_prio);
1033 		if (ret)
1034 			return ret;
1035 	}
1036 
1037 	if (config->activate_on_init) {
1038 		desc.slice_id = config->slice_id;
1039 		ret = llcc_slice_activate(&desc);
1040 	}
1041 
1042 	return ret;
1043 }
1044 
1045 static int qcom_llcc_cfg_program(struct platform_device *pdev,
1046 				 const struct qcom_llcc_config *cfg)
1047 {
1048 	int i;
1049 	u32 sz;
1050 	int ret = 0;
1051 	const struct llcc_slice_config *llcc_table;
1052 
1053 	sz = drv_data->cfg_size;
1054 	llcc_table = drv_data->cfg;
1055 
1056 	for (i = 0; i < sz; i++) {
1057 		ret = _qcom_llcc_cfg_program(&llcc_table[i], cfg);
1058 		if (ret)
1059 			return ret;
1060 	}
1061 
1062 	return ret;
1063 }
1064 
1065 static int qcom_llcc_get_cfg_index(struct platform_device *pdev, u8 *cfg_index, int num_config)
1066 {
1067 	int ret;
1068 
1069 	ret = nvmem_cell_read_u8(&pdev->dev, "multi-chan-ddr", cfg_index);
1070 	if (ret == -ENOENT || ret == -EOPNOTSUPP) {
1071 		if (num_config > 1)
1072 			return -EINVAL;
1073 		*cfg_index = 0;
1074 		return 0;
1075 	}
1076 
1077 	if (!ret && *cfg_index >= num_config)
1078 		ret = -EINVAL;
1079 
1080 	return ret;
1081 }
1082 
1083 static void qcom_llcc_remove(struct platform_device *pdev)
1084 {
1085 	/* Set the global pointer to a error code to avoid referencing it */
1086 	drv_data = ERR_PTR(-ENODEV);
1087 }
1088 
1089 static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, u8 index,
1090 					  const char *name)
1091 {
1092 	void __iomem *base;
1093 	struct regmap_config llcc_regmap_config = {
1094 		.reg_bits = 32,
1095 		.reg_stride = 4,
1096 		.val_bits = 32,
1097 		.fast_io = true,
1098 	};
1099 
1100 	base = devm_platform_ioremap_resource(pdev, index);
1101 	if (IS_ERR(base))
1102 		return ERR_CAST(base);
1103 
1104 	llcc_regmap_config.name = name;
1105 	return devm_regmap_init_mmio(&pdev->dev, base, &llcc_regmap_config);
1106 }
1107 
1108 static int qcom_llcc_probe(struct platform_device *pdev)
1109 {
1110 	u32 num_banks;
1111 	struct device *dev = &pdev->dev;
1112 	int ret, i;
1113 	struct platform_device *llcc_edac;
1114 	const struct qcom_sct_config *cfgs;
1115 	const struct qcom_llcc_config *cfg;
1116 	const struct llcc_slice_config *llcc_cfg;
1117 	u32 sz;
1118 	u8 cfg_index;
1119 	u32 version;
1120 	struct regmap *regmap;
1121 
1122 	if (!IS_ERR(drv_data))
1123 		return -EBUSY;
1124 
1125 	drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL);
1126 	if (!drv_data) {
1127 		ret = -ENOMEM;
1128 		goto err;
1129 	}
1130 
1131 	/* Initialize the first LLCC bank regmap */
1132 	regmap = qcom_llcc_init_mmio(pdev, 0, "llcc0_base");
1133 	if (IS_ERR(regmap)) {
1134 		ret = PTR_ERR(regmap);
1135 		goto err;
1136 	}
1137 
1138 	cfgs = of_device_get_match_data(&pdev->dev);
1139 	if (!cfgs) {
1140 		ret = -EINVAL;
1141 		goto err;
1142 	}
1143 	ret = qcom_llcc_get_cfg_index(pdev, &cfg_index, cfgs->num_config);
1144 	if (ret)
1145 		goto err;
1146 	cfg = &cfgs->llcc_config[cfg_index];
1147 
1148 	ret = regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_banks);
1149 	if (ret)
1150 		goto err;
1151 
1152 	num_banks &= LLCC_LB_CNT_MASK;
1153 	num_banks >>= LLCC_LB_CNT_SHIFT;
1154 	drv_data->num_banks = num_banks;
1155 
1156 	drv_data->regmaps = devm_kcalloc(dev, num_banks, sizeof(*drv_data->regmaps), GFP_KERNEL);
1157 	if (!drv_data->regmaps) {
1158 		ret = -ENOMEM;
1159 		goto err;
1160 	}
1161 
1162 	drv_data->regmaps[0] = regmap;
1163 
1164 	/* Initialize rest of LLCC bank regmaps */
1165 	for (i = 1; i < num_banks; i++) {
1166 		char *base = kasprintf(GFP_KERNEL, "llcc%d_base", i);
1167 
1168 		drv_data->regmaps[i] = qcom_llcc_init_mmio(pdev, i, base);
1169 		if (IS_ERR(drv_data->regmaps[i])) {
1170 			ret = PTR_ERR(drv_data->regmaps[i]);
1171 			kfree(base);
1172 			goto err;
1173 		}
1174 
1175 		kfree(base);
1176 	}
1177 
1178 	drv_data->bcast_regmap = qcom_llcc_init_mmio(pdev, i, "llcc_broadcast_base");
1179 	if (IS_ERR(drv_data->bcast_regmap)) {
1180 		ret = PTR_ERR(drv_data->bcast_regmap);
1181 		goto err;
1182 	}
1183 
1184 	/* Extract version of the IP */
1185 	ret = regmap_read(drv_data->bcast_regmap, cfg->reg_offset[LLCC_COMMON_HW_INFO],
1186 			  &version);
1187 	if (ret)
1188 		goto err;
1189 
1190 	drv_data->version = version;
1191 
1192 	llcc_cfg = cfg->sct_data;
1193 	sz = cfg->size;
1194 
1195 	for (i = 0; i < sz; i++)
1196 		if (llcc_cfg[i].slice_id > drv_data->max_slices)
1197 			drv_data->max_slices = llcc_cfg[i].slice_id;
1198 
1199 	drv_data->bitmap = devm_bitmap_zalloc(dev, drv_data->max_slices,
1200 					      GFP_KERNEL);
1201 	if (!drv_data->bitmap) {
1202 		ret = -ENOMEM;
1203 		goto err;
1204 	}
1205 
1206 	drv_data->cfg = llcc_cfg;
1207 	drv_data->cfg_size = sz;
1208 	drv_data->edac_reg_offset = cfg->edac_reg_offset;
1209 	mutex_init(&drv_data->lock);
1210 	platform_set_drvdata(pdev, drv_data);
1211 
1212 	ret = qcom_llcc_cfg_program(pdev, cfg);
1213 	if (ret)
1214 		goto err;
1215 
1216 	drv_data->ecc_irq = platform_get_irq_optional(pdev, 0);
1217 
1218 	/*
1219 	 * On some platforms, the access to EDAC registers will be locked by
1220 	 * the bootloader. So probing the EDAC driver will result in a crash.
1221 	 * Hence, disable the creation of EDAC platform device for the
1222 	 * problematic platforms.
1223 	 */
1224 	if (!cfg->no_edac) {
1225 		llcc_edac = platform_device_register_data(&pdev->dev,
1226 						"qcom_llcc_edac", -1, drv_data,
1227 						sizeof(*drv_data));
1228 		if (IS_ERR(llcc_edac))
1229 			dev_err(dev, "Failed to register llcc edac driver\n");
1230 	}
1231 
1232 	return 0;
1233 err:
1234 	drv_data = ERR_PTR(-ENODEV);
1235 	return ret;
1236 }
1237 
1238 static const struct of_device_id qcom_llcc_of_match[] = {
1239 	{ .compatible = "qcom,qdu1000-llcc", .data = &qdu1000_cfgs},
1240 	{ .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfgs },
1241 	{ .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfgs },
1242 	{ .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfgs },
1243 	{ .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfgs },
1244 	{ .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfgs },
1245 	{ .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfgs },
1246 	{ .compatible = "qcom,sm7150-llcc", .data = &sm7150_cfgs },
1247 	{ .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfgs },
1248 	{ .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfgs },
1249 	{ .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfgs },
1250 	{ .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfgs },
1251 	{ .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfgs },
1252 	{ }
1253 };
1254 MODULE_DEVICE_TABLE(of, qcom_llcc_of_match);
1255 
1256 static struct platform_driver qcom_llcc_driver = {
1257 	.driver = {
1258 		.name = "qcom-llcc",
1259 		.of_match_table = qcom_llcc_of_match,
1260 	},
1261 	.probe = qcom_llcc_probe,
1262 	.remove_new = qcom_llcc_remove,
1263 };
1264 module_platform_driver(qcom_llcc_driver);
1265 
1266 MODULE_DESCRIPTION("Qualcomm Last Level Cache Controller");
1267 MODULE_LICENSE("GPL v2");
1268