1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/bitmap.h> 9 #include <linux/bitops.h> 10 #include <linux/cleanup.h> 11 #include <linux/device.h> 12 #include <linux/io.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/mutex.h> 16 #include <linux/nvmem-consumer.h> 17 #include <linux/of.h> 18 #include <linux/regmap.h> 19 #include <linux/sizes.h> 20 #include <linux/slab.h> 21 #include <linux/soc/qcom/llcc-qcom.h> 22 23 #define ACTIVATE BIT(0) 24 #define DEACTIVATE BIT(1) 25 #define ACT_CLEAR BIT(0) 26 #define ACT_COMPLETE BIT(4) 27 #define ACT_CTRL_OPCODE_ACTIVATE BIT(0) 28 #define ACT_CTRL_OPCODE_DEACTIVATE BIT(1) 29 #define ACT_CTRL_ACT_TRIG BIT(0) 30 #define ACT_CTRL_OPCODE_SHIFT 0x01 31 #define ATTR1_PROBE_TARGET_WAYS_SHIFT 0x02 32 #define ATTR1_FIXED_SIZE_SHIFT 0x03 33 #define ATTR1_PRIORITY_SHIFT 0x04 34 #define ATTR1_MAX_CAP_SHIFT 0x10 35 #define ATTR0_RES_WAYS_MASK GENMASK(15, 0) 36 #define ATTR0_BONUS_WAYS_MASK GENMASK(31, 16) 37 #define ATTR0_BONUS_WAYS_SHIFT 0x10 38 #define LLCC_STATUS_READ_DELAY 100 39 40 #define CACHE_LINE_SIZE_SHIFT 6 41 42 #define LLCC_LB_CNT_MASK GENMASK(31, 28) 43 #define LLCC_LB_CNT_SHIFT 28 44 45 #define MAX_CAP_TO_BYTES(n) (n * SZ_1K) 46 #define LLCC_TRP_ACT_CTRLn(n) (n * SZ_4K) 47 #define LLCC_TRP_ACT_CLEARn(n) (8 + n * SZ_4K) 48 #define LLCC_TRP_STATUSn(n) (4 + n * SZ_4K) 49 #define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n) 50 #define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n) 51 #define LLCC_TRP_ATTR2_CFGn(n) (0x21100 + SZ_4 * n) 52 53 #define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00 54 #define LLCC_TRP_PCB_ACT 0x21f04 55 #define LLCC_TRP_ALGO_CFG1 0x21f0c 56 #define LLCC_TRP_ALGO_CFG2 0x21f10 57 #define LLCC_TRP_ALGO_CFG3 0x21f14 58 #define LLCC_TRP_ALGO_CFG4 0x21f18 59 #define LLCC_TRP_ALGO_CFG5 0x21f1c 60 #define LLCC_TRP_WRSC_EN 0x21f20 61 #define LLCC_TRP_ALGO_CFG6 0x21f24 62 #define LLCC_TRP_ALGO_CFG7 0x21f28 63 #define LLCC_TRP_WRSC_CACHEABLE_EN 0x21f2c 64 #define LLCC_TRP_ALGO_CFG8 0x21f30 65 66 #define LLCC_VERSION_2_0_0_0 0x02000000 67 #define LLCC_VERSION_2_1_0_0 0x02010000 68 #define LLCC_VERSION_4_1_0_0 0x04010000 69 70 /** 71 * struct llcc_slice_config - Data associated with the llcc slice 72 * @usecase_id: Unique id for the client's use case 73 * @slice_id: llcc slice id for each client 74 * @max_cap: The maximum capacity of the cache slice provided in KB 75 * @priority: Priority of the client used to select victim line for replacement 76 * @fixed_size: Boolean indicating if the slice has a fixed capacity 77 * @bonus_ways: Bonus ways are additional ways to be used for any slice, 78 * if client ends up using more than reserved cache ways. Bonus 79 * ways are allocated only if they are not reserved for some 80 * other client. 81 * @res_ways: Reserved ways for the cache slice, the reserved ways cannot 82 * be used by any other client than the one its assigned to. 83 * @cache_mode: Each slice operates as a cache, this controls the mode of the 84 * slice: normal or TCM(Tightly Coupled Memory) 85 * @probe_target_ways: Determines what ways to probe for access hit. When 86 * configured to 1 only bonus and reserved ways are probed. 87 * When configured to 0 all ways in llcc are probed. 88 * @dis_cap_alloc: Disable capacity based allocation for a client 89 * @retain_on_pc: If this bit is set and client has maintained active vote 90 * then the ways assigned to this client are not flushed on power 91 * collapse. 92 * @activate_on_init: Activate the slice immediately after it is programmed 93 * @write_scid_en: Bit enables write cache support for a given scid. 94 * @write_scid_cacheable_en: Enables write cache cacheable support for a 95 * given scid (not supported on v2 or older hardware). 96 * @stale_en: Bit enables stale. 97 * @stale_cap_en: Bit enables stale only if current scid is over-cap. 98 * @mru_uncap_en: Roll-over on reserved cache ways if current scid is 99 * under-cap. 100 * @mru_rollover: Roll-over on reserved cache ways. 101 * @alloc_oneway_en: Allways allocate one way on over-cap even if there's no 102 * same-scid lines for replacement. 103 * @ovcap_en: Once current scid is over-capacity, allocate other over-cap SCID. 104 * @ovcap_prio: Once current scid is over-capacity, allocate other low priority 105 * over-cap scid. Depends on corresponding bit being set in 106 * ovcap_en. 107 * @vict_prio: When current scid is under-capacity, allocate over other 108 * lower-than victim priority-line threshold scid. 109 */ 110 struct llcc_slice_config { 111 u32 usecase_id; 112 u32 slice_id; 113 u32 max_cap; 114 u32 priority; 115 bool fixed_size; 116 u32 bonus_ways; 117 u32 res_ways; 118 u32 cache_mode; 119 u32 probe_target_ways; 120 bool dis_cap_alloc; 121 bool retain_on_pc; 122 bool activate_on_init; 123 bool write_scid_en; 124 bool write_scid_cacheable_en; 125 bool stale_en; 126 bool stale_cap_en; 127 bool mru_uncap_en; 128 bool mru_rollover; 129 bool alloc_oneway_en; 130 bool ovcap_en; 131 bool ovcap_prio; 132 bool vict_prio; 133 }; 134 135 struct qcom_llcc_config { 136 const struct llcc_slice_config *sct_data; 137 const u32 *reg_offset; 138 const struct llcc_edac_reg_offset *edac_reg_offset; 139 int size; 140 bool need_llcc_cfg; 141 bool no_edac; 142 }; 143 144 struct qcom_sct_config { 145 const struct qcom_llcc_config *llcc_config; 146 int num_config; 147 }; 148 149 enum llcc_reg_offset { 150 LLCC_COMMON_HW_INFO, 151 LLCC_COMMON_STATUS0, 152 }; 153 154 static const struct llcc_slice_config sa8775p_data[] = { 155 {LLCC_CPUSS, 1, 2048, 1, 0, 0x00FF, 0x0, 0, 0, 0, 1, 1, 0, 0}, 156 {LLCC_VIDSC0, 2, 512, 3, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0}, 157 {LLCC_CPUSS1, 3, 1024, 1, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0}, 158 {LLCC_CPUHWT, 5, 512, 1, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0}, 159 {LLCC_AUDIO, 6, 1024, 1, 1, 0x00FF, 0x0, 0, 0, 0, 0, 0, 0, 0}, 160 {LLCC_CMPT, 10, 4096, 1, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0}, 161 {LLCC_GPUHTW, 11, 1024, 1, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0}, 162 {LLCC_GPU, 12, 1024, 1, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 1, 0}, 163 {LLCC_MMUHWT, 13, 1024, 1, 1, 0x00FF, 0x0, 0, 0, 0, 0, 1, 0, 0}, 164 {LLCC_CMPTDMA, 15, 1024, 1, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0}, 165 {LLCC_DISP, 16, 4096, 2, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0}, 166 {LLCC_VIDFW, 17, 3072, 1, 0, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0}, 167 {LLCC_AUDHW, 22, 1024, 1, 1, 0x00FF, 0x0, 0, 0, 0, 0, 0, 0, 0}, 168 {LLCC_CVP, 28, 256, 3, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0}, 169 {LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0xF0, 1, 0, 0, 1, 0, 0, 0}, 170 {LLCC_WRCACHE, 31, 512, 1, 1, 0x00FF, 0x0, 0, 0, 0, 0, 1, 0, 0}, 171 }; 172 173 static const struct llcc_slice_config sc7180_data[] = { 174 { LLCC_CPUSS, 1, 256, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 1 }, 175 { LLCC_MDM, 8, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 }, 176 { LLCC_GPUHTW, 11, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 }, 177 { LLCC_GPU, 12, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 }, 178 }; 179 180 static const struct llcc_slice_config sc7280_data[] = { 181 { LLCC_CPUSS, 1, 768, 1, 0, 0x3f, 0x0, 0, 0, 0, 1, 1, 0}, 182 { LLCC_MDMHPGRW, 7, 512, 2, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 183 { LLCC_CMPT, 10, 768, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 184 { LLCC_GPUHTW, 11, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 185 { LLCC_GPU, 12, 512, 1, 0, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 186 { LLCC_MMUHWT, 13, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 0, 1, 0}, 187 { LLCC_MDMPNG, 21, 768, 0, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 188 { LLCC_WLHW, 24, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 189 { LLCC_MODPE, 29, 64, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 190 }; 191 192 static const struct llcc_slice_config sc8180x_data[] = { 193 { LLCC_CPUSS, 1, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1 }, 194 { LLCC_VIDSC0, 2, 512, 2, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 195 { LLCC_VIDSC1, 3, 512, 2, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 196 { LLCC_AUDIO, 6, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 197 { LLCC_MDMHPGRW, 7, 3072, 1, 1, 0x3ff, 0xc00, 0, 0, 0, 1, 0 }, 198 { LLCC_MDM, 8, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 199 { LLCC_MODHW, 9, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 200 { LLCC_CMPT, 10, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 201 { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 202 { LLCC_GPU, 12, 5120, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 203 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1 }, 204 { LLCC_CMPTDMA, 15, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 205 { LLCC_DISP, 16, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 206 { LLCC_VIDFW, 17, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 207 { LLCC_MDMHPFX, 20, 1024, 2, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 208 { LLCC_MDMPNG, 21, 1024, 0, 1, 0xc, 0x0, 0, 0, 0, 1, 0 }, 209 { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 210 { LLCC_NPU, 23, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 211 { LLCC_WLHW, 24, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 212 { LLCC_MODPE, 29, 512, 1, 1, 0xc, 0x0, 0, 0, 0, 1, 0 }, 213 { LLCC_APTCM, 30, 512, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0 }, 214 { LLCC_WRCACHE, 31, 128, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0 }, 215 }; 216 217 static const struct llcc_slice_config sc8280xp_data[] = { 218 { LLCC_CPUSS, 1, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 }, 219 { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 220 { LLCC_AUDIO, 6, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, 221 { LLCC_CMPT, 10, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, 222 { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 223 { LLCC_GPU, 12, 4096, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 1 }, 224 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 225 { LLCC_DISP, 16, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 226 { LLCC_AUDHW, 22, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 227 { LLCC_ECC, 26, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 228 { LLCC_CVP, 28, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 229 { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0, 0 }, 230 { LLCC_WRCACHE, 31, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 231 { LLCC_CVPFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 232 { LLCC_CPUSS1, 3, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 233 { LLCC_CPUHWT, 5, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 234 }; 235 236 static const struct llcc_slice_config sdm845_data[] = { 237 { LLCC_CPUSS, 1, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 1 }, 238 { LLCC_VIDSC0, 2, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 }, 239 { LLCC_VIDSC1, 3, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 }, 240 { LLCC_ROTATOR, 4, 563, 2, 1, 0x0, 0x00e, 2, 0, 1, 1, 0 }, 241 { LLCC_VOICE, 5, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 242 { LLCC_AUDIO, 6, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 243 { LLCC_MDMHPGRW, 7, 1024, 2, 0, 0xfc, 0xf00, 0, 0, 1, 1, 0 }, 244 { LLCC_MDM, 8, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 245 { LLCC_CMPT, 10, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 246 { LLCC_GPUHTW, 11, 512, 1, 1, 0xc, 0x0, 0, 0, 1, 1, 0 }, 247 { LLCC_GPU, 12, 2304, 1, 0, 0xff0, 0x2, 0, 0, 1, 1, 0 }, 248 { LLCC_MMUHWT, 13, 256, 2, 0, 0x0, 0x1, 0, 0, 1, 0, 1 }, 249 { LLCC_CMPTDMA, 15, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 250 { LLCC_DISP, 16, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 251 { LLCC_VIDFW, 17, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 252 { LLCC_MDMHPFX, 20, 1024, 2, 1, 0x0, 0xf00, 0, 0, 1, 1, 0 }, 253 { LLCC_MDMPNG, 21, 1024, 0, 1, 0x1e, 0x0, 0, 0, 1, 1, 0 }, 254 { LLCC_AUDHW, 22, 1024, 1, 1, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 255 }; 256 257 static const struct llcc_slice_config sm6350_data[] = { 258 { LLCC_CPUSS, 1, 768, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 1 }, 259 { LLCC_MDM, 8, 512, 2, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 260 { LLCC_GPUHTW, 11, 256, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 261 { LLCC_GPU, 12, 512, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 262 { LLCC_MDMPNG, 21, 768, 0, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 263 { LLCC_NPU, 23, 768, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 264 { LLCC_MODPE, 29, 64, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 265 }; 266 267 static const struct llcc_slice_config sm7150_data[] = { 268 { LLCC_CPUSS, 1, 512, 1, 0, 0xF, 0x0, 0, 0, 0, 1, 1 }, 269 { LLCC_MDM, 8, 128, 2, 0, 0xF, 0x0, 0, 0, 0, 1, 0 }, 270 { LLCC_GPUHTW, 11, 256, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0 }, 271 { LLCC_GPU, 12, 256, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0 }, 272 { LLCC_NPU, 23, 512, 1, 0, 0xF, 0x0, 0, 0, 0, 1, 0 }, 273 }; 274 275 static const struct llcc_slice_config sm8150_data[] = { 276 { LLCC_CPUSS, 1, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 1 }, 277 { LLCC_VIDSC0, 2, 512, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 278 { LLCC_VIDSC1, 3, 512, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 279 { LLCC_AUDIO, 6, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 280 { LLCC_MDMHPGRW, 7, 3072, 1, 0, 0xFF, 0xF00, 0, 0, 0, 1, 0 }, 281 { LLCC_MDM, 8, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 282 { LLCC_MODHW, 9, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 283 { LLCC_CMPT, 10, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 284 { LLCC_GPUHTW , 11, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 285 { LLCC_GPU, 12, 2560, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 286 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1 }, 287 { LLCC_CMPTDMA, 15, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 288 { LLCC_DISP, 16, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 289 { LLCC_MDMHPFX, 20, 1024, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 290 { LLCC_MDMHPFX, 21, 1024, 0, 1, 0xF, 0x0, 0, 0, 0, 1, 0 }, 291 { LLCC_AUDHW, 22, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 292 { LLCC_NPU, 23, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 293 { LLCC_WLHW, 24, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 294 { LLCC_MODPE, 29, 256, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0 }, 295 { LLCC_APTCM, 30, 256, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0 }, 296 { LLCC_WRCACHE, 31, 128, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0 }, 297 }; 298 299 static const struct llcc_slice_config sm8250_data[] = { 300 { LLCC_CPUSS, 1, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 }, 301 { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 302 { LLCC_AUDIO, 6, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, 303 { LLCC_CMPT, 10, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, 304 { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 305 { LLCC_GPU, 12, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 1 }, 306 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 307 { LLCC_CMPTDMA, 15, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 308 { LLCC_DISP, 16, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 309 { LLCC_VIDFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 310 { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 311 { LLCC_NPU, 23, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 312 { LLCC_WLHW, 24, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 313 { LLCC_CVP, 28, 256, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 314 { LLCC_APTCM, 30, 128, 3, 0, 0x0, 0x3, 1, 0, 0, 1, 0, 0 }, 315 { LLCC_WRCACHE, 31, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 316 }; 317 318 static const struct llcc_slice_config sm8350_data[] = { 319 { LLCC_CPUSS, 1, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 1 }, 320 { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 321 { LLCC_AUDIO, 6, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, 322 { LLCC_MDMHPGRW, 7, 1024, 3, 0, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 323 { LLCC_MODHW, 9, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 324 { LLCC_CMPT, 10, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 325 { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 326 { LLCC_GPU, 12, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 }, 327 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 }, 328 { LLCC_DISP, 16, 3072, 2, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 329 { LLCC_MDMPNG, 21, 1024, 0, 1, 0xf, 0x0, 0, 0, 0, 0, 1, 0 }, 330 { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 331 { LLCC_CVP, 28, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 332 { LLCC_MODPE, 29, 256, 1, 1, 0xf, 0x0, 0, 0, 0, 0, 1, 0 }, 333 { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0x1, 1, 0, 0, 0, 1, 0 }, 334 { LLCC_WRCACHE, 31, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 }, 335 { LLCC_CVPFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 336 { LLCC_CPUSS1, 3, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 337 { LLCC_CPUHWT, 5, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 }, 338 }; 339 340 static const struct llcc_slice_config sm8450_data[] = { 341 {LLCC_CPUSS, 1, 3072, 1, 0, 0xFFFF, 0x0, 0, 0, 0, 1, 1, 0, 0 }, 342 {LLCC_VIDSC0, 2, 512, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 343 {LLCC_AUDIO, 6, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 }, 344 {LLCC_MDMHPGRW, 7, 1024, 3, 0, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 345 {LLCC_MODHW, 9, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 346 {LLCC_CMPT, 10, 4096, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 347 {LLCC_GPUHTW, 11, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 348 {LLCC_GPU, 12, 2048, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 1, 0 }, 349 {LLCC_MMUHWT, 13, 768, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0 }, 350 {LLCC_DISP, 16, 4096, 2, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 351 {LLCC_MDMPNG, 21, 1024, 1, 1, 0xF000, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 352 {LLCC_AUDHW, 22, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 }, 353 {LLCC_CVP, 28, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 354 {LLCC_MODPE, 29, 64, 1, 1, 0xF000, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 355 {LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0xF0, 1, 0, 0, 1, 0, 0, 0 }, 356 {LLCC_WRCACHE, 31, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0 }, 357 {LLCC_CVPFW, 17, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 358 {LLCC_CPUSS1, 3, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 359 {LLCC_CAMEXP0, 4, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 360 {LLCC_CPUMTE, 23, 256, 1, 1, 0x0FFF, 0x0, 0, 0, 0, 0, 1, 0, 0 }, 361 {LLCC_CPUHWT, 5, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 1, 0, 0 }, 362 {LLCC_CAMEXP1, 27, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 363 {LLCC_AENPU, 8, 2048, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 }, 364 }; 365 366 static const struct llcc_slice_config sm8550_data[] = { 367 {LLCC_CPUSS, 1, 5120, 1, 0, 0xFFFFFF, 0x0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 368 {LLCC_VIDSC0, 2, 512, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 369 {LLCC_AUDIO, 6, 1024, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 370 {LLCC_MDMHPGRW, 25, 1024, 4, 0, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 371 {LLCC_MODHW, 26, 1024, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 372 {LLCC_CMPT, 10, 4096, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 373 {LLCC_GPUHTW, 11, 512, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 374 {LLCC_GPU, 9, 3096, 1, 0, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, }, 375 {LLCC_MMUHWT, 18, 768, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 376 {LLCC_DISP, 16, 6144, 1, 1, 0xFFFFFF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 377 {LLCC_MDMPNG, 27, 1024, 0, 1, 0xF00000, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 378 {LLCC_AUDHW, 22, 1024, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 379 {LLCC_CVP, 8, 256, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 380 {LLCC_MODPE, 29, 64, 1, 1, 0xF00000, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, }, 381 {LLCC_WRCACHE, 31, 512, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 382 {LLCC_CAMEXP0, 4, 256, 4, 1, 0xF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 383 {LLCC_CPUHWT, 5, 512, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 384 {LLCC_CAMEXP1, 7, 3200, 3, 1, 0xFFFFF0, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 385 {LLCC_CMPTHCP, 17, 256, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 386 {LLCC_LCPDARE, 30, 128, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, }, 387 {LLCC_AENPU, 3, 3072, 1, 1, 0xFE01FF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 388 {LLCC_ISLAND1, 12, 1792, 7, 1, 0xFE00, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 389 {LLCC_ISLAND4, 15, 256, 7, 1, 0x10000, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 390 {LLCC_CAMEXP2, 19, 3200, 3, 1, 0xFFFFF0, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 391 {LLCC_CAMEXP3, 20, 3200, 2, 1, 0xFFFFF0, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 392 {LLCC_CAMEXP4, 21, 3200, 2, 1, 0xFFFFF0, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 393 {LLCC_DISP_WB, 23, 1024, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 394 {LLCC_DISP_1, 24, 6144, 1, 1, 0xFFFFFF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 395 {LLCC_VIDVSP, 28, 256, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 396 }; 397 398 static const struct llcc_slice_config sm8650_data[] = { 399 {LLCC_CPUSS, 1, 5120, 1, 0, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0}, 400 {LLCC_VIDSC0, 2, 512, 3, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 401 {LLCC_AUDIO, 6, 512, 1, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 402 {LLCC_MDMHPGRW, 25, 1024, 3, 0, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 403 {LLCC_MODHW, 26, 1024, 1, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 404 {LLCC_CMPT, 10, 4096, 1, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 405 {LLCC_GPUHTW, 11, 512, 1, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 406 {LLCC_GPU, 9, 3096, 1, 0, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0}, 407 {LLCC_MMUHWT, 18, 768, 1, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 408 {LLCC_DISP, 16, 6144, 1, 1, 0xFFFFFF, 0x0, 2, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 409 {LLCC_MDMHPFX, 24, 1024, 3, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 410 {LLCC_MDMPNG, 27, 1024, 0, 1, 0x000000, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 411 {LLCC_AUDHW, 22, 1024, 1, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 412 {LLCC_CVP, 8, 256, 3, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 413 {LLCC_MODPE, 29, 128, 1, 1, 0xF00000, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0}, 414 {LLCC_WRCACHE, 31, 512, 1, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 415 {LLCC_CAMEXP0, 4, 256, 3, 1, 0xF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 416 {LLCC_CAMEXP1, 7, 3200, 3, 1, 0xFFFFF0, 0x0, 2, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 417 {LLCC_CMPTHCP, 17, 256, 3, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 418 {LLCC_LCPDARE, 30, 128, 3, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0}, 419 {LLCC_AENPU, 3, 3072, 1, 1, 0xFFFFFF, 0x0, 2, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 420 {LLCC_ISLAND1, 12, 5888, 7, 1, 0x0, 0x7FFFFF, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 421 {LLCC_DISP_WB, 23, 1024, 3, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 422 {LLCC_VIDVSP, 28, 256, 3, 1, 0xFFFFFF, 0x0, 0, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 423 }; 424 425 static const struct llcc_slice_config qdu1000_data_2ch[] = { 426 { LLCC_MDMHPGRW, 7, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 427 { LLCC_MODHW, 9, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 428 { LLCC_MDMPNG, 21, 256, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 429 { LLCC_ECC, 26, 512, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 }, 430 { LLCC_MODPE, 29, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 431 { LLCC_APTCM, 30, 256, 3, 1, 0x0, 0xc, 1, 0, 0, 1, 0, 0, 0 }, 432 { LLCC_WRCACHE, 31, 128, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 }, 433 }; 434 435 static const struct llcc_slice_config qdu1000_data_4ch[] = { 436 { LLCC_MDMHPGRW, 7, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 437 { LLCC_MODHW, 9, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 438 { LLCC_MDMPNG, 21, 512, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 439 { LLCC_ECC, 26, 1024, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 }, 440 { LLCC_MODPE, 29, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 441 { LLCC_APTCM, 30, 512, 3, 1, 0x0, 0xc, 1, 0, 0, 1, 0, 0, 0 }, 442 { LLCC_WRCACHE, 31, 256, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 }, 443 }; 444 445 static const struct llcc_slice_config qdu1000_data_8ch[] = { 446 { LLCC_MDMHPGRW, 7, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 447 { LLCC_MODHW, 9, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 448 { LLCC_MDMPNG, 21, 1024, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 449 { LLCC_ECC, 26, 2048, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 }, 450 { LLCC_MODPE, 29, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 451 { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0xc, 1, 0, 0, 1, 0, 0, 0 }, 452 { LLCC_WRCACHE, 31, 512, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 }, 453 }; 454 455 static const struct llcc_slice_config x1e80100_data[] = { 456 {LLCC_CPUSS, 1, 6144, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 457 {LLCC_VIDSC0, 2, 512, 4, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 458 {LLCC_AUDIO, 6, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 459 {LLCC_CMPT, 10, 6144, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 460 {LLCC_GPUHTW, 11, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 461 {LLCC_GPU, 9, 4608, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0}, 462 {LLCC_MMUHWT, 18, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 463 {LLCC_AUDHW, 22, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 464 {LLCC_CVP, 8, 512, 4, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 465 {LLCC_WRCACHE, 31, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 466 {LLCC_CAMEXP0, 4, 256, 4, 1, 0x3, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 467 {LLCC_CAMEXP1, 7, 3072, 3, 1, 0xFFC, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 468 {LLCC_LCPDARE, 30, 512, 3, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0}, 469 {LLCC_AENPU, 3, 3072, 1, 1, 0xFFF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 470 {LLCC_ISLAND1, 12, 2048, 7, 1, 0x0, 0xF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 471 {LLCC_CAMEXP2, 19, 3072, 3, 1, 0xFFC, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 472 {LLCC_CAMEXP3, 20, 3072, 2, 1, 0xFFC, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 473 {LLCC_CAMEXP4, 21, 3072, 2, 1, 0xFFC, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 474 }; 475 476 static const struct llcc_edac_reg_offset llcc_v1_edac_reg_offset = { 477 .trp_ecc_error_status0 = 0x20344, 478 .trp_ecc_error_status1 = 0x20348, 479 .trp_ecc_sb_err_syn0 = 0x2304c, 480 .trp_ecc_db_err_syn0 = 0x20370, 481 .trp_ecc_error_cntr_clear = 0x20440, 482 .trp_interrupt_0_status = 0x20480, 483 .trp_interrupt_0_clear = 0x20484, 484 .trp_interrupt_0_enable = 0x20488, 485 486 /* LLCC Common registers */ 487 .cmn_status0 = 0x3000c, 488 .cmn_interrupt_0_enable = 0x3001c, 489 .cmn_interrupt_2_enable = 0x3003c, 490 491 /* LLCC DRP registers */ 492 .drp_ecc_error_cfg = 0x40000, 493 .drp_ecc_error_cntr_clear = 0x40004, 494 .drp_interrupt_status = 0x41000, 495 .drp_interrupt_clear = 0x41008, 496 .drp_interrupt_enable = 0x4100c, 497 .drp_ecc_error_status0 = 0x42044, 498 .drp_ecc_error_status1 = 0x42048, 499 .drp_ecc_sb_err_syn0 = 0x4204c, 500 .drp_ecc_db_err_syn0 = 0x42070, 501 }; 502 503 static const struct llcc_edac_reg_offset llcc_v2_1_edac_reg_offset = { 504 .trp_ecc_error_status0 = 0x20344, 505 .trp_ecc_error_status1 = 0x20348, 506 .trp_ecc_sb_err_syn0 = 0x2034c, 507 .trp_ecc_db_err_syn0 = 0x20370, 508 .trp_ecc_error_cntr_clear = 0x20440, 509 .trp_interrupt_0_status = 0x20480, 510 .trp_interrupt_0_clear = 0x20484, 511 .trp_interrupt_0_enable = 0x20488, 512 513 /* LLCC Common registers */ 514 .cmn_status0 = 0x3400c, 515 .cmn_interrupt_0_enable = 0x3401c, 516 .cmn_interrupt_2_enable = 0x3403c, 517 518 /* LLCC DRP registers */ 519 .drp_ecc_error_cfg = 0x50000, 520 .drp_ecc_error_cntr_clear = 0x50004, 521 .drp_interrupt_status = 0x50020, 522 .drp_interrupt_clear = 0x50028, 523 .drp_interrupt_enable = 0x5002c, 524 .drp_ecc_error_status0 = 0x520f4, 525 .drp_ecc_error_status1 = 0x520f8, 526 .drp_ecc_sb_err_syn0 = 0x520fc, 527 .drp_ecc_db_err_syn0 = 0x52120, 528 }; 529 530 /* LLCC register offset starting from v1.0.0 */ 531 static const u32 llcc_v1_reg_offset[] = { 532 [LLCC_COMMON_HW_INFO] = 0x00030000, 533 [LLCC_COMMON_STATUS0] = 0x0003000c, 534 }; 535 536 /* LLCC register offset starting from v2.0.1 */ 537 static const u32 llcc_v2_1_reg_offset[] = { 538 [LLCC_COMMON_HW_INFO] = 0x00034000, 539 [LLCC_COMMON_STATUS0] = 0x0003400c, 540 }; 541 542 static const struct qcom_llcc_config qdu1000_cfg[] = { 543 { 544 .sct_data = qdu1000_data_8ch, 545 .size = ARRAY_SIZE(qdu1000_data_8ch), 546 .need_llcc_cfg = true, 547 .reg_offset = llcc_v2_1_reg_offset, 548 .edac_reg_offset = &llcc_v2_1_edac_reg_offset, 549 }, 550 { 551 .sct_data = qdu1000_data_4ch, 552 .size = ARRAY_SIZE(qdu1000_data_4ch), 553 .need_llcc_cfg = true, 554 .reg_offset = llcc_v2_1_reg_offset, 555 .edac_reg_offset = &llcc_v2_1_edac_reg_offset, 556 }, 557 { 558 .sct_data = qdu1000_data_4ch, 559 .size = ARRAY_SIZE(qdu1000_data_4ch), 560 .need_llcc_cfg = true, 561 .reg_offset = llcc_v2_1_reg_offset, 562 .edac_reg_offset = &llcc_v2_1_edac_reg_offset, 563 }, 564 { 565 .sct_data = qdu1000_data_2ch, 566 .size = ARRAY_SIZE(qdu1000_data_2ch), 567 .need_llcc_cfg = true, 568 .reg_offset = llcc_v2_1_reg_offset, 569 .edac_reg_offset = &llcc_v2_1_edac_reg_offset, 570 }, 571 }; 572 573 static const struct qcom_llcc_config sa8775p_cfg[] = { 574 { 575 .sct_data = sa8775p_data, 576 .size = ARRAY_SIZE(sa8775p_data), 577 .need_llcc_cfg = true, 578 .reg_offset = llcc_v2_1_reg_offset, 579 .edac_reg_offset = &llcc_v2_1_edac_reg_offset, 580 }, 581 }; 582 583 static const struct qcom_llcc_config sc7180_cfg[] = { 584 { 585 .sct_data = sc7180_data, 586 .size = ARRAY_SIZE(sc7180_data), 587 .need_llcc_cfg = true, 588 .reg_offset = llcc_v1_reg_offset, 589 .edac_reg_offset = &llcc_v1_edac_reg_offset, 590 }, 591 }; 592 593 static const struct qcom_llcc_config sc7280_cfg[] = { 594 { 595 .sct_data = sc7280_data, 596 .size = ARRAY_SIZE(sc7280_data), 597 .need_llcc_cfg = true, 598 .reg_offset = llcc_v1_reg_offset, 599 .edac_reg_offset = &llcc_v1_edac_reg_offset, 600 }, 601 }; 602 603 static const struct qcom_llcc_config sc8180x_cfg[] = { 604 { 605 .sct_data = sc8180x_data, 606 .size = ARRAY_SIZE(sc8180x_data), 607 .need_llcc_cfg = true, 608 .reg_offset = llcc_v1_reg_offset, 609 .edac_reg_offset = &llcc_v1_edac_reg_offset, 610 }, 611 }; 612 613 static const struct qcom_llcc_config sc8280xp_cfg[] = { 614 { 615 .sct_data = sc8280xp_data, 616 .size = ARRAY_SIZE(sc8280xp_data), 617 .need_llcc_cfg = true, 618 .reg_offset = llcc_v1_reg_offset, 619 .edac_reg_offset = &llcc_v1_edac_reg_offset, 620 }, 621 }; 622 623 static const struct qcom_llcc_config sdm845_cfg[] = { 624 { 625 .sct_data = sdm845_data, 626 .size = ARRAY_SIZE(sdm845_data), 627 .need_llcc_cfg = false, 628 .reg_offset = llcc_v1_reg_offset, 629 .edac_reg_offset = &llcc_v1_edac_reg_offset, 630 .no_edac = true, 631 }, 632 }; 633 634 static const struct qcom_llcc_config sm6350_cfg[] = { 635 { 636 .sct_data = sm6350_data, 637 .size = ARRAY_SIZE(sm6350_data), 638 .need_llcc_cfg = true, 639 .reg_offset = llcc_v1_reg_offset, 640 .edac_reg_offset = &llcc_v1_edac_reg_offset, 641 }, 642 }; 643 644 static const struct qcom_llcc_config sm7150_cfg[] = { 645 { 646 .sct_data = sm7150_data, 647 .size = ARRAY_SIZE(sm7150_data), 648 .need_llcc_cfg = true, 649 .reg_offset = llcc_v1_reg_offset, 650 .edac_reg_offset = &llcc_v1_edac_reg_offset, 651 }, 652 }; 653 654 static const struct qcom_llcc_config sm8150_cfg[] = { 655 { 656 .sct_data = sm8150_data, 657 .size = ARRAY_SIZE(sm8150_data), 658 .need_llcc_cfg = true, 659 .reg_offset = llcc_v1_reg_offset, 660 .edac_reg_offset = &llcc_v1_edac_reg_offset, 661 }, 662 }; 663 664 static const struct qcom_llcc_config sm8250_cfg[] = { 665 { 666 .sct_data = sm8250_data, 667 .size = ARRAY_SIZE(sm8250_data), 668 .need_llcc_cfg = true, 669 .reg_offset = llcc_v1_reg_offset, 670 .edac_reg_offset = &llcc_v1_edac_reg_offset, 671 }, 672 }; 673 674 static const struct qcom_llcc_config sm8350_cfg[] = { 675 { 676 .sct_data = sm8350_data, 677 .size = ARRAY_SIZE(sm8350_data), 678 .need_llcc_cfg = true, 679 .reg_offset = llcc_v1_reg_offset, 680 .edac_reg_offset = &llcc_v1_edac_reg_offset, 681 }, 682 }; 683 684 static const struct qcom_llcc_config sm8450_cfg[] = { 685 { 686 .sct_data = sm8450_data, 687 .size = ARRAY_SIZE(sm8450_data), 688 .need_llcc_cfg = true, 689 .reg_offset = llcc_v2_1_reg_offset, 690 .edac_reg_offset = &llcc_v2_1_edac_reg_offset, 691 }, 692 }; 693 694 static const struct qcom_llcc_config sm8550_cfg[] = { 695 { 696 .sct_data = sm8550_data, 697 .size = ARRAY_SIZE(sm8550_data), 698 .need_llcc_cfg = true, 699 .reg_offset = llcc_v2_1_reg_offset, 700 .edac_reg_offset = &llcc_v2_1_edac_reg_offset, 701 }, 702 }; 703 704 static const struct qcom_llcc_config sm8650_cfg[] = { 705 { 706 .sct_data = sm8650_data, 707 .size = ARRAY_SIZE(sm8650_data), 708 .need_llcc_cfg = true, 709 .reg_offset = llcc_v2_1_reg_offset, 710 .edac_reg_offset = &llcc_v2_1_edac_reg_offset, 711 }, 712 }; 713 714 static const struct qcom_llcc_config x1e80100_cfg[] = { 715 { 716 .sct_data = x1e80100_data, 717 .size = ARRAY_SIZE(x1e80100_data), 718 .need_llcc_cfg = true, 719 .reg_offset = llcc_v2_1_reg_offset, 720 .edac_reg_offset = &llcc_v2_1_edac_reg_offset, 721 }, 722 }; 723 724 static const struct qcom_sct_config qdu1000_cfgs = { 725 .llcc_config = qdu1000_cfg, 726 .num_config = ARRAY_SIZE(qdu1000_cfg), 727 }; 728 729 static const struct qcom_sct_config sa8775p_cfgs = { 730 .llcc_config = sa8775p_cfg, 731 .num_config = ARRAY_SIZE(sa8775p_cfg), 732 }; 733 734 static const struct qcom_sct_config sc7180_cfgs = { 735 .llcc_config = sc7180_cfg, 736 .num_config = ARRAY_SIZE(sc7180_cfg), 737 }; 738 739 static const struct qcom_sct_config sc7280_cfgs = { 740 .llcc_config = sc7280_cfg, 741 .num_config = ARRAY_SIZE(sc7280_cfg), 742 }; 743 744 static const struct qcom_sct_config sc8180x_cfgs = { 745 .llcc_config = sc8180x_cfg, 746 .num_config = ARRAY_SIZE(sc8180x_cfg), 747 }; 748 749 static const struct qcom_sct_config sc8280xp_cfgs = { 750 .llcc_config = sc8280xp_cfg, 751 .num_config = ARRAY_SIZE(sc8280xp_cfg), 752 }; 753 754 static const struct qcom_sct_config sdm845_cfgs = { 755 .llcc_config = sdm845_cfg, 756 .num_config = ARRAY_SIZE(sdm845_cfg), 757 }; 758 759 static const struct qcom_sct_config sm6350_cfgs = { 760 .llcc_config = sm6350_cfg, 761 .num_config = ARRAY_SIZE(sm6350_cfg), 762 }; 763 764 static const struct qcom_sct_config sm7150_cfgs = { 765 .llcc_config = sm7150_cfg, 766 .num_config = ARRAY_SIZE(sm7150_cfg), 767 }; 768 769 static const struct qcom_sct_config sm8150_cfgs = { 770 .llcc_config = sm8150_cfg, 771 .num_config = ARRAY_SIZE(sm8150_cfg), 772 }; 773 774 static const struct qcom_sct_config sm8250_cfgs = { 775 .llcc_config = sm8250_cfg, 776 .num_config = ARRAY_SIZE(sm8250_cfg), 777 }; 778 779 static const struct qcom_sct_config sm8350_cfgs = { 780 .llcc_config = sm8350_cfg, 781 .num_config = ARRAY_SIZE(sm8350_cfg), 782 }; 783 784 static const struct qcom_sct_config sm8450_cfgs = { 785 .llcc_config = sm8450_cfg, 786 .num_config = ARRAY_SIZE(sm8450_cfg), 787 }; 788 789 static const struct qcom_sct_config sm8550_cfgs = { 790 .llcc_config = sm8550_cfg, 791 .num_config = ARRAY_SIZE(sm8550_cfg), 792 }; 793 794 static const struct qcom_sct_config sm8650_cfgs = { 795 .llcc_config = sm8650_cfg, 796 .num_config = ARRAY_SIZE(sm8650_cfg), 797 }; 798 799 static const struct qcom_sct_config x1e80100_cfgs = { 800 .llcc_config = x1e80100_cfg, 801 .num_config = ARRAY_SIZE(x1e80100_cfg), 802 }; 803 804 static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER; 805 806 /** 807 * llcc_slice_getd - get llcc slice descriptor 808 * @uid: usecase_id for the client 809 * 810 * A pointer to llcc slice descriptor will be returned on success 811 * and error pointer is returned on failure 812 */ 813 struct llcc_slice_desc *llcc_slice_getd(u32 uid) 814 { 815 const struct llcc_slice_config *cfg; 816 struct llcc_slice_desc *desc; 817 u32 sz, count; 818 819 if (IS_ERR(drv_data)) 820 return ERR_CAST(drv_data); 821 822 cfg = drv_data->cfg; 823 sz = drv_data->cfg_size; 824 825 for (count = 0; cfg && count < sz; count++, cfg++) 826 if (cfg->usecase_id == uid) 827 break; 828 829 if (count == sz || !cfg) 830 return ERR_PTR(-ENODEV); 831 832 desc = kzalloc(sizeof(*desc), GFP_KERNEL); 833 if (!desc) 834 return ERR_PTR(-ENOMEM); 835 836 desc->slice_id = cfg->slice_id; 837 desc->slice_size = cfg->max_cap; 838 839 return desc; 840 } 841 EXPORT_SYMBOL_GPL(llcc_slice_getd); 842 843 /** 844 * llcc_slice_putd - llcc slice descriptor 845 * @desc: Pointer to llcc slice descriptor 846 */ 847 void llcc_slice_putd(struct llcc_slice_desc *desc) 848 { 849 if (!IS_ERR_OR_NULL(desc)) 850 kfree(desc); 851 } 852 EXPORT_SYMBOL_GPL(llcc_slice_putd); 853 854 static int llcc_update_act_ctrl(u32 sid, 855 u32 act_ctrl_reg_val, u32 status) 856 { 857 struct regmap *regmap; 858 u32 act_ctrl_reg; 859 u32 act_clear_reg; 860 u32 status_reg; 861 u32 slice_status; 862 int ret; 863 864 if (IS_ERR(drv_data)) 865 return PTR_ERR(drv_data); 866 867 act_ctrl_reg = LLCC_TRP_ACT_CTRLn(sid); 868 act_clear_reg = LLCC_TRP_ACT_CLEARn(sid); 869 status_reg = LLCC_TRP_STATUSn(sid); 870 871 /* Set the ACTIVE trigger */ 872 act_ctrl_reg_val |= ACT_CTRL_ACT_TRIG; 873 ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg, 874 act_ctrl_reg_val); 875 if (ret) 876 return ret; 877 878 /* Clear the ACTIVE trigger */ 879 act_ctrl_reg_val &= ~ACT_CTRL_ACT_TRIG; 880 ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg, 881 act_ctrl_reg_val); 882 if (ret) 883 return ret; 884 885 if (drv_data->version >= LLCC_VERSION_4_1_0_0) { 886 regmap = drv_data->bcast_and_regmap ?: drv_data->bcast_regmap; 887 ret = regmap_read_poll_timeout(regmap, status_reg, 888 slice_status, (slice_status & ACT_COMPLETE), 889 0, LLCC_STATUS_READ_DELAY); 890 if (ret) 891 return ret; 892 } 893 894 ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg, 895 slice_status, !(slice_status & status), 896 0, LLCC_STATUS_READ_DELAY); 897 if (ret) 898 return ret; 899 900 if (drv_data->version >= LLCC_VERSION_4_1_0_0) 901 ret = regmap_write(drv_data->bcast_regmap, act_clear_reg, 902 ACT_CLEAR); 903 904 return ret; 905 } 906 907 /** 908 * llcc_slice_activate - Activate the llcc slice 909 * @desc: Pointer to llcc slice descriptor 910 * 911 * A value of zero will be returned on success and a negative errno will 912 * be returned in error cases 913 */ 914 int llcc_slice_activate(struct llcc_slice_desc *desc) 915 { 916 int ret; 917 u32 act_ctrl_val; 918 919 if (IS_ERR(drv_data)) 920 return PTR_ERR(drv_data); 921 922 if (IS_ERR_OR_NULL(desc)) 923 return -EINVAL; 924 925 mutex_lock(&drv_data->lock); 926 if (test_bit(desc->slice_id, drv_data->bitmap)) { 927 mutex_unlock(&drv_data->lock); 928 return 0; 929 } 930 931 act_ctrl_val = ACT_CTRL_OPCODE_ACTIVATE << ACT_CTRL_OPCODE_SHIFT; 932 933 ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val, 934 DEACTIVATE); 935 if (ret) { 936 mutex_unlock(&drv_data->lock); 937 return ret; 938 } 939 940 __set_bit(desc->slice_id, drv_data->bitmap); 941 mutex_unlock(&drv_data->lock); 942 943 return ret; 944 } 945 EXPORT_SYMBOL_GPL(llcc_slice_activate); 946 947 /** 948 * llcc_slice_deactivate - Deactivate the llcc slice 949 * @desc: Pointer to llcc slice descriptor 950 * 951 * A value of zero will be returned on success and a negative errno will 952 * be returned in error cases 953 */ 954 int llcc_slice_deactivate(struct llcc_slice_desc *desc) 955 { 956 u32 act_ctrl_val; 957 int ret; 958 959 if (IS_ERR(drv_data)) 960 return PTR_ERR(drv_data); 961 962 if (IS_ERR_OR_NULL(desc)) 963 return -EINVAL; 964 965 mutex_lock(&drv_data->lock); 966 if (!test_bit(desc->slice_id, drv_data->bitmap)) { 967 mutex_unlock(&drv_data->lock); 968 return 0; 969 } 970 act_ctrl_val = ACT_CTRL_OPCODE_DEACTIVATE << ACT_CTRL_OPCODE_SHIFT; 971 972 ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val, 973 ACTIVATE); 974 if (ret) { 975 mutex_unlock(&drv_data->lock); 976 return ret; 977 } 978 979 __clear_bit(desc->slice_id, drv_data->bitmap); 980 mutex_unlock(&drv_data->lock); 981 982 return ret; 983 } 984 EXPORT_SYMBOL_GPL(llcc_slice_deactivate); 985 986 /** 987 * llcc_get_slice_id - return the slice id 988 * @desc: Pointer to llcc slice descriptor 989 */ 990 int llcc_get_slice_id(struct llcc_slice_desc *desc) 991 { 992 if (IS_ERR_OR_NULL(desc)) 993 return -EINVAL; 994 995 return desc->slice_id; 996 } 997 EXPORT_SYMBOL_GPL(llcc_get_slice_id); 998 999 /** 1000 * llcc_get_slice_size - return the slice id 1001 * @desc: Pointer to llcc slice descriptor 1002 */ 1003 size_t llcc_get_slice_size(struct llcc_slice_desc *desc) 1004 { 1005 if (IS_ERR_OR_NULL(desc)) 1006 return 0; 1007 1008 return desc->slice_size; 1009 } 1010 EXPORT_SYMBOL_GPL(llcc_get_slice_size); 1011 1012 static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config, 1013 const struct qcom_llcc_config *cfg) 1014 { 1015 int ret; 1016 u32 attr2_cfg; 1017 u32 attr1_cfg; 1018 u32 attr0_cfg; 1019 u32 attr2_val; 1020 u32 attr1_val; 1021 u32 attr0_val; 1022 u32 max_cap_cacheline; 1023 struct llcc_slice_desc desc; 1024 1025 attr1_val = config->cache_mode; 1026 attr1_val |= config->probe_target_ways << ATTR1_PROBE_TARGET_WAYS_SHIFT; 1027 attr1_val |= config->fixed_size << ATTR1_FIXED_SIZE_SHIFT; 1028 attr1_val |= config->priority << ATTR1_PRIORITY_SHIFT; 1029 1030 max_cap_cacheline = MAX_CAP_TO_BYTES(config->max_cap); 1031 1032 /* 1033 * LLCC instances can vary for each target. 1034 * The SW writes to broadcast register which gets propagated 1035 * to each llcc instance (llcc0,.. llccN). 1036 * Since the size of the memory is divided equally amongst the 1037 * llcc instances, we need to configure the max cap accordingly. 1038 */ 1039 max_cap_cacheline = max_cap_cacheline / drv_data->num_banks; 1040 max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT; 1041 attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT; 1042 1043 attr1_cfg = LLCC_TRP_ATTR1_CFGn(config->slice_id); 1044 1045 ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, attr1_val); 1046 if (ret) 1047 return ret; 1048 1049 if (drv_data->version >= LLCC_VERSION_4_1_0_0) { 1050 attr2_cfg = LLCC_TRP_ATTR2_CFGn(config->slice_id); 1051 attr0_val = config->res_ways; 1052 attr2_val = config->bonus_ways; 1053 } else { 1054 attr0_val = config->res_ways & ATTR0_RES_WAYS_MASK; 1055 attr0_val |= config->bonus_ways << ATTR0_BONUS_WAYS_SHIFT; 1056 } 1057 1058 attr0_cfg = LLCC_TRP_ATTR0_CFGn(config->slice_id); 1059 1060 ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, attr0_val); 1061 if (ret) 1062 return ret; 1063 1064 if (drv_data->version >= LLCC_VERSION_4_1_0_0) { 1065 ret = regmap_write(drv_data->bcast_regmap, attr2_cfg, attr2_val); 1066 if (ret) 1067 return ret; 1068 } 1069 1070 if (cfg->need_llcc_cfg) { 1071 u32 disable_cap_alloc, retain_pc; 1072 1073 disable_cap_alloc = config->dis_cap_alloc << config->slice_id; 1074 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_SCID_DIS_CAP_ALLOC, 1075 BIT(config->slice_id), disable_cap_alloc); 1076 if (ret) 1077 return ret; 1078 1079 if (drv_data->version < LLCC_VERSION_4_1_0_0) { 1080 retain_pc = config->retain_on_pc << config->slice_id; 1081 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_PCB_ACT, 1082 BIT(config->slice_id), retain_pc); 1083 if (ret) 1084 return ret; 1085 } 1086 } 1087 1088 if (drv_data->version >= LLCC_VERSION_2_0_0_0) { 1089 u32 wren; 1090 1091 wren = config->write_scid_en << config->slice_id; 1092 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_EN, 1093 BIT(config->slice_id), wren); 1094 if (ret) 1095 return ret; 1096 } 1097 1098 if (drv_data->version >= LLCC_VERSION_2_1_0_0) { 1099 u32 wr_cache_en; 1100 1101 wr_cache_en = config->write_scid_cacheable_en << config->slice_id; 1102 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_CACHEABLE_EN, 1103 BIT(config->slice_id), wr_cache_en); 1104 if (ret) 1105 return ret; 1106 } 1107 1108 if (drv_data->version >= LLCC_VERSION_4_1_0_0) { 1109 u32 stale_en; 1110 u32 stale_cap_en; 1111 u32 mru_uncap_en; 1112 u32 mru_rollover; 1113 u32 alloc_oneway_en; 1114 u32 ovcap_en; 1115 u32 ovcap_prio; 1116 u32 vict_prio; 1117 1118 stale_en = config->stale_en << config->slice_id; 1119 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG1, 1120 BIT(config->slice_id), stale_en); 1121 if (ret) 1122 return ret; 1123 1124 stale_cap_en = config->stale_cap_en << config->slice_id; 1125 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG2, 1126 BIT(config->slice_id), stale_cap_en); 1127 if (ret) 1128 return ret; 1129 1130 mru_uncap_en = config->mru_uncap_en << config->slice_id; 1131 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG3, 1132 BIT(config->slice_id), mru_uncap_en); 1133 if (ret) 1134 return ret; 1135 1136 mru_rollover = config->mru_rollover << config->slice_id; 1137 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG4, 1138 BIT(config->slice_id), mru_rollover); 1139 if (ret) 1140 return ret; 1141 1142 alloc_oneway_en = config->alloc_oneway_en << config->slice_id; 1143 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG5, 1144 BIT(config->slice_id), alloc_oneway_en); 1145 if (ret) 1146 return ret; 1147 1148 ovcap_en = config->ovcap_en << config->slice_id; 1149 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG6, 1150 BIT(config->slice_id), ovcap_en); 1151 if (ret) 1152 return ret; 1153 1154 ovcap_prio = config->ovcap_prio << config->slice_id; 1155 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG7, 1156 BIT(config->slice_id), ovcap_prio); 1157 if (ret) 1158 return ret; 1159 1160 vict_prio = config->vict_prio << config->slice_id; 1161 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG8, 1162 BIT(config->slice_id), vict_prio); 1163 if (ret) 1164 return ret; 1165 } 1166 1167 if (config->activate_on_init) { 1168 desc.slice_id = config->slice_id; 1169 ret = llcc_slice_activate(&desc); 1170 } 1171 1172 return ret; 1173 } 1174 1175 static int qcom_llcc_cfg_program(struct platform_device *pdev, 1176 const struct qcom_llcc_config *cfg) 1177 { 1178 int i; 1179 u32 sz; 1180 int ret = 0; 1181 const struct llcc_slice_config *llcc_table; 1182 1183 sz = drv_data->cfg_size; 1184 llcc_table = drv_data->cfg; 1185 1186 for (i = 0; i < sz; i++) { 1187 ret = _qcom_llcc_cfg_program(&llcc_table[i], cfg); 1188 if (ret) 1189 return ret; 1190 } 1191 1192 return ret; 1193 } 1194 1195 static int qcom_llcc_get_cfg_index(struct platform_device *pdev, u8 *cfg_index, int num_config) 1196 { 1197 int ret; 1198 1199 ret = nvmem_cell_read_u8(&pdev->dev, "multi-chan-ddr", cfg_index); 1200 if (ret == -ENOENT || ret == -EOPNOTSUPP) { 1201 if (num_config > 1) 1202 return -EINVAL; 1203 *cfg_index = 0; 1204 return 0; 1205 } 1206 1207 if (!ret && *cfg_index >= num_config) 1208 ret = -EINVAL; 1209 1210 return ret; 1211 } 1212 1213 static void qcom_llcc_remove(struct platform_device *pdev) 1214 { 1215 /* Set the global pointer to a error code to avoid referencing it */ 1216 drv_data = ERR_PTR(-ENODEV); 1217 } 1218 1219 static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, u8 index, 1220 const char *name) 1221 { 1222 void __iomem *base; 1223 struct regmap_config llcc_regmap_config = { 1224 .reg_bits = 32, 1225 .reg_stride = 4, 1226 .val_bits = 32, 1227 .fast_io = true, 1228 }; 1229 1230 base = devm_platform_ioremap_resource(pdev, index); 1231 if (IS_ERR(base)) 1232 return ERR_CAST(base); 1233 1234 llcc_regmap_config.name = name; 1235 return devm_regmap_init_mmio(&pdev->dev, base, &llcc_regmap_config); 1236 } 1237 1238 static int qcom_llcc_probe(struct platform_device *pdev) 1239 { 1240 u32 num_banks; 1241 struct device *dev = &pdev->dev; 1242 int ret, i; 1243 struct platform_device *llcc_edac; 1244 const struct qcom_sct_config *cfgs; 1245 const struct qcom_llcc_config *cfg; 1246 const struct llcc_slice_config *llcc_cfg; 1247 u32 sz; 1248 u8 cfg_index; 1249 u32 version; 1250 struct regmap *regmap; 1251 1252 if (!IS_ERR(drv_data)) 1253 return -EBUSY; 1254 1255 drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); 1256 if (!drv_data) { 1257 ret = -ENOMEM; 1258 goto err; 1259 } 1260 1261 /* Initialize the first LLCC bank regmap */ 1262 regmap = qcom_llcc_init_mmio(pdev, 0, "llcc0_base"); 1263 if (IS_ERR(regmap)) { 1264 ret = PTR_ERR(regmap); 1265 goto err; 1266 } 1267 1268 cfgs = of_device_get_match_data(&pdev->dev); 1269 if (!cfgs) { 1270 ret = -EINVAL; 1271 goto err; 1272 } 1273 ret = qcom_llcc_get_cfg_index(pdev, &cfg_index, cfgs->num_config); 1274 if (ret) 1275 goto err; 1276 cfg = &cfgs->llcc_config[cfg_index]; 1277 1278 ret = regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_banks); 1279 if (ret) 1280 goto err; 1281 1282 num_banks &= LLCC_LB_CNT_MASK; 1283 num_banks >>= LLCC_LB_CNT_SHIFT; 1284 drv_data->num_banks = num_banks; 1285 1286 drv_data->regmaps = devm_kcalloc(dev, num_banks, sizeof(*drv_data->regmaps), GFP_KERNEL); 1287 if (!drv_data->regmaps) { 1288 ret = -ENOMEM; 1289 goto err; 1290 } 1291 1292 drv_data->regmaps[0] = regmap; 1293 1294 /* Initialize rest of LLCC bank regmaps */ 1295 for (i = 1; i < num_banks; i++) { 1296 char *base __free(kfree) = kasprintf(GFP_KERNEL, "llcc%d_base", i); 1297 1298 drv_data->regmaps[i] = qcom_llcc_init_mmio(pdev, i, base); 1299 if (IS_ERR(drv_data->regmaps[i])) { 1300 ret = PTR_ERR(drv_data->regmaps[i]); 1301 goto err; 1302 } 1303 } 1304 1305 drv_data->bcast_regmap = qcom_llcc_init_mmio(pdev, i, "llcc_broadcast_base"); 1306 if (IS_ERR(drv_data->bcast_regmap)) { 1307 ret = PTR_ERR(drv_data->bcast_regmap); 1308 goto err; 1309 } 1310 1311 /* Extract version of the IP */ 1312 ret = regmap_read(drv_data->bcast_regmap, cfg->reg_offset[LLCC_COMMON_HW_INFO], 1313 &version); 1314 if (ret) 1315 goto err; 1316 1317 drv_data->version = version; 1318 1319 /* Applicable only when drv_data->version >= 4.1 */ 1320 if (drv_data->version >= LLCC_VERSION_4_1_0_0) { 1321 drv_data->bcast_and_regmap = qcom_llcc_init_mmio(pdev, i + 1, "llcc_broadcast_and_base"); 1322 if (IS_ERR(drv_data->bcast_and_regmap)) { 1323 ret = PTR_ERR(drv_data->bcast_and_regmap); 1324 if (ret == -EINVAL) 1325 drv_data->bcast_and_regmap = NULL; 1326 else 1327 goto err; 1328 } 1329 } 1330 1331 llcc_cfg = cfg->sct_data; 1332 sz = cfg->size; 1333 1334 for (i = 0; i < sz; i++) 1335 if (llcc_cfg[i].slice_id > drv_data->max_slices) 1336 drv_data->max_slices = llcc_cfg[i].slice_id; 1337 1338 drv_data->bitmap = devm_bitmap_zalloc(dev, drv_data->max_slices, 1339 GFP_KERNEL); 1340 if (!drv_data->bitmap) { 1341 ret = -ENOMEM; 1342 goto err; 1343 } 1344 1345 drv_data->cfg = llcc_cfg; 1346 drv_data->cfg_size = sz; 1347 drv_data->edac_reg_offset = cfg->edac_reg_offset; 1348 mutex_init(&drv_data->lock); 1349 platform_set_drvdata(pdev, drv_data); 1350 1351 ret = qcom_llcc_cfg_program(pdev, cfg); 1352 if (ret) 1353 goto err; 1354 1355 drv_data->ecc_irq = platform_get_irq_optional(pdev, 0); 1356 1357 /* 1358 * On some platforms, the access to EDAC registers will be locked by 1359 * the bootloader. So probing the EDAC driver will result in a crash. 1360 * Hence, disable the creation of EDAC platform device for the 1361 * problematic platforms. 1362 */ 1363 if (!cfg->no_edac) { 1364 llcc_edac = platform_device_register_data(&pdev->dev, 1365 "qcom_llcc_edac", -1, drv_data, 1366 sizeof(*drv_data)); 1367 if (IS_ERR(llcc_edac)) 1368 dev_err(dev, "Failed to register llcc edac driver\n"); 1369 } 1370 1371 return 0; 1372 err: 1373 drv_data = ERR_PTR(-ENODEV); 1374 return ret; 1375 } 1376 1377 static const struct of_device_id qcom_llcc_of_match[] = { 1378 { .compatible = "qcom,qdu1000-llcc", .data = &qdu1000_cfgs}, 1379 { .compatible = "qcom,sa8775p-llcc", .data = &sa8775p_cfgs }, 1380 { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfgs }, 1381 { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfgs }, 1382 { .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfgs }, 1383 { .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfgs }, 1384 { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfgs }, 1385 { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfgs }, 1386 { .compatible = "qcom,sm7150-llcc", .data = &sm7150_cfgs }, 1387 { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfgs }, 1388 { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfgs }, 1389 { .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfgs }, 1390 { .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfgs }, 1391 { .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfgs }, 1392 { .compatible = "qcom,sm8650-llcc", .data = &sm8650_cfgs }, 1393 { .compatible = "qcom,x1e80100-llcc", .data = &x1e80100_cfgs }, 1394 { } 1395 }; 1396 MODULE_DEVICE_TABLE(of, qcom_llcc_of_match); 1397 1398 static struct platform_driver qcom_llcc_driver = { 1399 .driver = { 1400 .name = "qcom-llcc", 1401 .of_match_table = qcom_llcc_of_match, 1402 }, 1403 .probe = qcom_llcc_probe, 1404 .remove_new = qcom_llcc_remove, 1405 }; 1406 module_platform_driver(qcom_llcc_driver); 1407 1408 MODULE_DESCRIPTION("Qualcomm Last Level Cache Controller"); 1409 MODULE_LICENSE("GPL v2"); 1410