1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/cleanup.h> 9 #include <linux/device.h> 10 #include <linux/io.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/nvmem-consumer.h> 15 #include <linux/of.h> 16 #include <linux/of_reserved_mem.h> 17 #include <linux/regmap.h> 18 #include <linux/sizes.h> 19 #include <linux/slab.h> 20 #include <linux/soc/qcom/llcc-qcom.h> 21 22 #define ACTIVATE BIT(0) 23 #define DEACTIVATE BIT(1) 24 #define ACT_CLEAR BIT(0) 25 #define ACT_COMPLETE BIT(4) 26 #define ACT_CTRL_OPCODE_ACTIVATE BIT(0) 27 #define ACT_CTRL_OPCODE_DEACTIVATE BIT(1) 28 #define ACT_CTRL_ACT_TRIG BIT(0) 29 #define ACT_CTRL_OPCODE_SHIFT 1 30 #define ATTR1_PROBE_TARGET_WAYS_SHIFT 2 31 #define ATTR1_FIXED_SIZE_SHIFT 3 32 #define ATTR1_PRIORITY_SHIFT 4 33 #define ATTR1_MAX_CAP_SHIFT 16 34 #define ATTR0_RES_WAYS_MASK GENMASK(15, 0) 35 #define ATTR0_BONUS_WAYS_MASK GENMASK(31, 16) 36 #define ATTR0_BONUS_WAYS_SHIFT 16 37 #define ATTR2_PROBE_TARGET_WAYS_MASK BIT(4) 38 #define ATTR2_FIXED_SIZE_MASK BIT(8) 39 #define ATTR2_PRIORITY_MASK GENMASK(14, 12) 40 #define ATTR2_PARENT_SCID_MASK GENMASK(21, 16) 41 #define ATTR2_IN_A_GROUP_MASK BIT(24) 42 #define LLCC_STATUS_READ_DELAY 100 43 44 #define CACHE_LINE_SIZE_SHIFT 6 45 46 #define LLCC_LB_CNT_MASK GENMASK(31, 28) 47 #define LLCC_LB_CNT_SHIFT 28 48 49 #define MAX_CAP_TO_BYTES(n) (n * SZ_1K) 50 #define LLCC_TRP_ACT_CTRLn(n) (n * SZ_4K) 51 #define LLCC_TRP_ACT_CLEARn(n) (8 + n * SZ_4K) 52 #define LLCC_TRP_STATUSn(n) (4 + n * SZ_4K) 53 #define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n) 54 #define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n) 55 #define LLCC_TRP_ATTR2_CFGn(n) (0x21100 + SZ_4 * n) 56 #define LLCC_V6_TRP_ATTR0_CFGn(n) (cfg->reg_offset[LLCC_TRP_ATTR0_CFG] + SZ_64 * (n)) 57 #define LLCC_V6_TRP_ATTR1_CFGn(n) (cfg->reg_offset[LLCC_TRP_ATTR1_CFG] + SZ_64 * (n)) 58 #define LLCC_V6_TRP_ATTR2_CFGn(n) (cfg->reg_offset[LLCC_TRP_ATTR2_CFG] + SZ_64 * (n)) 59 #define LLCC_V6_TRP_ATTR3_CFGn(n) (cfg->reg_offset[LLCC_TRP_ATTR3_CFG] + SZ_64 * (n)) 60 61 #define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00 62 #define LLCC_TRP_PCB_ACT 0x21f04 63 #define LLCC_TRP_ALGO_CFG1 0x21f0c 64 #define LLCC_TRP_ALGO_CFG2 0x21f10 65 #define LLCC_TRP_ALGO_CFG3 0x21f14 66 #define LLCC_TRP_ALGO_CFG4 0x21f18 67 #define LLCC_TRP_ALGO_CFG5 0x21f1c 68 #define LLCC_TRP_WRSC_EN 0x21f20 69 #define LLCC_TRP_ALGO_CFG6 0x21f24 70 #define LLCC_TRP_ALGO_CFG7 0x21f28 71 #define LLCC_TRP_WRSC_CACHEABLE_EN 0x21f2c 72 #define LLCC_TRP_ALGO_CFG8 0x21f30 73 74 #define LLCC_VERSION_2_0_0_0 0x02000000 75 #define LLCC_VERSION_2_1_0_0 0x02010000 76 #define LLCC_VERSION_4_1_0_0 0x04010000 77 #define LLCC_VERSION_6_0_0_0 0X06000000 78 79 #define SLC_SCT_MEM_LAYOUT_VERSION1 1 /* SCT Memory layout version */ 80 #define SLC_SCT_DONE 0x00534354444f4e45 /* SCT programming OK */ 81 #define SLC_SCT_FAIL 0x005343544641494c /* SCT programming failed */ 82 #define SLC_SCT_NAME_LEN 15 83 #define SLC_SCT_SLICE_ACT_ON_BOOT BIT(25) 84 85 /** 86 * struct llcc_slice_config - Data associated with the LLCC slice 87 * @usecase_id: Unique id for the client's use case 88 * @slice_id: LLCC slice id for each client 89 * @max_cap: The maximum capacity of the cache slice provided in KB 90 * @priority: Priority of the client used to select victim line for replacement 91 * @fixed_size: Boolean indicating if the slice has a fixed capacity 92 * @bonus_ways: Bonus ways are additional ways to be used for any slice, 93 * if client ends up using more than reserved cache ways. Bonus 94 * ways are allocated only if they are not reserved for some 95 * other client. 96 * @res_ways: Reserved ways for the cache slice, the reserved ways cannot 97 * be used by any other client than the one its assigned to. 98 * @cache_mode: Each slice operates as a cache, this controls the mode of the 99 * slice: normal or TCM(Tightly Coupled Memory) 100 * @probe_target_ways: Determines what ways to probe for access hit. When 101 * configured to 1 only bonus and reserved ways are probed. 102 * When configured to 0 all ways in LLCC are probed. 103 * @dis_cap_alloc: Disable capacity based allocation for a client 104 * @retain_on_pc: If this bit is set and client has maintained active vote 105 * then the ways assigned to this client are not flushed on power 106 * collapse. 107 * @activate_on_init: Activate the slice immediately after it is programmed 108 * @write_scid_en: Bit enables write cache support for a given scid. 109 * @write_scid_cacheable_en: Enables write cache cacheable support for a 110 * given scid (not supported on v2 or older hardware). 111 * @stale_en: Bit enables stale. 112 * @stale_cap_en: Bit enables stale only if current scid is over-cap. 113 * @mru_uncap_en: Roll-over on reserved cache ways if current scid is 114 * under-cap. 115 * @mru_rollover: Roll-over on reserved cache ways. 116 * @alloc_oneway_en: Allways allocate one way on over-cap even if there's no 117 * same-scid lines for replacement. 118 * @ovcap_en: Once current scid is over-capacity, allocate other over-cap SCID. 119 * @ovcap_prio: Once current scid is over-capacity, allocate other low priority 120 * over-cap scid. Depends on corresponding bit being set in 121 * ovcap_en. 122 * @vict_prio: When current scid is under-capacity, allocate over other 123 * lower-than victim priority-line threshold scid. 124 * @parent_slice_id: For grouped slices, specifies the slice id of the parent. 125 */ 126 struct llcc_slice_config { 127 u32 usecase_id; 128 u32 slice_id; 129 u32 max_cap; 130 u32 priority; 131 bool fixed_size; 132 u32 bonus_ways; 133 u32 res_ways; 134 u32 cache_mode; 135 u32 probe_target_ways; 136 bool dis_cap_alloc; 137 bool retain_on_pc; 138 bool activate_on_init; 139 bool write_scid_en; 140 bool write_scid_cacheable_en; 141 bool stale_en; 142 bool stale_cap_en; 143 bool mru_uncap_en; 144 bool mru_rollover; 145 bool alloc_oneway_en; 146 bool ovcap_en; 147 bool ovcap_prio; 148 bool vict_prio; 149 u32 parent_slice_id; 150 }; 151 152 /* 153 * struct slc_sct_error - Represents SCT error 154 * @code: FW code status 155 * @param: Holds the SCT programming error 156 */ 157 struct slc_sct_error { 158 __le64 code; 159 __le64 param; 160 } __packed; 161 162 /* 163 * struct slc_sct_status - SCT programming status 164 * @program_status: Indicates programming success or failure 165 * @version: SCT mem layout version 166 * @error: Error enum and its param 167 */ 168 struct slc_sct_status { 169 __le64 program_status; 170 /* Use the lower 8 bits */ 171 __le64 version; 172 struct slc_sct_error error; 173 } __packed; 174 175 /* 176 * struct slc_sct_details - SCT details 177 * @revision: revision of the SCT table 178 * @name: name of the SCT table 179 */ 180 struct slc_sct_details { 181 u8 revision; 182 char name[SLC_SCT_NAME_LEN]; 183 } __packed; 184 185 /* 186 * struct tcm_mem_info - SC TCM Shared memory details 187 * @is_present: is TCM region present 188 * @offset: offset of TCM shared memory details 189 */ 190 struct slc_tcm_mem_info { 191 __le32 is_present; 192 __le32 offset; 193 } __packed; 194 195 /* 196 * struct slc_sct_slice_desc - Slice descriptor definition used in shmem 197 * @slice_id: SCID of the slice 198 * @usecase_id: Usecase ID of the slice 199 * @slice_properties: 200 * slice_size: Contains the slice descriptor size - 20 bit wide 201 * rsvd: Reserved space - 4 bit wide 202 * flags: Flags for descriptors - 3 bit wide 203 * MPAM SCID: Bit 24 204 * Activate on boot: Bit 25 205 * Non-HLOS SCID: Bit 26 206 * HWMutex: Ensures only one processor (CPU or MCU) at a time can 207 * access the LLCC hardware resources - 5 bit wide 208 */ 209 struct slc_sct_slice_desc { 210 __le16 slice_id; 211 __le16 usecase_id; 212 __le32 slice_properties; 213 } __packed; 214 215 /* 216 * struct slc_sct_mem - Shared memory structure 217 * @sct_status: Status of SCT programming 218 * @sct_details: Sct revision and name details 219 * @tcm_mem_info: TCM shared memory presence & offset info 220 * @slice_descs_count: Number of slice desc present in SCT 221 * @scid_max: Maximum no. of SCIDs supported 222 * @slice_descs: Array of SCT slice desc 223 */ 224 struct slc_sct_mem { 225 struct slc_sct_status sct_status; 226 struct slc_sct_details sct_details; 227 struct slc_tcm_mem_info tcm_mem_info; 228 __le32 slice_descs_count; 229 __le32 scid_max; 230 struct slc_sct_slice_desc slice_descs[] __counted_by_le(slice_descs_count); 231 } __packed; 232 233 struct qcom_llcc_config { 234 const struct llcc_slice_config *sct_data; 235 const u32 *reg_offset; 236 const struct llcc_edac_reg_offset *edac_reg_offset; 237 u32 max_cap_shift; /* instead of ATTR1_MAX_CAP_SHIFT */ 238 u32 num_banks; 239 int size; 240 bool skip_llcc_cfg; 241 bool no_edac; 242 bool irq_configured; 243 bool no_broadcast_register; 244 }; 245 246 struct qcom_sct_config { 247 const struct qcom_llcc_config *llcc_config; 248 int num_config; 249 }; 250 251 enum llcc_reg_offset { 252 LLCC_COMMON_HW_INFO, 253 LLCC_COMMON_STATUS0, 254 LLCC_TRP_ATTR0_CFG, 255 LLCC_TRP_ATTR1_CFG, 256 LLCC_TRP_ATTR2_CFG, 257 LLCC_TRP_ATTR3_CFG, 258 LLCC_TRP_SID_DIS_CAP_ALLOC, 259 LLCC_TRP_ALGO_STALE_EN, 260 LLCC_TRP_ALGO_STALE_CAP_EN, 261 LLCC_TRP_ALGO_MRU0, 262 LLCC_TRP_ALGO_MRU1, 263 LLCC_TRP_ALGO_ALLOC0, 264 LLCC_TRP_ALGO_ALLOC1, 265 LLCC_TRP_ALGO_ALLOC2, 266 LLCC_TRP_ALGO_ALLOC3, 267 LLCC_TRP_WRS_EN, 268 LLCC_TRP_WRS_CACHEABLE_EN, 269 }; 270 271 static const struct llcc_slice_config eliza_data[] = { 272 { 273 .usecase_id = LLCC_CPUSS, 274 .slice_id = 1, 275 .max_cap = 896, 276 .bonus_ways = 0xfff, 277 .activate_on_init = true, 278 .write_scid_en = true, 279 .stale_en = true, 280 }, 281 { 282 .usecase_id = LLCC_MDMHPFX, 283 .slice_id = 24, 284 .max_cap = 1024, 285 .priority = 5, 286 .fixed_size = true, 287 .bonus_ways = 0xfff, 288 }, 289 { 290 .usecase_id = LLCC_VIDSC0, 291 .slice_id = 2, 292 .max_cap = 128, 293 .priority = 5, 294 .fixed_size = true, 295 .bonus_ways = 0xfff, 296 }, 297 { 298 .usecase_id = LLCC_MDMHPGRW, 299 .slice_id = 25, 300 .max_cap = 1024, 301 .priority = 5, 302 .bonus_ways = 0xfff, 303 }, 304 { 305 .usecase_id = LLCC_GPUHTW, 306 .slice_id = 11, 307 .max_cap = 256, 308 .priority = 1, 309 .fixed_size = true, 310 .bonus_ways = 0xfff, 311 }, 312 { 313 .usecase_id = LLCC_GPU, 314 .slice_id = 9, 315 .max_cap = 896, 316 .priority = 1, 317 .bonus_ways = 0xfff, 318 .write_scid_cacheable_en = true, 319 }, 320 { 321 .usecase_id = LLCC_MMUHWT, 322 .slice_id = 18, 323 .max_cap = 256, 324 .priority = 1, 325 .fixed_size = true, 326 .bonus_ways = 0xfff, 327 .activate_on_init = true, 328 }, 329 { 330 .usecase_id = LLCC_MDMPNG, 331 .slice_id = 27, 332 .max_cap = 256, 333 .priority = 5, 334 .fixed_size = true, 335 .bonus_ways = 0xfff, 336 }, 337 { 338 .usecase_id = LLCC_MODPE, 339 .slice_id = 29, 340 .max_cap = 256, 341 .priority = 1, 342 .fixed_size = true, 343 .bonus_ways = 0xf00, 344 .alloc_oneway_en = true, 345 }, 346 { 347 .usecase_id = LLCC_WRCACHE, 348 .slice_id = 31, 349 .max_cap = 256, 350 .priority = 1, 351 .fixed_size = true, 352 .bonus_ways = 0xfff, 353 .activate_on_init = true, 354 }, 355 { 356 .usecase_id = LLCC_LCPDARE, 357 .slice_id = 30, 358 .max_cap = 128, 359 .priority = 5, 360 .fixed_size = true, 361 .bonus_ways = 0xfff, 362 .activate_on_init = true, 363 .alloc_oneway_en = true, 364 }, 365 { 366 .usecase_id = LLCC_ISLAND1, 367 .slice_id = 12, 368 .max_cap = 1280, 369 .priority = 7, 370 .fixed_size = true, 371 .res_ways = 0x3ff, 372 }, 373 { 374 .usecase_id = LLCC_CAMOFE, 375 .slice_id = 33, 376 .max_cap = 1024, 377 .priority = 1, 378 .fixed_size = true, 379 .bonus_ways = 0xfff, 380 .stale_en = true, 381 .parent_slice_id = 13, 382 }, 383 { 384 .usecase_id = LLCC_CAMRTIP, 385 .slice_id = 13, 386 .max_cap = 1024, 387 .priority = 1, 388 .fixed_size = true, 389 .bonus_ways = 0xfff, 390 .stale_en = true, 391 .parent_slice_id = 13, 392 }, 393 { 394 .usecase_id = LLCC_CAMSRTIP, 395 .slice_id = 14, 396 .max_cap = 512, 397 .priority = 1, 398 .fixed_size = true, 399 .bonus_ways = 0xfff, 400 .stale_en = true, 401 .parent_slice_id = 13, 402 }, 403 { 404 .usecase_id = LLCC_CAMRTRF, 405 .slice_id = 7, 406 .max_cap = 1024, 407 .priority = 1, 408 .fixed_size = true, 409 .bonus_ways = 0xfff, 410 .stale_en = true, 411 .parent_slice_id = 13, 412 }, 413 { 414 .usecase_id = LLCC_CAMSRTRF, 415 .slice_id = 21, 416 .max_cap = 1024, 417 .priority = 1, 418 .fixed_size = true, 419 .bonus_ways = 0xfff, 420 .stale_en = true, 421 .parent_slice_id = 13, 422 }, 423 { 424 .usecase_id = LLCC_CPUSSMPAM, 425 .slice_id = 6, 426 .max_cap = 512, 427 .priority = 0, 428 .fixed_size = true, 429 .bonus_ways = 0xfff, 430 .activate_on_init = true, 431 .write_scid_en = true, 432 .stale_en = true, 433 }, 434 }; 435 436 static const struct llcc_slice_config glymur_data[] = { 437 { 438 .usecase_id = LLCC_CPUSS, 439 .slice_id = 1, 440 .max_cap = 7680, 441 .priority = 1, 442 .bonus_ways = 0xFFF, 443 .res_ways = 0x0, 444 .vict_prio = true, 445 .activate_on_init = true, 446 }, { 447 .usecase_id = LLCC_VIDSC0, 448 .slice_id = 2, 449 .max_cap = 512, 450 .priority = 3, 451 .fixed_size = true, 452 .bonus_ways = 0xFFF, 453 .res_ways = 0x0, 454 .vict_prio = true, 455 }, { 456 .usecase_id = LLCC_AUDIO, 457 .slice_id = 6, 458 .max_cap = 1024, 459 .priority = 1, 460 .fixed_size = true, 461 .bonus_ways = 0xFFF, 462 .res_ways = 0x0, 463 .vict_prio = true, 464 }, { 465 .usecase_id = LLCC_VIDSC1, 466 .slice_id = 4, 467 .max_cap = 512, 468 .priority = 3, 469 .fixed_size = true, 470 .bonus_ways = 0xFFF, 471 .res_ways = 0x0, 472 .vict_prio = true, 473 }, { 474 .usecase_id = LLCC_CMPT, 475 .slice_id = 10, 476 .max_cap = 7680, 477 .priority = 1, 478 .fixed_size = true, 479 .bonus_ways = 0xFFF, 480 .res_ways = 0x0, 481 .vict_prio = true, 482 }, { 483 .usecase_id = LLCC_GPUHTW, 484 .slice_id = 11, 485 .max_cap = 512, 486 .priority = 1, 487 .fixed_size = true, 488 .bonus_ways = 0xFFF, 489 .res_ways = 0x0, 490 .vict_prio = true, 491 }, { 492 .usecase_id = LLCC_GPU, 493 .slice_id = 9, 494 .max_cap = 7680, 495 .priority = 1, 496 .bonus_ways = 0xFFF, 497 .res_ways = 0x0, 498 .write_scid_en = true, 499 .write_scid_cacheable_en = true, 500 .stale_en = true, 501 .vict_prio = true, 502 }, { 503 .usecase_id = LLCC_MMUHWT, 504 .slice_id = 18, 505 .max_cap = 768, 506 .priority = 1, 507 .fixed_size = true, 508 .bonus_ways = 0xFFF, 509 .res_ways = 0x0, 510 .vict_prio = true, 511 .activate_on_init = true, 512 }, { 513 .usecase_id = LLCC_AUDHW, 514 .slice_id = 22, 515 .max_cap = 1024, 516 .priority = 1, 517 .fixed_size = true, 518 .bonus_ways = 0xFFF, 519 .res_ways = 0x0, 520 .vict_prio = true, 521 }, { 522 .usecase_id = LLCC_CVP, 523 .slice_id = 8, 524 .max_cap = 64, 525 .priority = 3, 526 .fixed_size = true, 527 .bonus_ways = 0xFFF, 528 .res_ways = 0x0, 529 .vict_prio = true, 530 }, { 531 .usecase_id = LLCC_WRCACHE, 532 .slice_id = 31, 533 .max_cap = 1536, 534 .priority = 1, 535 .fixed_size = true, 536 .bonus_ways = 0xFFF, 537 .res_ways = 0x0, 538 .vict_prio = true, 539 .activate_on_init = true, 540 }, { 541 .usecase_id = LLCC_CMPTHCP, 542 .slice_id = 17, 543 .max_cap = 256, 544 .priority = 3, 545 .fixed_size = true, 546 .bonus_ways = 0xFFF, 547 .res_ways = 0x0, 548 .vict_prio = true, 549 }, { 550 .usecase_id = LLCC_LCPDARE, 551 .slice_id = 30, 552 .max_cap = 768, 553 .priority = 3, 554 .fixed_size = true, 555 .bonus_ways = 0xFFF, 556 .res_ways = 0x0, 557 .alloc_oneway_en = true, 558 .vict_prio = true, 559 .activate_on_init = true, 560 }, { 561 .usecase_id = LLCC_AENPU, 562 .slice_id = 3, 563 .max_cap = 3072, 564 .priority = 1, 565 .fixed_size = true, 566 .bonus_ways = 0xFFF, 567 .res_ways = 0x0, 568 .cache_mode = 2, 569 .vict_prio = true, 570 }, { 571 .usecase_id = LLCC_ISLAND1, 572 .slice_id = 12, 573 .max_cap = 5632, 574 .priority = 7, 575 .fixed_size = true, 576 .bonus_ways = 0x0, 577 .res_ways = 0x7FF, 578 .vict_prio = true, 579 }, { 580 .usecase_id = LLCC_VIDVSP, 581 .slice_id = 28, 582 .max_cap = 256, 583 .priority = 3, 584 .fixed_size = true, 585 .bonus_ways = 0xFFF, 586 .res_ways = 0x0, 587 .vict_prio = true, 588 }, { 589 .usecase_id = LLCC_OOBM_NS, 590 .slice_id = 5, 591 .max_cap = 512, 592 .priority = 1, 593 .bonus_ways = 0xFFF, 594 .res_ways = 0x0, 595 .vict_prio = true, 596 }, { 597 .usecase_id = LLCC_CPUSS_OPP, 598 .slice_id = 32, 599 .max_cap = 0, 600 .fixed_size = true, 601 .bonus_ways = 0x0, 602 .res_ways = 0x0, 603 .vict_prio = true, 604 .activate_on_init = true, 605 }, { 606 .usecase_id = LLCC_PCIE_TCU, 607 .slice_id = 19, 608 .max_cap = 256, 609 .priority = 1, 610 .fixed_size = true, 611 .bonus_ways = 0xFFF, 612 .res_ways = 0x0, 613 .vict_prio = true, 614 .activate_on_init = true, 615 }, { 616 .usecase_id = LLCC_VIDSC_VSP1, 617 .slice_id = 29, 618 .max_cap = 256, 619 .priority = 3, 620 .fixed_size = true, 621 .bonus_ways = 0xFFF, 622 .res_ways = 0x0, 623 .vict_prio = true, 624 } 625 }; 626 627 static const struct llcc_slice_config ipq5424_data[] = { 628 { 629 .usecase_id = LLCC_CPUSS, 630 .slice_id = 1, 631 .max_cap = 768, 632 .priority = 1, 633 .bonus_ways = 0xFFFF, 634 .retain_on_pc = true, 635 .activate_on_init = true, 636 .write_scid_cacheable_en = true, 637 .stale_en = true, 638 .stale_cap_en = true, 639 .alloc_oneway_en = true, 640 .ovcap_en = true, 641 .ovcap_prio = true, 642 .vict_prio = true, 643 }, 644 { 645 .usecase_id = LLCC_VIDSC0, 646 .slice_id = 2, 647 .max_cap = 256, 648 .priority = 2, 649 .fixed_size = true, 650 .bonus_ways = 0xF000, 651 .retain_on_pc = true, 652 .activate_on_init = true, 653 .write_scid_cacheable_en = true, 654 .stale_en = true, 655 .stale_cap_en = true, 656 }, 657 }; 658 659 static const struct llcc_slice_config kaanapali_data[] = { 660 { 661 .usecase_id = LLCC_CPUSS, 662 .slice_id = 1, 663 .max_cap = 5120, 664 .priority = 1, 665 .bonus_ways = 0xffffffff, 666 .activate_on_init = true, 667 .write_scid_en = true, 668 .stale_en = true, 669 .mru_uncap_en = true, 670 .vict_prio = true, 671 }, { 672 .usecase_id = LLCC_VIDSC0, 673 .slice_id = 2, 674 .max_cap = 512, 675 .priority = 4, 676 .fixed_size = true, 677 .bonus_ways = 0xffffffff, 678 .mru_uncap_en = true, 679 .vict_prio = true, 680 }, { 681 .usecase_id = LLCC_AUDIO, 682 .slice_id = 35, 683 .max_cap = 512, 684 .priority = 1, 685 .fixed_size = true, 686 .bonus_ways = 0xffffffff, 687 .mru_uncap_en = true, 688 .vict_prio = true, 689 }, { 690 .usecase_id = LLCC_MDMHPGRW, 691 .slice_id = 25, 692 .max_cap = 1024, 693 .priority = 5, 694 .bonus_ways = 0xffffffff, 695 .mru_uncap_en = true, 696 .vict_prio = true, 697 }, { 698 .usecase_id = LLCC_CMPT, 699 .slice_id = 34, 700 .max_cap = 4096, 701 .priority = 1, 702 .fixed_size = true, 703 .bonus_ways = 0xffffffff, 704 .mru_uncap_en = true, 705 .vict_prio = true, 706 }, { 707 .usecase_id = LLCC_GPUHTW, 708 .slice_id = 11, 709 .max_cap = 512, 710 .priority = 1, 711 .fixed_size = true, 712 .bonus_ways = 0xffffffff, 713 .mru_uncap_en = true, 714 .vict_prio = true, 715 }, { 716 .usecase_id = LLCC_GPU, 717 .slice_id = 9, 718 .max_cap = 5632, 719 .priority = 1, 720 .fixed_size = true, 721 .bonus_ways = 0xffffffff, 722 .write_scid_cacheable_en = true, 723 .mru_uncap_en = true, 724 .vict_prio = true, 725 }, { 726 .usecase_id = LLCC_MMUHWT, 727 .slice_id = 18, 728 .max_cap = 768, 729 .priority = 1, 730 .fixed_size = true, 731 .bonus_ways = 0xffffffff, 732 .activate_on_init = true, 733 .mru_uncap_en = true, 734 .vict_prio = true, 735 }, { 736 .usecase_id = LLCC_DISP, 737 .slice_id = 16, 738 .max_cap = 7168, 739 .priority = 1, 740 .fixed_size = true, 741 .bonus_ways = 0xffffffff, 742 .cache_mode = 2, 743 .stale_en = true, 744 .mru_uncap_en = true, 745 .vict_prio = true, 746 }, { 747 .usecase_id = LLCC_MDMHPFX, 748 .slice_id = 24, 749 .max_cap = 1024, 750 .priority = 5, 751 .fixed_size = true, 752 .bonus_ways = 0xffffffff, 753 .mru_uncap_en = true, 754 .vict_prio = true, 755 }, { 756 .usecase_id = LLCC_MDMPNG, 757 .slice_id = 27, 758 .max_cap = 256, 759 .priority = 5, 760 .bonus_ways = 0xfffff, 761 .mru_uncap_en = true, 762 .vict_prio = true, 763 }, { 764 .usecase_id = LLCC_CVP, 765 .slice_id = 8, 766 .max_cap = 800, 767 .priority = 5, 768 .fixed_size = true, 769 .bonus_ways = 0xffffffff, 770 .mru_uncap_en = true, 771 .ovcap_en = true, 772 .vict_prio = true, 773 .parent_slice_id = 33, 774 }, { 775 .usecase_id = LLCC_MODPE, 776 .slice_id = 29, 777 .max_cap = 256, 778 .priority = 1, 779 .fixed_size = true, 780 .bonus_ways = 0xf0000000, 781 .mru_uncap_en = true, 782 .alloc_oneway_en = true, 783 .vict_prio = true, 784 }, { 785 .usecase_id = LLCC_WRCACHE, 786 .slice_id = 31, 787 .max_cap = 512, 788 .priority = 1, 789 .fixed_size = true, 790 .bonus_ways = 0xffffffff, 791 .activate_on_init = true, 792 .mru_uncap_en = true, 793 .vict_prio = true, 794 }, { 795 .usecase_id = LLCC_CVPFW, 796 .slice_id = 19, 797 .max_cap = 512, 798 .priority = 5, 799 .fixed_size = true, 800 .bonus_ways = 0xffffffff, 801 .mru_uncap_en = true, 802 .vict_prio = true, 803 .parent_slice_id = 33, 804 }, { 805 .usecase_id = LLCC_CPUMTE, 806 .slice_id = 7, 807 .max_cap = 256, 808 .priority = 1, 809 .fixed_size = true, 810 .bonus_ways = 0xffffffff, 811 .mru_uncap_en = true, 812 .vict_prio = true, 813 }, { 814 .usecase_id = LLCC_CMPTHCP, 815 .slice_id = 15, 816 .max_cap = 256, 817 .priority = 4, 818 .fixed_size = true, 819 .bonus_ways = 0xffffffff, 820 .mru_uncap_en = true, 821 .vict_prio = true, 822 }, { 823 .usecase_id = LLCC_LCPDARE, 824 .slice_id = 30, 825 .max_cap = 128, 826 .priority = 5, 827 .fixed_size = true, 828 .bonus_ways = 0xffffffff, 829 .activate_on_init = true, 830 .mru_uncap_en = true, 831 .alloc_oneway_en = true, 832 .vict_prio = true, 833 }, { 834 .usecase_id = LLCC_AENPU, 835 .slice_id = 3, 836 .max_cap = 3072, 837 .priority = 1, 838 .fixed_size = true, 839 .bonus_ways = 0xffffffff, 840 .cache_mode = 2, 841 .mru_uncap_en = true, 842 .vict_prio = true, 843 }, { 844 .usecase_id = LLCC_ISLAND1, 845 .slice_id = 12, 846 .max_cap = 7936, 847 .priority = 7, 848 .fixed_size = true, 849 .bonus_ways = 0x7fffffff, 850 .mru_uncap_en = true, 851 .vict_prio = true, 852 }, { 853 .usecase_id = LLCC_DISP_WB, 854 .slice_id = 23, 855 .max_cap = 512, 856 .priority = 4, 857 .fixed_size = true, 858 .bonus_ways = 0xffffffff, 859 .mru_uncap_en = true, 860 .vict_prio = true, 861 }, { 862 .usecase_id = LLCC_VIDVSP, 863 .slice_id = 4, 864 .max_cap = 256, 865 .priority = 4, 866 .fixed_size = true, 867 .bonus_ways = 0xffffffff, 868 .mru_uncap_en = true, 869 .vict_prio = true, 870 }, { 871 .usecase_id = LLCC_VIDDEC, 872 .slice_id = 5, 873 .max_cap = 512, 874 .priority = 4, 875 .fixed_size = true, 876 .bonus_ways = 0xffffffff, 877 .cache_mode = 2, 878 .mru_uncap_en = true, 879 .ovcap_en = true, 880 .vict_prio = true, 881 .parent_slice_id = 33, 882 }, { 883 .usecase_id = LLCC_CAMOFE, 884 .slice_id = 33, 885 .max_cap = 6144, 886 .priority = 4, 887 .fixed_size = true, 888 .bonus_ways = 0xffffffff, 889 .stale_en = true, 890 .mru_uncap_en = true, 891 .ovcap_en = true, 892 .vict_prio = true, 893 .parent_slice_id = 33, 894 }, { 895 .usecase_id = LLCC_CAMRTIP, 896 .slice_id = 13, 897 .max_cap = 6144, 898 .priority = 4, 899 .fixed_size = true, 900 .bonus_ways = 0xffffffff, 901 .stale_en = true, 902 .mru_uncap_en = true, 903 .ovcap_en = true, 904 .vict_prio = true, 905 .parent_slice_id = 33, 906 }, { 907 .usecase_id = LLCC_CAMRTRF, 908 .slice_id = 10, 909 .max_cap = 3584, 910 .priority = 3, 911 .fixed_size = true, 912 .bonus_ways = 0xffffffff, 913 .stale_en = true, 914 .mru_uncap_en = true, 915 .ovcap_en = true, 916 .vict_prio = true, 917 .parent_slice_id = 33, 918 }, { 919 .usecase_id = LLCC_CAMSRTRF, 920 .slice_id = 21, 921 .max_cap = 6144, 922 .priority = 1, 923 .fixed_size = true, 924 .bonus_ways = 0xffffffff, 925 .stale_en = true, 926 .mru_uncap_en = true, 927 .ovcap_en = true, 928 .vict_prio = true, 929 .parent_slice_id = 33, 930 }, { 931 .usecase_id = LLCC_VIDEO_APV, 932 .slice_id = 6, 933 .max_cap = 768, 934 .priority = 4, 935 .fixed_size = true, 936 .bonus_ways = 0xffffffff, 937 .mru_uncap_en = true, 938 .vict_prio = true, 939 }, { 940 .usecase_id = LLCC_COMPUTE1, 941 .slice_id = 22, 942 .max_cap = 4096, 943 .priority = 1, 944 .fixed_size = true, 945 .bonus_ways = 0xffffffff, 946 .mru_uncap_en = true, 947 .vict_prio = true, 948 }, { 949 .usecase_id = LLCC_CPUSS_OPP, 950 .slice_id = 32, 951 .max_cap = 0, 952 .priority = 0, 953 .fixed_size = true, 954 .bonus_ways = 0, 955 .activate_on_init = true, 956 .write_scid_en = true, 957 .mru_uncap_en = true, 958 .vict_prio = true, 959 }, { 960 .usecase_id = LLCC_CPUSSMPAM, 961 .slice_id = 17, 962 .max_cap = 2048, 963 .priority = 1, 964 .fixed_size = true, 965 .bonus_ways = 0xffffffff, 966 .activate_on_init = true, 967 .write_scid_en = true, 968 .stale_en = true, 969 .mru_uncap_en = true, 970 .vict_prio = true, 971 }, { 972 .usecase_id = LLCC_CAM_IPE_STROV, 973 .slice_id = 14, 974 .max_cap = 400, 975 .priority = 5, 976 .fixed_size = true, 977 .bonus_ways = 0xffffffff, 978 .mru_uncap_en = true, 979 .ovcap_en = true, 980 .vict_prio = true, 981 .parent_slice_id = 33, 982 }, { 983 .usecase_id = LLCC_CAM_OFE_STROV, 984 .slice_id = 20, 985 .max_cap = 400, 986 .priority = 5, 987 .fixed_size = true, 988 .bonus_ways = 0xffffffff, 989 .mru_uncap_en = true, 990 .ovcap_en = true, 991 .vict_prio = true, 992 .parent_slice_id = 33, 993 }, { 994 .usecase_id = LLCC_CPUSS_HEU, 995 .slice_id = 28, 996 .max_cap = 0, 997 .priority = 0, 998 .fixed_size = true, 999 .bonus_ways = 0, 1000 .mru_uncap_en = true, 1001 .ovcap_en = true, 1002 .vict_prio = true, 1003 }, { 1004 .usecase_id = LLCC_MDM_PNG_FIXED, 1005 .slice_id = 26, 1006 .max_cap = 256, 1007 .priority = 5, 1008 .fixed_size = true, 1009 .bonus_ways = 0xff000000, 1010 .activate_on_init = true, 1011 .write_scid_en = true, 1012 .mru_uncap_en = true, 1013 .vict_prio = true, 1014 }, 1015 }; 1016 1017 static const struct llcc_slice_config sa8775p_data[] = { 1018 { 1019 .usecase_id = LLCC_CPUSS, 1020 .slice_id = 1, 1021 .max_cap = 2048, 1022 .priority = 1, 1023 .bonus_ways = 0xff, 1024 .cache_mode = 0, 1025 .retain_on_pc = true, 1026 .activate_on_init = true, 1027 }, { 1028 .usecase_id = LLCC_VIDSC0, 1029 .slice_id = 2, 1030 .max_cap = 512, 1031 .priority = 3, 1032 .fixed_size = true, 1033 .bonus_ways = 0xff, 1034 .cache_mode = 0, 1035 .retain_on_pc = true, 1036 }, { 1037 .usecase_id = LLCC_CPUSS1, 1038 .slice_id = 3, 1039 .max_cap = 1024, 1040 .priority = 1, 1041 .fixed_size = true, 1042 .bonus_ways = 0xff, 1043 .cache_mode = 0, 1044 .retain_on_pc = true, 1045 }, { 1046 .usecase_id = LLCC_CPUHWT, 1047 .slice_id = 5, 1048 .max_cap = 512, 1049 .priority = 1, 1050 .fixed_size = true, 1051 .bonus_ways = 0xff, 1052 .cache_mode = 0, 1053 .retain_on_pc = true, 1054 }, { 1055 .usecase_id = LLCC_AUDIO, 1056 .slice_id = 6, 1057 .max_cap = 1024, 1058 .priority = 1, 1059 .fixed_size = true, 1060 .bonus_ways = 0xff, 1061 .cache_mode = 0, 1062 }, { 1063 .usecase_id = LLCC_CMPT, 1064 .slice_id = 10, 1065 .max_cap = 4096, 1066 .priority = 1, 1067 .fixed_size = true, 1068 .bonus_ways = 0xff, 1069 .cache_mode = 0, 1070 .retain_on_pc = true, 1071 }, { 1072 .usecase_id = LLCC_GPUHTW, 1073 .slice_id = 11, 1074 .max_cap = 1024, 1075 .priority = 1, 1076 .fixed_size = true, 1077 .bonus_ways = 0xff, 1078 .cache_mode = 0, 1079 .retain_on_pc = true, 1080 }, { 1081 .usecase_id = LLCC_GPU, 1082 .slice_id = 12, 1083 .max_cap = 1024, 1084 .priority = 1, 1085 .fixed_size = true, 1086 .bonus_ways = 0xff, 1087 .cache_mode = 0, 1088 .retain_on_pc = true, 1089 .write_scid_en = true, 1090 }, { 1091 .usecase_id = LLCC_MMUHWT, 1092 .slice_id = 13, 1093 .max_cap = 1024, 1094 .priority = 1, 1095 .fixed_size = true, 1096 .bonus_ways = 0xff, 1097 .cache_mode = 0, 1098 .activate_on_init = true, 1099 }, { 1100 .usecase_id = LLCC_CMPTDMA, 1101 .slice_id = 15, 1102 .max_cap = 1024, 1103 .priority = 1, 1104 .fixed_size = true, 1105 .bonus_ways = 0xff, 1106 .cache_mode = 0, 1107 .retain_on_pc = true, 1108 }, { 1109 .usecase_id = LLCC_DISP, 1110 .slice_id = 16, 1111 .max_cap = 4096, 1112 .priority = 2, 1113 .fixed_size = true, 1114 .bonus_ways = 0xff, 1115 .cache_mode = 0, 1116 .retain_on_pc = true, 1117 }, { 1118 .usecase_id = LLCC_VIDFW, 1119 .slice_id = 17, 1120 .max_cap = 3072, 1121 .priority = 1, 1122 .bonus_ways = 0xff, 1123 .cache_mode = 0, 1124 .retain_on_pc = true, 1125 }, { 1126 .usecase_id = LLCC_AUDHW, 1127 .slice_id = 22, 1128 .max_cap = 1024, 1129 .priority = 1, 1130 .fixed_size = true, 1131 .bonus_ways = 0xff, 1132 .cache_mode = 0, 1133 }, { 1134 .usecase_id = LLCC_CVP, 1135 .slice_id = 28, 1136 .max_cap = 256, 1137 .priority = 3, 1138 .fixed_size = true, 1139 .bonus_ways = 0xff, 1140 .cache_mode = 0, 1141 .retain_on_pc = true, 1142 }, { 1143 .usecase_id = LLCC_APTCM, 1144 .slice_id = 30, 1145 .max_cap = 1024, 1146 .priority = 3, 1147 .fixed_size = true, 1148 .res_ways = 0xf0, 1149 .cache_mode = 1, 1150 .retain_on_pc = true, 1151 }, { 1152 .usecase_id = LLCC_WRCACHE, 1153 .slice_id = 31, 1154 .max_cap = 512, 1155 .priority = 1, 1156 .fixed_size = true, 1157 .bonus_ways = 0xff, 1158 .cache_mode = 0, 1159 .activate_on_init = true, 1160 }, 1161 }; 1162 1163 static const struct llcc_slice_config sar1130p_data[] = { 1164 { 1165 .usecase_id = LLCC_CPUSS, 1166 .slice_id = 1, 1167 .max_cap = 4096, 1168 .priority = 1, 1169 .bonus_ways = 0x1fff, 1170 .res_ways = 0x0, 1171 .cache_mode = 0, 1172 .retain_on_pc = true, 1173 .activate_on_init = true, 1174 }, { 1175 .usecase_id = LLCC_VIDSC0, 1176 .slice_id = 2, 1177 .max_cap = 512, 1178 .priority = 3, 1179 .fixed_size = true, 1180 .bonus_ways = 0x1fff, 1181 .res_ways = 0x0, 1182 .cache_mode = 0, 1183 .retain_on_pc = true, 1184 }, { 1185 .usecase_id = LLCC_AUDIO, 1186 .slice_id = 6, 1187 .max_cap = 1024, 1188 .priority = 3, 1189 .fixed_size = true, 1190 .bonus_ways = 0x1fff, 1191 .res_ways = 0x0, 1192 .cache_mode = 0, 1193 .retain_on_pc = true, 1194 }, { 1195 .usecase_id = LLCC_CMPT, 1196 .slice_id = 10, 1197 .max_cap = 1024, 1198 .priority = 1, 1199 .fixed_size = true, 1200 .bonus_ways = 0x1fff, 1201 .res_ways = 0x0, 1202 .cache_mode = 0, 1203 .retain_on_pc = true, 1204 }, { 1205 .usecase_id = LLCC_GPUHTW, 1206 .slice_id = 11, 1207 .max_cap = 0, 1208 .priority = 1, 1209 .fixed_size = true, 1210 .bonus_ways = 0x1fff, 1211 .res_ways = 0x0, 1212 .cache_mode = 0, 1213 .retain_on_pc = true, 1214 }, { 1215 .usecase_id = LLCC_GPU, 1216 .slice_id = 12, 1217 .max_cap = 3072, 1218 .priority = 3, 1219 .fixed_size = true, 1220 .bonus_ways = 0x1fff, 1221 .res_ways = 0x0, 1222 .cache_mode = 0, 1223 .retain_on_pc = true, 1224 .write_scid_en = true, 1225 }, { 1226 .usecase_id = LLCC_MMUHWT, 1227 .slice_id = 13, 1228 .max_cap = 512, 1229 .priority = 1, 1230 .fixed_size = true, 1231 .bonus_ways = 0x1fff, 1232 .res_ways = 0x0, 1233 .cache_mode = 0, 1234 }, { 1235 .usecase_id = LLCC_DISP, 1236 .slice_id = 16, 1237 .max_cap = 12800, 1238 .priority = 1, 1239 .fixed_size = true, 1240 .bonus_ways = 0x1fff, 1241 .res_ways = 0x0, 1242 .cache_mode = 0, 1243 .retain_on_pc = true, 1244 }, { 1245 .usecase_id = LLCC_CVP, 1246 .slice_id = 28, 1247 .max_cap = 256, 1248 .priority = 3, 1249 .fixed_size = true, 1250 .bonus_ways = 0x1fff, 1251 .res_ways = 0x0, 1252 .cache_mode = 0, 1253 .retain_on_pc = true, 1254 }, { 1255 .usecase_id = LLCC_APTCM, 1256 .slice_id = 26, 1257 .max_cap = 2048, 1258 .priority = 3, 1259 .fixed_size = true, 1260 .bonus_ways = 0x0, 1261 .res_ways = 0x3, 1262 .cache_mode = true, 1263 .dis_cap_alloc = true, 1264 .retain_on_pc = true, 1265 }, { 1266 .usecase_id = LLCC_WRCACHE, 1267 .slice_id = 31, 1268 .max_cap = 256, 1269 .priority = 1, 1270 .fixed_size = true, 1271 .bonus_ways = 0x1fff, 1272 .res_ways = 0x0, 1273 .cache_mode = 0, 1274 .activate_on_init = true, 1275 }, { 1276 .usecase_id = LLCC_AENPU, 1277 .slice_id = 30, 1278 .max_cap = 3072, 1279 .priority = 3, 1280 .fixed_size = true, 1281 .bonus_ways = 0x1fff, 1282 .res_ways = 0x0, 1283 .cache_mode = 0, 1284 .retain_on_pc = true, 1285 }, { 1286 .usecase_id = LLCC_DISP_LEFT, 1287 .slice_id = 17, 1288 .max_cap = 0, 1289 .priority = 1, 1290 .fixed_size = true, 1291 .bonus_ways = 0x0, 1292 .res_ways = 0x0, 1293 .cache_mode = 0, 1294 .retain_on_pc = true, 1295 }, { 1296 .usecase_id = LLCC_DISP_RIGHT, 1297 .slice_id = 18, 1298 .max_cap = 0, 1299 .priority = 1, 1300 .fixed_size = true, 1301 .bonus_ways = 0x0, 1302 .res_ways = 0x0, 1303 .cache_mode = 0, 1304 .retain_on_pc = true, 1305 }, { 1306 .usecase_id = LLCC_EVCS_LEFT, 1307 .slice_id = 22, 1308 .max_cap = 0, 1309 .priority = 1, 1310 .fixed_size = true, 1311 .bonus_ways = 0x0, 1312 .res_ways = 0x0, 1313 .cache_mode = 0, 1314 .retain_on_pc = true, 1315 }, { 1316 .usecase_id = LLCC_EVCS_RIGHT, 1317 .slice_id = 23, 1318 .max_cap = 0, 1319 .priority = 1, 1320 .fixed_size = true, 1321 .bonus_ways = 0x0, 1322 .res_ways = 0x0, 1323 .cache_mode = 0, 1324 .retain_on_pc = true, 1325 }, 1326 }; 1327 1328 static const struct llcc_slice_config sar2130p_data[] = { 1329 { 1330 .usecase_id = LLCC_CPUSS, 1331 .slice_id = 1, 1332 .max_cap = 6144, 1333 .priority = 1, 1334 .fixed_size = 0, 1335 .bonus_ways = 0x3fffffff, 1336 .res_ways = 0x0, 1337 .cache_mode = 0, 1338 .retain_on_pc = true, 1339 .activate_on_init = true, 1340 }, { 1341 .usecase_id = LLCC_VIDSC0, 1342 .slice_id = 2, 1343 .max_cap = 128, 1344 .priority = 2, 1345 .fixed_size = true, 1346 .bonus_ways = 0x3fffffff, 1347 .res_ways = 0x0, 1348 .cache_mode = 0, 1349 .retain_on_pc = true, 1350 }, { 1351 .usecase_id = LLCC_AUDIO, 1352 .slice_id = 6, 1353 .max_cap = 1024, 1354 .priority = 3, 1355 .fixed_size = true, 1356 .bonus_ways = 0x3fffffff, 1357 .res_ways = 0x0, 1358 .cache_mode = 0, 1359 .retain_on_pc = true, 1360 }, { 1361 .usecase_id = LLCC_CMPT, 1362 .slice_id = 10, 1363 .max_cap = 1024, 1364 .priority = 1, 1365 .fixed_size = true, 1366 .bonus_ways = 0x3fffffff, 1367 .res_ways = 0x0, 1368 .cache_mode = 0, 1369 .retain_on_pc = true, 1370 }, { 1371 .usecase_id = LLCC_GPUHTW, 1372 .slice_id = 11, 1373 .max_cap = 0, 1374 .priority = 1, 1375 .fixed_size = true, 1376 .bonus_ways = 0x3fffffff, 1377 .res_ways = 0x0, 1378 .cache_mode = 0, 1379 .retain_on_pc = true, 1380 }, { 1381 .usecase_id = LLCC_GPU, 1382 .slice_id = 12, 1383 .max_cap = 1536, 1384 .priority = 2, 1385 .fixed_size = true, 1386 .bonus_ways = 0x3fffffff, 1387 .res_ways = 0x0, 1388 .cache_mode = 0, 1389 .retain_on_pc = true, 1390 .write_scid_en = true, 1391 }, { 1392 .usecase_id = LLCC_MMUHWT, 1393 .slice_id = 13, 1394 .max_cap = 1024, 1395 .priority = 1, 1396 .fixed_size = true, 1397 .bonus_ways = 0x3fffffff, 1398 .res_ways = 0x0, 1399 .cache_mode = 0, 1400 .activate_on_init = true, 1401 }, { 1402 .usecase_id = LLCC_DISP, 1403 .slice_id = 16, 1404 .max_cap = 0, 1405 .priority = 1, 1406 .fixed_size = true, 1407 .bonus_ways = 0x3fffffff, 1408 .res_ways = 0x0, 1409 .cache_mode = 0, 1410 .retain_on_pc = true, 1411 }, { 1412 .usecase_id = LLCC_APTCM, 1413 .slice_id = 26, 1414 .max_cap = 2048, 1415 .priority = 3, 1416 .fixed_size = true, 1417 .bonus_ways = 0x0, 1418 .res_ways = 0x3, 1419 .cache_mode = true, 1420 .dis_cap_alloc = true, 1421 .retain_on_pc = true, 1422 }, { 1423 .usecase_id = LLCC_WRCACHE, 1424 .slice_id = 31, 1425 .max_cap = 256, 1426 .priority = 1, 1427 .fixed_size = true, 1428 .bonus_ways = 0x3fffffff, 1429 .res_ways = 0x0, 1430 .cache_mode = 0, 1431 .activate_on_init = true, 1432 }, { 1433 .usecase_id = LLCC_VIEYE, 1434 .slice_id = 7, 1435 .max_cap = 7168, 1436 .priority = 4, 1437 .fixed_size = true, 1438 .bonus_ways = 0x3fffffff, 1439 .res_ways = 0x0, 1440 .cache_mode = 0, 1441 .retain_on_pc = true, 1442 }, { 1443 .usecase_id = LLCC_VIDPTH, 1444 .slice_id = 8, 1445 .max_cap = 7168, 1446 .priority = 4, 1447 .fixed_size = true, 1448 .bonus_ways = 0x3fffffff, 1449 .res_ways = 0x0, 1450 .cache_mode = 0, 1451 .retain_on_pc = true, 1452 }, { 1453 .usecase_id = LLCC_GPUMV, 1454 .slice_id = 9, 1455 .max_cap = 2048, 1456 .priority = 2, 1457 .fixed_size = true, 1458 .bonus_ways = 0x3fffffff, 1459 .res_ways = 0x0, 1460 .cache_mode = 0, 1461 .retain_on_pc = true, 1462 }, { 1463 .usecase_id = LLCC_EVA_LEFT, 1464 .slice_id = 20, 1465 .max_cap = 7168, 1466 .priority = 5, 1467 .fixed_size = true, 1468 .bonus_ways = 0x3ffffffc, 1469 .res_ways = 0x0, 1470 .cache_mode = 0, 1471 .retain_on_pc = true, 1472 }, { 1473 .usecase_id = LLCC_EVA_RIGHT, 1474 .slice_id = 21, 1475 .max_cap = 7168, 1476 .priority = 5, 1477 .fixed_size = true, 1478 .bonus_ways = 0x3ffffffc, 1479 .res_ways = 0x0, 1480 .cache_mode = 0, 1481 .retain_on_pc = true, 1482 }, { 1483 .usecase_id = LLCC_EVAGAIN, 1484 .slice_id = 25, 1485 .max_cap = 1024, 1486 .priority = 2, 1487 .fixed_size = true, 1488 .bonus_ways = 0x3fffffff, 1489 .res_ways = 0x0, 1490 .cache_mode = 0, 1491 .retain_on_pc = true, 1492 }, { 1493 .usecase_id = LLCC_AENPU, 1494 .slice_id = 30, 1495 .max_cap = 3072, 1496 .priority = 3, 1497 .fixed_size = true, 1498 .bonus_ways = 0x3fffffff, 1499 .res_ways = 0x0, 1500 .cache_mode = 0, 1501 .retain_on_pc = true, 1502 }, { 1503 .usecase_id = LLCC_VIPTH, 1504 .slice_id = 29, 1505 .max_cap = 1024, 1506 .priority = 4, 1507 .fixed_size = true, 1508 .bonus_ways = 0x3fffffff, 1509 .res_ways = 0x0, 1510 .cache_mode = 0, 1511 .retain_on_pc = true, 1512 }, { 1513 .usecase_id = LLCC_DISP_LEFT, 1514 .slice_id = 17, 1515 .max_cap = 0, 1516 .priority = 1, 1517 .fixed_size = true, 1518 .bonus_ways = 0x0, 1519 .res_ways = 0x0, 1520 .cache_mode = 0, 1521 .retain_on_pc = true, 1522 }, { 1523 .usecase_id = LLCC_DISP_RIGHT, 1524 .slice_id = 18, 1525 .max_cap = 0, 1526 .priority = 1, 1527 .fixed_size = true, 1528 .bonus_ways = 0x0, 1529 .res_ways = 0x0, 1530 .cache_mode = 0, 1531 .retain_on_pc = true, 1532 }, { 1533 .usecase_id = LLCC_EVCS_LEFT, 1534 .slice_id = 22, 1535 .max_cap = 0, 1536 .priority = 1, 1537 .fixed_size = true, 1538 .bonus_ways = 0x0, 1539 .res_ways = 0x0, 1540 .cache_mode = 0, 1541 .retain_on_pc = true, 1542 }, { 1543 .usecase_id = LLCC_EVCS_RIGHT, 1544 .slice_id = 23, 1545 .max_cap = 0, 1546 .priority = 1, 1547 .fixed_size = true, 1548 .bonus_ways = 0x0, 1549 .res_ways = 0x0, 1550 .cache_mode = 0, 1551 .retain_on_pc = true, 1552 }, { 1553 .usecase_id = LLCC_SPAD, 1554 .slice_id = 24, 1555 .max_cap = 7168, 1556 .priority = 1, 1557 .fixed_size = true, 1558 .bonus_ways = 0x0, 1559 .res_ways = 0x0, 1560 .cache_mode = 0, 1561 .retain_on_pc = true, 1562 }, 1563 }; 1564 1565 static const struct llcc_slice_config sc7180_data[] = { 1566 { 1567 .usecase_id = LLCC_CPUSS, 1568 .slice_id = 1, 1569 .max_cap = 256, 1570 .priority = 1, 1571 .bonus_ways = 0xf, 1572 .cache_mode = 0, 1573 .retain_on_pc = true, 1574 .activate_on_init = true, 1575 }, { 1576 .usecase_id = LLCC_MDM, 1577 .slice_id = 8, 1578 .max_cap = 128, 1579 .priority = 1, 1580 .bonus_ways = 0xf, 1581 .cache_mode = 0, 1582 .retain_on_pc = true, 1583 }, { 1584 .usecase_id = LLCC_GPUHTW, 1585 .slice_id = 11, 1586 .max_cap = 128, 1587 .priority = 1, 1588 .bonus_ways = 0xf, 1589 .cache_mode = 0, 1590 .retain_on_pc = true, 1591 }, { 1592 .usecase_id = LLCC_GPU, 1593 .slice_id = 12, 1594 .max_cap = 128, 1595 .priority = 1, 1596 .bonus_ways = 0xf, 1597 .cache_mode = 0, 1598 .retain_on_pc = true, 1599 }, 1600 }; 1601 1602 static const struct llcc_slice_config sc7280_data[] = { 1603 { 1604 .usecase_id = LLCC_CPUSS, 1605 .slice_id = 1, 1606 .max_cap = 768, 1607 .priority = 1, 1608 .bonus_ways = 0x3f, 1609 .cache_mode = 0, 1610 .retain_on_pc = true, 1611 .activate_on_init = true, 1612 }, { 1613 .usecase_id = LLCC_MDMHPGRW, 1614 .slice_id = 7, 1615 .max_cap = 512, 1616 .priority = 2, 1617 .fixed_size = true, 1618 .bonus_ways = 0x3f, 1619 .cache_mode = 0, 1620 .retain_on_pc = true, 1621 }, { 1622 .usecase_id = LLCC_CMPT, 1623 .slice_id = 10, 1624 .max_cap = 768, 1625 .priority = 1, 1626 .fixed_size = true, 1627 .bonus_ways = 0x3f, 1628 .cache_mode = 0, 1629 .retain_on_pc = true, 1630 }, { 1631 .usecase_id = LLCC_GPUHTW, 1632 .slice_id = 11, 1633 .max_cap = 256, 1634 .priority = 1, 1635 .fixed_size = true, 1636 .bonus_ways = 0x3f, 1637 .cache_mode = 0, 1638 .retain_on_pc = true, 1639 }, { 1640 .usecase_id = LLCC_GPU, 1641 .slice_id = 12, 1642 .max_cap = 512, 1643 .priority = 1, 1644 .bonus_ways = 0x3f, 1645 .cache_mode = 0, 1646 .retain_on_pc = true, 1647 }, { 1648 .usecase_id = LLCC_MMUHWT, 1649 .slice_id = 13, 1650 .max_cap = 256, 1651 .priority = 1, 1652 .fixed_size = true, 1653 .bonus_ways = 0x3f, 1654 .cache_mode = 0, 1655 .activate_on_init = true, 1656 }, { 1657 .usecase_id = LLCC_MDMPNG, 1658 .slice_id = 21, 1659 .max_cap = 768, 1660 .priority = 0, 1661 .fixed_size = true, 1662 .bonus_ways = 0x3f, 1663 .cache_mode = 0, 1664 .retain_on_pc = true, 1665 }, { 1666 .usecase_id = LLCC_WLHW, 1667 .slice_id = 24, 1668 .max_cap = 256, 1669 .priority = 1, 1670 .fixed_size = true, 1671 .bonus_ways = 0x3f, 1672 .cache_mode = 0, 1673 .retain_on_pc = true, 1674 }, { 1675 .usecase_id = LLCC_MODPE, 1676 .slice_id = 29, 1677 .max_cap = 64, 1678 .priority = 1, 1679 .fixed_size = true, 1680 .bonus_ways = 0x3f, 1681 .cache_mode = 0, 1682 .retain_on_pc = true, 1683 }, 1684 }; 1685 1686 static const struct llcc_slice_config sc8180x_data[] = { 1687 { 1688 .usecase_id = LLCC_CPUSS, 1689 .slice_id = 1, 1690 .max_cap = 6144, 1691 .priority = 1, 1692 .fixed_size = true, 1693 .bonus_ways = 0xfff, 1694 .cache_mode = 0, 1695 .retain_on_pc = true, 1696 .activate_on_init = true, 1697 }, { 1698 .usecase_id = LLCC_VIDSC0, 1699 .slice_id = 2, 1700 .max_cap = 512, 1701 .priority = 2, 1702 .fixed_size = true, 1703 .bonus_ways = 0xfff, 1704 .cache_mode = 0, 1705 .retain_on_pc = true, 1706 }, { 1707 .usecase_id = LLCC_VIDSC1, 1708 .slice_id = 3, 1709 .max_cap = 512, 1710 .priority = 2, 1711 .fixed_size = true, 1712 .bonus_ways = 0xfff, 1713 .cache_mode = 0, 1714 .retain_on_pc = true, 1715 }, { 1716 .usecase_id = LLCC_AUDIO, 1717 .slice_id = 6, 1718 .max_cap = 1024, 1719 .priority = 1, 1720 .fixed_size = true, 1721 .bonus_ways = 0xfff, 1722 .cache_mode = 0, 1723 .retain_on_pc = true, 1724 }, { 1725 .usecase_id = LLCC_MDMHPGRW, 1726 .slice_id = 7, 1727 .max_cap = 3072, 1728 .priority = 1, 1729 .fixed_size = true, 1730 .bonus_ways = 0x3ff, 1731 .res_ways = 0xc00, 1732 .cache_mode = 0, 1733 .retain_on_pc = true, 1734 }, { 1735 .usecase_id = LLCC_MDM, 1736 .slice_id = 8, 1737 .max_cap = 3072, 1738 .priority = 1, 1739 .fixed_size = true, 1740 .bonus_ways = 0xfff, 1741 .cache_mode = 0, 1742 .retain_on_pc = true, 1743 }, { 1744 .usecase_id = LLCC_MODHW, 1745 .slice_id = 9, 1746 .max_cap = 1024, 1747 .priority = 1, 1748 .fixed_size = true, 1749 .bonus_ways = 0xfff, 1750 .cache_mode = 0, 1751 .retain_on_pc = true, 1752 }, { 1753 .usecase_id = LLCC_CMPT, 1754 .slice_id = 10, 1755 .max_cap = 6144, 1756 .priority = 1, 1757 .fixed_size = true, 1758 .bonus_ways = 0xfff, 1759 .cache_mode = 0, 1760 .retain_on_pc = true, 1761 }, { 1762 .usecase_id = LLCC_GPUHTW, 1763 .slice_id = 11, 1764 .max_cap = 1024, 1765 .priority = 1, 1766 .fixed_size = true, 1767 .bonus_ways = 0xfff, 1768 .cache_mode = 0, 1769 .retain_on_pc = true, 1770 }, { 1771 .usecase_id = LLCC_GPU, 1772 .slice_id = 12, 1773 .max_cap = 5120, 1774 .priority = 1, 1775 .fixed_size = true, 1776 .bonus_ways = 0xfff, 1777 .cache_mode = 0, 1778 .retain_on_pc = true, 1779 }, { 1780 .usecase_id = LLCC_MMUHWT, 1781 .slice_id = 13, 1782 .max_cap = 1024, 1783 .priority = 1, 1784 .fixed_size = true, 1785 .bonus_ways = 0xfff, 1786 .cache_mode = 0, 1787 .activate_on_init = true, 1788 }, { 1789 .usecase_id = LLCC_CMPTDMA, 1790 .slice_id = 15, 1791 .max_cap = 6144, 1792 .priority = 1, 1793 .fixed_size = true, 1794 .bonus_ways = 0xfff, 1795 .cache_mode = 0, 1796 .retain_on_pc = true, 1797 }, { 1798 .usecase_id = LLCC_DISP, 1799 .slice_id = 16, 1800 .max_cap = 6144, 1801 .priority = 1, 1802 .fixed_size = true, 1803 .bonus_ways = 0xfff, 1804 .cache_mode = 0, 1805 .retain_on_pc = true, 1806 }, { 1807 .usecase_id = LLCC_VIDFW, 1808 .slice_id = 17, 1809 .max_cap = 1024, 1810 .priority = 1, 1811 .fixed_size = true, 1812 .bonus_ways = 0xfff, 1813 .cache_mode = 0, 1814 .retain_on_pc = true, 1815 }, { 1816 .usecase_id = LLCC_MDMHPFX, 1817 .slice_id = 20, 1818 .max_cap = 1024, 1819 .priority = 2, 1820 .fixed_size = true, 1821 .bonus_ways = 0xfff, 1822 .cache_mode = 0, 1823 .retain_on_pc = true, 1824 }, { 1825 .usecase_id = LLCC_MDMPNG, 1826 .slice_id = 21, 1827 .max_cap = 1024, 1828 .priority = 0, 1829 .fixed_size = true, 1830 .bonus_ways = 0xc, 1831 .cache_mode = 0, 1832 .retain_on_pc = true, 1833 }, { 1834 .usecase_id = LLCC_AUDHW, 1835 .slice_id = 22, 1836 .max_cap = 1024, 1837 .priority = 1, 1838 .fixed_size = true, 1839 .bonus_ways = 0xfff, 1840 .cache_mode = 0, 1841 .retain_on_pc = true, 1842 }, { 1843 .usecase_id = LLCC_NPU, 1844 .slice_id = 23, 1845 .max_cap = 6144, 1846 .priority = 1, 1847 .fixed_size = true, 1848 .bonus_ways = 0xfff, 1849 .cache_mode = 0, 1850 .retain_on_pc = true, 1851 }, { 1852 .usecase_id = LLCC_WLHW, 1853 .slice_id = 24, 1854 .max_cap = 6144, 1855 .priority = 1, 1856 .fixed_size = true, 1857 .bonus_ways = 0xfff, 1858 .cache_mode = 0, 1859 .retain_on_pc = true, 1860 }, { 1861 .usecase_id = LLCC_MODPE, 1862 .slice_id = 29, 1863 .max_cap = 512, 1864 .priority = 1, 1865 .fixed_size = true, 1866 .bonus_ways = 0xc, 1867 .cache_mode = 0, 1868 .retain_on_pc = true, 1869 }, { 1870 .usecase_id = LLCC_APTCM, 1871 .slice_id = 30, 1872 .max_cap = 512, 1873 .priority = 3, 1874 .fixed_size = true, 1875 .res_ways = 0x1, 1876 .cache_mode = 1, 1877 .retain_on_pc = true, 1878 }, { 1879 .usecase_id = LLCC_WRCACHE, 1880 .slice_id = 31, 1881 .max_cap = 128, 1882 .priority = 1, 1883 .fixed_size = true, 1884 .bonus_ways = 0xfff, 1885 .cache_mode = 0, 1886 }, 1887 }; 1888 1889 static const struct llcc_slice_config sc8280xp_data[] = { 1890 { 1891 .usecase_id = LLCC_CPUSS, 1892 .slice_id = 1, 1893 .max_cap = 6144, 1894 .priority = 1, 1895 .fixed_size = true, 1896 .bonus_ways = 0xfff, 1897 .cache_mode = 0, 1898 .retain_on_pc = true, 1899 .activate_on_init = true, 1900 }, { 1901 .usecase_id = LLCC_VIDSC0, 1902 .slice_id = 2, 1903 .max_cap = 512, 1904 .priority = 3, 1905 .fixed_size = true, 1906 .bonus_ways = 0xfff, 1907 .cache_mode = 0, 1908 .retain_on_pc = true, 1909 }, { 1910 .usecase_id = LLCC_AUDIO, 1911 .slice_id = 6, 1912 .max_cap = 1024, 1913 .priority = 1, 1914 .fixed_size = true, 1915 .bonus_ways = 0xfff, 1916 .cache_mode = 0, 1917 }, { 1918 .usecase_id = LLCC_CMPT, 1919 .slice_id = 10, 1920 .max_cap = 6144, 1921 .priority = 1, 1922 .fixed_size = true, 1923 .bonus_ways = 0xfff, 1924 .cache_mode = 0, 1925 }, { 1926 .usecase_id = LLCC_GPUHTW, 1927 .slice_id = 11, 1928 .max_cap = 1024, 1929 .priority = 1, 1930 .fixed_size = true, 1931 .bonus_ways = 0xfff, 1932 .cache_mode = 0, 1933 .retain_on_pc = true, 1934 }, { 1935 .usecase_id = LLCC_GPU, 1936 .slice_id = 12, 1937 .max_cap = 4096, 1938 .priority = 1, 1939 .fixed_size = true, 1940 .bonus_ways = 0xfff, 1941 .cache_mode = 0, 1942 .retain_on_pc = true, 1943 .write_scid_en = true, 1944 }, { 1945 .usecase_id = LLCC_MMUHWT, 1946 .slice_id = 13, 1947 .max_cap = 1024, 1948 .priority = 1, 1949 .fixed_size = true, 1950 .bonus_ways = 0xfff, 1951 .cache_mode = 0, 1952 .activate_on_init = true, 1953 }, { 1954 .usecase_id = LLCC_DISP, 1955 .slice_id = 16, 1956 .max_cap = 6144, 1957 .priority = 1, 1958 .fixed_size = true, 1959 .bonus_ways = 0xfff, 1960 .cache_mode = 0, 1961 .retain_on_pc = true, 1962 }, { 1963 .usecase_id = LLCC_AUDHW, 1964 .slice_id = 22, 1965 .max_cap = 2048, 1966 .priority = 1, 1967 .fixed_size = true, 1968 .bonus_ways = 0xfff, 1969 .cache_mode = 0, 1970 .retain_on_pc = true, 1971 }, { 1972 .usecase_id = LLCC_ECC, 1973 .slice_id = 26, 1974 .max_cap = 1024, 1975 .priority = 1, 1976 .fixed_size = true, 1977 .bonus_ways = 0xfff, 1978 .cache_mode = 0, 1979 .retain_on_pc = true, 1980 }, { 1981 .usecase_id = LLCC_CVP, 1982 .slice_id = 28, 1983 .max_cap = 512, 1984 .priority = 3, 1985 .fixed_size = true, 1986 .bonus_ways = 0xfff, 1987 .cache_mode = 0, 1988 .retain_on_pc = true, 1989 }, { 1990 .usecase_id = LLCC_APTCM, 1991 .slice_id = 30, 1992 .max_cap = 1024, 1993 .priority = 3, 1994 .fixed_size = true, 1995 .res_ways = 0x1, 1996 .cache_mode = 1, 1997 .retain_on_pc = true, 1998 }, { 1999 .usecase_id = LLCC_WRCACHE, 2000 .slice_id = 31, 2001 .max_cap = 1024, 2002 .priority = 1, 2003 .fixed_size = true, 2004 .bonus_ways = 0xfff, 2005 .cache_mode = 0, 2006 .activate_on_init = true, 2007 }, { 2008 .usecase_id = LLCC_CVPFW, 2009 .slice_id = 17, 2010 .max_cap = 512, 2011 .priority = 1, 2012 .bonus_ways = 0xfff, 2013 .cache_mode = 0, 2014 .retain_on_pc = true, 2015 }, { 2016 .usecase_id = LLCC_CPUSS1, 2017 .slice_id = 3, 2018 .max_cap = 2048, 2019 .priority = 1, 2020 .fixed_size = true, 2021 .bonus_ways = 0xfff, 2022 .cache_mode = 0, 2023 .retain_on_pc = true, 2024 }, { 2025 .usecase_id = LLCC_CPUHWT, 2026 .slice_id = 5, 2027 .max_cap = 512, 2028 .priority = 1, 2029 .fixed_size = true, 2030 .bonus_ways = 0xfff, 2031 .cache_mode = 0, 2032 .activate_on_init = true, 2033 }, 2034 }; 2035 2036 static const struct llcc_slice_config sdm670_data[] = { 2037 { 2038 .usecase_id = LLCC_CPUSS, 2039 .slice_id = 1, 2040 .max_cap = 512, 2041 .priority = 1, 2042 .bonus_ways = 0xf, 2043 .res_ways = 0x0, 2044 .cache_mode = 0, 2045 .dis_cap_alloc = true, 2046 .retain_on_pc = true, 2047 .activate_on_init = true, 2048 }, { 2049 .usecase_id = LLCC_ROTATOR, 2050 .slice_id = 4, 2051 .max_cap = 384, 2052 .priority = 2, 2053 .fixed_size = true, 2054 .bonus_ways = 0x0, 2055 .res_ways = 0xe, 2056 .cache_mode = 2, 2057 .dis_cap_alloc = true, 2058 .retain_on_pc = true, 2059 }, { 2060 .usecase_id = LLCC_VOICE, 2061 .slice_id = 5, 2062 .max_cap = 512, 2063 .priority = 1, 2064 .bonus_ways = 0xf, 2065 .res_ways = 0x0, 2066 .cache_mode = 0, 2067 .dis_cap_alloc = true, 2068 .retain_on_pc = true, 2069 }, { 2070 .usecase_id = LLCC_AUDIO, 2071 .slice_id = 6, 2072 .max_cap = 512, 2073 .priority = 1, 2074 .bonus_ways = 0xf, 2075 .res_ways = 0x0, 2076 .cache_mode = 0, 2077 .dis_cap_alloc = true, 2078 .retain_on_pc = true, 2079 }, { 2080 .usecase_id = LLCC_MDM, 2081 .slice_id = 8, 2082 .max_cap = 512, 2083 .priority = 1, 2084 .bonus_ways = 0xf, 2085 .res_ways = 0x0, 2086 .cache_mode = 0, 2087 .dis_cap_alloc = true, 2088 .retain_on_pc = true, 2089 }, { 2090 .usecase_id = LLCC_GPU, 2091 .slice_id = 12, 2092 .max_cap = 384, 2093 .priority = 1, 2094 .fixed_size = true, 2095 .bonus_ways = 0x0, 2096 .res_ways = 0x0, 2097 .cache_mode = 0, 2098 .dis_cap_alloc = true, 2099 .retain_on_pc = true, 2100 }, { 2101 .usecase_id = LLCC_MMUHWT, 2102 .slice_id = 13, 2103 .max_cap = 512, 2104 .priority = 1, 2105 .bonus_ways = 0xf, 2106 .res_ways = 0x0, 2107 .cache_mode = 0, 2108 .dis_cap_alloc = true, 2109 .activate_on_init = true, 2110 }, { 2111 .usecase_id = LLCC_AUDHW, 2112 .slice_id = 22, 2113 .max_cap = 512, 2114 .priority = 1, 2115 .fixed_size = true, 2116 .bonus_ways = 0xf, 2117 .res_ways = 0x0, 2118 .cache_mode = 0, 2119 .dis_cap_alloc = true, 2120 .retain_on_pc = true, 2121 }, 2122 }; 2123 2124 static const struct llcc_slice_config sdm845_data[] = {{ 2125 .usecase_id = LLCC_CPUSS, 2126 .slice_id = 1, 2127 .max_cap = 2816, 2128 .priority = 1, 2129 .bonus_ways = 0xffc, 2130 .res_ways = 0x2, 2131 .cache_mode = 0, 2132 .dis_cap_alloc = true, 2133 .retain_on_pc = true, 2134 .activate_on_init = true, 2135 }, { 2136 .usecase_id = LLCC_VIDSC0, 2137 .slice_id = 2, 2138 .max_cap = 512, 2139 .priority = 2, 2140 .fixed_size = true, 2141 .res_ways = 0xf0, 2142 .cache_mode = 0, 2143 .dis_cap_alloc = true, 2144 .retain_on_pc = true, 2145 }, { 2146 .usecase_id = LLCC_VIDSC1, 2147 .slice_id = 3, 2148 .max_cap = 512, 2149 .priority = 2, 2150 .fixed_size = true, 2151 .res_ways = 0xf0, 2152 .cache_mode = 0, 2153 .dis_cap_alloc = true, 2154 .retain_on_pc = true, 2155 }, { 2156 .usecase_id = LLCC_ROTATOR, 2157 .slice_id = 4, 2158 .max_cap = 563, 2159 .priority = 2, 2160 .fixed_size = true, 2161 .res_ways = 0xe, 2162 .cache_mode = 2, 2163 .dis_cap_alloc = true, 2164 .retain_on_pc = true, 2165 }, { 2166 .usecase_id = LLCC_VOICE, 2167 .slice_id = 5, 2168 .max_cap = 2816, 2169 .priority = 1, 2170 .bonus_ways = 0xffc, 2171 .res_ways = 0x2, 2172 .cache_mode = 0, 2173 .dis_cap_alloc = true, 2174 .retain_on_pc = true, 2175 }, { 2176 .usecase_id = LLCC_AUDIO, 2177 .slice_id = 6, 2178 .max_cap = 2816, 2179 .priority = 1, 2180 .bonus_ways = 0xffc, 2181 .res_ways = 0x2, 2182 .cache_mode = 0, 2183 .dis_cap_alloc = true, 2184 .retain_on_pc = true, 2185 }, { 2186 .usecase_id = LLCC_MDMHPGRW, 2187 .slice_id = 7, 2188 .max_cap = 1024, 2189 .priority = 2, 2190 .bonus_ways = 0xfc, 2191 .res_ways = 0xf00, 2192 .cache_mode = 0, 2193 .dis_cap_alloc = true, 2194 .retain_on_pc = true, 2195 }, { 2196 .usecase_id = LLCC_MDM, 2197 .slice_id = 8, 2198 .max_cap = 2816, 2199 .priority = 1, 2200 .bonus_ways = 0xffc, 2201 .res_ways = 0x2, 2202 .cache_mode = 0, 2203 .dis_cap_alloc = true, 2204 .retain_on_pc = true, 2205 }, { 2206 .usecase_id = LLCC_CMPT, 2207 .slice_id = 10, 2208 .max_cap = 2816, 2209 .priority = 1, 2210 .bonus_ways = 0xffc, 2211 .res_ways = 0x2, 2212 .cache_mode = 0, 2213 .dis_cap_alloc = true, 2214 .retain_on_pc = true, 2215 }, { 2216 .usecase_id = LLCC_GPUHTW, 2217 .slice_id = 11, 2218 .max_cap = 512, 2219 .priority = 1, 2220 .fixed_size = true, 2221 .bonus_ways = 0xc, 2222 .cache_mode = 0, 2223 .dis_cap_alloc = true, 2224 .retain_on_pc = true, 2225 }, { 2226 .usecase_id = LLCC_GPU, 2227 .slice_id = 12, 2228 .max_cap = 2304, 2229 .priority = 1, 2230 .bonus_ways = 0xff0, 2231 .res_ways = 0x2, 2232 .cache_mode = 0, 2233 .dis_cap_alloc = true, 2234 .retain_on_pc = true, 2235 }, { 2236 .usecase_id = LLCC_MMUHWT, 2237 .slice_id = 13, 2238 .max_cap = 256, 2239 .priority = 2, 2240 .res_ways = 0x1, 2241 .cache_mode = 0, 2242 .dis_cap_alloc = true, 2243 .activate_on_init = true, 2244 }, { 2245 .usecase_id = LLCC_CMPTDMA, 2246 .slice_id = 15, 2247 .max_cap = 2816, 2248 .priority = 1, 2249 .bonus_ways = 0xffc, 2250 .res_ways = 0x2, 2251 .cache_mode = 0, 2252 .dis_cap_alloc = true, 2253 .retain_on_pc = true, 2254 }, { 2255 .usecase_id = LLCC_DISP, 2256 .slice_id = 16, 2257 .max_cap = 2816, 2258 .priority = 1, 2259 .bonus_ways = 0xffc, 2260 .res_ways = 0x2, 2261 .cache_mode = 0, 2262 .dis_cap_alloc = true, 2263 .retain_on_pc = true, 2264 }, { 2265 .usecase_id = LLCC_VIDFW, 2266 .slice_id = 17, 2267 .max_cap = 2816, 2268 .priority = 1, 2269 .bonus_ways = 0xffc, 2270 .res_ways = 0x2, 2271 .cache_mode = 0, 2272 .dis_cap_alloc = true, 2273 .retain_on_pc = true, 2274 }, { 2275 .usecase_id = LLCC_MDMHPFX, 2276 .slice_id = 20, 2277 .max_cap = 1024, 2278 .priority = 2, 2279 .fixed_size = true, 2280 .res_ways = 0xf00, 2281 .cache_mode = 0, 2282 .dis_cap_alloc = true, 2283 .retain_on_pc = true, 2284 }, { 2285 .usecase_id = LLCC_MDMPNG, 2286 .slice_id = 21, 2287 .max_cap = 1024, 2288 .priority = 0, 2289 .fixed_size = true, 2290 .bonus_ways = 0x1e, 2291 .cache_mode = 0, 2292 .dis_cap_alloc = true, 2293 .retain_on_pc = true, 2294 }, { 2295 .usecase_id = LLCC_AUDHW, 2296 .slice_id = 22, 2297 .max_cap = 1024, 2298 .priority = 1, 2299 .fixed_size = true, 2300 .bonus_ways = 0xffc, 2301 .res_ways = 0x2, 2302 .cache_mode = 0, 2303 .dis_cap_alloc = true, 2304 .retain_on_pc = true, 2305 }, 2306 }; 2307 2308 static const struct llcc_slice_config shikra_data[] = { 2309 { 2310 .usecase_id = LLCC_ECC, 2311 .slice_id = 26, 2312 .max_cap = 256, 2313 .priority = 3, 2314 .fixed_size = true, 2315 .bonus_ways = 0x3, 2316 .cache_mode = 0, 2317 .activate_on_init = true, 2318 .vict_prio = true, 2319 }, 2320 }; 2321 2322 static const struct llcc_slice_config sm6350_data[] = { 2323 { 2324 .usecase_id = LLCC_CPUSS, 2325 .slice_id = 1, 2326 .max_cap = 768, 2327 .priority = 1, 2328 .bonus_ways = 0xfff, 2329 .cache_mode = 0, 2330 .activate_on_init = true, 2331 .write_scid_en = true, 2332 }, { 2333 .usecase_id = LLCC_MDM, 2334 .slice_id = 8, 2335 .max_cap = 512, 2336 .priority = 2, 2337 .bonus_ways = 0xfff, 2338 .cache_mode = 0, 2339 .activate_on_init = true, 2340 }, { 2341 .usecase_id = LLCC_GPUHTW, 2342 .slice_id = 11, 2343 .max_cap = 256, 2344 .priority = 1, 2345 .bonus_ways = 0xfff, 2346 .cache_mode = 0, 2347 .activate_on_init = true, 2348 }, { 2349 .usecase_id = LLCC_GPU, 2350 .slice_id = 12, 2351 .max_cap = 512, 2352 .priority = 1, 2353 .bonus_ways = 0xfff, 2354 .cache_mode = 0, 2355 .activate_on_init = true, 2356 }, { 2357 .usecase_id = LLCC_MDMPNG, 2358 .slice_id = 21, 2359 .max_cap = 768, 2360 .priority = 0, 2361 .fixed_size = true, 2362 .bonus_ways = 0xfff, 2363 .cache_mode = 0, 2364 .activate_on_init = true, 2365 }, { 2366 .usecase_id = LLCC_NPU, 2367 .slice_id = 23, 2368 .max_cap = 768, 2369 .priority = 1, 2370 .bonus_ways = 0xfff, 2371 .cache_mode = 0, 2372 .activate_on_init = true, 2373 }, { 2374 .usecase_id = LLCC_MODPE, 2375 .slice_id = 29, 2376 .max_cap = 64, 2377 .priority = 1, 2378 .fixed_size = true, 2379 .bonus_ways = 0xfff, 2380 .cache_mode = 0, 2381 .activate_on_init = true, 2382 }, 2383 }; 2384 2385 static const struct llcc_slice_config sm7150_data[] = { 2386 { 2387 .usecase_id = LLCC_CPUSS, 2388 .slice_id = 1, 2389 .max_cap = 512, 2390 .priority = 1, 2391 .bonus_ways = 0xf, 2392 .cache_mode = 0, 2393 .retain_on_pc = true, 2394 .activate_on_init = true, 2395 }, { 2396 .usecase_id = LLCC_MDM, 2397 .slice_id = 8, 2398 .max_cap = 128, 2399 .priority = 2, 2400 .bonus_ways = 0xf, 2401 .cache_mode = 0, 2402 .retain_on_pc = true, 2403 }, { 2404 .usecase_id = LLCC_GPUHTW, 2405 .slice_id = 11, 2406 .max_cap = 256, 2407 .priority = 1, 2408 .fixed_size = true, 2409 .bonus_ways = 0xf, 2410 .cache_mode = 0, 2411 .retain_on_pc = true, 2412 }, { 2413 .usecase_id = LLCC_GPU, 2414 .slice_id = 12, 2415 .max_cap = 256, 2416 .priority = 1, 2417 .fixed_size = true, 2418 .bonus_ways = 0xf, 2419 .cache_mode = 0, 2420 .retain_on_pc = true, 2421 }, { 2422 .usecase_id = LLCC_NPU, 2423 .slice_id = 23, 2424 .max_cap = 512, 2425 .priority = 1, 2426 .bonus_ways = 0xf, 2427 .cache_mode = 0, 2428 .retain_on_pc = true, 2429 }, 2430 }; 2431 2432 static const struct llcc_slice_config sm8150_data[] = { 2433 { 2434 .usecase_id = LLCC_CPUSS, 2435 .slice_id = 1, 2436 .max_cap = 3072, 2437 .priority = 1, 2438 .fixed_size = true, 2439 .bonus_ways = 0xfff, 2440 .cache_mode = 0, 2441 .retain_on_pc = true, 2442 .activate_on_init = true, 2443 }, { 2444 .usecase_id = LLCC_VIDSC0, 2445 .slice_id = 2, 2446 .max_cap = 512, 2447 .priority = 2, 2448 .fixed_size = true, 2449 .bonus_ways = 0xfff, 2450 .cache_mode = 0, 2451 .retain_on_pc = true, 2452 }, { 2453 .usecase_id = LLCC_VIDSC1, 2454 .slice_id = 3, 2455 .max_cap = 512, 2456 .priority = 2, 2457 .fixed_size = true, 2458 .bonus_ways = 0xfff, 2459 .cache_mode = 0, 2460 .retain_on_pc = true, 2461 }, { 2462 .usecase_id = LLCC_AUDIO, 2463 .slice_id = 6, 2464 .max_cap = 1024, 2465 .priority = 1, 2466 .fixed_size = true, 2467 .bonus_ways = 0xfff, 2468 .cache_mode = 0, 2469 .retain_on_pc = true, 2470 }, { 2471 .usecase_id = LLCC_MDMHPGRW, 2472 .slice_id = 7, 2473 .max_cap = 3072, 2474 .priority = 1, 2475 .bonus_ways = 0xff, 2476 .res_ways = 0xf00, 2477 .cache_mode = 0, 2478 .retain_on_pc = true, 2479 }, { 2480 .usecase_id = LLCC_MDM, 2481 .slice_id = 8, 2482 .max_cap = 3072, 2483 .priority = 1, 2484 .fixed_size = true, 2485 .bonus_ways = 0xfff, 2486 .cache_mode = 0, 2487 .retain_on_pc = true, 2488 }, { 2489 .usecase_id = LLCC_MODHW, 2490 .slice_id = 9, 2491 .max_cap = 1024, 2492 .priority = 1, 2493 .fixed_size = true, 2494 .bonus_ways = 0xfff, 2495 .cache_mode = 0, 2496 .retain_on_pc = true, 2497 }, { 2498 .usecase_id = LLCC_CMPT, 2499 .slice_id = 10, 2500 .max_cap = 3072, 2501 .priority = 1, 2502 .fixed_size = true, 2503 .bonus_ways = 0xfff, 2504 .cache_mode = 0, 2505 .retain_on_pc = true, 2506 }, { 2507 .usecase_id = LLCC_GPUHTW, 2508 .slice_id = 11, 2509 .max_cap = 512, 2510 .priority = 1, 2511 .fixed_size = true, 2512 .bonus_ways = 0xfff, 2513 .cache_mode = 0, 2514 .retain_on_pc = true, 2515 }, { 2516 .usecase_id = LLCC_GPU, 2517 .slice_id = 12, 2518 .max_cap = 2560, 2519 .priority = 1, 2520 .fixed_size = true, 2521 .bonus_ways = 0xfff, 2522 .cache_mode = 0, 2523 .retain_on_pc = true, 2524 }, { 2525 .usecase_id = LLCC_MMUHWT, 2526 .slice_id = 13, 2527 .max_cap = 1024, 2528 .priority = 1, 2529 .fixed_size = true, 2530 .bonus_ways = 0xfff, 2531 .cache_mode = 0, 2532 .activate_on_init = true, 2533 }, { 2534 .usecase_id = LLCC_CMPTDMA, 2535 .slice_id = 15, 2536 .max_cap = 3072, 2537 .priority = 1, 2538 .fixed_size = true, 2539 .bonus_ways = 0xfff, 2540 .cache_mode = 0, 2541 .retain_on_pc = true, 2542 }, { 2543 .usecase_id = LLCC_DISP, 2544 .slice_id = 16, 2545 .max_cap = 3072, 2546 .priority = 1, 2547 .fixed_size = true, 2548 .bonus_ways = 0xfff, 2549 .cache_mode = 0, 2550 .retain_on_pc = true, 2551 }, { 2552 .usecase_id = LLCC_MDMHPFX, 2553 .slice_id = 20, 2554 .max_cap = 1024, 2555 .priority = 2, 2556 .fixed_size = true, 2557 .bonus_ways = 0xfff, 2558 .cache_mode = 0, 2559 .retain_on_pc = true, 2560 }, { 2561 .usecase_id = LLCC_MDMHPFX, 2562 .slice_id = 21, 2563 .max_cap = 1024, 2564 .priority = 0, 2565 .fixed_size = true, 2566 .bonus_ways = 0xf, 2567 .cache_mode = 0, 2568 .retain_on_pc = true, 2569 }, { 2570 .usecase_id = LLCC_AUDHW, 2571 .slice_id = 22, 2572 .max_cap = 1024, 2573 .priority = 1, 2574 .fixed_size = true, 2575 .bonus_ways = 0xfff, 2576 .cache_mode = 0, 2577 .retain_on_pc = true, 2578 }, { 2579 .usecase_id = LLCC_NPU, 2580 .slice_id = 23, 2581 .max_cap = 3072, 2582 .priority = 1, 2583 .fixed_size = true, 2584 .bonus_ways = 0xfff, 2585 .cache_mode = 0, 2586 .retain_on_pc = true, 2587 }, { 2588 .usecase_id = LLCC_WLHW, 2589 .slice_id = 24, 2590 .max_cap = 3072, 2591 .priority = 1, 2592 .fixed_size = true, 2593 .bonus_ways = 0xfff, 2594 .cache_mode = 0, 2595 .retain_on_pc = true, 2596 }, { 2597 .usecase_id = LLCC_MODPE, 2598 .slice_id = 29, 2599 .max_cap = 256, 2600 .priority = 1, 2601 .fixed_size = true, 2602 .bonus_ways = 0xf, 2603 .cache_mode = 0, 2604 .retain_on_pc = true, 2605 }, { 2606 .usecase_id = LLCC_APTCM, 2607 .slice_id = 30, 2608 .max_cap = 256, 2609 .priority = 3, 2610 .fixed_size = true, 2611 .res_ways = 0x1, 2612 .cache_mode = 1, 2613 .retain_on_pc = true, 2614 }, { 2615 .usecase_id = LLCC_WRCACHE, 2616 .slice_id = 31, 2617 .max_cap = 128, 2618 .priority = 1, 2619 .fixed_size = true, 2620 .bonus_ways = 0xfff, 2621 .cache_mode = 0, 2622 }, 2623 }; 2624 2625 static const struct llcc_slice_config sm8250_data[] = { 2626 { 2627 .usecase_id = LLCC_CPUSS, 2628 .slice_id = 1, 2629 .max_cap = 3072, 2630 .priority = 1, 2631 .fixed_size = true, 2632 .bonus_ways = 0xfff, 2633 .cache_mode = 0, 2634 .retain_on_pc = true, 2635 .activate_on_init = true, 2636 }, { 2637 .usecase_id = LLCC_VIDSC0, 2638 .slice_id = 2, 2639 .max_cap = 512, 2640 .priority = 3, 2641 .fixed_size = true, 2642 .bonus_ways = 0xfff, 2643 .cache_mode = 0, 2644 .retain_on_pc = true, 2645 }, { 2646 .usecase_id = LLCC_AUDIO, 2647 .slice_id = 6, 2648 .max_cap = 1024, 2649 .priority = 1, 2650 .bonus_ways = 0xfff, 2651 .cache_mode = 0, 2652 }, { 2653 .usecase_id = LLCC_CMPT, 2654 .slice_id = 10, 2655 .max_cap = 1024, 2656 .priority = 1, 2657 .bonus_ways = 0xfff, 2658 .cache_mode = 0, 2659 }, { 2660 .usecase_id = LLCC_GPUHTW, 2661 .slice_id = 11, 2662 .max_cap = 1024, 2663 .priority = 1, 2664 .fixed_size = true, 2665 .bonus_ways = 0xfff, 2666 .cache_mode = 0, 2667 .retain_on_pc = true, 2668 }, { 2669 .usecase_id = LLCC_GPU, 2670 .slice_id = 12, 2671 .max_cap = 1024, 2672 .priority = 1, 2673 .bonus_ways = 0xfff, 2674 .cache_mode = 0, 2675 .retain_on_pc = true, 2676 .write_scid_en = true, 2677 }, { 2678 .usecase_id = LLCC_MMUHWT, 2679 .slice_id = 13, 2680 .max_cap = 1024, 2681 .priority = 1, 2682 .fixed_size = true, 2683 .bonus_ways = 0xfff, 2684 .cache_mode = 0, 2685 .activate_on_init = true, 2686 }, { 2687 .usecase_id = LLCC_CMPTDMA, 2688 .slice_id = 15, 2689 .max_cap = 1024, 2690 .priority = 1, 2691 .bonus_ways = 0xfff, 2692 .cache_mode = 0, 2693 .retain_on_pc = true, 2694 }, { 2695 .usecase_id = LLCC_DISP, 2696 .slice_id = 16, 2697 .max_cap = 3072, 2698 .priority = 1, 2699 .fixed_size = true, 2700 .bonus_ways = 0xfff, 2701 .cache_mode = 0, 2702 .retain_on_pc = true, 2703 }, { 2704 .usecase_id = LLCC_VIDFW, 2705 .slice_id = 17, 2706 .max_cap = 512, 2707 .priority = 1, 2708 .bonus_ways = 0xfff, 2709 .cache_mode = 0, 2710 .retain_on_pc = true, 2711 }, { 2712 .usecase_id = LLCC_AUDHW, 2713 .slice_id = 22, 2714 .max_cap = 1024, 2715 .priority = 1, 2716 .fixed_size = true, 2717 .bonus_ways = 0xfff, 2718 .cache_mode = 0, 2719 .retain_on_pc = true, 2720 }, { 2721 .usecase_id = LLCC_NPU, 2722 .slice_id = 23, 2723 .max_cap = 3072, 2724 .priority = 1, 2725 .fixed_size = true, 2726 .bonus_ways = 0xfff, 2727 .cache_mode = 0, 2728 .retain_on_pc = true, 2729 }, { 2730 .usecase_id = LLCC_WLHW, 2731 .slice_id = 24, 2732 .max_cap = 1024, 2733 .priority = 1, 2734 .bonus_ways = 0xfff, 2735 .cache_mode = 0, 2736 .retain_on_pc = true, 2737 }, { 2738 .usecase_id = LLCC_CVP, 2739 .slice_id = 28, 2740 .max_cap = 256, 2741 .priority = 3, 2742 .fixed_size = true, 2743 .bonus_ways = 0xfff, 2744 .cache_mode = 0, 2745 .retain_on_pc = true, 2746 }, { 2747 .usecase_id = LLCC_APTCM, 2748 .slice_id = 30, 2749 .max_cap = 128, 2750 .priority = 3, 2751 .res_ways = 0x3, 2752 .cache_mode = 1, 2753 .retain_on_pc = true, 2754 }, { 2755 .usecase_id = LLCC_WRCACHE, 2756 .slice_id = 31, 2757 .max_cap = 256, 2758 .priority = 1, 2759 .fixed_size = true, 2760 .bonus_ways = 0xfff, 2761 .cache_mode = 0, 2762 .activate_on_init = true, 2763 }, 2764 }; 2765 2766 static const struct llcc_slice_config sm8350_data[] = { 2767 { 2768 .usecase_id = LLCC_CPUSS, 2769 .slice_id = 1, 2770 .max_cap = 3072, 2771 .priority = 1, 2772 .fixed_size = true, 2773 .bonus_ways = 0xfff, 2774 .cache_mode = 0, 2775 .activate_on_init = true, 2776 .write_scid_en = true, 2777 }, { 2778 .usecase_id = LLCC_VIDSC0, 2779 .slice_id = 2, 2780 .max_cap = 512, 2781 .priority = 3, 2782 .fixed_size = true, 2783 .bonus_ways = 0xfff, 2784 .cache_mode = 0, 2785 .activate_on_init = true, 2786 }, { 2787 .usecase_id = LLCC_AUDIO, 2788 .slice_id = 6, 2789 .max_cap = 1024, 2790 .priority = 1, 2791 .fixed_size = true, 2792 .bonus_ways = 0xfff, 2793 .cache_mode = 0, 2794 }, { 2795 .usecase_id = LLCC_MDMHPGRW, 2796 .slice_id = 7, 2797 .max_cap = 1024, 2798 .priority = 3, 2799 .bonus_ways = 0xfff, 2800 .cache_mode = 0, 2801 .activate_on_init = true, 2802 }, { 2803 .usecase_id = LLCC_MODHW, 2804 .slice_id = 9, 2805 .max_cap = 1024, 2806 .priority = 1, 2807 .fixed_size = true, 2808 .bonus_ways = 0xfff, 2809 .cache_mode = 0, 2810 .activate_on_init = true, 2811 }, { 2812 .usecase_id = LLCC_CMPT, 2813 .slice_id = 10, 2814 .max_cap = 3072, 2815 .priority = 1, 2816 .fixed_size = true, 2817 .bonus_ways = 0xfff, 2818 .cache_mode = 0, 2819 .activate_on_init = true, 2820 }, { 2821 .usecase_id = LLCC_GPUHTW, 2822 .slice_id = 11, 2823 .max_cap = 1024, 2824 .priority = 1, 2825 .fixed_size = true, 2826 .bonus_ways = 0xfff, 2827 .cache_mode = 0, 2828 .activate_on_init = true, 2829 }, { 2830 .usecase_id = LLCC_GPU, 2831 .slice_id = 12, 2832 .max_cap = 1024, 2833 .priority = 1, 2834 .bonus_ways = 0xfff, 2835 .cache_mode = 0, 2836 .retain_on_pc = true, 2837 .activate_on_init = true, 2838 }, { 2839 .usecase_id = LLCC_MMUHWT, 2840 .slice_id = 13, 2841 .max_cap = 1024, 2842 .priority = 1, 2843 .fixed_size = true, 2844 .bonus_ways = 0xfff, 2845 .cache_mode = 0, 2846 .write_scid_en = true, 2847 }, { 2848 .usecase_id = LLCC_DISP, 2849 .slice_id = 16, 2850 .max_cap = 3072, 2851 .priority = 2, 2852 .fixed_size = true, 2853 .bonus_ways = 0xfff, 2854 .cache_mode = 0, 2855 .activate_on_init = true, 2856 }, { 2857 .usecase_id = LLCC_MDMPNG, 2858 .slice_id = 21, 2859 .max_cap = 1024, 2860 .priority = 0, 2861 .fixed_size = true, 2862 .bonus_ways = 0xf, 2863 .cache_mode = 0, 2864 .activate_on_init = true, 2865 }, { 2866 .usecase_id = LLCC_AUDHW, 2867 .slice_id = 22, 2868 .max_cap = 1024, 2869 .priority = 1, 2870 .fixed_size = true, 2871 .bonus_ways = 0xfff, 2872 .cache_mode = 0, 2873 .activate_on_init = true, 2874 }, { 2875 .usecase_id = LLCC_CVP, 2876 .slice_id = 28, 2877 .max_cap = 512, 2878 .priority = 3, 2879 .fixed_size = true, 2880 .bonus_ways = 0xfff, 2881 .cache_mode = 0, 2882 .activate_on_init = true, 2883 }, { 2884 .usecase_id = LLCC_MODPE, 2885 .slice_id = 29, 2886 .max_cap = 256, 2887 .priority = 1, 2888 .fixed_size = true, 2889 .bonus_ways = 0xf, 2890 .cache_mode = 0, 2891 .activate_on_init = true, 2892 }, { 2893 .usecase_id = LLCC_APTCM, 2894 .slice_id = 30, 2895 .max_cap = 1024, 2896 .priority = 3, 2897 .fixed_size = true, 2898 .res_ways = 0x1, 2899 .cache_mode = 1, 2900 .activate_on_init = true, 2901 }, { 2902 .usecase_id = LLCC_WRCACHE, 2903 .slice_id = 31, 2904 .max_cap = 512, 2905 .priority = 1, 2906 .fixed_size = true, 2907 .bonus_ways = 0xfff, 2908 .cache_mode = 0, 2909 .write_scid_en = true, 2910 }, { 2911 .usecase_id = LLCC_CVPFW, 2912 .slice_id = 17, 2913 .max_cap = 512, 2914 .priority = 1, 2915 .bonus_ways = 0xfff, 2916 .cache_mode = 0, 2917 .activate_on_init = true, 2918 }, { 2919 .usecase_id = LLCC_CPUSS1, 2920 .slice_id = 3, 2921 .max_cap = 1024, 2922 .priority = 1, 2923 .fixed_size = true, 2924 .bonus_ways = 0xfff, 2925 .cache_mode = 0, 2926 .activate_on_init = true, 2927 }, { 2928 .usecase_id = LLCC_CPUHWT, 2929 .slice_id = 5, 2930 .max_cap = 512, 2931 .priority = 1, 2932 .fixed_size = true, 2933 .bonus_ways = 0xfff, 2934 .cache_mode = 0, 2935 .write_scid_en = true, 2936 }, 2937 }; 2938 2939 static const struct llcc_slice_config sm8450_data[] = { 2940 { 2941 .usecase_id = LLCC_CPUSS, 2942 .slice_id = 1, 2943 .max_cap = 3072, 2944 .priority = 1, 2945 .bonus_ways = 0xffff, 2946 .cache_mode = 0, 2947 .retain_on_pc = true, 2948 .activate_on_init = true, 2949 }, { 2950 .usecase_id = LLCC_VIDSC0, 2951 .slice_id = 2, 2952 .max_cap = 512, 2953 .priority = 3, 2954 .fixed_size = true, 2955 .bonus_ways = 0xffff, 2956 .cache_mode = 0, 2957 .retain_on_pc = true, 2958 }, { 2959 .usecase_id = LLCC_AUDIO, 2960 .slice_id = 6, 2961 .max_cap = 1024, 2962 .priority = 1, 2963 .fixed_size = true, 2964 .bonus_ways = 0xffff, 2965 .cache_mode = 0, 2966 }, { 2967 .usecase_id = LLCC_MDMHPGRW, 2968 .slice_id = 7, 2969 .max_cap = 1024, 2970 .priority = 3, 2971 .bonus_ways = 0xffff, 2972 .cache_mode = 0, 2973 .retain_on_pc = true, 2974 }, { 2975 .usecase_id = LLCC_MODHW, 2976 .slice_id = 9, 2977 .max_cap = 1024, 2978 .priority = 1, 2979 .fixed_size = true, 2980 .bonus_ways = 0xffff, 2981 .cache_mode = 0, 2982 .retain_on_pc = true, 2983 }, { 2984 .usecase_id = LLCC_CMPT, 2985 .slice_id = 10, 2986 .max_cap = 4096, 2987 .priority = 1, 2988 .fixed_size = true, 2989 .bonus_ways = 0xffff, 2990 .cache_mode = 0, 2991 .retain_on_pc = true, 2992 }, { 2993 .usecase_id = LLCC_GPUHTW, 2994 .slice_id = 11, 2995 .max_cap = 512, 2996 .priority = 1, 2997 .fixed_size = true, 2998 .bonus_ways = 0xffff, 2999 .cache_mode = 0, 3000 .retain_on_pc = true, 3001 }, { 3002 .usecase_id = LLCC_GPU, 3003 .slice_id = 12, 3004 .max_cap = 2048, 3005 .priority = 1, 3006 .fixed_size = true, 3007 .bonus_ways = 0xffff, 3008 .cache_mode = 0, 3009 .retain_on_pc = true, 3010 .write_scid_en = true, 3011 }, { 3012 .usecase_id = LLCC_MMUHWT, 3013 .slice_id = 13, 3014 .max_cap = 768, 3015 .priority = 1, 3016 .fixed_size = true, 3017 .bonus_ways = 0xffff, 3018 .cache_mode = 0, 3019 .activate_on_init = true, 3020 }, { 3021 .usecase_id = LLCC_DISP, 3022 .slice_id = 16, 3023 .max_cap = 4096, 3024 .priority = 2, 3025 .fixed_size = true, 3026 .bonus_ways = 0xffff, 3027 .cache_mode = 0, 3028 .retain_on_pc = true, 3029 }, { 3030 .usecase_id = LLCC_MDMPNG, 3031 .slice_id = 21, 3032 .max_cap = 1024, 3033 .priority = 1, 3034 .fixed_size = true, 3035 .bonus_ways = 0xf000, 3036 .cache_mode = 0, 3037 .retain_on_pc = true, 3038 }, { 3039 .usecase_id = LLCC_AUDHW, 3040 .slice_id = 22, 3041 .max_cap = 1024, 3042 .priority = 1, 3043 .fixed_size = true, 3044 .bonus_ways = 0xffff, 3045 .cache_mode = 0, 3046 }, { 3047 .usecase_id = LLCC_CVP, 3048 .slice_id = 28, 3049 .max_cap = 256, 3050 .priority = 3, 3051 .fixed_size = true, 3052 .bonus_ways = 0xffff, 3053 .cache_mode = 0, 3054 .retain_on_pc = true, 3055 }, { 3056 .usecase_id = LLCC_MODPE, 3057 .slice_id = 29, 3058 .max_cap = 64, 3059 .priority = 1, 3060 .fixed_size = true, 3061 .bonus_ways = 0xf000, 3062 .cache_mode = 0, 3063 .retain_on_pc = true, 3064 }, { 3065 .usecase_id = LLCC_APTCM, 3066 .slice_id = 30, 3067 .max_cap = 1024, 3068 .priority = 3, 3069 .fixed_size = true, 3070 .res_ways = 0xf0, 3071 .cache_mode = 1, 3072 .retain_on_pc = true, 3073 }, { 3074 .usecase_id = LLCC_WRCACHE, 3075 .slice_id = 31, 3076 .max_cap = 512, 3077 .priority = 1, 3078 .fixed_size = true, 3079 .bonus_ways = 0xffff, 3080 .cache_mode = 0, 3081 .activate_on_init = true, 3082 }, { 3083 .usecase_id = LLCC_CVPFW, 3084 .slice_id = 17, 3085 .max_cap = 512, 3086 .priority = 1, 3087 .fixed_size = true, 3088 .bonus_ways = 0xffff, 3089 .cache_mode = 0, 3090 .retain_on_pc = true, 3091 }, { 3092 .usecase_id = LLCC_CPUSS1, 3093 .slice_id = 3, 3094 .max_cap = 1024, 3095 .priority = 1, 3096 .fixed_size = true, 3097 .bonus_ways = 0xffff, 3098 .cache_mode = 0, 3099 .retain_on_pc = true, 3100 }, { 3101 .usecase_id = LLCC_CAMEXP0, 3102 .slice_id = 4, 3103 .max_cap = 256, 3104 .priority = 3, 3105 .fixed_size = true, 3106 .bonus_ways = 0xffff, 3107 .cache_mode = 0, 3108 .retain_on_pc = true, 3109 }, { 3110 .usecase_id = LLCC_CPUMTE, 3111 .slice_id = 23, 3112 .max_cap = 256, 3113 .priority = 1, 3114 .fixed_size = true, 3115 .bonus_ways = 0xfff, 3116 .cache_mode = 0, 3117 .activate_on_init = true, 3118 }, { 3119 .usecase_id = LLCC_CPUHWT, 3120 .slice_id = 5, 3121 .max_cap = 512, 3122 .priority = 1, 3123 .fixed_size = true, 3124 .bonus_ways = 0xffff, 3125 .cache_mode = 0, 3126 .retain_on_pc = true, 3127 .activate_on_init = true, 3128 }, { 3129 .usecase_id = LLCC_CAMEXP1, 3130 .slice_id = 27, 3131 .max_cap = 256, 3132 .priority = 3, 3133 .fixed_size = true, 3134 .bonus_ways = 0xffff, 3135 .cache_mode = 0, 3136 .retain_on_pc = true, 3137 }, { 3138 .usecase_id = LLCC_AENPU, 3139 .slice_id = 8, 3140 .max_cap = 2048, 3141 .priority = 1, 3142 .fixed_size = true, 3143 .bonus_ways = 0xffff, 3144 .cache_mode = 0, 3145 }, 3146 }; 3147 3148 static const struct llcc_slice_config sm8550_data[] = { 3149 { 3150 .usecase_id = LLCC_CPUSS, 3151 .slice_id = 1, 3152 .max_cap = 5120, 3153 .priority = 1, 3154 .bonus_ways = 0xffffff, 3155 .cache_mode = 0, 3156 .activate_on_init = true, 3157 .write_scid_en = true, 3158 }, { 3159 .usecase_id = LLCC_VIDSC0, 3160 .slice_id = 2, 3161 .max_cap = 512, 3162 .priority = 4, 3163 .fixed_size = true, 3164 .bonus_ways = 0xffffff, 3165 .cache_mode = 0, 3166 }, { 3167 .usecase_id = LLCC_AUDIO, 3168 .slice_id = 6, 3169 .max_cap = 1024, 3170 .priority = 1, 3171 .fixed_size = true, 3172 .bonus_ways = 0xffffff, 3173 .cache_mode = 0, 3174 }, { 3175 .usecase_id = LLCC_MDMHPGRW, 3176 .slice_id = 25, 3177 .max_cap = 1024, 3178 .priority = 4, 3179 .bonus_ways = 0xffffff, 3180 .cache_mode = 0, 3181 }, { 3182 .usecase_id = LLCC_MODHW, 3183 .slice_id = 26, 3184 .max_cap = 1024, 3185 .priority = 1, 3186 .fixed_size = true, 3187 .bonus_ways = 0xffffff, 3188 .cache_mode = 0, 3189 }, { 3190 .usecase_id = LLCC_CMPT, 3191 .slice_id = 10, 3192 .max_cap = 4096, 3193 .priority = 1, 3194 .fixed_size = true, 3195 .bonus_ways = 0xffffff, 3196 .cache_mode = 0, 3197 }, { 3198 .usecase_id = LLCC_GPUHTW, 3199 .slice_id = 11, 3200 .max_cap = 512, 3201 .priority = 1, 3202 .fixed_size = true, 3203 .bonus_ways = 0xffffff, 3204 .cache_mode = 0, 3205 }, { 3206 .usecase_id = LLCC_GPU, 3207 .slice_id = 9, 3208 .max_cap = 3096, 3209 .priority = 1, 3210 .bonus_ways = 0xffffff, 3211 .cache_mode = 0, 3212 .write_scid_en = true, 3213 .write_scid_cacheable_en = true, 3214 }, { 3215 .usecase_id = LLCC_MMUHWT, 3216 .slice_id = 18, 3217 .max_cap = 768, 3218 .priority = 1, 3219 .fixed_size = true, 3220 .bonus_ways = 0xffffff, 3221 .cache_mode = 0, 3222 .activate_on_init = true, 3223 }, { 3224 .usecase_id = LLCC_DISP, 3225 .slice_id = 16, 3226 .max_cap = 6144, 3227 .priority = 1, 3228 .fixed_size = true, 3229 .bonus_ways = 0xffffff, 3230 .cache_mode = 2, 3231 }, { 3232 .usecase_id = LLCC_MDMPNG, 3233 .slice_id = 27, 3234 .max_cap = 1024, 3235 .priority = 0, 3236 .fixed_size = true, 3237 .bonus_ways = 0xf00000, 3238 .cache_mode = 0, 3239 }, { 3240 .usecase_id = LLCC_AUDHW, 3241 .slice_id = 22, 3242 .max_cap = 1024, 3243 .priority = 1, 3244 .fixed_size = true, 3245 .bonus_ways = 0xffffff, 3246 .cache_mode = 0, 3247 }, { 3248 .usecase_id = LLCC_CVP, 3249 .slice_id = 8, 3250 .max_cap = 256, 3251 .priority = 4, 3252 .fixed_size = true, 3253 .bonus_ways = 0xffffff, 3254 .cache_mode = 0, 3255 }, { 3256 .usecase_id = LLCC_MODPE, 3257 .slice_id = 29, 3258 .max_cap = 64, 3259 .priority = 1, 3260 .fixed_size = true, 3261 .bonus_ways = 0xf00000, 3262 .cache_mode = 0, 3263 .alloc_oneway_en = true, 3264 .vict_prio = true, 3265 }, { 3266 .usecase_id = LLCC_WRCACHE, 3267 .slice_id = 31, 3268 .max_cap = 512, 3269 .priority = 1, 3270 .fixed_size = true, 3271 .bonus_ways = 0xffffff, 3272 .cache_mode = 0, 3273 .activate_on_init = true, 3274 }, { 3275 .usecase_id = LLCC_CAMEXP0, 3276 .slice_id = 4, 3277 .max_cap = 256, 3278 .priority = 4, 3279 .fixed_size = true, 3280 .bonus_ways = 0xf, 3281 .cache_mode = 0, 3282 }, { 3283 .usecase_id = LLCC_CPUHWT, 3284 .slice_id = 5, 3285 .max_cap = 512, 3286 .priority = 1, 3287 .fixed_size = true, 3288 .bonus_ways = 0xffffff, 3289 .cache_mode = 0, 3290 .activate_on_init = true, 3291 }, { 3292 .usecase_id = LLCC_CAMEXP1, 3293 .slice_id = 7, 3294 .max_cap = 3200, 3295 .priority = 3, 3296 .fixed_size = true, 3297 .bonus_ways = 0xfffff0, 3298 .cache_mode = 2, 3299 }, { 3300 .usecase_id = LLCC_CMPTHCP, 3301 .slice_id = 17, 3302 .max_cap = 256, 3303 .priority = 4, 3304 .fixed_size = true, 3305 .bonus_ways = 0xffffff, 3306 .cache_mode = 0, 3307 }, { 3308 .usecase_id = LLCC_LCPDARE, 3309 .slice_id = 30, 3310 .max_cap = 128, 3311 .priority = 4, 3312 .fixed_size = true, 3313 .bonus_ways = 0xffffff, 3314 .cache_mode = 0, 3315 .activate_on_init = true, 3316 .alloc_oneway_en = true, 3317 .vict_prio = true, 3318 }, { 3319 .usecase_id = LLCC_AENPU, 3320 .slice_id = 3, 3321 .max_cap = 3072, 3322 .priority = 1, 3323 .fixed_size = true, 3324 .bonus_ways = 0xfe01ff, 3325 .cache_mode = 2, 3326 }, { 3327 .usecase_id = LLCC_ISLAND1, 3328 .slice_id = 12, 3329 .max_cap = 1792, 3330 .priority = 7, 3331 .fixed_size = true, 3332 .bonus_ways = 0xfe00, 3333 .cache_mode = 0, 3334 }, { 3335 .usecase_id = LLCC_ISLAND4, 3336 .slice_id = 15, 3337 .max_cap = 256, 3338 .priority = 7, 3339 .fixed_size = true, 3340 .bonus_ways = 0x10000, 3341 .cache_mode = 0, 3342 }, { 3343 .usecase_id = LLCC_CAMEXP2, 3344 .slice_id = 19, 3345 .max_cap = 3200, 3346 .priority = 3, 3347 .fixed_size = true, 3348 .bonus_ways = 0xfffff0, 3349 .cache_mode = 2, 3350 }, { 3351 .usecase_id = LLCC_CAMEXP3, 3352 .slice_id = 20, 3353 .max_cap = 3200, 3354 .priority = 2, 3355 .fixed_size = true, 3356 .bonus_ways = 0xfffff0, 3357 .cache_mode = 2, 3358 }, { 3359 .usecase_id = LLCC_CAMEXP4, 3360 .slice_id = 21, 3361 .max_cap = 3200, 3362 .priority = 2, 3363 .fixed_size = true, 3364 .bonus_ways = 0xfffff0, 3365 .cache_mode = 2, 3366 }, { 3367 .usecase_id = LLCC_DISP_WB, 3368 .slice_id = 23, 3369 .max_cap = 1024, 3370 .priority = 4, 3371 .fixed_size = true, 3372 .bonus_ways = 0xffffff, 3373 .cache_mode = 0, 3374 }, { 3375 .usecase_id = LLCC_DISP_1, 3376 .slice_id = 24, 3377 .max_cap = 6144, 3378 .priority = 1, 3379 .fixed_size = true, 3380 .bonus_ways = 0xffffff, 3381 .cache_mode = 2, 3382 }, { 3383 .usecase_id = LLCC_VIDVSP, 3384 .slice_id = 28, 3385 .max_cap = 256, 3386 .priority = 4, 3387 .fixed_size = true, 3388 .bonus_ways = 0xffffff, 3389 .cache_mode = 0, 3390 }, 3391 }; 3392 3393 static const struct llcc_slice_config sm8650_data[] = { 3394 { 3395 .usecase_id = LLCC_CPUSS, 3396 .slice_id = 1, 3397 .max_cap = 5120, 3398 .priority = 1, 3399 .bonus_ways = 0xffffff, 3400 .cache_mode = 0, 3401 .activate_on_init = true, 3402 .stale_en = true, 3403 }, { 3404 .usecase_id = LLCC_VIDSC0, 3405 .slice_id = 2, 3406 .max_cap = 512, 3407 .priority = 3, 3408 .fixed_size = true, 3409 .bonus_ways = 0xffffff, 3410 .cache_mode = 0, 3411 }, { 3412 .usecase_id = LLCC_AUDIO, 3413 .slice_id = 6, 3414 .max_cap = 512, 3415 .priority = 1, 3416 .fixed_size = true, 3417 .bonus_ways = 0xffffff, 3418 .cache_mode = 0, 3419 }, { 3420 .usecase_id = LLCC_MDMHPGRW, 3421 .slice_id = 25, 3422 .max_cap = 1024, 3423 .priority = 3, 3424 .bonus_ways = 0xffffff, 3425 .cache_mode = 0, 3426 }, { 3427 .usecase_id = LLCC_MODHW, 3428 .slice_id = 26, 3429 .max_cap = 1024, 3430 .priority = 1, 3431 .fixed_size = true, 3432 .bonus_ways = 0xffffff, 3433 .cache_mode = 0, 3434 }, { 3435 .usecase_id = LLCC_CMPT, 3436 .slice_id = 10, 3437 .max_cap = 4096, 3438 .priority = 1, 3439 .fixed_size = true, 3440 .bonus_ways = 0xffffff, 3441 .cache_mode = 0, 3442 }, { 3443 .usecase_id = LLCC_GPUHTW, 3444 .slice_id = 11, 3445 .max_cap = 512, 3446 .priority = 1, 3447 .fixed_size = true, 3448 .bonus_ways = 0xffffff, 3449 .cache_mode = 0, 3450 }, { 3451 .usecase_id = LLCC_GPU, 3452 .slice_id = 9, 3453 .max_cap = 3096, 3454 .priority = 1, 3455 .bonus_ways = 0xffffff, 3456 .cache_mode = 0, 3457 .write_scid_en = true, 3458 .write_scid_cacheable_en = true, 3459 }, { 3460 .usecase_id = LLCC_MMUHWT, 3461 .slice_id = 18, 3462 .max_cap = 768, 3463 .priority = 1, 3464 .fixed_size = true, 3465 .bonus_ways = 0xffffff, 3466 .cache_mode = 0, 3467 .activate_on_init = true, 3468 }, { 3469 .usecase_id = LLCC_DISP, 3470 .slice_id = 16, 3471 .max_cap = 6144, 3472 .priority = 1, 3473 .fixed_size = true, 3474 .bonus_ways = 0xffffff, 3475 .cache_mode = 2, 3476 }, { 3477 .usecase_id = LLCC_MDMHPFX, 3478 .slice_id = 24, 3479 .max_cap = 1024, 3480 .priority = 3, 3481 .fixed_size = true, 3482 .bonus_ways = 0xffffff, 3483 .cache_mode = 0, 3484 }, { 3485 .usecase_id = LLCC_MDMPNG, 3486 .slice_id = 27, 3487 .max_cap = 1024, 3488 .priority = 0, 3489 .fixed_size = true, 3490 .cache_mode = 0, 3491 }, { 3492 .usecase_id = LLCC_AUDHW, 3493 .slice_id = 22, 3494 .max_cap = 1024, 3495 .priority = 1, 3496 .fixed_size = true, 3497 .bonus_ways = 0xffffff, 3498 .cache_mode = 0, 3499 }, { 3500 .usecase_id = LLCC_CVP, 3501 .slice_id = 8, 3502 .max_cap = 256, 3503 .priority = 3, 3504 .fixed_size = true, 3505 .bonus_ways = 0xffffff, 3506 .cache_mode = 0, 3507 }, { 3508 .usecase_id = LLCC_MODPE, 3509 .slice_id = 29, 3510 .max_cap = 128, 3511 .priority = 1, 3512 .fixed_size = true, 3513 .bonus_ways = 0xf00000, 3514 .cache_mode = 0, 3515 .alloc_oneway_en = true, 3516 }, { 3517 .usecase_id = LLCC_WRCACHE, 3518 .slice_id = 31, 3519 .max_cap = 512, 3520 .priority = 1, 3521 .fixed_size = true, 3522 .bonus_ways = 0xffffff, 3523 .cache_mode = 0, 3524 .activate_on_init = true, 3525 }, { 3526 .usecase_id = LLCC_CAMEXP0, 3527 .slice_id = 4, 3528 .max_cap = 256, 3529 .priority = 3, 3530 .fixed_size = true, 3531 .bonus_ways = 0xf, 3532 .cache_mode = 0, 3533 }, { 3534 .usecase_id = LLCC_CAMEXP1, 3535 .slice_id = 7, 3536 .max_cap = 3200, 3537 .priority = 3, 3538 .fixed_size = true, 3539 .bonus_ways = 0xfffff0, 3540 .cache_mode = 2, 3541 }, { 3542 .usecase_id = LLCC_CMPTHCP, 3543 .slice_id = 17, 3544 .max_cap = 256, 3545 .priority = 3, 3546 .fixed_size = true, 3547 .bonus_ways = 0xffffff, 3548 .cache_mode = 0, 3549 }, { 3550 .usecase_id = LLCC_LCPDARE, 3551 .slice_id = 30, 3552 .max_cap = 128, 3553 .priority = 3, 3554 .fixed_size = true, 3555 .bonus_ways = 0xffffff, 3556 .cache_mode = 0, 3557 .activate_on_init = true, 3558 .alloc_oneway_en = true, 3559 }, { 3560 .usecase_id = LLCC_AENPU, 3561 .slice_id = 3, 3562 .max_cap = 3072, 3563 .priority = 1, 3564 .fixed_size = true, 3565 .bonus_ways = 0xffffff, 3566 .cache_mode = 2, 3567 }, { 3568 .usecase_id = LLCC_ISLAND1, 3569 .slice_id = 12, 3570 .max_cap = 5888, 3571 .priority = 7, 3572 .fixed_size = true, 3573 .res_ways = 0x7fffff, 3574 .cache_mode = 0, 3575 }, { 3576 .usecase_id = LLCC_DISP_WB, 3577 .slice_id = 23, 3578 .max_cap = 1024, 3579 .priority = 3, 3580 .fixed_size = true, 3581 .bonus_ways = 0xffffff, 3582 .cache_mode = 0, 3583 }, { 3584 .usecase_id = LLCC_VIDVSP, 3585 .slice_id = 28, 3586 .max_cap = 256, 3587 .priority = 3, 3588 .fixed_size = true, 3589 .bonus_ways = 0xffffff, 3590 .cache_mode = 0, 3591 }, 3592 }; 3593 3594 static const struct llcc_slice_config sm8750_data[] = { 3595 { 3596 .usecase_id = LLCC_CPUSS, 3597 .slice_id = 1, 3598 .max_cap = 5120, 3599 .priority = 1, 3600 .bonus_ways = 0xffffffff, 3601 .activate_on_init = true, 3602 .write_scid_en = true, 3603 }, { 3604 .usecase_id = LLCC_MDMHPFX, 3605 .slice_id = 24, 3606 .max_cap = 1024, 3607 .priority = 5, 3608 .fixed_size = true, 3609 .bonus_ways = 0xffffffff, 3610 }, { 3611 .usecase_id = LLCC_VIDSC0, 3612 .slice_id = 2, 3613 .max_cap = 512, 3614 .priority = 4, 3615 .fixed_size = true, 3616 .bonus_ways = 0xffffffff, 3617 }, { 3618 .usecase_id = LLCC_AUDIO, 3619 .slice_id = 35, 3620 .max_cap = 512, 3621 .priority = 1, 3622 .fixed_size = true, 3623 .bonus_ways = 0xffffffff, 3624 }, { 3625 .usecase_id = LLCC_MDMHPGRW, 3626 .slice_id = 25, 3627 .max_cap = 1024, 3628 .priority = 5, 3629 .bonus_ways = 0xffffffff, 3630 }, { 3631 .usecase_id = LLCC_MODHW, 3632 .slice_id = 26, 3633 .max_cap = 1024, 3634 .priority = 1, 3635 .fixed_size = true, 3636 .bonus_ways = 0xffffffff, 3637 }, { 3638 .usecase_id = LLCC_CMPT, 3639 .slice_id = 34, 3640 .max_cap = 4096, 3641 .priority = 1, 3642 .fixed_size = true, 3643 .bonus_ways = 0xffffffff, 3644 }, { 3645 .usecase_id = LLCC_GPUHTW, 3646 .slice_id = 11, 3647 .max_cap = 512, 3648 .priority = 1, 3649 .fixed_size = true, 3650 .bonus_ways = 0xffffffff, 3651 }, { 3652 .usecase_id = LLCC_GPU, 3653 .slice_id = 9, 3654 .max_cap = 5632, 3655 .priority = 1, 3656 .fixed_size = true, 3657 .bonus_ways = 0xffffffff, 3658 .write_scid_en = true, 3659 .write_scid_cacheable_en = true 3660 }, { 3661 .usecase_id = LLCC_MMUHWT, 3662 .slice_id = 18, 3663 .max_cap = 768, 3664 .priority = 1, 3665 .fixed_size = true, 3666 .bonus_ways = 0xffffffff, 3667 .activate_on_init = true, 3668 }, { 3669 .usecase_id = LLCC_DISP, 3670 .slice_id = 16, 3671 .max_cap = 7168, 3672 .priority = 1, 3673 .fixed_size = true, 3674 .bonus_ways = 0xffffffff, 3675 .cache_mode = 2, 3676 .stale_en = true, 3677 }, { 3678 .usecase_id = LLCC_VIDFW, 3679 .slice_id = 17, 3680 .priority = 4, 3681 .fixed_size = true, 3682 .bonus_ways = 0xffffffff, 3683 }, { 3684 .usecase_id = LLCC_CAMFW, 3685 .slice_id = 20, 3686 .priority = 4, 3687 .fixed_size = true, 3688 .bonus_ways = 0xffffffff, 3689 }, { 3690 .usecase_id = LLCC_MDMPNG, 3691 .slice_id = 27, 3692 .max_cap = 256, 3693 .priority = 5, 3694 .fixed_size = true, 3695 .bonus_ways = 0xf0000000, 3696 }, { 3697 .usecase_id = LLCC_AUDHW, 3698 .slice_id = 22, 3699 .max_cap = 512, 3700 .priority = 1, 3701 .fixed_size = true, 3702 .bonus_ways = 0xffffffff, 3703 }, { 3704 .usecase_id = LLCC_CVP, 3705 .slice_id = 8, 3706 .max_cap = 800, 3707 .priority = 5, 3708 .fixed_size = true, 3709 .bonus_ways = 0xffffffff, 3710 .vict_prio = true, 3711 }, { 3712 .usecase_id = LLCC_MODPE, 3713 .slice_id = 29, 3714 .max_cap = 256, 3715 .priority = 1, 3716 .fixed_size = true, 3717 .bonus_ways = 0xf0000000, 3718 .alloc_oneway_en = true, 3719 }, { 3720 .usecase_id = LLCC_WRCACHE, 3721 .slice_id = 31, 3722 .max_cap = 512, 3723 .priority = 1, 3724 .fixed_size = true, 3725 .bonus_ways = 0xffffffff, 3726 .activate_on_init = true, 3727 }, { 3728 .usecase_id = LLCC_CVPFW, 3729 .slice_id = 19, 3730 .max_cap = 64, 3731 .priority = 4, 3732 .fixed_size = true, 3733 .bonus_ways = 0xffffffff, 3734 }, { 3735 .usecase_id = LLCC_CMPTHCP, 3736 .slice_id = 15, 3737 .max_cap = 256, 3738 .priority = 4, 3739 .fixed_size = true, 3740 .bonus_ways = 0xffffffff, 3741 }, { 3742 .usecase_id = LLCC_LCPDARE, 3743 .slice_id = 30, 3744 .max_cap = 128, 3745 .priority = 5, 3746 .fixed_size = true, 3747 .bonus_ways = 0xffffffff, 3748 .activate_on_init = true, 3749 .alloc_oneway_en = true, 3750 }, { 3751 .usecase_id = LLCC_AENPU, 3752 .slice_id = 3, 3753 .max_cap = 3072, 3754 .priority = 1, 3755 .fixed_size = true, 3756 .bonus_ways = 0xffffffff, 3757 .cache_mode = 2, 3758 }, { 3759 .usecase_id = LLCC_ISLAND1, 3760 .slice_id = 12, 3761 .max_cap = 7936, 3762 .priority = 7, 3763 .fixed_size = true, 3764 .bonus_ways = 0x7fffffff, 3765 }, { 3766 .usecase_id = LLCC_DISP_WB, 3767 .slice_id = 23, 3768 .max_cap = 512, 3769 .priority = 4, 3770 .fixed_size = true, 3771 .bonus_ways = 0xffffffff, 3772 }, { 3773 .usecase_id = LLCC_VIDVSP, 3774 .slice_id = 4, 3775 .max_cap = 256, 3776 .priority = 4, 3777 .fixed_size = true, 3778 .bonus_ways = 0xffffffff, 3779 }, { 3780 .usecase_id = LLCC_VIDDEC, 3781 .slice_id = 5, 3782 .max_cap = 6144, 3783 .priority = 4, 3784 .fixed_size = true, 3785 .bonus_ways = 0xffffffff, 3786 .cache_mode = 2, 3787 .ovcap_prio = true, 3788 .parent_slice_id = 33, 3789 }, { 3790 .usecase_id = LLCC_CAMOFE, 3791 .slice_id = 33, 3792 .max_cap = 6144, 3793 .priority = 4, 3794 .fixed_size = true, 3795 .bonus_ways = 0xffffffff, 3796 .stale_en = true, 3797 .ovcap_prio = true, 3798 .parent_slice_id = 33, 3799 }, { 3800 .usecase_id = LLCC_CAMRTIP, 3801 .slice_id = 13, 3802 .max_cap = 1024, 3803 .priority = 4, 3804 .fixed_size = true, 3805 .bonus_ways = 0xffffffff, 3806 .stale_en = true, 3807 .ovcap_prio = true, 3808 .parent_slice_id = 33, 3809 }, { 3810 .usecase_id = LLCC_CAMSRTIP, 3811 .slice_id = 14, 3812 .max_cap = 6144, 3813 .priority = 4, 3814 .fixed_size = true, 3815 .bonus_ways = 0xffffffff, 3816 .stale_en = true, 3817 .ovcap_prio = true, 3818 .parent_slice_id = 33, 3819 }, { 3820 .usecase_id = LLCC_CAMRTRF, 3821 .slice_id = 7, 3822 .max_cap = 3584, 3823 .priority = 1, 3824 .fixed_size = true, 3825 .bonus_ways = 0xffffffff, 3826 .stale_en = true, 3827 .ovcap_prio = true, 3828 .parent_slice_id = 33, 3829 }, { 3830 .usecase_id = LLCC_CAMSRTRF, 3831 .slice_id = 21, 3832 .max_cap = 6144, 3833 .priority = 1, 3834 .fixed_size = true, 3835 .bonus_ways = 0xffffffff, 3836 .stale_en = true, 3837 .ovcap_prio = true, 3838 .parent_slice_id = 33, 3839 }, { 3840 .usecase_id = LLCC_CPUSSMPAM, 3841 .slice_id = 6, 3842 .max_cap = 2048, 3843 .priority = 1, 3844 .fixed_size = true, 3845 .bonus_ways = 0xffffffff, 3846 .activate_on_init = true, 3847 .write_scid_en = true, 3848 }, 3849 }; 3850 3851 static const struct llcc_slice_config qcs615_data[] = { 3852 { 3853 .usecase_id = LLCC_CPUSS, 3854 .slice_id = 1, 3855 .max_cap = 128, 3856 .priority = 1, 3857 .bonus_ways = 0xf, 3858 .cache_mode = 0, 3859 .activate_on_init = true, 3860 .write_scid_en = true, 3861 }, { 3862 .usecase_id = LLCC_MDM, 3863 .slice_id = 8, 3864 .max_cap = 256, 3865 .priority = 0, 3866 .fixed_size = true, 3867 .bonus_ways = 0xf, 3868 .cache_mode = 0, 3869 .activate_on_init = true, 3870 }, { 3871 .usecase_id = LLCC_GPUHTW, 3872 .slice_id = 11, 3873 .max_cap = 128, 3874 .priority = 1, 3875 .fixed_size = true, 3876 .bonus_ways = 0xf, 3877 .cache_mode = 0, 3878 .activate_on_init = true, 3879 }, { 3880 .usecase_id = LLCC_GPU, 3881 .slice_id = 12, 3882 .max_cap = 128, 3883 .priority = 1, 3884 .bonus_ways = 0xf, 3885 .cache_mode = 0, 3886 .activate_on_init = true, 3887 }, 3888 }; 3889 3890 static const struct llcc_slice_config qcs8300_data[] = { 3891 { 3892 .usecase_id = LLCC_GPUHTW, 3893 .slice_id = 11, 3894 .max_cap = 128, 3895 .priority = 1, 3896 .fixed_size = true, 3897 .bonus_ways = 0xf, 3898 .cache_mode = 0, 3899 .retain_on_pc = true, 3900 }, { 3901 .usecase_id = LLCC_GPU, 3902 .slice_id = 12, 3903 .max_cap = 512, 3904 .priority = 1, 3905 .fixed_size = true, 3906 .bonus_ways = 0xf, 3907 .cache_mode = 0, 3908 .retain_on_pc = true, 3909 .write_scid_en = true, 3910 }, { 3911 .usecase_id = LLCC_MMUHWT, 3912 .slice_id = 13, 3913 .max_cap = 128, 3914 .priority = 1, 3915 .fixed_size = true, 3916 .bonus_ways = 0xf, 3917 .cache_mode = 0, 3918 .activate_on_init = true, 3919 }, { 3920 .usecase_id = LLCC_ECC, 3921 .slice_id = 26, 3922 .max_cap = 256, 3923 .priority = 3, 3924 .fixed_size = true, 3925 .bonus_ways = 0xf, 3926 .cache_mode = 0, 3927 .activate_on_init = true, 3928 }, { 3929 .usecase_id = LLCC_WRCACHE, 3930 .slice_id = 31, 3931 .max_cap = 128, 3932 .priority = 1, 3933 .fixed_size = true, 3934 .bonus_ways = 0xf, 3935 .cache_mode = 0, 3936 .activate_on_init = true, 3937 }, 3938 }; 3939 3940 static const struct llcc_slice_config qdu1000_data_2ch[] = { 3941 { 3942 .usecase_id = LLCC_MDMHPGRW, 3943 .slice_id = 7, 3944 .max_cap = 512, 3945 .priority = 1, 3946 .fixed_size = true, 3947 .bonus_ways = 0xfff, 3948 .cache_mode = 0, 3949 .retain_on_pc = true, 3950 }, { 3951 .usecase_id = LLCC_MODHW, 3952 .slice_id = 9, 3953 .max_cap = 256, 3954 .priority = 1, 3955 .fixed_size = true, 3956 .bonus_ways = 0xfff, 3957 .cache_mode = 0, 3958 .retain_on_pc = true, 3959 }, { 3960 .usecase_id = LLCC_MDMPNG, 3961 .slice_id = 21, 3962 .max_cap = 256, 3963 .priority = 0, 3964 .fixed_size = true, 3965 .bonus_ways = 0x3, 3966 .cache_mode = 0, 3967 .retain_on_pc = true, 3968 }, { 3969 .usecase_id = LLCC_ECC, 3970 .slice_id = 26, 3971 .max_cap = 512, 3972 .priority = 3, 3973 .fixed_size = true, 3974 .bonus_ways = 0xffc, 3975 .cache_mode = 0, 3976 .activate_on_init = true, 3977 }, { 3978 .usecase_id = LLCC_MODPE, 3979 .slice_id = 29, 3980 .max_cap = 256, 3981 .priority = 1, 3982 .fixed_size = true, 3983 .bonus_ways = 0xfff, 3984 .cache_mode = 0, 3985 .retain_on_pc = true, 3986 }, { 3987 .usecase_id = LLCC_APTCM, 3988 .slice_id = 30, 3989 .max_cap = 256, 3990 .priority = 3, 3991 .fixed_size = true, 3992 .res_ways = 0xc, 3993 .cache_mode = 1, 3994 .retain_on_pc = true, 3995 }, { 3996 .usecase_id = LLCC_WRCACHE, 3997 .slice_id = 31, 3998 .max_cap = 128, 3999 .priority = 1, 4000 .fixed_size = true, 4001 .bonus_ways = 0x3, 4002 .cache_mode = 0, 4003 .activate_on_init = true, 4004 }, 4005 }; 4006 4007 static const struct llcc_slice_config qdu1000_data_4ch[] = { 4008 { 4009 .usecase_id = LLCC_MDMHPGRW, 4010 .slice_id = 7, 4011 .max_cap = 1024, 4012 .priority = 1, 4013 .fixed_size = true, 4014 .bonus_ways = 0xfff, 4015 .cache_mode = 0, 4016 .retain_on_pc = true, 4017 }, { 4018 .usecase_id = LLCC_MODHW, 4019 .slice_id = 9, 4020 .max_cap = 512, 4021 .priority = 1, 4022 .fixed_size = true, 4023 .bonus_ways = 0xfff, 4024 .cache_mode = 0, 4025 .retain_on_pc = true, 4026 }, { 4027 .usecase_id = LLCC_MDMPNG, 4028 .slice_id = 21, 4029 .max_cap = 512, 4030 .priority = 0, 4031 .fixed_size = true, 4032 .bonus_ways = 0x3, 4033 .cache_mode = 0, 4034 .retain_on_pc = true, 4035 }, { 4036 .usecase_id = LLCC_ECC, 4037 .slice_id = 26, 4038 .max_cap = 1024, 4039 .priority = 3, 4040 .fixed_size = true, 4041 .bonus_ways = 0xffc, 4042 .cache_mode = 0, 4043 .activate_on_init = true, 4044 }, { 4045 .usecase_id = LLCC_MODPE, 4046 .slice_id = 29, 4047 .max_cap = 512, 4048 .priority = 1, 4049 .fixed_size = true, 4050 .bonus_ways = 0xfff, 4051 .cache_mode = 0, 4052 .retain_on_pc = true, 4053 }, { 4054 .usecase_id = LLCC_APTCM, 4055 .slice_id = 30, 4056 .max_cap = 512, 4057 .priority = 3, 4058 .fixed_size = true, 4059 .res_ways = 0xc, 4060 .cache_mode = 1, 4061 .retain_on_pc = true, 4062 }, { 4063 .usecase_id = LLCC_WRCACHE, 4064 .slice_id = 31, 4065 .max_cap = 256, 4066 .priority = 1, 4067 .fixed_size = true, 4068 .bonus_ways = 0x3, 4069 .cache_mode = 0, 4070 .activate_on_init = true, 4071 }, 4072 }; 4073 4074 static const struct llcc_slice_config qdu1000_data_8ch[] = { 4075 { 4076 .usecase_id = LLCC_MDMHPGRW, 4077 .slice_id = 7, 4078 .max_cap = 2048, 4079 .priority = 1, 4080 .fixed_size = true, 4081 .bonus_ways = 0xfff, 4082 .cache_mode = 0, 4083 .retain_on_pc = true, 4084 }, { 4085 .usecase_id = LLCC_MODHW, 4086 .slice_id = 9, 4087 .max_cap = 1024, 4088 .priority = 1, 4089 .fixed_size = true, 4090 .bonus_ways = 0xfff, 4091 .cache_mode = 0, 4092 .retain_on_pc = true, 4093 }, { 4094 .usecase_id = LLCC_MDMPNG, 4095 .slice_id = 21, 4096 .max_cap = 1024, 4097 .priority = 0, 4098 .fixed_size = true, 4099 .bonus_ways = 0x3, 4100 .cache_mode = 0, 4101 .retain_on_pc = true, 4102 }, { 4103 .usecase_id = LLCC_ECC, 4104 .slice_id = 26, 4105 .max_cap = 2048, 4106 .priority = 3, 4107 .fixed_size = true, 4108 .bonus_ways = 0xffc, 4109 .cache_mode = 0, 4110 .activate_on_init = true, 4111 }, { 4112 .usecase_id = LLCC_MODPE, 4113 .slice_id = 29, 4114 .max_cap = 1024, 4115 .priority = 1, 4116 .fixed_size = true, 4117 .bonus_ways = 0xfff, 4118 .cache_mode = 0, 4119 .retain_on_pc = true, 4120 }, { 4121 .usecase_id = LLCC_APTCM, 4122 .slice_id = 30, 4123 .max_cap = 1024, 4124 .priority = 3, 4125 .fixed_size = true, 4126 .res_ways = 0xc, 4127 .cache_mode = 1, 4128 .retain_on_pc = true, 4129 }, { 4130 .usecase_id = LLCC_WRCACHE, 4131 .slice_id = 31, 4132 .max_cap = 512, 4133 .priority = 1, 4134 .fixed_size = true, 4135 .bonus_ways = 0x3, 4136 .cache_mode = 0, 4137 .activate_on_init = true, 4138 }, 4139 }; 4140 4141 static const struct llcc_slice_config x1e80100_data[] = { 4142 { 4143 .usecase_id = LLCC_CPUSS, 4144 .slice_id = 1, 4145 .max_cap = 6144, 4146 .priority = 1, 4147 .fixed_size = true, 4148 .bonus_ways = 0xfff, 4149 .cache_mode = 0, 4150 .activate_on_init = true, 4151 }, { 4152 .usecase_id = LLCC_VIDSC0, 4153 .slice_id = 2, 4154 .max_cap = 512, 4155 .priority = 4, 4156 .fixed_size = true, 4157 .bonus_ways = 0xfff, 4158 .cache_mode = 0, 4159 }, { 4160 .usecase_id = LLCC_AUDIO, 4161 .slice_id = 6, 4162 .max_cap = 1024, 4163 .priority = 1, 4164 .fixed_size = true, 4165 .bonus_ways = 0xfff, 4166 .cache_mode = 0, 4167 }, { 4168 .usecase_id = LLCC_CMPT, 4169 .slice_id = 10, 4170 .max_cap = 6144, 4171 .priority = 1, 4172 .fixed_size = true, 4173 .bonus_ways = 0xfff, 4174 .cache_mode = 0, 4175 }, { 4176 .usecase_id = LLCC_GPUHTW, 4177 .slice_id = 11, 4178 .max_cap = 512, 4179 .priority = 1, 4180 .fixed_size = true, 4181 .bonus_ways = 0xfff, 4182 .cache_mode = 0, 4183 }, { 4184 .usecase_id = LLCC_GPU, 4185 .slice_id = 9, 4186 .max_cap = 4608, 4187 .priority = 1, 4188 .bonus_ways = 0xfff, 4189 .cache_mode = 0, 4190 .write_scid_en = true, 4191 .write_scid_cacheable_en = true, 4192 .stale_en = true, 4193 }, { 4194 .usecase_id = LLCC_MMUHWT, 4195 .slice_id = 18, 4196 .max_cap = 512, 4197 .priority = 1, 4198 .fixed_size = true, 4199 .bonus_ways = 0xfff, 4200 .cache_mode = 0, 4201 .activate_on_init = true, 4202 }, { 4203 .usecase_id = LLCC_AUDHW, 4204 .slice_id = 22, 4205 .max_cap = 1024, 4206 .priority = 1, 4207 .fixed_size = true, 4208 .bonus_ways = 0xfff, 4209 .cache_mode = 0, 4210 }, { 4211 .usecase_id = LLCC_CVP, 4212 .slice_id = 8, 4213 .max_cap = 512, 4214 .priority = 4, 4215 .fixed_size = true, 4216 .bonus_ways = 0xfff, 4217 .cache_mode = 0, 4218 }, { 4219 .usecase_id = LLCC_WRCACHE, 4220 .slice_id = 31, 4221 .max_cap = 1024, 4222 .priority = 1, 4223 .fixed_size = true, 4224 .bonus_ways = 0xfff, 4225 .cache_mode = 0, 4226 .activate_on_init = true, 4227 }, { 4228 .usecase_id = LLCC_CAMEXP0, 4229 .slice_id = 4, 4230 .max_cap = 256, 4231 .priority = 4, 4232 .fixed_size = true, 4233 .bonus_ways = 0x3, 4234 .cache_mode = 0, 4235 }, { 4236 .usecase_id = LLCC_CAMEXP1, 4237 .slice_id = 7, 4238 .max_cap = 3072, 4239 .priority = 3, 4240 .fixed_size = true, 4241 .bonus_ways = 0xffc, 4242 .cache_mode = 2, 4243 }, { 4244 .usecase_id = LLCC_LCPDARE, 4245 .slice_id = 30, 4246 .max_cap = 512, 4247 .priority = 3, 4248 .fixed_size = true, 4249 .bonus_ways = 0xfff, 4250 .cache_mode = 0, 4251 .activate_on_init = true, 4252 .alloc_oneway_en = true, 4253 }, { 4254 .usecase_id = LLCC_AENPU, 4255 .slice_id = 3, 4256 .max_cap = 3072, 4257 .priority = 1, 4258 .fixed_size = true, 4259 .bonus_ways = 0xfff, 4260 .cache_mode = 2, 4261 }, { 4262 .usecase_id = LLCC_ISLAND1, 4263 .slice_id = 12, 4264 .max_cap = 2048, 4265 .priority = 7, 4266 .fixed_size = true, 4267 .res_ways = 0xf, 4268 .cache_mode = 0, 4269 }, { 4270 .usecase_id = LLCC_CAMEXP2, 4271 .slice_id = 19, 4272 .max_cap = 3072, 4273 .priority = 3, 4274 .fixed_size = true, 4275 .bonus_ways = 0xffc, 4276 .cache_mode = 2, 4277 }, { 4278 .usecase_id = LLCC_CAMEXP3, 4279 .slice_id = 20, 4280 .max_cap = 3072, 4281 .priority = 2, 4282 .fixed_size = true, 4283 .bonus_ways = 0xffc, 4284 .cache_mode = 2, 4285 }, { 4286 .usecase_id = LLCC_CAMEXP4, 4287 .slice_id = 21, 4288 .max_cap = 3072, 4289 .priority = 2, 4290 .fixed_size = true, 4291 .bonus_ways = 0xffc, 4292 .cache_mode = 2, 4293 }, 4294 }; 4295 4296 static const struct llcc_edac_reg_offset llcc_v1_edac_reg_offset = { 4297 .trp_ecc_error_status0 = 0x20344, 4298 .trp_ecc_error_status1 = 0x20348, 4299 .trp_ecc_sb_err_syn0 = 0x2034c, 4300 .trp_ecc_db_err_syn0 = 0x20370, 4301 .trp_ecc_error_cntr_clear = 0x20440, 4302 .trp_interrupt_0_status = 0x20480, 4303 .trp_interrupt_0_clear = 0x20484, 4304 .trp_interrupt_0_enable = 0x20488, 4305 4306 /* LLCC Common registers */ 4307 .cmn_status0 = 0x3000c, 4308 .cmn_interrupt_0_enable = 0x3001c, 4309 .cmn_interrupt_2_enable = 0x3003c, 4310 4311 /* LLCC DRP registers */ 4312 .drp_ecc_error_cfg = 0x40000, 4313 .drp_ecc_error_cntr_clear = 0x40004, 4314 .drp_interrupt_status = 0x41000, 4315 .drp_interrupt_clear = 0x41008, 4316 .drp_interrupt_enable = 0x4100c, 4317 .drp_ecc_error_status0 = 0x42044, 4318 .drp_ecc_error_status1 = 0x42048, 4319 .drp_ecc_sb_err_syn0 = 0x4204c, 4320 .drp_ecc_db_err_syn0 = 0x42070, 4321 }; 4322 4323 static const struct llcc_edac_reg_offset llcc_v2_1_edac_reg_offset = { 4324 .trp_ecc_error_status0 = 0x20344, 4325 .trp_ecc_error_status1 = 0x20348, 4326 .trp_ecc_sb_err_syn0 = 0x2034c, 4327 .trp_ecc_db_err_syn0 = 0x20370, 4328 .trp_ecc_error_cntr_clear = 0x20440, 4329 .trp_interrupt_0_status = 0x20480, 4330 .trp_interrupt_0_clear = 0x20484, 4331 .trp_interrupt_0_enable = 0x20488, 4332 4333 /* LLCC Common registers */ 4334 .cmn_status0 = 0x3400c, 4335 .cmn_interrupt_0_enable = 0x3401c, 4336 .cmn_interrupt_2_enable = 0x3403c, 4337 4338 /* LLCC DRP registers */ 4339 .drp_ecc_error_cfg = 0x50000, 4340 .drp_ecc_error_cntr_clear = 0x50004, 4341 .drp_interrupt_status = 0x50020, 4342 .drp_interrupt_clear = 0x50028, 4343 .drp_interrupt_enable = 0x5002c, 4344 .drp_ecc_error_status0 = 0x520f4, 4345 .drp_ecc_error_status1 = 0x520f8, 4346 .drp_ecc_sb_err_syn0 = 0x520fc, 4347 .drp_ecc_db_err_syn0 = 0x52120, 4348 }; 4349 4350 static const struct llcc_edac_reg_offset llcc_v6_edac_reg_offset = { 4351 .trp_ecc_error_status0 = 0x47448, 4352 .trp_ecc_error_status1 = 0x47450, 4353 .trp_ecc_sb_err_syn0 = 0x47490, 4354 .trp_ecc_db_err_syn0 = 0x474d0, 4355 .trp_ecc_error_cntr_clear = 0x47444, 4356 .trp_interrupt_0_status = 0x47600, 4357 .trp_interrupt_0_clear = 0x47604, 4358 .trp_interrupt_0_enable = 0x47608, 4359 4360 /* LLCC Common registers */ 4361 .cmn_status0 = 0x6400c, 4362 .cmn_interrupt_0_enable = 0x6401c, 4363 .cmn_interrupt_2_enable = 0x6403c, 4364 4365 /* LLCC DRP registers */ 4366 .drp_ecc_error_cfg = 0x80000, 4367 .drp_ecc_error_cntr_clear = 0x80004, 4368 .drp_interrupt_status = 0x80020, 4369 .drp_interrupt_clear = 0x80028, 4370 .drp_interrupt_enable = 0x8002c, 4371 .drp_ecc_error_status0 = 0x820f4, 4372 .drp_ecc_error_status1 = 0x820f8, 4373 .drp_ecc_sb_err_syn0 = 0x820fc, 4374 .drp_ecc_db_err_syn0 = 0x82120, 4375 }; 4376 4377 /* LLCC register offset starting from v1.0.0 */ 4378 static const u32 llcc_v1_reg_offset[] = { 4379 [LLCC_COMMON_HW_INFO] = 0x00030000, 4380 [LLCC_COMMON_STATUS0] = 0x0003000c, 4381 }; 4382 4383 /* LLCC register offset starting from v2.0.1 */ 4384 static const u32 llcc_v2_1_reg_offset[] = { 4385 [LLCC_COMMON_HW_INFO] = 0x00034000, 4386 [LLCC_COMMON_STATUS0] = 0x0003400c, 4387 }; 4388 4389 /* LLCC register offset starting from v6.0.0 */ 4390 static const u32 llcc_v6_reg_offset[] = { 4391 [LLCC_COMMON_HW_INFO] = 0x00064000, 4392 [LLCC_COMMON_STATUS0] = 0x0006400c, 4393 [LLCC_TRP_ATTR0_CFG] = 0x00041000, 4394 [LLCC_TRP_ATTR1_CFG] = 0x00041008, 4395 [LLCC_TRP_ATTR2_CFG] = 0x00041010, 4396 [LLCC_TRP_ATTR3_CFG] = 0x00041014, 4397 [LLCC_TRP_SID_DIS_CAP_ALLOC] = 0x00042000, 4398 [LLCC_TRP_ALGO_STALE_EN] = 0x00042008, 4399 [LLCC_TRP_ALGO_STALE_CAP_EN] = 0x00042010, 4400 [LLCC_TRP_ALGO_MRU0] = 0x00042018, 4401 [LLCC_TRP_ALGO_MRU1] = 0x00042020, 4402 [LLCC_TRP_ALGO_ALLOC0] = 0x00042028, 4403 [LLCC_TRP_ALGO_ALLOC1] = 0x00042030, 4404 [LLCC_TRP_ALGO_ALLOC2] = 0x00042038, 4405 [LLCC_TRP_ALGO_ALLOC3] = 0x00042040, 4406 [LLCC_TRP_WRS_EN] = 0x00042080, 4407 [LLCC_TRP_WRS_CACHEABLE_EN] = 0x00042088, 4408 }; 4409 4410 static const struct qcom_llcc_config hawi_sct_cfg[] = { 4411 { 4412 .sct_data = NULL, 4413 .size = 0, 4414 .reg_offset = llcc_v6_reg_offset, 4415 .edac_reg_offset = &llcc_v6_edac_reg_offset, 4416 }, 4417 }; 4418 4419 static const struct qcom_llcc_config eliza_cfg[] = { 4420 { 4421 .sct_data = eliza_data, 4422 .size = ARRAY_SIZE(eliza_data), 4423 .reg_offset = llcc_v6_reg_offset, 4424 .edac_reg_offset = &llcc_v6_edac_reg_offset, 4425 }, 4426 }; 4427 4428 static const struct qcom_llcc_config kaanapali_cfg[] = { 4429 { 4430 .sct_data = kaanapali_data, 4431 .size = ARRAY_SIZE(kaanapali_data), 4432 .reg_offset = llcc_v6_reg_offset, 4433 .edac_reg_offset = &llcc_v6_edac_reg_offset, 4434 }, 4435 }; 4436 4437 static const struct qcom_llcc_config glymur_cfg[] = { 4438 { 4439 .sct_data = glymur_data, 4440 .size = ARRAY_SIZE(glymur_data), 4441 .reg_offset = llcc_v6_reg_offset, 4442 .edac_reg_offset = &llcc_v2_1_edac_reg_offset, 4443 .no_edac = true, 4444 }, 4445 }; 4446 4447 static const struct qcom_llcc_config qcs615_cfg[] = { 4448 { 4449 .sct_data = qcs615_data, 4450 .size = ARRAY_SIZE(qcs615_data), 4451 .reg_offset = llcc_v1_reg_offset, 4452 .edac_reg_offset = &llcc_v1_edac_reg_offset, 4453 }, 4454 }; 4455 4456 static const struct qcom_llcc_config qcs8300_cfg[] = { 4457 { 4458 .sct_data = qcs8300_data, 4459 .size = ARRAY_SIZE(qcs8300_data), 4460 .reg_offset = llcc_v2_1_reg_offset, 4461 .edac_reg_offset = &llcc_v2_1_edac_reg_offset, 4462 .num_banks = 4, 4463 }, 4464 }; 4465 4466 static const struct qcom_llcc_config qdu1000_cfg[] = { 4467 { 4468 .sct_data = qdu1000_data_8ch, 4469 .size = ARRAY_SIZE(qdu1000_data_8ch), 4470 .reg_offset = llcc_v2_1_reg_offset, 4471 .edac_reg_offset = &llcc_v2_1_edac_reg_offset, 4472 }, 4473 { 4474 .sct_data = qdu1000_data_4ch, 4475 .size = ARRAY_SIZE(qdu1000_data_4ch), 4476 .reg_offset = llcc_v2_1_reg_offset, 4477 .edac_reg_offset = &llcc_v2_1_edac_reg_offset, 4478 }, 4479 { 4480 .sct_data = qdu1000_data_4ch, 4481 .size = ARRAY_SIZE(qdu1000_data_4ch), 4482 .reg_offset = llcc_v2_1_reg_offset, 4483 .edac_reg_offset = &llcc_v2_1_edac_reg_offset, 4484 }, 4485 { 4486 .sct_data = qdu1000_data_2ch, 4487 .size = ARRAY_SIZE(qdu1000_data_2ch), 4488 .reg_offset = llcc_v2_1_reg_offset, 4489 .edac_reg_offset = &llcc_v2_1_edac_reg_offset, 4490 }, 4491 }; 4492 4493 static const struct qcom_llcc_config ipq5424_cfg[] = { 4494 { 4495 .sct_data = ipq5424_data, 4496 .size = ARRAY_SIZE(ipq5424_data), 4497 .reg_offset = llcc_v2_1_reg_offset, 4498 .edac_reg_offset = &llcc_v2_1_edac_reg_offset, 4499 .no_broadcast_register = true, 4500 }, 4501 }; 4502 4503 static const struct qcom_llcc_config sa8775p_cfg[] = { 4504 { 4505 .sct_data = sa8775p_data, 4506 .size = ARRAY_SIZE(sa8775p_data), 4507 .reg_offset = llcc_v2_1_reg_offset, 4508 .edac_reg_offset = &llcc_v2_1_edac_reg_offset, 4509 }, 4510 }; 4511 4512 static const struct qcom_llcc_config sar1130p_cfg[] = { 4513 { 4514 .sct_data = sar1130p_data, 4515 .size = ARRAY_SIZE(sar1130p_data), 4516 .reg_offset = llcc_v2_1_reg_offset, 4517 .edac_reg_offset = &llcc_v2_1_edac_reg_offset, 4518 .max_cap_shift = 14, 4519 .num_banks = 2, 4520 }, 4521 }; 4522 4523 static const struct qcom_llcc_config sar2130p_cfg[] = { 4524 { 4525 .sct_data = sar2130p_data, 4526 .size = ARRAY_SIZE(sar2130p_data), 4527 .reg_offset = llcc_v2_1_reg_offset, 4528 .edac_reg_offset = &llcc_v2_1_edac_reg_offset, 4529 .max_cap_shift = 14, 4530 .num_banks = 2, 4531 }, 4532 }; 4533 4534 static const struct qcom_llcc_config sc7180_cfg[] = { 4535 { 4536 .sct_data = sc7180_data, 4537 .size = ARRAY_SIZE(sc7180_data), 4538 .reg_offset = llcc_v1_reg_offset, 4539 .edac_reg_offset = &llcc_v1_edac_reg_offset, 4540 }, 4541 }; 4542 4543 static const struct qcom_llcc_config sc7280_cfg[] = { 4544 { 4545 .sct_data = sc7280_data, 4546 .size = ARRAY_SIZE(sc7280_data), 4547 .reg_offset = llcc_v1_reg_offset, 4548 .edac_reg_offset = &llcc_v1_edac_reg_offset, 4549 }, 4550 }; 4551 4552 static const struct qcom_llcc_config sc8180x_cfg[] = { 4553 { 4554 .sct_data = sc8180x_data, 4555 .size = ARRAY_SIZE(sc8180x_data), 4556 .reg_offset = llcc_v1_reg_offset, 4557 .edac_reg_offset = &llcc_v1_edac_reg_offset, 4558 }, 4559 }; 4560 4561 static const struct qcom_llcc_config sc8280xp_cfg[] = { 4562 { 4563 .sct_data = sc8280xp_data, 4564 .size = ARRAY_SIZE(sc8280xp_data), 4565 .reg_offset = llcc_v1_reg_offset, 4566 .edac_reg_offset = &llcc_v1_edac_reg_offset, 4567 }, 4568 }; 4569 4570 static const struct qcom_llcc_config sdm670_cfg[] = { 4571 { 4572 .sct_data = sdm670_data, 4573 .size = ARRAY_SIZE(sdm670_data), 4574 .skip_llcc_cfg = true, 4575 .reg_offset = llcc_v1_reg_offset, 4576 .edac_reg_offset = &llcc_v1_edac_reg_offset, 4577 .no_edac = true, 4578 }, 4579 }; 4580 4581 static const struct qcom_llcc_config sdm845_cfg[] = { 4582 { 4583 .sct_data = sdm845_data, 4584 .size = ARRAY_SIZE(sdm845_data), 4585 .skip_llcc_cfg = true, 4586 .reg_offset = llcc_v1_reg_offset, 4587 .edac_reg_offset = &llcc_v1_edac_reg_offset, 4588 .no_edac = true, 4589 }, 4590 }; 4591 4592 static const struct qcom_llcc_config shikra_cfg[] = { 4593 { 4594 .sct_data = shikra_data, 4595 .size = ARRAY_SIZE(shikra_data), 4596 .reg_offset = llcc_v2_1_reg_offset, 4597 .edac_reg_offset = &llcc_v2_1_edac_reg_offset, 4598 .irq_configured = true, 4599 }, 4600 }; 4601 4602 static const struct qcom_llcc_config sm6350_cfg[] = { 4603 { 4604 .sct_data = sm6350_data, 4605 .size = ARRAY_SIZE(sm6350_data), 4606 .reg_offset = llcc_v1_reg_offset, 4607 .edac_reg_offset = &llcc_v1_edac_reg_offset, 4608 }, 4609 }; 4610 4611 static const struct qcom_llcc_config sm7150_cfg[] = { 4612 { 4613 .sct_data = sm7150_data, 4614 .size = ARRAY_SIZE(sm7150_data), 4615 .reg_offset = llcc_v1_reg_offset, 4616 .edac_reg_offset = &llcc_v1_edac_reg_offset, 4617 }, 4618 }; 4619 4620 static const struct qcom_llcc_config sm8150_cfg[] = { 4621 { 4622 .sct_data = sm8150_data, 4623 .size = ARRAY_SIZE(sm8150_data), 4624 .reg_offset = llcc_v1_reg_offset, 4625 .edac_reg_offset = &llcc_v1_edac_reg_offset, 4626 }, 4627 }; 4628 4629 static const struct qcom_llcc_config sm8250_cfg[] = { 4630 { 4631 .sct_data = sm8250_data, 4632 .size = ARRAY_SIZE(sm8250_data), 4633 .reg_offset = llcc_v1_reg_offset, 4634 .edac_reg_offset = &llcc_v1_edac_reg_offset, 4635 }, 4636 }; 4637 4638 static const struct qcom_llcc_config sm8350_cfg[] = { 4639 { 4640 .sct_data = sm8350_data, 4641 .size = ARRAY_SIZE(sm8350_data), 4642 .reg_offset = llcc_v1_reg_offset, 4643 .edac_reg_offset = &llcc_v1_edac_reg_offset, 4644 }, 4645 }; 4646 4647 static const struct qcom_llcc_config sm8450_cfg[] = { 4648 { 4649 .sct_data = sm8450_data, 4650 .size = ARRAY_SIZE(sm8450_data), 4651 .reg_offset = llcc_v2_1_reg_offset, 4652 .edac_reg_offset = &llcc_v2_1_edac_reg_offset, 4653 }, 4654 }; 4655 4656 static const struct qcom_llcc_config sm8550_cfg[] = { 4657 { 4658 .sct_data = sm8550_data, 4659 .size = ARRAY_SIZE(sm8550_data), 4660 .reg_offset = llcc_v2_1_reg_offset, 4661 .edac_reg_offset = &llcc_v2_1_edac_reg_offset, 4662 }, 4663 }; 4664 4665 static const struct qcom_llcc_config sm8650_cfg[] = { 4666 { 4667 .sct_data = sm8650_data, 4668 .size = ARRAY_SIZE(sm8650_data), 4669 .reg_offset = llcc_v2_1_reg_offset, 4670 .edac_reg_offset = &llcc_v2_1_edac_reg_offset, 4671 }, 4672 }; 4673 4674 static const struct qcom_llcc_config sm8750_cfg[] = { 4675 { 4676 .sct_data = sm8750_data, 4677 .size = ARRAY_SIZE(sm8750_data), 4678 .skip_llcc_cfg = false, 4679 .reg_offset = llcc_v6_reg_offset, 4680 .edac_reg_offset = &llcc_v6_edac_reg_offset, 4681 }, 4682 }; 4683 4684 static const struct qcom_llcc_config x1e80100_cfg[] = { 4685 { 4686 .sct_data = x1e80100_data, 4687 .size = ARRAY_SIZE(x1e80100_data), 4688 .reg_offset = llcc_v2_1_reg_offset, 4689 .edac_reg_offset = &llcc_v2_1_edac_reg_offset, 4690 .irq_configured = true, 4691 }, 4692 }; 4693 4694 static const struct qcom_sct_config hawi_sct_cfgs = { 4695 .llcc_config = hawi_sct_cfg, 4696 .num_config = ARRAY_SIZE(hawi_sct_cfg), 4697 }; 4698 4699 static const struct qcom_sct_config eliza_cfgs = { 4700 .llcc_config = eliza_cfg, 4701 .num_config = ARRAY_SIZE(eliza_cfg), 4702 }; 4703 4704 static const struct qcom_sct_config kaanapali_cfgs = { 4705 .llcc_config = kaanapali_cfg, 4706 .num_config = ARRAY_SIZE(kaanapali_cfg), 4707 }; 4708 4709 static const struct qcom_sct_config glymur_cfgs = { 4710 .llcc_config = glymur_cfg, 4711 .num_config = ARRAY_SIZE(glymur_cfg), 4712 }; 4713 4714 static const struct qcom_sct_config qcs615_cfgs = { 4715 .llcc_config = qcs615_cfg, 4716 .num_config = ARRAY_SIZE(qcs615_cfg), 4717 }; 4718 4719 static const struct qcom_sct_config qcs8300_cfgs = { 4720 .llcc_config = qcs8300_cfg, 4721 .num_config = ARRAY_SIZE(qcs8300_cfg), 4722 }; 4723 4724 static const struct qcom_sct_config qdu1000_cfgs = { 4725 .llcc_config = qdu1000_cfg, 4726 .num_config = ARRAY_SIZE(qdu1000_cfg), 4727 }; 4728 4729 static const struct qcom_sct_config ipq5424_cfgs = { 4730 .llcc_config = ipq5424_cfg, 4731 .num_config = ARRAY_SIZE(ipq5424_cfg), 4732 }; 4733 4734 static const struct qcom_sct_config sa8775p_cfgs = { 4735 .llcc_config = sa8775p_cfg, 4736 .num_config = ARRAY_SIZE(sa8775p_cfg), 4737 }; 4738 4739 static const struct qcom_sct_config sar1130p_cfgs = { 4740 .llcc_config = sar1130p_cfg, 4741 .num_config = ARRAY_SIZE(sar1130p_cfg), 4742 }; 4743 4744 static const struct qcom_sct_config sar2130p_cfgs = { 4745 .llcc_config = sar2130p_cfg, 4746 .num_config = ARRAY_SIZE(sar2130p_cfg), 4747 }; 4748 4749 static const struct qcom_sct_config sc7180_cfgs = { 4750 .llcc_config = sc7180_cfg, 4751 .num_config = ARRAY_SIZE(sc7180_cfg), 4752 }; 4753 4754 static const struct qcom_sct_config sc7280_cfgs = { 4755 .llcc_config = sc7280_cfg, 4756 .num_config = ARRAY_SIZE(sc7280_cfg), 4757 }; 4758 4759 static const struct qcom_sct_config sc8180x_cfgs = { 4760 .llcc_config = sc8180x_cfg, 4761 .num_config = ARRAY_SIZE(sc8180x_cfg), 4762 }; 4763 4764 static const struct qcom_sct_config sc8280xp_cfgs = { 4765 .llcc_config = sc8280xp_cfg, 4766 .num_config = ARRAY_SIZE(sc8280xp_cfg), 4767 }; 4768 4769 static const struct qcom_sct_config sdm670_cfgs = { 4770 .llcc_config = sdm670_cfg, 4771 .num_config = ARRAY_SIZE(sdm670_cfg), 4772 }; 4773 4774 static const struct qcom_sct_config sdm845_cfgs = { 4775 .llcc_config = sdm845_cfg, 4776 .num_config = ARRAY_SIZE(sdm845_cfg), 4777 }; 4778 4779 static const struct qcom_sct_config shikra_cfgs = { 4780 .llcc_config = shikra_cfg, 4781 .num_config = ARRAY_SIZE(shikra_cfg), 4782 }; 4783 4784 static const struct qcom_sct_config sm6350_cfgs = { 4785 .llcc_config = sm6350_cfg, 4786 .num_config = ARRAY_SIZE(sm6350_cfg), 4787 }; 4788 4789 static const struct qcom_sct_config sm7150_cfgs = { 4790 .llcc_config = sm7150_cfg, 4791 .num_config = ARRAY_SIZE(sm7150_cfg), 4792 }; 4793 4794 static const struct qcom_sct_config sm8150_cfgs = { 4795 .llcc_config = sm8150_cfg, 4796 .num_config = ARRAY_SIZE(sm8150_cfg), 4797 }; 4798 4799 static const struct qcom_sct_config sm8250_cfgs = { 4800 .llcc_config = sm8250_cfg, 4801 .num_config = ARRAY_SIZE(sm8250_cfg), 4802 }; 4803 4804 static const struct qcom_sct_config sm8350_cfgs = { 4805 .llcc_config = sm8350_cfg, 4806 .num_config = ARRAY_SIZE(sm8350_cfg), 4807 }; 4808 4809 static const struct qcom_sct_config sm8450_cfgs = { 4810 .llcc_config = sm8450_cfg, 4811 .num_config = ARRAY_SIZE(sm8450_cfg), 4812 }; 4813 4814 static const struct qcom_sct_config sm8550_cfgs = { 4815 .llcc_config = sm8550_cfg, 4816 .num_config = ARRAY_SIZE(sm8550_cfg), 4817 }; 4818 4819 static const struct qcom_sct_config sm8650_cfgs = { 4820 .llcc_config = sm8650_cfg, 4821 .num_config = ARRAY_SIZE(sm8650_cfg), 4822 }; 4823 4824 static const struct qcom_sct_config sm8750_cfgs = { 4825 .llcc_config = sm8750_cfg, 4826 .num_config = ARRAY_SIZE(sm8750_cfg), 4827 }; 4828 4829 static const struct qcom_sct_config x1e80100_cfgs = { 4830 .llcc_config = x1e80100_cfg, 4831 .num_config = ARRAY_SIZE(x1e80100_cfg), 4832 }; 4833 4834 static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER; 4835 4836 /** 4837 * llcc_slice_getd - get LLCC slice descriptor 4838 * @uid: usecase_id for the client 4839 * 4840 * A pointer to LLCC slice descriptor will be returned on success 4841 * and error pointer is returned on failure 4842 */ 4843 struct llcc_slice_desc *llcc_slice_getd(u32 uid) 4844 { 4845 if (IS_ERR(drv_data)) 4846 return ERR_CAST(drv_data); 4847 4848 if (IS_ERR_OR_NULL(drv_data->desc)) 4849 return ERR_PTR(-ENODEV); 4850 4851 for (u32 i = 0; i < drv_data->cfg_size; i++) { 4852 if (uid == drv_data->desc[i].uid) 4853 return &drv_data->desc[i]; 4854 } 4855 4856 dev_err(drv_data->dev, "Failed to get slice desc for uid: %u\n", uid); 4857 4858 return ERR_PTR(-EINVAL); 4859 } 4860 EXPORT_SYMBOL_GPL(llcc_slice_getd); 4861 4862 /** 4863 * llcc_slice_putd - LLCC slice descriptor 4864 * @desc: Pointer to LLCC slice descriptor 4865 */ 4866 void llcc_slice_putd(struct llcc_slice_desc *desc) 4867 { 4868 if (!IS_ERR_OR_NULL(desc)) 4869 return; 4870 } 4871 EXPORT_SYMBOL_GPL(llcc_slice_putd); 4872 4873 static int llcc_update_act_ctrl(u32 sid, 4874 u32 act_ctrl_reg_val, u32 status) 4875 { 4876 struct regmap *regmap; 4877 u32 act_ctrl_reg; 4878 u32 act_clear_reg; 4879 u32 status_reg; 4880 u32 slice_status; 4881 int ret; 4882 4883 if (IS_ERR(drv_data)) 4884 return PTR_ERR(drv_data); 4885 4886 act_ctrl_reg = LLCC_TRP_ACT_CTRLn(sid); 4887 act_clear_reg = LLCC_TRP_ACT_CLEARn(sid); 4888 status_reg = LLCC_TRP_STATUSn(sid); 4889 4890 /* Set the ACTIVE trigger */ 4891 act_ctrl_reg_val |= ACT_CTRL_ACT_TRIG; 4892 ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg, 4893 act_ctrl_reg_val); 4894 if (ret) 4895 return ret; 4896 4897 /* Clear the ACTIVE trigger */ 4898 act_ctrl_reg_val &= ~ACT_CTRL_ACT_TRIG; 4899 ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg, 4900 act_ctrl_reg_val); 4901 if (ret) 4902 return ret; 4903 4904 if (drv_data->version >= LLCC_VERSION_4_1_0_0) { 4905 regmap = drv_data->bcast_and_regmap ?: drv_data->bcast_regmap; 4906 ret = regmap_read_poll_timeout(regmap, status_reg, 4907 slice_status, (slice_status & ACT_COMPLETE), 4908 0, LLCC_STATUS_READ_DELAY); 4909 if (ret) 4910 return ret; 4911 } 4912 4913 ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg, 4914 slice_status, !(slice_status & status), 4915 0, LLCC_STATUS_READ_DELAY); 4916 if (ret) 4917 return ret; 4918 4919 if (drv_data->version >= LLCC_VERSION_4_1_0_0) 4920 ret = regmap_write(drv_data->bcast_regmap, act_clear_reg, 4921 ACT_CLEAR); 4922 4923 return ret; 4924 } 4925 4926 /** 4927 * llcc_slice_activate - Activate the LLCC slice 4928 * @desc: Pointer to LLCC slice descriptor 4929 * 4930 * A value of zero will be returned on success and a negative errno will 4931 * be returned in error cases 4932 */ 4933 int llcc_slice_activate(struct llcc_slice_desc *desc) 4934 { 4935 int ret; 4936 u32 act_ctrl_val; 4937 4938 if (IS_ERR(drv_data)) 4939 return PTR_ERR(drv_data); 4940 4941 if (IS_ERR_OR_NULL(desc)) 4942 return -EINVAL; 4943 4944 guard(mutex)(&drv_data->lock); 4945 /* Already active; try to take another reference. */ 4946 if (refcount_inc_not_zero(&desc->refcount)) 4947 return 0; 4948 4949 act_ctrl_val = ACT_CTRL_OPCODE_ACTIVATE << ACT_CTRL_OPCODE_SHIFT; 4950 ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val, 4951 DEACTIVATE); 4952 if (ret) 4953 return ret; 4954 4955 /* Set first reference */ 4956 refcount_set(&desc->refcount, 1); 4957 4958 return 0; 4959 } 4960 EXPORT_SYMBOL_GPL(llcc_slice_activate); 4961 4962 /** 4963 * llcc_slice_deactivate - Deactivate the LLCC slice 4964 * @desc: Pointer to LLCC slice descriptor 4965 * 4966 * A value of zero will be returned on success and a negative errno will 4967 * be returned in error cases 4968 */ 4969 int llcc_slice_deactivate(struct llcc_slice_desc *desc) 4970 { 4971 u32 act_ctrl_val; 4972 int ret; 4973 4974 if (IS_ERR(drv_data)) 4975 return PTR_ERR(drv_data); 4976 4977 if (IS_ERR_OR_NULL(desc)) 4978 return -EINVAL; 4979 4980 guard(mutex)(&drv_data->lock); 4981 /* refcount > 1, drop one ref and we’re done. */ 4982 if (refcount_dec_not_one(&desc->refcount)) 4983 return 0; 4984 4985 act_ctrl_val = ACT_CTRL_OPCODE_DEACTIVATE << ACT_CTRL_OPCODE_SHIFT; 4986 ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val, 4987 ACTIVATE); 4988 if (ret) 4989 return ret; 4990 4991 /* Finalize: atomically transition 1 -> 0 */ 4992 WARN_ON_ONCE(!refcount_dec_if_one(&desc->refcount)); 4993 4994 return 0; 4995 } 4996 EXPORT_SYMBOL_GPL(llcc_slice_deactivate); 4997 4998 /** 4999 * llcc_get_slice_id - return the slice id 5000 * @desc: Pointer to LLCC slice descriptor 5001 */ 5002 int llcc_get_slice_id(struct llcc_slice_desc *desc) 5003 { 5004 if (IS_ERR_OR_NULL(desc)) 5005 return -EINVAL; 5006 5007 return desc->slice_id; 5008 } 5009 EXPORT_SYMBOL_GPL(llcc_get_slice_id); 5010 5011 /** 5012 * llcc_get_slice_size - return the slice id 5013 * @desc: Pointer to LLCC slice descriptor 5014 */ 5015 size_t llcc_get_slice_size(struct llcc_slice_desc *desc) 5016 { 5017 if (IS_ERR_OR_NULL(desc)) 5018 return 0; 5019 5020 return desc->slice_size; 5021 } 5022 EXPORT_SYMBOL_GPL(llcc_get_slice_size); 5023 5024 static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config, 5025 const struct qcom_llcc_config *cfg) 5026 { 5027 int ret; 5028 u32 attr2_cfg; 5029 u32 attr1_cfg; 5030 u32 attr0_cfg; 5031 u32 attr2_val; 5032 u32 attr1_val; 5033 u32 attr0_val; 5034 u32 max_cap_cacheline; 5035 struct llcc_slice_desc *desc; 5036 5037 attr1_val = config->cache_mode; 5038 attr1_val |= config->probe_target_ways << ATTR1_PROBE_TARGET_WAYS_SHIFT; 5039 attr1_val |= config->fixed_size << ATTR1_FIXED_SIZE_SHIFT; 5040 attr1_val |= config->priority << ATTR1_PRIORITY_SHIFT; 5041 5042 max_cap_cacheline = MAX_CAP_TO_BYTES(config->max_cap); 5043 5044 /* 5045 * LLCC instances can vary for each target. 5046 * The SW writes to broadcast register which gets propagated 5047 * to each LLCC instance (llcc0,.. llccN). 5048 * Since the size of the memory is divided equally amongst the 5049 * LLCC instances, we need to configure the max cap accordingly. 5050 */ 5051 max_cap_cacheline = max_cap_cacheline / drv_data->num_banks; 5052 max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT; 5053 if (cfg->max_cap_shift) 5054 attr1_val |= max_cap_cacheline << cfg->max_cap_shift; 5055 else 5056 attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT; 5057 5058 attr1_cfg = LLCC_TRP_ATTR1_CFGn(config->slice_id); 5059 5060 ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, attr1_val); 5061 if (ret) 5062 return ret; 5063 5064 if (drv_data->version >= LLCC_VERSION_4_1_0_0) { 5065 attr2_cfg = LLCC_TRP_ATTR2_CFGn(config->slice_id); 5066 attr0_val = config->res_ways; 5067 attr2_val = config->bonus_ways; 5068 } else { 5069 attr0_val = config->res_ways & ATTR0_RES_WAYS_MASK; 5070 attr0_val |= config->bonus_ways << ATTR0_BONUS_WAYS_SHIFT; 5071 } 5072 5073 attr0_cfg = LLCC_TRP_ATTR0_CFGn(config->slice_id); 5074 5075 ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, attr0_val); 5076 if (ret) 5077 return ret; 5078 5079 if (drv_data->version >= LLCC_VERSION_4_1_0_0) { 5080 ret = regmap_write(drv_data->bcast_regmap, attr2_cfg, attr2_val); 5081 if (ret) 5082 return ret; 5083 } 5084 5085 /* At least SDM845 disallows non-secure writes to these registers */ 5086 if (!cfg->skip_llcc_cfg) { 5087 u32 disable_cap_alloc, retain_pc; 5088 5089 disable_cap_alloc = config->dis_cap_alloc << config->slice_id; 5090 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_SCID_DIS_CAP_ALLOC, 5091 BIT(config->slice_id), disable_cap_alloc); 5092 if (ret) 5093 return ret; 5094 5095 if (drv_data->version < LLCC_VERSION_4_1_0_0) { 5096 retain_pc = config->retain_on_pc << config->slice_id; 5097 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_PCB_ACT, 5098 BIT(config->slice_id), retain_pc); 5099 if (ret) 5100 return ret; 5101 } 5102 } 5103 5104 if (drv_data->version >= LLCC_VERSION_2_0_0_0) { 5105 u32 wren; 5106 5107 wren = config->write_scid_en << config->slice_id; 5108 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_EN, 5109 BIT(config->slice_id), wren); 5110 if (ret) 5111 return ret; 5112 } 5113 5114 if (drv_data->version >= LLCC_VERSION_2_1_0_0) { 5115 u32 wr_cache_en; 5116 5117 wr_cache_en = config->write_scid_cacheable_en << config->slice_id; 5118 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_CACHEABLE_EN, 5119 BIT(config->slice_id), wr_cache_en); 5120 if (ret) 5121 return ret; 5122 } 5123 5124 if (drv_data->version >= LLCC_VERSION_4_1_0_0) { 5125 u32 stale_en; 5126 u32 stale_cap_en; 5127 u32 mru_uncap_en; 5128 u32 mru_rollover; 5129 u32 alloc_oneway_en; 5130 u32 ovcap_en; 5131 u32 ovcap_prio; 5132 u32 vict_prio; 5133 5134 stale_en = config->stale_en << config->slice_id; 5135 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG1, 5136 BIT(config->slice_id), stale_en); 5137 if (ret) 5138 return ret; 5139 5140 stale_cap_en = config->stale_cap_en << config->slice_id; 5141 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG2, 5142 BIT(config->slice_id), stale_cap_en); 5143 if (ret) 5144 return ret; 5145 5146 mru_uncap_en = config->mru_uncap_en << config->slice_id; 5147 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG3, 5148 BIT(config->slice_id), mru_uncap_en); 5149 if (ret) 5150 return ret; 5151 5152 mru_rollover = config->mru_rollover << config->slice_id; 5153 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG4, 5154 BIT(config->slice_id), mru_rollover); 5155 if (ret) 5156 return ret; 5157 5158 alloc_oneway_en = config->alloc_oneway_en << config->slice_id; 5159 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG5, 5160 BIT(config->slice_id), alloc_oneway_en); 5161 if (ret) 5162 return ret; 5163 5164 ovcap_en = config->ovcap_en << config->slice_id; 5165 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG6, 5166 BIT(config->slice_id), ovcap_en); 5167 if (ret) 5168 return ret; 5169 5170 ovcap_prio = config->ovcap_prio << config->slice_id; 5171 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG7, 5172 BIT(config->slice_id), ovcap_prio); 5173 if (ret) 5174 return ret; 5175 5176 vict_prio = config->vict_prio << config->slice_id; 5177 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG8, 5178 BIT(config->slice_id), vict_prio); 5179 if (ret) 5180 return ret; 5181 } 5182 5183 if (config->activate_on_init) { 5184 desc = llcc_slice_getd(config->usecase_id); 5185 if (IS_ERR(desc)) 5186 return PTR_ERR(desc); 5187 5188 ret = llcc_slice_activate(desc); 5189 } 5190 5191 return ret; 5192 } 5193 5194 static int _qcom_llcc_cfg_program_v6(const struct llcc_slice_config *config, 5195 const struct qcom_llcc_config *cfg) 5196 { 5197 u32 stale_en, stale_cap_en, mru_uncap_en, mru_rollover; 5198 u32 alloc_oneway_en, ovcap_en, ovcap_prio, vict_prio; 5199 u32 attr0_cfg, attr1_cfg, attr2_cfg, attr3_cfg; 5200 u32 attr0_val, attr1_val, attr2_val, attr3_val; 5201 u32 slice_offset, reg_offset; 5202 struct llcc_slice_desc *desc; 5203 u32 wren, wr_cache_en; 5204 int ret; 5205 5206 attr0_cfg = LLCC_V6_TRP_ATTR0_CFGn(config->slice_id); 5207 attr1_cfg = LLCC_V6_TRP_ATTR1_CFGn(config->slice_id); 5208 attr2_cfg = LLCC_V6_TRP_ATTR2_CFGn(config->slice_id); 5209 attr3_cfg = LLCC_V6_TRP_ATTR3_CFGn(config->slice_id); 5210 5211 attr0_val = config->res_ways; 5212 attr1_val = config->bonus_ways; 5213 attr2_val = config->cache_mode; 5214 attr2_val |= FIELD_PREP(ATTR2_PROBE_TARGET_WAYS_MASK, config->probe_target_ways); 5215 attr2_val |= FIELD_PREP(ATTR2_FIXED_SIZE_MASK, config->fixed_size); 5216 attr2_val |= FIELD_PREP(ATTR2_PRIORITY_MASK, config->priority); 5217 5218 if (config->parent_slice_id && config->fixed_size) { 5219 attr2_val |= FIELD_PREP(ATTR2_PARENT_SCID_MASK, config->parent_slice_id); 5220 attr2_val |= ATTR2_IN_A_GROUP_MASK; 5221 } 5222 5223 attr3_val = MAX_CAP_TO_BYTES(config->max_cap); 5224 attr3_val /= drv_data->num_banks; 5225 attr3_val >>= CACHE_LINE_SIZE_SHIFT; 5226 5227 ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, attr0_val); 5228 if (ret) 5229 return ret; 5230 5231 ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, attr1_val); 5232 if (ret) 5233 return ret; 5234 5235 ret = regmap_write(drv_data->bcast_regmap, attr2_cfg, attr2_val); 5236 if (ret) 5237 return ret; 5238 5239 ret = regmap_write(drv_data->bcast_regmap, attr3_cfg, attr3_val); 5240 if (ret) 5241 return ret; 5242 5243 slice_offset = config->slice_id % 32; 5244 reg_offset = (config->slice_id / 32) * 4; 5245 5246 wren = config->write_scid_en << slice_offset; 5247 ret = regmap_update_bits(drv_data->bcast_regmap, 5248 cfg->reg_offset[LLCC_TRP_WRS_EN] + reg_offset, 5249 BIT(slice_offset), wren); 5250 if (ret) 5251 return ret; 5252 5253 wr_cache_en = config->write_scid_cacheable_en << slice_offset; 5254 ret = regmap_update_bits(drv_data->bcast_regmap, 5255 cfg->reg_offset[LLCC_TRP_WRS_CACHEABLE_EN] + reg_offset, 5256 BIT(slice_offset), wr_cache_en); 5257 if (ret) 5258 return ret; 5259 5260 stale_en = config->stale_en << slice_offset; 5261 ret = regmap_update_bits(drv_data->bcast_regmap, 5262 cfg->reg_offset[LLCC_TRP_ALGO_STALE_EN] + reg_offset, 5263 BIT(slice_offset), stale_en); 5264 if (ret) 5265 return ret; 5266 5267 stale_cap_en = config->stale_cap_en << slice_offset; 5268 ret = regmap_update_bits(drv_data->bcast_regmap, 5269 cfg->reg_offset[LLCC_TRP_ALGO_STALE_CAP_EN] + reg_offset, 5270 BIT(slice_offset), stale_cap_en); 5271 if (ret) 5272 return ret; 5273 5274 mru_uncap_en = config->mru_uncap_en << slice_offset; 5275 ret = regmap_update_bits(drv_data->bcast_regmap, 5276 cfg->reg_offset[LLCC_TRP_ALGO_MRU0] + reg_offset, 5277 BIT(slice_offset), mru_uncap_en); 5278 if (ret) 5279 return ret; 5280 5281 mru_rollover = config->mru_rollover << slice_offset; 5282 ret = regmap_update_bits(drv_data->bcast_regmap, 5283 cfg->reg_offset[LLCC_TRP_ALGO_MRU1] + reg_offset, 5284 BIT(slice_offset), mru_rollover); 5285 if (ret) 5286 return ret; 5287 5288 alloc_oneway_en = config->alloc_oneway_en << slice_offset; 5289 ret = regmap_update_bits(drv_data->bcast_regmap, 5290 cfg->reg_offset[LLCC_TRP_ALGO_ALLOC0] + reg_offset, 5291 BIT(slice_offset), alloc_oneway_en); 5292 if (ret) 5293 return ret; 5294 5295 ovcap_en = config->ovcap_en << slice_offset; 5296 ret = regmap_update_bits(drv_data->bcast_regmap, 5297 cfg->reg_offset[LLCC_TRP_ALGO_ALLOC1] + reg_offset, 5298 BIT(slice_offset), ovcap_en); 5299 if (ret) 5300 return ret; 5301 5302 ovcap_prio = config->ovcap_prio << slice_offset; 5303 ret = regmap_update_bits(drv_data->bcast_regmap, 5304 cfg->reg_offset[LLCC_TRP_ALGO_ALLOC2] + reg_offset, 5305 BIT(slice_offset), ovcap_prio); 5306 if (ret) 5307 return ret; 5308 5309 vict_prio = config->vict_prio << slice_offset; 5310 ret = regmap_update_bits(drv_data->bcast_regmap, 5311 cfg->reg_offset[LLCC_TRP_ALGO_ALLOC3] + reg_offset, 5312 BIT(slice_offset), vict_prio); 5313 if (ret) 5314 return ret; 5315 5316 if (config->activate_on_init) { 5317 desc = llcc_slice_getd(config->usecase_id); 5318 if (PTR_ERR_OR_ZERO(desc)) 5319 return -EINVAL; 5320 5321 ret = llcc_slice_activate(desc); 5322 } 5323 5324 return ret; 5325 } 5326 5327 static int qcom_llcc_cfg_program(struct platform_device *pdev, 5328 const struct qcom_llcc_config *cfg) 5329 { 5330 int i; 5331 u32 sz; 5332 int ret = 0; 5333 const struct llcc_slice_config *llcc_table; 5334 5335 sz = drv_data->cfg_size; 5336 llcc_table = drv_data->cfg; 5337 5338 for (i = 0; i < sz; i++) { 5339 drv_data->desc[i].uid = llcc_table[i].usecase_id; 5340 drv_data->desc[i].slice_id = llcc_table[i].slice_id; 5341 drv_data->desc[i].slice_size = llcc_table[i].max_cap; 5342 } 5343 5344 if (drv_data->version >= LLCC_VERSION_6_0_0_0) { 5345 for (i = 0; i < sz; i++) { 5346 ret = _qcom_llcc_cfg_program_v6(&llcc_table[i], cfg); 5347 if (ret) 5348 return ret; 5349 } 5350 } else { 5351 for (i = 0; i < sz; i++) { 5352 ret = _qcom_llcc_cfg_program(&llcc_table[i], cfg); 5353 if (ret) 5354 return ret; 5355 } 5356 } 5357 5358 return ret; 5359 } 5360 5361 static int qcom_llcc_get_cfg_index(struct platform_device *pdev, u8 *cfg_index, int num_config) 5362 { 5363 int ret; 5364 5365 ret = nvmem_cell_read_u8(&pdev->dev, "multi-chan-ddr", cfg_index); 5366 if (ret == -ENOENT || ret == -EOPNOTSUPP) { 5367 if (num_config > 1) 5368 return -EINVAL; 5369 *cfg_index = 0; 5370 return 0; 5371 } 5372 5373 if (!ret && *cfg_index >= num_config) 5374 ret = -EINVAL; 5375 5376 return ret; 5377 } 5378 5379 static int qcom_llcc_verify_fw_config(struct device *dev, 5380 const struct slc_sct_mem *slc_mem) 5381 { 5382 u64 program_status; 5383 5384 program_status = le64_to_cpu(slc_mem->sct_status.program_status); 5385 5386 if (program_status == SLC_SCT_DONE) { 5387 u32 desc_count = le32_to_cpu(slc_mem->slice_descs_count); 5388 u32 scid_max = le32_to_cpu(slc_mem->scid_max); 5389 5390 if (desc_count > scid_max) { 5391 dev_err(dev, "Descriptor count above max limit (%u > %u)\n", 5392 desc_count, scid_max); 5393 return -EINVAL; 5394 } 5395 5396 u8 revision = slc_mem->sct_details.revision; 5397 char name_buf[SLC_SCT_NAME_LEN]; 5398 5399 memcpy(name_buf, slc_mem->sct_details.name, 5400 SLC_SCT_NAME_LEN - 1); 5401 name_buf[SLC_SCT_NAME_LEN - 1] = '\0'; 5402 5403 dev_dbg(dev, "SCT init: desc_count=%u, rev=%u, name=%s\n", 5404 desc_count, revision, name_buf); 5405 5406 return 0; 5407 } else if (program_status == SLC_SCT_FAIL) { 5408 u8 version = (u8)(le64_to_cpu(slc_mem->sct_status.version)); 5409 u64 code = le64_to_cpu(slc_mem->sct_status.error.code); 5410 u64 param = le64_to_cpu(slc_mem->sct_status.error.param); 5411 5412 if (version == SLC_SCT_MEM_LAYOUT_VERSION1) { 5413 dev_err(dev, "SCT init failed: code = %llu, param = %llu, version = 0x%x\n", 5414 code, param, version); 5415 } else { 5416 dev_err(dev, "Found unsupported version %u\n", version); 5417 } 5418 } else { 5419 dev_err(dev, "Unknown SCT Initialization error\n"); 5420 } 5421 5422 return -EINVAL; 5423 } 5424 5425 static int qcom_llcc_get_fw_config(struct platform_device *pdev) 5426 { 5427 const struct slc_sct_mem *slc_mem = NULL; 5428 const struct slc_sct_slice_desc *memslice; 5429 struct device *dev = &pdev->dev; 5430 u32 slice_properties; 5431 struct resource res; 5432 u32 i, sz; 5433 int ret; 5434 5435 ret = of_reserved_mem_region_to_resource(dev->of_node, 0, &res); 5436 if (ret) { 5437 dev_err(dev, "Unable to locate DT /reserved-memory resource\n"); 5438 return ret; 5439 } 5440 5441 slc_mem = devm_memremap(dev, res.start, resource_size(&res), MEMREMAP_WB); 5442 if (IS_ERR(slc_mem)) { 5443 dev_err(dev, "Failed to memremap SLC shared memory\n"); 5444 return PTR_ERR(slc_mem); 5445 } 5446 5447 ret = qcom_llcc_verify_fw_config(dev, slc_mem); 5448 if (ret) 5449 return ret; 5450 5451 sz = le32_to_cpu(slc_mem->slice_descs_count); 5452 5453 drv_data->desc = devm_kcalloc(dev, sz, sizeof(struct llcc_slice_desc), 5454 GFP_KERNEL); 5455 if (!drv_data->desc) 5456 return -ENOMEM; 5457 5458 for (i = 0; i < sz; i++) { 5459 memslice = &slc_mem->slice_descs[i]; 5460 drv_data->desc[i].slice_id = le16_to_cpu(memslice->slice_id); 5461 drv_data->desc[i].uid = le16_to_cpu(memslice->usecase_id); 5462 slice_properties = le32_to_cpu(memslice->slice_properties); 5463 /* Set refcount to 1 if FW already activated this descriptor */ 5464 if (FIELD_GET(SLC_SCT_SLICE_ACT_ON_BOOT, slice_properties)) 5465 refcount_set(&drv_data->desc[i].refcount, 1); 5466 } 5467 5468 drv_data->cfg = NULL; 5469 drv_data->cfg_size = sz; 5470 5471 return 0; 5472 } 5473 5474 static void qcom_llcc_remove(struct platform_device *pdev) 5475 { 5476 /* Set the global pointer to a error code to avoid referencing it */ 5477 drv_data = ERR_PTR(-ENODEV); 5478 } 5479 5480 static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, u8 index, 5481 const char *name) 5482 { 5483 void __iomem *base; 5484 struct regmap_config llcc_regmap_config = { 5485 .reg_bits = 32, 5486 .reg_stride = 4, 5487 .val_bits = 32, 5488 }; 5489 5490 base = devm_platform_ioremap_resource(pdev, index); 5491 if (IS_ERR(base)) 5492 return ERR_CAST(base); 5493 5494 llcc_regmap_config.name = name; 5495 return devm_regmap_init_mmio(&pdev->dev, base, &llcc_regmap_config); 5496 } 5497 5498 static int qcom_llcc_probe(struct platform_device *pdev) 5499 { 5500 u32 num_banks; 5501 struct device *dev = &pdev->dev; 5502 int ret, i; 5503 struct platform_device *llcc_edac; 5504 const struct qcom_sct_config *cfgs; 5505 const struct qcom_llcc_config *cfg; 5506 u8 cfg_index; 5507 u32 version; 5508 struct regmap *regmap; 5509 5510 if (!IS_ERR(drv_data)) 5511 return -EBUSY; 5512 5513 drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); 5514 if (!drv_data) { 5515 ret = -ENOMEM; 5516 goto err; 5517 } 5518 5519 /* Initialize the first LLCC bank regmap */ 5520 regmap = qcom_llcc_init_mmio(pdev, 0, "llcc0_base"); 5521 if (IS_ERR(regmap)) { 5522 ret = PTR_ERR(regmap); 5523 goto err; 5524 } 5525 5526 cfgs = of_device_get_match_data(&pdev->dev); 5527 if (!cfgs) { 5528 ret = -EINVAL; 5529 goto err; 5530 } 5531 ret = qcom_llcc_get_cfg_index(pdev, &cfg_index, cfgs->num_config); 5532 if (ret) 5533 goto err; 5534 cfg = &cfgs->llcc_config[cfg_index]; 5535 5536 if (cfg->num_banks) { 5537 num_banks = cfg->num_banks; 5538 } else { 5539 ret = regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_banks); 5540 if (ret) 5541 goto err; 5542 5543 num_banks &= LLCC_LB_CNT_MASK; 5544 num_banks >>= LLCC_LB_CNT_SHIFT; 5545 } 5546 5547 drv_data->num_banks = num_banks; 5548 5549 drv_data->regmaps = devm_kcalloc(dev, num_banks, sizeof(*drv_data->regmaps), GFP_KERNEL); 5550 if (!drv_data->regmaps) { 5551 ret = -ENOMEM; 5552 goto err; 5553 } 5554 5555 drv_data->regmaps[0] = regmap; 5556 5557 /* Initialize rest of LLCC bank regmaps */ 5558 for (i = 1; i < num_banks; i++) { 5559 char *base __free(kfree) = kasprintf(GFP_KERNEL, "llcc%d_base", i); 5560 5561 drv_data->regmaps[i] = qcom_llcc_init_mmio(pdev, i, base); 5562 if (IS_ERR(drv_data->regmaps[i])) { 5563 ret = PTR_ERR(drv_data->regmaps[i]); 5564 goto err; 5565 } 5566 } 5567 5568 drv_data->bcast_regmap = qcom_llcc_init_mmio(pdev, i, "llcc_broadcast_base"); 5569 if (IS_ERR(drv_data->bcast_regmap)) { 5570 if (cfg->no_broadcast_register) { 5571 drv_data->bcast_regmap = regmap; 5572 } else { 5573 ret = PTR_ERR(drv_data->bcast_regmap); 5574 goto err; 5575 } 5576 } 5577 5578 /* Extract version of the IP */ 5579 ret = regmap_read(drv_data->bcast_regmap, cfg->reg_offset[LLCC_COMMON_HW_INFO], 5580 &version); 5581 if (ret) 5582 goto err; 5583 5584 drv_data->version = version; 5585 5586 /* Applicable only when drv_data->version >= 4.1 */ 5587 if (drv_data->version >= LLCC_VERSION_4_1_0_0) { 5588 drv_data->bcast_and_regmap = qcom_llcc_init_mmio(pdev, i + 1, "llcc_broadcast_and_base"); 5589 if (IS_ERR(drv_data->bcast_and_regmap)) { 5590 ret = PTR_ERR(drv_data->bcast_and_regmap); 5591 if (ret == -EINVAL) 5592 drv_data->bcast_and_regmap = NULL; 5593 else 5594 goto err; 5595 } 5596 } 5597 5598 mutex_init(&drv_data->lock); 5599 if (!cfg->size) { 5600 ret = qcom_llcc_get_fw_config(pdev); 5601 if (ret) 5602 goto err; 5603 } else { 5604 drv_data->cfg = cfg->sct_data; 5605 drv_data->cfg_size = cfg->size; 5606 drv_data->desc = devm_kcalloc(dev, cfg->size, 5607 sizeof(struct llcc_slice_desc), GFP_KERNEL); 5608 5609 if (!drv_data->desc) { 5610 ret = -ENOMEM; 5611 goto err; 5612 } 5613 5614 ret = qcom_llcc_cfg_program(pdev, cfg); 5615 if (ret) 5616 goto err; 5617 } 5618 5619 drv_data->ecc_irq = platform_get_irq_optional(pdev, 0); 5620 drv_data->edac_reg_offset = cfg->edac_reg_offset; 5621 drv_data->ecc_irq_configured = cfg->irq_configured; 5622 drv_data->dev = dev; 5623 5624 /* 5625 * On some platforms, the access to EDAC registers will be locked by 5626 * the bootloader. So probing the EDAC driver will result in a crash. 5627 * Hence, disable the creation of EDAC platform device for the 5628 * problematic platforms. 5629 */ 5630 if (!cfg->no_edac) { 5631 llcc_edac = platform_device_register_data(&pdev->dev, 5632 "qcom_llcc_edac", -1, drv_data, 5633 sizeof(*drv_data)); 5634 if (IS_ERR(llcc_edac)) 5635 dev_err(dev, "Failed to register LLCC EDAC driver\n"); 5636 } 5637 5638 platform_set_drvdata(pdev, drv_data); 5639 5640 return 0; 5641 err: 5642 drv_data = ERR_PTR(-ENODEV); 5643 return ret; 5644 } 5645 5646 static const struct of_device_id qcom_llcc_of_match[] = { 5647 { .compatible = "qcom,eliza-llcc", .data = &eliza_cfgs }, 5648 { .compatible = "qcom,glymur-llcc", .data = &glymur_cfgs }, 5649 { .compatible = "qcom,hawi-llcc", .data = &hawi_sct_cfgs }, 5650 { .compatible = "qcom,ipq5424-llcc", .data = &ipq5424_cfgs}, 5651 { .compatible = "qcom,kaanapali-llcc", .data = &kaanapali_cfgs}, 5652 { .compatible = "qcom,qcs615-llcc", .data = &qcs615_cfgs}, 5653 { .compatible = "qcom,qcs8300-llcc", .data = &qcs8300_cfgs}, 5654 { .compatible = "qcom,qdu1000-llcc", .data = &qdu1000_cfgs}, 5655 { .compatible = "qcom,sa8775p-llcc", .data = &sa8775p_cfgs }, 5656 { .compatible = "qcom,sar1130p-llcc", .data = &sar1130p_cfgs }, 5657 { .compatible = "qcom,sar2130p-llcc", .data = &sar2130p_cfgs }, 5658 { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfgs }, 5659 { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfgs }, 5660 { .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfgs }, 5661 { .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfgs }, 5662 { .compatible = "qcom,sdm670-llcc", .data = &sdm670_cfgs }, 5663 { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfgs }, 5664 { .compatible = "qcom,shikra-llcc", .data = &shikra_cfgs }, 5665 { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfgs }, 5666 { .compatible = "qcom,sm7150-llcc", .data = &sm7150_cfgs }, 5667 { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfgs }, 5668 { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfgs }, 5669 { .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfgs }, 5670 { .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfgs }, 5671 { .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfgs }, 5672 { .compatible = "qcom,sm8650-llcc", .data = &sm8650_cfgs }, 5673 { .compatible = "qcom,sm8750-llcc", .data = &sm8750_cfgs }, 5674 { .compatible = "qcom,x1e80100-llcc", .data = &x1e80100_cfgs }, 5675 { } 5676 }; 5677 MODULE_DEVICE_TABLE(of, qcom_llcc_of_match); 5678 5679 static struct platform_driver qcom_llcc_driver = { 5680 .driver = { 5681 .name = "qcom-llcc", 5682 .of_match_table = qcom_llcc_of_match, 5683 }, 5684 .probe = qcom_llcc_probe, 5685 .remove = qcom_llcc_remove, 5686 }; 5687 module_platform_driver(qcom_llcc_driver); 5688 5689 MODULE_DESCRIPTION("Qualcomm Last Level Cache Controller"); 5690 MODULE_LICENSE("GPL v2"); 5691