1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/bits.h> 8 #include <linux/clk.h> 9 #include <linux/completion.h> 10 #include <linux/cpu.h> 11 #include <linux/cpuidle.h> 12 #include <linux/debugfs.h> 13 #include <linux/device.h> 14 #include <linux/init.h> 15 #include <linux/interrupt.h> 16 #include <linux/kernel.h> 17 #include <linux/kthread.h> 18 #include <linux/module.h> 19 #include <linux/mutex.h> 20 #include <linux/nvmem-consumer.h> 21 #include <linux/of_address.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_platform.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_domain.h> 26 #include <linux/pm_opp.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/regulator/consumer.h> 29 #include <linux/reset.h> 30 #include <linux/seq_file.h> 31 #include <linux/slab.h> 32 #include <linux/spinlock.h> 33 #include <linux/thermal.h> 34 35 /* svs bank 1-line software id */ 36 #define SVSB_CPU_LITTLE BIT(0) 37 #define SVSB_CPU_BIG BIT(1) 38 #define SVSB_CCI BIT(2) 39 #define SVSB_GPU BIT(3) 40 41 /* svs bank 2-line type */ 42 #define SVSB_LOW BIT(8) 43 #define SVSB_HIGH BIT(9) 44 45 /* svs bank mode support */ 46 #define SVSB_MODE_ALL_DISABLE 0 47 #define SVSB_MODE_INIT01 BIT(1) 48 #define SVSB_MODE_INIT02 BIT(2) 49 #define SVSB_MODE_MON BIT(3) 50 51 /* svs bank volt flags */ 52 #define SVSB_INIT01_PD_REQ BIT(0) 53 #define SVSB_INIT01_VOLT_IGNORE BIT(1) 54 #define SVSB_INIT01_VOLT_INC_ONLY BIT(2) 55 #define SVSB_MON_VOLT_IGNORE BIT(16) 56 #define SVSB_REMOVE_DVTFIXED_VOLT BIT(24) 57 58 /* svs bank register fields and common configuration */ 59 #define SVSB_PTPCONFIG_DETMAX GENMASK(15, 0) 60 #define SVSB_DET_MAX FIELD_PREP(SVSB_PTPCONFIG_DETMAX, 0xffff) 61 #define SVSB_DET_WINDOW 0xa28 62 63 /* DESCHAR */ 64 #define SVSB_DESCHAR_FLD_MDES GENMASK(7, 0) 65 #define SVSB_DESCHAR_FLD_BDES GENMASK(15, 8) 66 67 /* TEMPCHAR */ 68 #define SVSB_TEMPCHAR_FLD_DVT_FIXED GENMASK(7, 0) 69 #define SVSB_TEMPCHAR_FLD_MTDES GENMASK(15, 8) 70 #define SVSB_TEMPCHAR_FLD_VCO GENMASK(23, 16) 71 72 /* DETCHAR */ 73 #define SVSB_DETCHAR_FLD_DCMDET GENMASK(7, 0) 74 #define SVSB_DETCHAR_FLD_DCBDET GENMASK(15, 8) 75 76 /* SVSEN (PTPEN) */ 77 #define SVSB_PTPEN_INIT01 BIT(0) 78 #define SVSB_PTPEN_MON BIT(1) 79 #define SVSB_PTPEN_INIT02 (SVSB_PTPEN_INIT01 | BIT(2)) 80 #define SVSB_PTPEN_OFF 0x0 81 82 /* FREQPCTS */ 83 #define SVSB_FREQPCTS_FLD_PCT0_4 GENMASK(7, 0) 84 #define SVSB_FREQPCTS_FLD_PCT1_5 GENMASK(15, 8) 85 #define SVSB_FREQPCTS_FLD_PCT2_6 GENMASK(23, 16) 86 #define SVSB_FREQPCTS_FLD_PCT3_7 GENMASK(31, 24) 87 88 /* INTSTS */ 89 #define SVSB_INTSTS_VAL_CLEAN 0x00ffffff 90 #define SVSB_INTSTS_F0_COMPLETE BIT(0) 91 #define SVSB_INTSTS_FLD_MONVOP GENMASK(23, 16) 92 #define SVSB_RUNCONFIG_DEFAULT 0x80000000 93 94 /* LIMITVALS */ 95 #define SVSB_LIMITVALS_FLD_DTLO GENMASK(7, 0) 96 #define SVSB_LIMITVALS_FLD_DTHI GENMASK(15, 8) 97 #define SVSB_LIMITVALS_FLD_VMIN GENMASK(23, 16) 98 #define SVSB_LIMITVALS_FLD_VMAX GENMASK(31, 24) 99 #define SVSB_VAL_DTHI 0x1 100 #define SVSB_VAL_DTLO 0xfe 101 102 /* INTEN */ 103 #define SVSB_INTEN_F0EN BIT(0) 104 #define SVSB_INTEN_DACK0UPEN BIT(8) 105 #define SVSB_INTEN_DC0EN BIT(9) 106 #define SVSB_INTEN_DC1EN BIT(10) 107 #define SVSB_INTEN_DACK0LOEN BIT(11) 108 #define SVSB_INTEN_INITPROD_OVF_EN BIT(12) 109 #define SVSB_INTEN_INITSUM_OVF_EN BIT(14) 110 #define SVSB_INTEN_MONVOPEN GENMASK(23, 16) 111 #define SVSB_INTEN_INIT0x (SVSB_INTEN_F0EN | SVSB_INTEN_DACK0UPEN | \ 112 SVSB_INTEN_DC0EN | SVSB_INTEN_DC1EN | \ 113 SVSB_INTEN_DACK0LOEN | \ 114 SVSB_INTEN_INITPROD_OVF_EN | \ 115 SVSB_INTEN_INITSUM_OVF_EN) 116 117 /* TSCALCS */ 118 #define SVSB_TSCALCS_FLD_MTS GENMASK(11, 0) 119 #define SVSB_TSCALCS_FLD_BTS GENMASK(23, 12) 120 121 /* INIT2VALS */ 122 #define SVSB_INIT2VALS_FLD_DCVOFFSETIN GENMASK(15, 0) 123 #define SVSB_INIT2VALS_FLD_AGEVOFFSETIN GENMASK(31, 16) 124 125 /* VOPS */ 126 #define SVSB_VOPS_FLD_VOP0_4 GENMASK(7, 0) 127 #define SVSB_VOPS_FLD_VOP1_5 GENMASK(15, 8) 128 #define SVSB_VOPS_FLD_VOP2_6 GENMASK(23, 16) 129 #define SVSB_VOPS_FLD_VOP3_7 GENMASK(31, 24) 130 131 /* svs bank related setting */ 132 #define BITS8 8 133 #define MAX_OPP_ENTRIES 16 134 #define REG_BYTES 4 135 #define SVSB_DC_SIGNED_BIT BIT(15) 136 #define SVSB_DET_CLK_EN BIT(31) 137 #define SVSB_TEMP_LOWER_BOUND 0xb2 138 #define SVSB_TEMP_UPPER_BOUND 0x64 139 140 static DEFINE_SPINLOCK(svs_lock); 141 142 #ifdef CONFIG_DEBUG_FS 143 #define debug_fops_ro(name) \ 144 static int svs_##name##_debug_open(struct inode *inode, \ 145 struct file *filp) \ 146 { \ 147 return single_open(filp, svs_##name##_debug_show, \ 148 inode->i_private); \ 149 } \ 150 static const struct file_operations svs_##name##_debug_fops = { \ 151 .owner = THIS_MODULE, \ 152 .open = svs_##name##_debug_open, \ 153 .read = seq_read, \ 154 .llseek = seq_lseek, \ 155 .release = single_release, \ 156 } 157 158 #define debug_fops_rw(name) \ 159 static int svs_##name##_debug_open(struct inode *inode, \ 160 struct file *filp) \ 161 { \ 162 return single_open(filp, svs_##name##_debug_show, \ 163 inode->i_private); \ 164 } \ 165 static const struct file_operations svs_##name##_debug_fops = { \ 166 .owner = THIS_MODULE, \ 167 .open = svs_##name##_debug_open, \ 168 .read = seq_read, \ 169 .write = svs_##name##_debug_write, \ 170 .llseek = seq_lseek, \ 171 .release = single_release, \ 172 } 173 174 #define svs_dentry_data(name) {__stringify(name), &svs_##name##_debug_fops} 175 #endif 176 177 /** 178 * enum svsb_phase - svs bank phase enumeration 179 * @SVSB_PHASE_ERROR: svs bank encounters unexpected condition 180 * @SVSB_PHASE_INIT01: svs bank basic init for data calibration 181 * @SVSB_PHASE_INIT02: svs bank can provide voltages to opp table 182 * @SVSB_PHASE_MON: svs bank can provide voltages with thermal effect 183 * @SVSB_PHASE_MAX: total number of svs bank phase (debug purpose) 184 * 185 * Each svs bank has its own independent phase and we enable each svs bank by 186 * running their phase orderly. However, when svs bank encounters unexpected 187 * condition, it will fire an irq (PHASE_ERROR) to inform svs software. 188 * 189 * svs bank general phase-enabled order: 190 * SVSB_PHASE_INIT01 -> SVSB_PHASE_INIT02 -> SVSB_PHASE_MON 191 */ 192 enum svsb_phase { 193 SVSB_PHASE_ERROR = 0, 194 SVSB_PHASE_INIT01, 195 SVSB_PHASE_INIT02, 196 SVSB_PHASE_MON, 197 SVSB_PHASE_MAX, 198 }; 199 200 enum svs_reg_index { 201 DESCHAR = 0, 202 TEMPCHAR, 203 DETCHAR, 204 AGECHAR, 205 DCCONFIG, 206 AGECONFIG, 207 FREQPCT30, 208 FREQPCT74, 209 LIMITVALS, 210 VBOOT, 211 DETWINDOW, 212 CONFIG, 213 TSCALCS, 214 RUNCONFIG, 215 SVSEN, 216 INIT2VALS, 217 DCVALUES, 218 AGEVALUES, 219 VOP30, 220 VOP74, 221 TEMP, 222 INTSTS, 223 INTSTSRAW, 224 INTEN, 225 CHKINT, 226 CHKSHIFT, 227 STATUS, 228 VDESIGN30, 229 VDESIGN74, 230 DVT30, 231 DVT74, 232 AGECOUNT, 233 SMSTATE0, 234 SMSTATE1, 235 CTL0, 236 DESDETSEC, 237 TEMPAGESEC, 238 CTRLSPARE0, 239 CTRLSPARE1, 240 CTRLSPARE2, 241 CTRLSPARE3, 242 CORESEL, 243 THERMINTST, 244 INTST, 245 THSTAGE0ST, 246 THSTAGE1ST, 247 THSTAGE2ST, 248 THAHBST0, 249 THAHBST1, 250 SPARE0, 251 SPARE1, 252 SPARE2, 253 SPARE3, 254 THSLPEVEB, 255 SVS_REG_MAX, 256 }; 257 258 static const u32 svs_regs_v2[] = { 259 [DESCHAR] = 0xc00, 260 [TEMPCHAR] = 0xc04, 261 [DETCHAR] = 0xc08, 262 [AGECHAR] = 0xc0c, 263 [DCCONFIG] = 0xc10, 264 [AGECONFIG] = 0xc14, 265 [FREQPCT30] = 0xc18, 266 [FREQPCT74] = 0xc1c, 267 [LIMITVALS] = 0xc20, 268 [VBOOT] = 0xc24, 269 [DETWINDOW] = 0xc28, 270 [CONFIG] = 0xc2c, 271 [TSCALCS] = 0xc30, 272 [RUNCONFIG] = 0xc34, 273 [SVSEN] = 0xc38, 274 [INIT2VALS] = 0xc3c, 275 [DCVALUES] = 0xc40, 276 [AGEVALUES] = 0xc44, 277 [VOP30] = 0xc48, 278 [VOP74] = 0xc4c, 279 [TEMP] = 0xc50, 280 [INTSTS] = 0xc54, 281 [INTSTSRAW] = 0xc58, 282 [INTEN] = 0xc5c, 283 [CHKINT] = 0xc60, 284 [CHKSHIFT] = 0xc64, 285 [STATUS] = 0xc68, 286 [VDESIGN30] = 0xc6c, 287 [VDESIGN74] = 0xc70, 288 [DVT30] = 0xc74, 289 [DVT74] = 0xc78, 290 [AGECOUNT] = 0xc7c, 291 [SMSTATE0] = 0xc80, 292 [SMSTATE1] = 0xc84, 293 [CTL0] = 0xc88, 294 [DESDETSEC] = 0xce0, 295 [TEMPAGESEC] = 0xce4, 296 [CTRLSPARE0] = 0xcf0, 297 [CTRLSPARE1] = 0xcf4, 298 [CTRLSPARE2] = 0xcf8, 299 [CTRLSPARE3] = 0xcfc, 300 [CORESEL] = 0xf00, 301 [THERMINTST] = 0xf04, 302 [INTST] = 0xf08, 303 [THSTAGE0ST] = 0xf0c, 304 [THSTAGE1ST] = 0xf10, 305 [THSTAGE2ST] = 0xf14, 306 [THAHBST0] = 0xf18, 307 [THAHBST1] = 0xf1c, 308 [SPARE0] = 0xf20, 309 [SPARE1] = 0xf24, 310 [SPARE2] = 0xf28, 311 [SPARE3] = 0xf2c, 312 [THSLPEVEB] = 0xf30, 313 }; 314 315 /** 316 * struct svs_platform - svs platform control 317 * @base: svs platform register base 318 * @dev: svs platform device 319 * @main_clk: main clock for svs bank 320 * @pbank: svs bank pointer needing to be protected by spin_lock section 321 * @banks: svs banks that svs platform supports 322 * @rst: svs platform reset control 323 * @efuse_max: total number of svs efuse 324 * @tefuse_max: total number of thermal efuse 325 * @regs: svs platform registers map 326 * @bank_max: total number of svs banks 327 * @efuse: svs efuse data received from NVMEM framework 328 * @tefuse: thermal efuse data received from NVMEM framework 329 */ 330 struct svs_platform { 331 void __iomem *base; 332 struct device *dev; 333 struct clk *main_clk; 334 struct svs_bank *pbank; 335 struct svs_bank *banks; 336 struct reset_control *rst; 337 size_t efuse_max; 338 size_t tefuse_max; 339 const u32 *regs; 340 u32 bank_max; 341 u32 *efuse; 342 u32 *tefuse; 343 }; 344 345 struct svs_platform_data { 346 char *name; 347 struct svs_bank *banks; 348 bool (*efuse_parsing)(struct svs_platform *svsp); 349 int (*probe)(struct svs_platform *svsp); 350 const u32 *regs; 351 u32 bank_max; 352 }; 353 354 /** 355 * struct svs_bank - svs bank representation 356 * @dev: bank device 357 * @opp_dev: device for opp table/buck control 358 * @init_completion: the timeout completion for bank init 359 * @buck: regulator used by opp_dev 360 * @tzd: thermal zone device for getting temperature 361 * @lock: mutex lock to protect voltage update process 362 * @set_freq_pct: function pointer to set bank frequency percent table 363 * @get_volts: function pointer to get bank voltages 364 * @name: bank name 365 * @buck_name: regulator name 366 * @tzone_name: thermal zone name 367 * @phase: bank current phase 368 * @volt_od: bank voltage overdrive 369 * @reg_data: bank register data in different phase for debug purpose 370 * @pm_runtime_enabled_count: bank pm runtime enabled count 371 * @mode_support: bank mode support. 372 * @freq_base: reference frequency for bank init 373 * @turn_freq_base: refenrece frequency for 2-line turn point 374 * @vboot: voltage request for bank init01 only 375 * @opp_dfreq: default opp frequency table 376 * @opp_dvolt: default opp voltage table 377 * @freq_pct: frequency percent table for bank init 378 * @volt: bank voltage table 379 * @volt_step: bank voltage step 380 * @volt_base: bank voltage base 381 * @volt_flags: bank voltage flags 382 * @vmax: bank voltage maximum 383 * @vmin: bank voltage minimum 384 * @age_config: bank age configuration 385 * @age_voffset_in: bank age voltage offset 386 * @dc_config: bank dc configuration 387 * @dc_voffset_in: bank dc voltage offset 388 * @dvt_fixed: bank dvt fixed value 389 * @vco: bank VCO value 390 * @chk_shift: bank chicken shift 391 * @core_sel: bank selection 392 * @opp_count: bank opp count 393 * @int_st: bank interrupt identification 394 * @sw_id: bank software identification 395 * @cpu_id: cpu core id for SVS CPU bank use only 396 * @ctl0: TS-x selection 397 * @temp: bank temperature 398 * @tzone_htemp: thermal zone high temperature threshold 399 * @tzone_htemp_voffset: thermal zone high temperature voltage offset 400 * @tzone_ltemp: thermal zone low temperature threshold 401 * @tzone_ltemp_voffset: thermal zone low temperature voltage offset 402 * @bts: svs efuse data 403 * @mts: svs efuse data 404 * @bdes: svs efuse data 405 * @mdes: svs efuse data 406 * @mtdes: svs efuse data 407 * @dcbdet: svs efuse data 408 * @dcmdet: svs efuse data 409 * @turn_pt: 2-line turn point tells which opp_volt calculated by high/low bank 410 * @vbin_turn_pt: voltage bin turn point helps know which svsb_volt should be overridden 411 * @type: bank type to represent it is 2-line (high/low) bank or 1-line bank 412 * 413 * Svs bank will generate suitalbe voltages by below general math equation 414 * and provide these voltages to opp voltage table. 415 * 416 * opp_volt[i] = (volt[i] * volt_step) + volt_base; 417 */ 418 struct svs_bank { 419 struct device *dev; 420 struct device *opp_dev; 421 struct completion init_completion; 422 struct regulator *buck; 423 struct thermal_zone_device *tzd; 424 struct mutex lock; /* lock to protect voltage update process */ 425 void (*set_freq_pct)(struct svs_platform *svsp); 426 void (*get_volts)(struct svs_platform *svsp); 427 char *name; 428 char *buck_name; 429 char *tzone_name; 430 enum svsb_phase phase; 431 s32 volt_od; 432 u32 reg_data[SVSB_PHASE_MAX][SVS_REG_MAX]; 433 u32 pm_runtime_enabled_count; 434 u32 mode_support; 435 u32 freq_base; 436 u32 turn_freq_base; 437 u32 vboot; 438 u32 opp_dfreq[MAX_OPP_ENTRIES]; 439 u32 opp_dvolt[MAX_OPP_ENTRIES]; 440 u32 freq_pct[MAX_OPP_ENTRIES]; 441 u32 volt[MAX_OPP_ENTRIES]; 442 u32 volt_step; 443 u32 volt_base; 444 u32 volt_flags; 445 u32 vmax; 446 u32 vmin; 447 u32 age_config; 448 u32 age_voffset_in; 449 u32 dc_config; 450 u32 dc_voffset_in; 451 u32 dvt_fixed; 452 u32 vco; 453 u32 chk_shift; 454 u32 core_sel; 455 u32 opp_count; 456 u32 int_st; 457 u32 sw_id; 458 u32 cpu_id; 459 u32 ctl0; 460 u32 temp; 461 u32 tzone_htemp; 462 u32 tzone_htemp_voffset; 463 u32 tzone_ltemp; 464 u32 tzone_ltemp_voffset; 465 u32 bts; 466 u32 mts; 467 u32 bdes; 468 u32 mdes; 469 u32 mtdes; 470 u32 dcbdet; 471 u32 dcmdet; 472 u32 turn_pt; 473 u32 vbin_turn_pt; 474 u32 type; 475 }; 476 477 static u32 percent(u32 numerator, u32 denominator) 478 { 479 /* If not divide 1000, "numerator * 100" will have data overflow. */ 480 numerator /= 1000; 481 denominator /= 1000; 482 483 return DIV_ROUND_UP(numerator * 100, denominator); 484 } 485 486 static u32 svs_readl_relaxed(struct svs_platform *svsp, enum svs_reg_index rg_i) 487 { 488 return readl_relaxed(svsp->base + svsp->regs[rg_i]); 489 } 490 491 static void svs_writel_relaxed(struct svs_platform *svsp, u32 val, 492 enum svs_reg_index rg_i) 493 { 494 writel_relaxed(val, svsp->base + svsp->regs[rg_i]); 495 } 496 497 static void svs_switch_bank(struct svs_platform *svsp) 498 { 499 struct svs_bank *svsb = svsp->pbank; 500 501 svs_writel_relaxed(svsp, svsb->core_sel, CORESEL); 502 } 503 504 static u32 svs_bank_volt_to_opp_volt(u32 svsb_volt, u32 svsb_volt_step, 505 u32 svsb_volt_base) 506 { 507 return (svsb_volt * svsb_volt_step) + svsb_volt_base; 508 } 509 510 static u32 svs_opp_volt_to_bank_volt(u32 opp_u_volt, u32 svsb_volt_step, 511 u32 svsb_volt_base) 512 { 513 return (opp_u_volt - svsb_volt_base) / svsb_volt_step; 514 } 515 516 static int svs_sync_bank_volts_from_opp(struct svs_bank *svsb) 517 { 518 struct dev_pm_opp *opp; 519 u32 i, opp_u_volt; 520 521 for (i = 0; i < svsb->opp_count; i++) { 522 opp = dev_pm_opp_find_freq_exact(svsb->opp_dev, 523 svsb->opp_dfreq[i], 524 true); 525 if (IS_ERR(opp)) { 526 dev_err(svsb->dev, "cannot find freq = %u (%ld)\n", 527 svsb->opp_dfreq[i], PTR_ERR(opp)); 528 return PTR_ERR(opp); 529 } 530 531 opp_u_volt = dev_pm_opp_get_voltage(opp); 532 svsb->volt[i] = svs_opp_volt_to_bank_volt(opp_u_volt, 533 svsb->volt_step, 534 svsb->volt_base); 535 dev_pm_opp_put(opp); 536 } 537 538 return 0; 539 } 540 541 static int svs_adjust_pm_opp_volts(struct svs_bank *svsb) 542 { 543 int ret = -EPERM, tzone_temp = 0; 544 u32 i, svsb_volt, opp_volt, temp_voffset = 0, opp_start, opp_stop; 545 546 mutex_lock(&svsb->lock); 547 548 /* 549 * 2-line bank updates its corresponding opp volts. 550 * 1-line bank updates all opp volts. 551 */ 552 if (svsb->type == SVSB_HIGH) { 553 opp_start = 0; 554 opp_stop = svsb->turn_pt; 555 } else if (svsb->type == SVSB_LOW) { 556 opp_start = svsb->turn_pt; 557 opp_stop = svsb->opp_count; 558 } else { 559 opp_start = 0; 560 opp_stop = svsb->opp_count; 561 } 562 563 /* Get thermal effect */ 564 if (!IS_ERR_OR_NULL(svsb->tzd)) { 565 ret = thermal_zone_get_temp(svsb->tzd, &tzone_temp); 566 if (ret || (svsb->temp > SVSB_TEMP_UPPER_BOUND && 567 svsb->temp < SVSB_TEMP_LOWER_BOUND)) { 568 dev_err(svsb->dev, "%s: %d (0x%x), run default volts\n", 569 svsb->tzone_name, ret, svsb->temp); 570 svsb->phase = SVSB_PHASE_ERROR; 571 } 572 573 if (tzone_temp >= svsb->tzone_htemp) 574 temp_voffset += svsb->tzone_htemp_voffset; 575 else if (tzone_temp <= svsb->tzone_ltemp) 576 temp_voffset += svsb->tzone_ltemp_voffset; 577 578 /* 2-line bank update all opp volts when running mon mode */ 579 if (svsb->phase == SVSB_PHASE_MON && (svsb->type == SVSB_HIGH || 580 svsb->type == SVSB_LOW)) { 581 opp_start = 0; 582 opp_stop = svsb->opp_count; 583 } 584 } 585 586 /* vmin <= svsb_volt (opp_volt) <= default opp voltage */ 587 for (i = opp_start; i < opp_stop; i++) { 588 switch (svsb->phase) { 589 case SVSB_PHASE_ERROR: 590 opp_volt = svsb->opp_dvolt[i]; 591 break; 592 case SVSB_PHASE_INIT01: 593 /* do nothing */ 594 goto unlock_mutex; 595 case SVSB_PHASE_INIT02: 596 case SVSB_PHASE_MON: 597 svsb_volt = max(svsb->volt[i] + temp_voffset, svsb->vmin); 598 opp_volt = svs_bank_volt_to_opp_volt(svsb_volt, 599 svsb->volt_step, 600 svsb->volt_base); 601 break; 602 default: 603 dev_err(svsb->dev, "unknown phase: %u\n", svsb->phase); 604 ret = -EINVAL; 605 goto unlock_mutex; 606 } 607 608 opp_volt = min(opp_volt, svsb->opp_dvolt[i]); 609 ret = dev_pm_opp_adjust_voltage(svsb->opp_dev, 610 svsb->opp_dfreq[i], 611 opp_volt, opp_volt, 612 svsb->opp_dvolt[i]); 613 if (ret) { 614 dev_err(svsb->dev, "set %uuV fail: %d\n", 615 opp_volt, ret); 616 goto unlock_mutex; 617 } 618 } 619 620 unlock_mutex: 621 mutex_unlock(&svsb->lock); 622 623 return ret; 624 } 625 626 static void svs_bank_disable_and_restore_default_volts(struct svs_platform *svsp, 627 struct svs_bank *svsb) 628 { 629 unsigned long flags; 630 631 if (svsb->mode_support == SVSB_MODE_ALL_DISABLE) 632 return; 633 634 spin_lock_irqsave(&svs_lock, flags); 635 svsp->pbank = svsb; 636 svs_switch_bank(svsp); 637 svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN); 638 svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS); 639 spin_unlock_irqrestore(&svs_lock, flags); 640 641 svsb->phase = SVSB_PHASE_ERROR; 642 svs_adjust_pm_opp_volts(svsb); 643 } 644 645 #ifdef CONFIG_DEBUG_FS 646 static int svs_dump_debug_show(struct seq_file *m, void *p) 647 { 648 struct svs_platform *svsp = (struct svs_platform *)m->private; 649 struct svs_bank *svsb; 650 unsigned long svs_reg_addr; 651 u32 idx, i, j, bank_id; 652 653 for (i = 0; i < svsp->efuse_max; i++) 654 if (svsp->efuse && svsp->efuse[i]) 655 seq_printf(m, "M_HW_RES%d = 0x%08x\n", 656 i, svsp->efuse[i]); 657 658 for (i = 0; i < svsp->tefuse_max; i++) 659 if (svsp->tefuse) 660 seq_printf(m, "THERMAL_EFUSE%d = 0x%08x\n", 661 i, svsp->tefuse[i]); 662 663 for (bank_id = 0, idx = 0; idx < svsp->bank_max; idx++, bank_id++) { 664 svsb = &svsp->banks[idx]; 665 666 for (i = SVSB_PHASE_INIT01; i <= SVSB_PHASE_MON; i++) { 667 seq_printf(m, "Bank_number = %u\n", bank_id); 668 669 if (i == SVSB_PHASE_INIT01 || i == SVSB_PHASE_INIT02) 670 seq_printf(m, "mode = init%d\n", i); 671 else if (i == SVSB_PHASE_MON) 672 seq_puts(m, "mode = mon\n"); 673 else 674 seq_puts(m, "mode = error\n"); 675 676 for (j = DESCHAR; j < SVS_REG_MAX; j++) { 677 svs_reg_addr = (unsigned long)(svsp->base + 678 svsp->regs[j]); 679 seq_printf(m, "0x%08lx = 0x%08x\n", 680 svs_reg_addr, svsb->reg_data[i][j]); 681 } 682 } 683 } 684 685 return 0; 686 } 687 688 debug_fops_ro(dump); 689 690 static int svs_enable_debug_show(struct seq_file *m, void *v) 691 { 692 struct svs_bank *svsb = (struct svs_bank *)m->private; 693 694 switch (svsb->phase) { 695 case SVSB_PHASE_ERROR: 696 seq_puts(m, "disabled\n"); 697 break; 698 case SVSB_PHASE_INIT01: 699 seq_puts(m, "init1\n"); 700 break; 701 case SVSB_PHASE_INIT02: 702 seq_puts(m, "init2\n"); 703 break; 704 case SVSB_PHASE_MON: 705 seq_puts(m, "mon mode\n"); 706 break; 707 default: 708 seq_puts(m, "unknown\n"); 709 break; 710 } 711 712 return 0; 713 } 714 715 static ssize_t svs_enable_debug_write(struct file *filp, 716 const char __user *buffer, 717 size_t count, loff_t *pos) 718 { 719 struct svs_bank *svsb = file_inode(filp)->i_private; 720 struct svs_platform *svsp = dev_get_drvdata(svsb->dev); 721 int enabled, ret; 722 char *buf = NULL; 723 724 if (count >= PAGE_SIZE) 725 return -EINVAL; 726 727 buf = (char *)memdup_user_nul(buffer, count); 728 if (IS_ERR(buf)) 729 return PTR_ERR(buf); 730 731 ret = kstrtoint(buf, 10, &enabled); 732 if (ret) 733 return ret; 734 735 if (!enabled) { 736 svs_bank_disable_and_restore_default_volts(svsp, svsb); 737 svsb->mode_support = SVSB_MODE_ALL_DISABLE; 738 } 739 740 kfree(buf); 741 742 return count; 743 } 744 745 debug_fops_rw(enable); 746 747 static int svs_status_debug_show(struct seq_file *m, void *v) 748 { 749 struct svs_bank *svsb = (struct svs_bank *)m->private; 750 struct dev_pm_opp *opp; 751 int tzone_temp = 0, ret; 752 u32 i; 753 754 ret = thermal_zone_get_temp(svsb->tzd, &tzone_temp); 755 if (ret) 756 seq_printf(m, "%s: temperature ignore, vbin_turn_pt = %u, turn_pt = %u\n", 757 svsb->name, svsb->vbin_turn_pt, svsb->turn_pt); 758 else 759 seq_printf(m, "%s: temperature = %d, vbin_turn_pt = %u, turn_pt = %u\n", 760 svsb->name, tzone_temp, svsb->vbin_turn_pt, 761 svsb->turn_pt); 762 763 for (i = 0; i < svsb->opp_count; i++) { 764 opp = dev_pm_opp_find_freq_exact(svsb->opp_dev, 765 svsb->opp_dfreq[i], true); 766 if (IS_ERR(opp)) { 767 seq_printf(m, "%s: cannot find freq = %u (%ld)\n", 768 svsb->name, svsb->opp_dfreq[i], 769 PTR_ERR(opp)); 770 return PTR_ERR(opp); 771 } 772 773 seq_printf(m, "opp_freq[%02u]: %u, opp_volt[%02u]: %lu, ", 774 i, svsb->opp_dfreq[i], i, 775 dev_pm_opp_get_voltage(opp)); 776 seq_printf(m, "svsb_volt[%02u]: 0x%x, freq_pct[%02u]: %u\n", 777 i, svsb->volt[i], i, svsb->freq_pct[i]); 778 dev_pm_opp_put(opp); 779 } 780 781 return 0; 782 } 783 784 debug_fops_ro(status); 785 786 static int svs_create_debug_cmds(struct svs_platform *svsp) 787 { 788 struct svs_bank *svsb; 789 struct dentry *svs_dir, *svsb_dir, *file_entry; 790 const char *d = "/sys/kernel/debug/svs"; 791 u32 i, idx; 792 793 struct svs_dentry { 794 const char *name; 795 const struct file_operations *fops; 796 }; 797 798 struct svs_dentry svs_entries[] = { 799 svs_dentry_data(dump), 800 }; 801 802 struct svs_dentry svsb_entries[] = { 803 svs_dentry_data(enable), 804 svs_dentry_data(status), 805 }; 806 807 svs_dir = debugfs_create_dir("svs", NULL); 808 if (IS_ERR(svs_dir)) { 809 dev_err(svsp->dev, "cannot create %s: %ld\n", 810 d, PTR_ERR(svs_dir)); 811 return PTR_ERR(svs_dir); 812 } 813 814 for (i = 0; i < ARRAY_SIZE(svs_entries); i++) { 815 file_entry = debugfs_create_file(svs_entries[i].name, 0664, 816 svs_dir, svsp, 817 svs_entries[i].fops); 818 if (IS_ERR(file_entry)) { 819 dev_err(svsp->dev, "cannot create %s/%s: %ld\n", 820 d, svs_entries[i].name, PTR_ERR(file_entry)); 821 return PTR_ERR(file_entry); 822 } 823 } 824 825 for (idx = 0; idx < svsp->bank_max; idx++) { 826 svsb = &svsp->banks[idx]; 827 828 if (svsb->mode_support == SVSB_MODE_ALL_DISABLE) 829 continue; 830 831 svsb_dir = debugfs_create_dir(svsb->name, svs_dir); 832 if (IS_ERR(svsb_dir)) { 833 dev_err(svsp->dev, "cannot create %s/%s: %ld\n", 834 d, svsb->name, PTR_ERR(svsb_dir)); 835 return PTR_ERR(svsb_dir); 836 } 837 838 for (i = 0; i < ARRAY_SIZE(svsb_entries); i++) { 839 file_entry = debugfs_create_file(svsb_entries[i].name, 840 0664, svsb_dir, svsb, 841 svsb_entries[i].fops); 842 if (IS_ERR(file_entry)) { 843 dev_err(svsp->dev, "no %s/%s/%s?: %ld\n", 844 d, svsb->name, svsb_entries[i].name, 845 PTR_ERR(file_entry)); 846 return PTR_ERR(file_entry); 847 } 848 } 849 } 850 851 return 0; 852 } 853 #endif /* CONFIG_DEBUG_FS */ 854 855 static u32 interpolate(u32 f0, u32 f1, u32 v0, u32 v1, u32 fx) 856 { 857 u32 vx; 858 859 if (v0 == v1 || f0 == f1) 860 return v0; 861 862 /* *100 to have decimal fraction factor */ 863 vx = (v0 * 100) - ((((v0 - v1) * 100) / (f0 - f1)) * (f0 - fx)); 864 865 return DIV_ROUND_UP(vx, 100); 866 } 867 868 static void svs_get_bank_volts_v3(struct svs_platform *svsp) 869 { 870 struct svs_bank *svsb = svsp->pbank; 871 u32 i, j, *vop, vop74, vop30, turn_pt = svsb->turn_pt; 872 u32 b_sft, shift_byte = 0, opp_start = 0, opp_stop = 0; 873 u32 middle_index = (svsb->opp_count / 2); 874 875 if (svsb->phase == SVSB_PHASE_MON && 876 svsb->volt_flags & SVSB_MON_VOLT_IGNORE) 877 return; 878 879 vop74 = svs_readl_relaxed(svsp, VOP74); 880 vop30 = svs_readl_relaxed(svsp, VOP30); 881 882 /* Target is to set svsb->volt[] by algorithm */ 883 if (turn_pt < middle_index) { 884 if (svsb->type == SVSB_HIGH) { 885 /* volt[0] ~ volt[turn_pt - 1] */ 886 for (i = 0; i < turn_pt; i++) { 887 b_sft = BITS8 * (shift_byte % REG_BYTES); 888 vop = (shift_byte < REG_BYTES) ? &vop30 : 889 &vop74; 890 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); 891 shift_byte++; 892 } 893 } else if (svsb->type == SVSB_LOW) { 894 /* volt[turn_pt] + volt[j] ~ volt[opp_count - 1] */ 895 j = svsb->opp_count - 7; 896 svsb->volt[turn_pt] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30); 897 shift_byte++; 898 for (i = j; i < svsb->opp_count; i++) { 899 b_sft = BITS8 * (shift_byte % REG_BYTES); 900 vop = (shift_byte < REG_BYTES) ? &vop30 : 901 &vop74; 902 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); 903 shift_byte++; 904 } 905 906 /* volt[turn_pt + 1] ~ volt[j - 1] by interpolate */ 907 for (i = turn_pt + 1; i < j; i++) 908 svsb->volt[i] = interpolate(svsb->freq_pct[turn_pt], 909 svsb->freq_pct[j], 910 svsb->volt[turn_pt], 911 svsb->volt[j], 912 svsb->freq_pct[i]); 913 } 914 } else { 915 if (svsb->type == SVSB_HIGH) { 916 /* volt[0] + volt[j] ~ volt[turn_pt - 1] */ 917 j = turn_pt - 7; 918 svsb->volt[0] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30); 919 shift_byte++; 920 for (i = j; i < turn_pt; i++) { 921 b_sft = BITS8 * (shift_byte % REG_BYTES); 922 vop = (shift_byte < REG_BYTES) ? &vop30 : 923 &vop74; 924 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); 925 shift_byte++; 926 } 927 928 /* volt[1] ~ volt[j - 1] by interpolate */ 929 for (i = 1; i < j; i++) 930 svsb->volt[i] = interpolate(svsb->freq_pct[0], 931 svsb->freq_pct[j], 932 svsb->volt[0], 933 svsb->volt[j], 934 svsb->freq_pct[i]); 935 } else if (svsb->type == SVSB_LOW) { 936 /* volt[turn_pt] ~ volt[opp_count - 1] */ 937 for (i = turn_pt; i < svsb->opp_count; i++) { 938 b_sft = BITS8 * (shift_byte % REG_BYTES); 939 vop = (shift_byte < REG_BYTES) ? &vop30 : 940 &vop74; 941 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); 942 shift_byte++; 943 } 944 } 945 } 946 947 if (svsb->type == SVSB_HIGH) { 948 opp_start = 0; 949 opp_stop = svsb->turn_pt; 950 } else if (svsb->type == SVSB_LOW) { 951 opp_start = svsb->turn_pt; 952 opp_stop = svsb->opp_count; 953 } 954 955 for (i = opp_start; i < opp_stop; i++) 956 if (svsb->volt_flags & SVSB_REMOVE_DVTFIXED_VOLT) 957 svsb->volt[i] -= svsb->dvt_fixed; 958 959 /* For voltage bin support */ 960 if (svsb->opp_dfreq[0] > svsb->freq_base) { 961 svsb->volt[0] = svs_opp_volt_to_bank_volt(svsb->opp_dvolt[0], 962 svsb->volt_step, 963 svsb->volt_base); 964 965 /* Find voltage bin turn point */ 966 for (i = 0; i < svsb->opp_count; i++) { 967 if (svsb->opp_dfreq[i] <= svsb->freq_base) { 968 svsb->vbin_turn_pt = i; 969 break; 970 } 971 } 972 973 /* Override svs bank voltages */ 974 for (i = 1; i < svsb->vbin_turn_pt; i++) 975 svsb->volt[i] = interpolate(svsb->freq_pct[0], 976 svsb->freq_pct[svsb->vbin_turn_pt], 977 svsb->volt[0], 978 svsb->volt[svsb->vbin_turn_pt], 979 svsb->freq_pct[i]); 980 } 981 } 982 983 static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp) 984 { 985 struct svs_bank *svsb = svsp->pbank; 986 u32 i, j, *freq_pct, freq_pct74 = 0, freq_pct30 = 0; 987 u32 b_sft, shift_byte = 0, turn_pt; 988 u32 middle_index = (svsb->opp_count / 2); 989 990 for (i = 0; i < svsb->opp_count; i++) { 991 if (svsb->opp_dfreq[i] <= svsb->turn_freq_base) { 992 svsb->turn_pt = i; 993 break; 994 } 995 } 996 997 turn_pt = svsb->turn_pt; 998 999 /* Target is to fill out freq_pct74 / freq_pct30 by algorithm */ 1000 if (turn_pt < middle_index) { 1001 if (svsb->type == SVSB_HIGH) { 1002 /* 1003 * If we don't handle this situation, 1004 * SVSB_HIGH's FREQPCT74 / FREQPCT30 would keep "0" 1005 * and this leads SVSB_LOW to work abnormally. 1006 */ 1007 if (turn_pt == 0) 1008 freq_pct30 = svsb->freq_pct[0]; 1009 1010 /* freq_pct[0] ~ freq_pct[turn_pt - 1] */ 1011 for (i = 0; i < turn_pt; i++) { 1012 b_sft = BITS8 * (shift_byte % REG_BYTES); 1013 freq_pct = (shift_byte < REG_BYTES) ? 1014 &freq_pct30 : &freq_pct74; 1015 *freq_pct |= (svsb->freq_pct[i] << b_sft); 1016 shift_byte++; 1017 } 1018 } else if (svsb->type == SVSB_LOW) { 1019 /* 1020 * freq_pct[turn_pt] + 1021 * freq_pct[opp_count - 7] ~ freq_pct[opp_count -1] 1022 */ 1023 freq_pct30 = svsb->freq_pct[turn_pt]; 1024 shift_byte++; 1025 j = svsb->opp_count - 7; 1026 for (i = j; i < svsb->opp_count; i++) { 1027 b_sft = BITS8 * (shift_byte % REG_BYTES); 1028 freq_pct = (shift_byte < REG_BYTES) ? 1029 &freq_pct30 : &freq_pct74; 1030 *freq_pct |= (svsb->freq_pct[i] << b_sft); 1031 shift_byte++; 1032 } 1033 } 1034 } else { 1035 if (svsb->type == SVSB_HIGH) { 1036 /* 1037 * freq_pct[0] + 1038 * freq_pct[turn_pt - 7] ~ freq_pct[turn_pt - 1] 1039 */ 1040 freq_pct30 = svsb->freq_pct[0]; 1041 shift_byte++; 1042 j = turn_pt - 7; 1043 for (i = j; i < turn_pt; i++) { 1044 b_sft = BITS8 * (shift_byte % REG_BYTES); 1045 freq_pct = (shift_byte < REG_BYTES) ? 1046 &freq_pct30 : &freq_pct74; 1047 *freq_pct |= (svsb->freq_pct[i] << b_sft); 1048 shift_byte++; 1049 } 1050 } else if (svsb->type == SVSB_LOW) { 1051 /* freq_pct[turn_pt] ~ freq_pct[opp_count - 1] */ 1052 for (i = turn_pt; i < svsb->opp_count; i++) { 1053 b_sft = BITS8 * (shift_byte % REG_BYTES); 1054 freq_pct = (shift_byte < REG_BYTES) ? 1055 &freq_pct30 : &freq_pct74; 1056 *freq_pct |= (svsb->freq_pct[i] << b_sft); 1057 shift_byte++; 1058 } 1059 } 1060 } 1061 1062 svs_writel_relaxed(svsp, freq_pct74, FREQPCT74); 1063 svs_writel_relaxed(svsp, freq_pct30, FREQPCT30); 1064 } 1065 1066 static void svs_get_bank_volts_v2(struct svs_platform *svsp) 1067 { 1068 struct svs_bank *svsb = svsp->pbank; 1069 u32 temp, i; 1070 1071 temp = svs_readl_relaxed(svsp, VOP74); 1072 svsb->volt[14] = FIELD_GET(SVSB_VOPS_FLD_VOP3_7, temp); 1073 svsb->volt[12] = FIELD_GET(SVSB_VOPS_FLD_VOP2_6, temp); 1074 svsb->volt[10] = FIELD_GET(SVSB_VOPS_FLD_VOP1_5, temp); 1075 svsb->volt[8] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, temp); 1076 1077 temp = svs_readl_relaxed(svsp, VOP30); 1078 svsb->volt[6] = FIELD_GET(SVSB_VOPS_FLD_VOP3_7, temp); 1079 svsb->volt[4] = FIELD_GET(SVSB_VOPS_FLD_VOP2_6, temp); 1080 svsb->volt[2] = FIELD_GET(SVSB_VOPS_FLD_VOP1_5, temp); 1081 svsb->volt[0] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, temp); 1082 1083 for (i = 0; i <= 12; i += 2) 1084 svsb->volt[i + 1] = interpolate(svsb->freq_pct[i], 1085 svsb->freq_pct[i + 2], 1086 svsb->volt[i], 1087 svsb->volt[i + 2], 1088 svsb->freq_pct[i + 1]); 1089 1090 svsb->volt[15] = interpolate(svsb->freq_pct[12], 1091 svsb->freq_pct[14], 1092 svsb->volt[12], 1093 svsb->volt[14], 1094 svsb->freq_pct[15]); 1095 1096 for (i = 0; i < svsb->opp_count; i++) 1097 svsb->volt[i] += svsb->volt_od; 1098 1099 /* For voltage bin support */ 1100 if (svsb->opp_dfreq[0] > svsb->freq_base) { 1101 svsb->volt[0] = svs_opp_volt_to_bank_volt(svsb->opp_dvolt[0], 1102 svsb->volt_step, 1103 svsb->volt_base); 1104 1105 /* Find voltage bin turn point */ 1106 for (i = 0; i < svsb->opp_count; i++) { 1107 if (svsb->opp_dfreq[i] <= svsb->freq_base) { 1108 svsb->vbin_turn_pt = i; 1109 break; 1110 } 1111 } 1112 1113 /* Override svs bank voltages */ 1114 for (i = 1; i < svsb->vbin_turn_pt; i++) 1115 svsb->volt[i] = interpolate(svsb->freq_pct[0], 1116 svsb->freq_pct[svsb->vbin_turn_pt], 1117 svsb->volt[0], 1118 svsb->volt[svsb->vbin_turn_pt], 1119 svsb->freq_pct[i]); 1120 } 1121 } 1122 1123 static void svs_set_bank_freq_pct_v2(struct svs_platform *svsp) 1124 { 1125 struct svs_bank *svsb = svsp->pbank; 1126 u32 freqpct74_val, freqpct30_val; 1127 1128 freqpct74_val = FIELD_PREP(SVSB_FREQPCTS_FLD_PCT0_4, svsb->freq_pct[8]) | 1129 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT1_5, svsb->freq_pct[10]) | 1130 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT2_6, svsb->freq_pct[12]) | 1131 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT3_7, svsb->freq_pct[14]); 1132 1133 freqpct30_val = FIELD_PREP(SVSB_FREQPCTS_FLD_PCT0_4, svsb->freq_pct[0]) | 1134 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT1_5, svsb->freq_pct[2]) | 1135 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT2_6, svsb->freq_pct[4]) | 1136 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT3_7, svsb->freq_pct[6]); 1137 1138 svs_writel_relaxed(svsp, freqpct74_val, FREQPCT74); 1139 svs_writel_relaxed(svsp, freqpct30_val, FREQPCT30); 1140 } 1141 1142 static void svs_set_bank_phase(struct svs_platform *svsp, 1143 enum svsb_phase target_phase) 1144 { 1145 struct svs_bank *svsb = svsp->pbank; 1146 u32 des_char, temp_char, det_char, limit_vals, init2vals, ts_calcs; 1147 1148 svs_switch_bank(svsp); 1149 1150 des_char = FIELD_PREP(SVSB_DESCHAR_FLD_BDES, svsb->bdes) | 1151 FIELD_PREP(SVSB_DESCHAR_FLD_MDES, svsb->mdes); 1152 svs_writel_relaxed(svsp, des_char, DESCHAR); 1153 1154 temp_char = FIELD_PREP(SVSB_TEMPCHAR_FLD_VCO, svsb->vco) | 1155 FIELD_PREP(SVSB_TEMPCHAR_FLD_MTDES, svsb->mtdes) | 1156 FIELD_PREP(SVSB_TEMPCHAR_FLD_DVT_FIXED, svsb->dvt_fixed); 1157 svs_writel_relaxed(svsp, temp_char, TEMPCHAR); 1158 1159 det_char = FIELD_PREP(SVSB_DETCHAR_FLD_DCBDET, svsb->dcbdet) | 1160 FIELD_PREP(SVSB_DETCHAR_FLD_DCMDET, svsb->dcmdet); 1161 svs_writel_relaxed(svsp, det_char, DETCHAR); 1162 1163 svs_writel_relaxed(svsp, svsb->dc_config, DCCONFIG); 1164 svs_writel_relaxed(svsp, svsb->age_config, AGECONFIG); 1165 svs_writel_relaxed(svsp, SVSB_RUNCONFIG_DEFAULT, RUNCONFIG); 1166 1167 svsb->set_freq_pct(svsp); 1168 1169 limit_vals = FIELD_PREP(SVSB_LIMITVALS_FLD_DTLO, SVSB_VAL_DTLO) | 1170 FIELD_PREP(SVSB_LIMITVALS_FLD_DTHI, SVSB_VAL_DTHI) | 1171 FIELD_PREP(SVSB_LIMITVALS_FLD_VMIN, svsb->vmin) | 1172 FIELD_PREP(SVSB_LIMITVALS_FLD_VMAX, svsb->vmax); 1173 svs_writel_relaxed(svsp, limit_vals, LIMITVALS); 1174 1175 svs_writel_relaxed(svsp, SVSB_DET_WINDOW, DETWINDOW); 1176 svs_writel_relaxed(svsp, SVSB_DET_MAX, CONFIG); 1177 svs_writel_relaxed(svsp, svsb->chk_shift, CHKSHIFT); 1178 svs_writel_relaxed(svsp, svsb->ctl0, CTL0); 1179 svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS); 1180 1181 switch (target_phase) { 1182 case SVSB_PHASE_INIT01: 1183 svs_writel_relaxed(svsp, svsb->vboot, VBOOT); 1184 svs_writel_relaxed(svsp, SVSB_INTEN_INIT0x, INTEN); 1185 svs_writel_relaxed(svsp, SVSB_PTPEN_INIT01, SVSEN); 1186 break; 1187 case SVSB_PHASE_INIT02: 1188 init2vals = FIELD_PREP(SVSB_INIT2VALS_FLD_AGEVOFFSETIN, svsb->age_voffset_in) | 1189 FIELD_PREP(SVSB_INIT2VALS_FLD_DCVOFFSETIN, svsb->dc_voffset_in); 1190 svs_writel_relaxed(svsp, SVSB_INTEN_INIT0x, INTEN); 1191 svs_writel_relaxed(svsp, init2vals, INIT2VALS); 1192 svs_writel_relaxed(svsp, SVSB_PTPEN_INIT02, SVSEN); 1193 break; 1194 case SVSB_PHASE_MON: 1195 ts_calcs = FIELD_PREP(SVSB_TSCALCS_FLD_BTS, svsb->bts) | 1196 FIELD_PREP(SVSB_TSCALCS_FLD_MTS, svsb->mts); 1197 svs_writel_relaxed(svsp, ts_calcs, TSCALCS); 1198 svs_writel_relaxed(svsp, SVSB_INTEN_MONVOPEN, INTEN); 1199 svs_writel_relaxed(svsp, SVSB_PTPEN_MON, SVSEN); 1200 break; 1201 default: 1202 dev_err(svsb->dev, "requested unknown target phase: %u\n", 1203 target_phase); 1204 break; 1205 } 1206 } 1207 1208 static inline void svs_save_bank_register_data(struct svs_platform *svsp, 1209 enum svsb_phase phase) 1210 { 1211 struct svs_bank *svsb = svsp->pbank; 1212 enum svs_reg_index rg_i; 1213 1214 for (rg_i = DESCHAR; rg_i < SVS_REG_MAX; rg_i++) 1215 svsb->reg_data[phase][rg_i] = svs_readl_relaxed(svsp, rg_i); 1216 } 1217 1218 static inline void svs_error_isr_handler(struct svs_platform *svsp) 1219 { 1220 struct svs_bank *svsb = svsp->pbank; 1221 1222 dev_err(svsb->dev, "%s: CORESEL = 0x%08x\n", 1223 __func__, svs_readl_relaxed(svsp, CORESEL)); 1224 dev_err(svsb->dev, "SVSEN = 0x%08x, INTSTS = 0x%08x\n", 1225 svs_readl_relaxed(svsp, SVSEN), 1226 svs_readl_relaxed(svsp, INTSTS)); 1227 dev_err(svsb->dev, "SMSTATE0 = 0x%08x, SMSTATE1 = 0x%08x\n", 1228 svs_readl_relaxed(svsp, SMSTATE0), 1229 svs_readl_relaxed(svsp, SMSTATE1)); 1230 dev_err(svsb->dev, "TEMP = 0x%08x\n", svs_readl_relaxed(svsp, TEMP)); 1231 1232 svs_save_bank_register_data(svsp, SVSB_PHASE_ERROR); 1233 1234 svsb->phase = SVSB_PHASE_ERROR; 1235 svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN); 1236 svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS); 1237 } 1238 1239 static inline void svs_init01_isr_handler(struct svs_platform *svsp) 1240 { 1241 struct svs_bank *svsb = svsp->pbank; 1242 1243 dev_info(svsb->dev, "%s: VDN74~30:0x%08x~0x%08x, DC:0x%08x\n", 1244 __func__, svs_readl_relaxed(svsp, VDESIGN74), 1245 svs_readl_relaxed(svsp, VDESIGN30), 1246 svs_readl_relaxed(svsp, DCVALUES)); 1247 1248 svs_save_bank_register_data(svsp, SVSB_PHASE_INIT01); 1249 1250 svsb->phase = SVSB_PHASE_INIT01; 1251 svsb->dc_voffset_in = ~(svs_readl_relaxed(svsp, DCVALUES) & 1252 GENMASK(15, 0)) + 1; 1253 if (svsb->volt_flags & SVSB_INIT01_VOLT_IGNORE || 1254 (svsb->dc_voffset_in & SVSB_DC_SIGNED_BIT && 1255 svsb->volt_flags & SVSB_INIT01_VOLT_INC_ONLY)) 1256 svsb->dc_voffset_in = 0; 1257 1258 svsb->age_voffset_in = svs_readl_relaxed(svsp, AGEVALUES) & 1259 GENMASK(15, 0); 1260 1261 svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN); 1262 svs_writel_relaxed(svsp, SVSB_INTSTS_F0_COMPLETE, INTSTS); 1263 svsb->core_sel &= ~SVSB_DET_CLK_EN; 1264 } 1265 1266 static inline void svs_init02_isr_handler(struct svs_platform *svsp) 1267 { 1268 struct svs_bank *svsb = svsp->pbank; 1269 1270 dev_info(svsb->dev, "%s: VOP74~30:0x%08x~0x%08x, DC:0x%08x\n", 1271 __func__, svs_readl_relaxed(svsp, VOP74), 1272 svs_readl_relaxed(svsp, VOP30), 1273 svs_readl_relaxed(svsp, DCVALUES)); 1274 1275 svs_save_bank_register_data(svsp, SVSB_PHASE_INIT02); 1276 1277 svsb->phase = SVSB_PHASE_INIT02; 1278 svsb->get_volts(svsp); 1279 1280 svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN); 1281 svs_writel_relaxed(svsp, SVSB_INTSTS_F0_COMPLETE, INTSTS); 1282 } 1283 1284 static inline void svs_mon_mode_isr_handler(struct svs_platform *svsp) 1285 { 1286 struct svs_bank *svsb = svsp->pbank; 1287 1288 svs_save_bank_register_data(svsp, SVSB_PHASE_MON); 1289 1290 svsb->phase = SVSB_PHASE_MON; 1291 svsb->get_volts(svsp); 1292 1293 svsb->temp = svs_readl_relaxed(svsp, TEMP) & GENMASK(7, 0); 1294 svs_writel_relaxed(svsp, SVSB_INTSTS_FLD_MONVOP, INTSTS); 1295 } 1296 1297 static irqreturn_t svs_isr(int irq, void *data) 1298 { 1299 struct svs_platform *svsp = data; 1300 struct svs_bank *svsb = NULL; 1301 unsigned long flags; 1302 u32 idx, int_sts, svs_en; 1303 1304 for (idx = 0; idx < svsp->bank_max; idx++) { 1305 svsb = &svsp->banks[idx]; 1306 WARN(!svsb, "%s: svsb(%s) is null", __func__, svsb->name); 1307 1308 spin_lock_irqsave(&svs_lock, flags); 1309 svsp->pbank = svsb; 1310 1311 /* Find out which svs bank fires interrupt */ 1312 if (svsb->int_st & svs_readl_relaxed(svsp, INTST)) { 1313 spin_unlock_irqrestore(&svs_lock, flags); 1314 continue; 1315 } 1316 1317 svs_switch_bank(svsp); 1318 int_sts = svs_readl_relaxed(svsp, INTSTS); 1319 svs_en = svs_readl_relaxed(svsp, SVSEN); 1320 1321 if (int_sts == SVSB_INTSTS_F0_COMPLETE && 1322 svs_en == SVSB_PTPEN_INIT01) 1323 svs_init01_isr_handler(svsp); 1324 else if (int_sts == SVSB_INTSTS_F0_COMPLETE && 1325 svs_en == SVSB_PTPEN_INIT02) 1326 svs_init02_isr_handler(svsp); 1327 else if (int_sts & SVSB_INTSTS_FLD_MONVOP) 1328 svs_mon_mode_isr_handler(svsp); 1329 else 1330 svs_error_isr_handler(svsp); 1331 1332 spin_unlock_irqrestore(&svs_lock, flags); 1333 break; 1334 } 1335 1336 svs_adjust_pm_opp_volts(svsb); 1337 1338 if (svsb->phase == SVSB_PHASE_INIT01 || 1339 svsb->phase == SVSB_PHASE_INIT02) 1340 complete(&svsb->init_completion); 1341 1342 return IRQ_HANDLED; 1343 } 1344 1345 static int svs_init01(struct svs_platform *svsp) 1346 { 1347 struct svs_bank *svsb; 1348 unsigned long flags, time_left; 1349 bool search_done; 1350 int ret = 0, r; 1351 u32 opp_freq, opp_vboot, buck_volt, idx, i; 1352 1353 /* Keep CPUs' core power on for svs_init01 initialization */ 1354 cpuidle_pause_and_lock(); 1355 1356 /* Svs bank init01 preparation - power enable */ 1357 for (idx = 0; idx < svsp->bank_max; idx++) { 1358 svsb = &svsp->banks[idx]; 1359 1360 if (!(svsb->mode_support & SVSB_MODE_INIT01)) 1361 continue; 1362 1363 ret = regulator_enable(svsb->buck); 1364 if (ret) { 1365 dev_err(svsb->dev, "%s enable fail: %d\n", 1366 svsb->buck_name, ret); 1367 goto svs_init01_resume_cpuidle; 1368 } 1369 1370 /* Some buck doesn't support mode change. Show fail msg only */ 1371 ret = regulator_set_mode(svsb->buck, REGULATOR_MODE_FAST); 1372 if (ret) 1373 dev_notice(svsb->dev, "set fast mode fail: %d\n", ret); 1374 1375 if (svsb->volt_flags & SVSB_INIT01_PD_REQ) { 1376 if (!pm_runtime_enabled(svsb->opp_dev)) { 1377 pm_runtime_enable(svsb->opp_dev); 1378 svsb->pm_runtime_enabled_count++; 1379 } 1380 1381 ret = pm_runtime_resume_and_get(svsb->opp_dev); 1382 if (ret < 0) { 1383 dev_err(svsb->dev, "mtcmos on fail: %d\n", ret); 1384 goto svs_init01_resume_cpuidle; 1385 } 1386 } 1387 } 1388 1389 /* 1390 * Svs bank init01 preparation - vboot voltage adjustment 1391 * Sometimes two svs banks use the same buck. Therefore, 1392 * we have to set each svs bank to target voltage(vboot) first. 1393 */ 1394 for (idx = 0; idx < svsp->bank_max; idx++) { 1395 svsb = &svsp->banks[idx]; 1396 1397 if (!(svsb->mode_support & SVSB_MODE_INIT01)) 1398 continue; 1399 1400 /* 1401 * Find the fastest freq that can be run at vboot and 1402 * fix to that freq until svs_init01 is done. 1403 */ 1404 search_done = false; 1405 opp_vboot = svs_bank_volt_to_opp_volt(svsb->vboot, 1406 svsb->volt_step, 1407 svsb->volt_base); 1408 1409 for (i = 0; i < svsb->opp_count; i++) { 1410 opp_freq = svsb->opp_dfreq[i]; 1411 if (!search_done && svsb->opp_dvolt[i] <= opp_vboot) { 1412 ret = dev_pm_opp_adjust_voltage(svsb->opp_dev, 1413 opp_freq, 1414 opp_vboot, 1415 opp_vboot, 1416 opp_vboot); 1417 if (ret) { 1418 dev_err(svsb->dev, 1419 "set opp %uuV vboot fail: %d\n", 1420 opp_vboot, ret); 1421 goto svs_init01_finish; 1422 } 1423 1424 search_done = true; 1425 } else { 1426 ret = dev_pm_opp_disable(svsb->opp_dev, 1427 svsb->opp_dfreq[i]); 1428 if (ret) { 1429 dev_err(svsb->dev, 1430 "opp %uHz disable fail: %d\n", 1431 svsb->opp_dfreq[i], ret); 1432 goto svs_init01_finish; 1433 } 1434 } 1435 } 1436 } 1437 1438 /* Svs bank init01 begins */ 1439 for (idx = 0; idx < svsp->bank_max; idx++) { 1440 svsb = &svsp->banks[idx]; 1441 1442 if (!(svsb->mode_support & SVSB_MODE_INIT01)) 1443 continue; 1444 1445 opp_vboot = svs_bank_volt_to_opp_volt(svsb->vboot, 1446 svsb->volt_step, 1447 svsb->volt_base); 1448 1449 buck_volt = regulator_get_voltage(svsb->buck); 1450 if (buck_volt != opp_vboot) { 1451 dev_err(svsb->dev, 1452 "buck voltage: %uuV, expected vboot: %uuV\n", 1453 buck_volt, opp_vboot); 1454 ret = -EPERM; 1455 goto svs_init01_finish; 1456 } 1457 1458 spin_lock_irqsave(&svs_lock, flags); 1459 svsp->pbank = svsb; 1460 svs_set_bank_phase(svsp, SVSB_PHASE_INIT01); 1461 spin_unlock_irqrestore(&svs_lock, flags); 1462 1463 time_left = wait_for_completion_timeout(&svsb->init_completion, 1464 msecs_to_jiffies(5000)); 1465 if (!time_left) { 1466 dev_err(svsb->dev, "init01 completion timeout\n"); 1467 ret = -EBUSY; 1468 goto svs_init01_finish; 1469 } 1470 } 1471 1472 svs_init01_finish: 1473 for (idx = 0; idx < svsp->bank_max; idx++) { 1474 svsb = &svsp->banks[idx]; 1475 1476 if (!(svsb->mode_support & SVSB_MODE_INIT01)) 1477 continue; 1478 1479 for (i = 0; i < svsb->opp_count; i++) { 1480 r = dev_pm_opp_enable(svsb->opp_dev, 1481 svsb->opp_dfreq[i]); 1482 if (r) 1483 dev_err(svsb->dev, "opp %uHz enable fail: %d\n", 1484 svsb->opp_dfreq[i], r); 1485 } 1486 1487 if (svsb->volt_flags & SVSB_INIT01_PD_REQ) { 1488 r = pm_runtime_put_sync(svsb->opp_dev); 1489 if (r) 1490 dev_err(svsb->dev, "mtcmos off fail: %d\n", r); 1491 1492 if (svsb->pm_runtime_enabled_count > 0) { 1493 pm_runtime_disable(svsb->opp_dev); 1494 svsb->pm_runtime_enabled_count--; 1495 } 1496 } 1497 1498 r = regulator_set_mode(svsb->buck, REGULATOR_MODE_NORMAL); 1499 if (r) 1500 dev_notice(svsb->dev, "set normal mode fail: %d\n", r); 1501 1502 r = regulator_disable(svsb->buck); 1503 if (r) 1504 dev_err(svsb->dev, "%s disable fail: %d\n", 1505 svsb->buck_name, r); 1506 } 1507 1508 svs_init01_resume_cpuidle: 1509 cpuidle_resume_and_unlock(); 1510 1511 return ret; 1512 } 1513 1514 static int svs_init02(struct svs_platform *svsp) 1515 { 1516 struct svs_bank *svsb; 1517 unsigned long flags, time_left; 1518 int ret; 1519 u32 idx; 1520 1521 for (idx = 0; idx < svsp->bank_max; idx++) { 1522 svsb = &svsp->banks[idx]; 1523 1524 if (!(svsb->mode_support & SVSB_MODE_INIT02)) 1525 continue; 1526 1527 reinit_completion(&svsb->init_completion); 1528 spin_lock_irqsave(&svs_lock, flags); 1529 svsp->pbank = svsb; 1530 svs_set_bank_phase(svsp, SVSB_PHASE_INIT02); 1531 spin_unlock_irqrestore(&svs_lock, flags); 1532 1533 time_left = wait_for_completion_timeout(&svsb->init_completion, 1534 msecs_to_jiffies(5000)); 1535 if (!time_left) { 1536 dev_err(svsb->dev, "init02 completion timeout\n"); 1537 ret = -EBUSY; 1538 goto out_of_init02; 1539 } 1540 } 1541 1542 /* 1543 * 2-line high/low bank update its corresponding opp voltages only. 1544 * Therefore, we sync voltages from opp for high/low bank voltages 1545 * consistency. 1546 */ 1547 for (idx = 0; idx < svsp->bank_max; idx++) { 1548 svsb = &svsp->banks[idx]; 1549 1550 if (!(svsb->mode_support & SVSB_MODE_INIT02)) 1551 continue; 1552 1553 if (svsb->type == SVSB_HIGH || svsb->type == SVSB_LOW) { 1554 if (svs_sync_bank_volts_from_opp(svsb)) { 1555 dev_err(svsb->dev, "sync volt fail\n"); 1556 ret = -EPERM; 1557 goto out_of_init02; 1558 } 1559 } 1560 } 1561 1562 return 0; 1563 1564 out_of_init02: 1565 for (idx = 0; idx < svsp->bank_max; idx++) { 1566 svsb = &svsp->banks[idx]; 1567 svs_bank_disable_and_restore_default_volts(svsp, svsb); 1568 } 1569 1570 return ret; 1571 } 1572 1573 static void svs_mon_mode(struct svs_platform *svsp) 1574 { 1575 struct svs_bank *svsb; 1576 unsigned long flags; 1577 u32 idx; 1578 1579 for (idx = 0; idx < svsp->bank_max; idx++) { 1580 svsb = &svsp->banks[idx]; 1581 1582 if (!(svsb->mode_support & SVSB_MODE_MON)) 1583 continue; 1584 1585 spin_lock_irqsave(&svs_lock, flags); 1586 svsp->pbank = svsb; 1587 svs_set_bank_phase(svsp, SVSB_PHASE_MON); 1588 spin_unlock_irqrestore(&svs_lock, flags); 1589 } 1590 } 1591 1592 static int svs_start(struct svs_platform *svsp) 1593 { 1594 int ret; 1595 1596 ret = svs_init01(svsp); 1597 if (ret) 1598 return ret; 1599 1600 ret = svs_init02(svsp); 1601 if (ret) 1602 return ret; 1603 1604 svs_mon_mode(svsp); 1605 1606 return 0; 1607 } 1608 1609 static int svs_suspend(struct device *dev) 1610 { 1611 struct svs_platform *svsp = dev_get_drvdata(dev); 1612 struct svs_bank *svsb; 1613 int ret; 1614 u32 idx; 1615 1616 for (idx = 0; idx < svsp->bank_max; idx++) { 1617 svsb = &svsp->banks[idx]; 1618 svs_bank_disable_and_restore_default_volts(svsp, svsb); 1619 } 1620 1621 ret = reset_control_assert(svsp->rst); 1622 if (ret) { 1623 dev_err(svsp->dev, "cannot assert reset %d\n", ret); 1624 return ret; 1625 } 1626 1627 clk_disable_unprepare(svsp->main_clk); 1628 1629 return 0; 1630 } 1631 1632 static int svs_resume(struct device *dev) 1633 { 1634 struct svs_platform *svsp = dev_get_drvdata(dev); 1635 int ret; 1636 1637 ret = clk_prepare_enable(svsp->main_clk); 1638 if (ret) { 1639 dev_err(svsp->dev, "cannot enable main_clk, disable svs\n"); 1640 return ret; 1641 } 1642 1643 ret = reset_control_deassert(svsp->rst); 1644 if (ret) { 1645 dev_err(svsp->dev, "cannot deassert reset %d\n", ret); 1646 goto out_of_resume; 1647 } 1648 1649 ret = svs_init02(svsp); 1650 if (ret) 1651 goto svs_resume_reset_assert; 1652 1653 svs_mon_mode(svsp); 1654 1655 return 0; 1656 1657 svs_resume_reset_assert: 1658 dev_err(svsp->dev, "assert reset: %d\n", 1659 reset_control_assert(svsp->rst)); 1660 1661 out_of_resume: 1662 clk_disable_unprepare(svsp->main_clk); 1663 return ret; 1664 } 1665 1666 static int svs_bank_resource_setup(struct svs_platform *svsp) 1667 { 1668 struct svs_bank *svsb; 1669 struct dev_pm_opp *opp; 1670 unsigned long freq; 1671 int count, ret; 1672 u32 idx, i; 1673 1674 dev_set_drvdata(svsp->dev, svsp); 1675 1676 for (idx = 0; idx < svsp->bank_max; idx++) { 1677 svsb = &svsp->banks[idx]; 1678 1679 switch (svsb->sw_id) { 1680 case SVSB_CPU_LITTLE: 1681 svsb->name = "SVSB_CPU_LITTLE"; 1682 break; 1683 case SVSB_CPU_BIG: 1684 svsb->name = "SVSB_CPU_BIG"; 1685 break; 1686 case SVSB_CCI: 1687 svsb->name = "SVSB_CCI"; 1688 break; 1689 case SVSB_GPU: 1690 if (svsb->type == SVSB_HIGH) 1691 svsb->name = "SVSB_GPU_HIGH"; 1692 else if (svsb->type == SVSB_LOW) 1693 svsb->name = "SVSB_GPU_LOW"; 1694 else 1695 svsb->name = "SVSB_GPU"; 1696 break; 1697 default: 1698 dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); 1699 return -EINVAL; 1700 } 1701 1702 svsb->dev = devm_kzalloc(svsp->dev, sizeof(*svsb->dev), 1703 GFP_KERNEL); 1704 if (!svsb->dev) 1705 return -ENOMEM; 1706 1707 ret = dev_set_name(svsb->dev, "%s", svsb->name); 1708 if (ret) 1709 return ret; 1710 1711 dev_set_drvdata(svsb->dev, svsp); 1712 1713 ret = devm_pm_opp_of_add_table(svsb->opp_dev); 1714 if (ret) { 1715 dev_err(svsb->dev, "add opp table fail: %d\n", ret); 1716 return ret; 1717 } 1718 1719 mutex_init(&svsb->lock); 1720 init_completion(&svsb->init_completion); 1721 1722 if (svsb->mode_support & SVSB_MODE_INIT01) { 1723 svsb->buck = devm_regulator_get_optional(svsb->opp_dev, 1724 svsb->buck_name); 1725 if (IS_ERR(svsb->buck)) { 1726 dev_err(svsb->dev, "cannot get \"%s-supply\"\n", 1727 svsb->buck_name); 1728 return PTR_ERR(svsb->buck); 1729 } 1730 } 1731 1732 if (!IS_ERR_OR_NULL(svsb->tzone_name)) { 1733 svsb->tzd = thermal_zone_get_zone_by_name(svsb->tzone_name); 1734 if (IS_ERR(svsb->tzd)) { 1735 dev_err(svsb->dev, "cannot get \"%s\" thermal zone\n", 1736 svsb->tzone_name); 1737 return PTR_ERR(svsb->tzd); 1738 } 1739 } 1740 1741 count = dev_pm_opp_get_opp_count(svsb->opp_dev); 1742 if (svsb->opp_count != count) { 1743 dev_err(svsb->dev, 1744 "opp_count not \"%u\" but get \"%d\"?\n", 1745 svsb->opp_count, count); 1746 return count; 1747 } 1748 1749 for (i = 0, freq = U32_MAX; i < svsb->opp_count; i++, freq--) { 1750 opp = dev_pm_opp_find_freq_floor(svsb->opp_dev, &freq); 1751 if (IS_ERR(opp)) { 1752 dev_err(svsb->dev, "cannot find freq = %ld\n", 1753 PTR_ERR(opp)); 1754 return PTR_ERR(opp); 1755 } 1756 1757 svsb->opp_dfreq[i] = freq; 1758 svsb->opp_dvolt[i] = dev_pm_opp_get_voltage(opp); 1759 svsb->freq_pct[i] = percent(svsb->opp_dfreq[i], 1760 svsb->freq_base); 1761 dev_pm_opp_put(opp); 1762 } 1763 } 1764 1765 return 0; 1766 } 1767 1768 static int svs_get_efuse_data(struct svs_platform *svsp, 1769 const char *nvmem_cell_name, 1770 u32 **svsp_efuse, size_t *svsp_efuse_max) 1771 { 1772 struct nvmem_cell *cell; 1773 1774 cell = nvmem_cell_get(svsp->dev, nvmem_cell_name); 1775 if (IS_ERR(cell)) { 1776 dev_err(svsp->dev, "no \"%s\"? %ld\n", 1777 nvmem_cell_name, PTR_ERR(cell)); 1778 return PTR_ERR(cell); 1779 } 1780 1781 *svsp_efuse = nvmem_cell_read(cell, svsp_efuse_max); 1782 if (IS_ERR(*svsp_efuse)) { 1783 dev_err(svsp->dev, "cannot read \"%s\" efuse: %ld\n", 1784 nvmem_cell_name, PTR_ERR(*svsp_efuse)); 1785 nvmem_cell_put(cell); 1786 return PTR_ERR(*svsp_efuse); 1787 } 1788 1789 *svsp_efuse_max /= sizeof(u32); 1790 nvmem_cell_put(cell); 1791 1792 return 0; 1793 } 1794 1795 static bool svs_mt8192_efuse_parsing(struct svs_platform *svsp) 1796 { 1797 struct svs_bank *svsb; 1798 u32 idx, i, vmin, golden_temp; 1799 int ret; 1800 1801 for (i = 0; i < svsp->efuse_max; i++) 1802 if (svsp->efuse[i]) 1803 dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", 1804 i, svsp->efuse[i]); 1805 1806 if (!svsp->efuse[9]) { 1807 dev_notice(svsp->dev, "svs_efuse[9] = 0x0?\n"); 1808 return false; 1809 } 1810 1811 /* Svs efuse parsing */ 1812 vmin = (svsp->efuse[19] >> 4) & GENMASK(1, 0); 1813 1814 for (idx = 0; idx < svsp->bank_max; idx++) { 1815 svsb = &svsp->banks[idx]; 1816 1817 if (vmin == 0x1) 1818 svsb->vmin = 0x1e; 1819 1820 if (svsb->type == SVSB_LOW) { 1821 svsb->mtdes = svsp->efuse[10] & GENMASK(7, 0); 1822 svsb->bdes = (svsp->efuse[10] >> 16) & GENMASK(7, 0); 1823 svsb->mdes = (svsp->efuse[10] >> 24) & GENMASK(7, 0); 1824 svsb->dcbdet = (svsp->efuse[17]) & GENMASK(7, 0); 1825 svsb->dcmdet = (svsp->efuse[17] >> 8) & GENMASK(7, 0); 1826 } else if (svsb->type == SVSB_HIGH) { 1827 svsb->mtdes = svsp->efuse[9] & GENMASK(7, 0); 1828 svsb->bdes = (svsp->efuse[9] >> 16) & GENMASK(7, 0); 1829 svsb->mdes = (svsp->efuse[9] >> 24) & GENMASK(7, 0); 1830 svsb->dcbdet = (svsp->efuse[17] >> 16) & GENMASK(7, 0); 1831 svsb->dcmdet = (svsp->efuse[17] >> 24) & GENMASK(7, 0); 1832 } 1833 1834 svsb->vmax += svsb->dvt_fixed; 1835 } 1836 1837 ret = svs_get_efuse_data(svsp, "t-calibration-data", 1838 &svsp->tefuse, &svsp->tefuse_max); 1839 if (ret) 1840 return false; 1841 1842 for (i = 0; i < svsp->tefuse_max; i++) 1843 if (svsp->tefuse[i] != 0) 1844 break; 1845 1846 if (i == svsp->tefuse_max) 1847 golden_temp = 50; /* All thermal efuse data are 0 */ 1848 else 1849 golden_temp = (svsp->tefuse[0] >> 24) & GENMASK(7, 0); 1850 1851 for (idx = 0; idx < svsp->bank_max; idx++) { 1852 svsb = &svsp->banks[idx]; 1853 svsb->mts = 500; 1854 svsb->bts = (((500 * golden_temp + 250460) / 1000) - 25) * 4; 1855 } 1856 1857 return true; 1858 } 1859 1860 static bool svs_mt8188_efuse_parsing(struct svs_platform *svsp) 1861 { 1862 struct svs_bank *svsb; 1863 u32 idx, i, golden_temp; 1864 int ret; 1865 1866 for (i = 0; i < svsp->efuse_max; i++) 1867 if (svsp->efuse[i]) 1868 dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", 1869 i, svsp->efuse[i]); 1870 1871 if (!svsp->efuse[5]) { 1872 dev_notice(svsp->dev, "svs_efuse[5] = 0x0?\n"); 1873 return false; 1874 } 1875 1876 /* Svs efuse parsing */ 1877 for (idx = 0; idx < svsp->bank_max; idx++) { 1878 svsb = &svsp->banks[idx]; 1879 1880 if (svsb->type == SVSB_LOW) { 1881 svsb->mtdes = svsp->efuse[5] & GENMASK(7, 0); 1882 svsb->bdes = (svsp->efuse[5] >> 16) & GENMASK(7, 0); 1883 svsb->mdes = (svsp->efuse[5] >> 24) & GENMASK(7, 0); 1884 svsb->dcbdet = (svsp->efuse[15] >> 16) & GENMASK(7, 0); 1885 svsb->dcmdet = (svsp->efuse[15] >> 24) & GENMASK(7, 0); 1886 } else if (svsb->type == SVSB_HIGH) { 1887 svsb->mtdes = svsp->efuse[4] & GENMASK(7, 0); 1888 svsb->bdes = (svsp->efuse[4] >> 16) & GENMASK(7, 0); 1889 svsb->mdes = (svsp->efuse[4] >> 24) & GENMASK(7, 0); 1890 svsb->dcbdet = svsp->efuse[14] & GENMASK(7, 0); 1891 svsb->dcmdet = (svsp->efuse[14] >> 8) & GENMASK(7, 0); 1892 } 1893 1894 svsb->vmax += svsb->dvt_fixed; 1895 } 1896 1897 ret = svs_get_efuse_data(svsp, "t-calibration-data", 1898 &svsp->tefuse, &svsp->tefuse_max); 1899 if (ret) 1900 return false; 1901 1902 for (i = 0; i < svsp->tefuse_max; i++) 1903 if (svsp->tefuse[i] != 0) 1904 break; 1905 1906 if (i == svsp->tefuse_max) 1907 golden_temp = 50; /* All thermal efuse data are 0 */ 1908 else 1909 golden_temp = (svsp->tefuse[0] >> 24) & GENMASK(7, 0); 1910 1911 for (idx = 0; idx < svsp->bank_max; idx++) { 1912 svsb = &svsp->banks[idx]; 1913 svsb->mts = 500; 1914 svsb->bts = (((500 * golden_temp + 250460) / 1000) - 25) * 4; 1915 } 1916 1917 return true; 1918 } 1919 1920 static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp) 1921 { 1922 struct svs_bank *svsb; 1923 int format[6], x_roomt[6], o_vtsmcu[5], o_vtsabb, tb_roomt = 0; 1924 int adc_ge_t, adc_oe_t, ge, oe, gain, degc_cali, adc_cali_en_t; 1925 int o_slope, o_slope_sign, ts_id; 1926 u32 idx, i, ft_pgm, mts, temp0, temp1, temp2; 1927 int ret; 1928 1929 for (i = 0; i < svsp->efuse_max; i++) 1930 if (svsp->efuse[i]) 1931 dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", 1932 i, svsp->efuse[i]); 1933 1934 if (!svsp->efuse[2]) { 1935 dev_notice(svsp->dev, "svs_efuse[2] = 0x0?\n"); 1936 return false; 1937 } 1938 1939 /* Svs efuse parsing */ 1940 ft_pgm = (svsp->efuse[0] >> 4) & GENMASK(3, 0); 1941 1942 for (idx = 0; idx < svsp->bank_max; idx++) { 1943 svsb = &svsp->banks[idx]; 1944 1945 if (ft_pgm <= 1) 1946 svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE; 1947 1948 switch (svsb->sw_id) { 1949 case SVSB_CPU_LITTLE: 1950 svsb->bdes = svsp->efuse[16] & GENMASK(7, 0); 1951 svsb->mdes = (svsp->efuse[16] >> 8) & GENMASK(7, 0); 1952 svsb->dcbdet = (svsp->efuse[16] >> 16) & GENMASK(7, 0); 1953 svsb->dcmdet = (svsp->efuse[16] >> 24) & GENMASK(7, 0); 1954 svsb->mtdes = (svsp->efuse[17] >> 16) & GENMASK(7, 0); 1955 1956 if (ft_pgm <= 3) 1957 svsb->volt_od += 10; 1958 else 1959 svsb->volt_od += 2; 1960 break; 1961 case SVSB_CPU_BIG: 1962 svsb->bdes = svsp->efuse[18] & GENMASK(7, 0); 1963 svsb->mdes = (svsp->efuse[18] >> 8) & GENMASK(7, 0); 1964 svsb->dcbdet = (svsp->efuse[18] >> 16) & GENMASK(7, 0); 1965 svsb->dcmdet = (svsp->efuse[18] >> 24) & GENMASK(7, 0); 1966 svsb->mtdes = svsp->efuse[17] & GENMASK(7, 0); 1967 1968 if (ft_pgm <= 3) 1969 svsb->volt_od += 15; 1970 else 1971 svsb->volt_od += 12; 1972 break; 1973 case SVSB_CCI: 1974 svsb->bdes = svsp->efuse[4] & GENMASK(7, 0); 1975 svsb->mdes = (svsp->efuse[4] >> 8) & GENMASK(7, 0); 1976 svsb->dcbdet = (svsp->efuse[4] >> 16) & GENMASK(7, 0); 1977 svsb->dcmdet = (svsp->efuse[4] >> 24) & GENMASK(7, 0); 1978 svsb->mtdes = (svsp->efuse[5] >> 16) & GENMASK(7, 0); 1979 1980 if (ft_pgm <= 3) 1981 svsb->volt_od += 10; 1982 else 1983 svsb->volt_od += 2; 1984 break; 1985 case SVSB_GPU: 1986 svsb->bdes = svsp->efuse[6] & GENMASK(7, 0); 1987 svsb->mdes = (svsp->efuse[6] >> 8) & GENMASK(7, 0); 1988 svsb->dcbdet = (svsp->efuse[6] >> 16) & GENMASK(7, 0); 1989 svsb->dcmdet = (svsp->efuse[6] >> 24) & GENMASK(7, 0); 1990 svsb->mtdes = svsp->efuse[5] & GENMASK(7, 0); 1991 1992 if (ft_pgm >= 2) { 1993 svsb->freq_base = 800000000; /* 800MHz */ 1994 svsb->dvt_fixed = 2; 1995 } 1996 break; 1997 default: 1998 dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); 1999 return false; 2000 } 2001 } 2002 2003 ret = svs_get_efuse_data(svsp, "t-calibration-data", 2004 &svsp->tefuse, &svsp->tefuse_max); 2005 if (ret) 2006 return false; 2007 2008 /* Thermal efuse parsing */ 2009 adc_ge_t = (svsp->tefuse[1] >> 22) & GENMASK(9, 0); 2010 adc_oe_t = (svsp->tefuse[1] >> 12) & GENMASK(9, 0); 2011 2012 o_vtsmcu[0] = (svsp->tefuse[0] >> 17) & GENMASK(8, 0); 2013 o_vtsmcu[1] = (svsp->tefuse[0] >> 8) & GENMASK(8, 0); 2014 o_vtsmcu[2] = svsp->tefuse[1] & GENMASK(8, 0); 2015 o_vtsmcu[3] = (svsp->tefuse[2] >> 23) & GENMASK(8, 0); 2016 o_vtsmcu[4] = (svsp->tefuse[2] >> 5) & GENMASK(8, 0); 2017 o_vtsabb = (svsp->tefuse[2] >> 14) & GENMASK(8, 0); 2018 2019 degc_cali = (svsp->tefuse[0] >> 1) & GENMASK(5, 0); 2020 adc_cali_en_t = svsp->tefuse[0] & BIT(0); 2021 o_slope_sign = (svsp->tefuse[0] >> 7) & BIT(0); 2022 2023 ts_id = (svsp->tefuse[1] >> 9) & BIT(0); 2024 if (!ts_id) { 2025 o_slope = 1534; 2026 } else { 2027 o_slope = (svsp->tefuse[0] >> 26) & GENMASK(5, 0); 2028 if (!o_slope_sign) 2029 o_slope = 1534 + o_slope * 10; 2030 else 2031 o_slope = 1534 - o_slope * 10; 2032 } 2033 2034 if (adc_cali_en_t == 0 || 2035 adc_ge_t < 265 || adc_ge_t > 758 || 2036 adc_oe_t < 265 || adc_oe_t > 758 || 2037 o_vtsmcu[0] < -8 || o_vtsmcu[0] > 484 || 2038 o_vtsmcu[1] < -8 || o_vtsmcu[1] > 484 || 2039 o_vtsmcu[2] < -8 || o_vtsmcu[2] > 484 || 2040 o_vtsmcu[3] < -8 || o_vtsmcu[3] > 484 || 2041 o_vtsmcu[4] < -8 || o_vtsmcu[4] > 484 || 2042 o_vtsabb < -8 || o_vtsabb > 484 || 2043 degc_cali < 1 || degc_cali > 63) { 2044 dev_err(svsp->dev, "bad thermal efuse, no mon mode\n"); 2045 goto remove_mt8183_svsb_mon_mode; 2046 } 2047 2048 ge = ((adc_ge_t - 512) * 10000) / 4096; 2049 oe = (adc_oe_t - 512); 2050 gain = (10000 + ge); 2051 2052 format[0] = (o_vtsmcu[0] + 3350 - oe); 2053 format[1] = (o_vtsmcu[1] + 3350 - oe); 2054 format[2] = (o_vtsmcu[2] + 3350 - oe); 2055 format[3] = (o_vtsmcu[3] + 3350 - oe); 2056 format[4] = (o_vtsmcu[4] + 3350 - oe); 2057 format[5] = (o_vtsabb + 3350 - oe); 2058 2059 for (i = 0; i < 6; i++) 2060 x_roomt[i] = (((format[i] * 10000) / 4096) * 10000) / gain; 2061 2062 temp0 = (10000 * 100000 / gain) * 15 / 18; 2063 mts = (temp0 * 10) / o_slope; 2064 2065 for (idx = 0; idx < svsp->bank_max; idx++) { 2066 svsb = &svsp->banks[idx]; 2067 svsb->mts = mts; 2068 2069 switch (svsb->sw_id) { 2070 case SVSB_CPU_LITTLE: 2071 tb_roomt = x_roomt[3]; 2072 break; 2073 case SVSB_CPU_BIG: 2074 tb_roomt = x_roomt[4]; 2075 break; 2076 case SVSB_CCI: 2077 tb_roomt = x_roomt[3]; 2078 break; 2079 case SVSB_GPU: 2080 tb_roomt = x_roomt[1]; 2081 break; 2082 default: 2083 dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); 2084 goto remove_mt8183_svsb_mon_mode; 2085 } 2086 2087 temp0 = (degc_cali * 10 / 2); 2088 temp1 = ((10000 * 100000 / 4096 / gain) * 2089 oe + tb_roomt * 10) * 15 / 18; 2090 temp2 = temp1 * 100 / o_slope; 2091 2092 svsb->bts = (temp0 + temp2 - 250) * 4 / 10; 2093 } 2094 2095 return true; 2096 2097 remove_mt8183_svsb_mon_mode: 2098 for (idx = 0; idx < svsp->bank_max; idx++) { 2099 svsb = &svsp->banks[idx]; 2100 svsb->mode_support &= ~SVSB_MODE_MON; 2101 } 2102 2103 return true; 2104 } 2105 2106 static struct device *svs_get_subsys_device(struct svs_platform *svsp, 2107 const char *node_name) 2108 { 2109 struct platform_device *pdev; 2110 struct device_node *np; 2111 2112 np = of_find_node_by_name(NULL, node_name); 2113 if (!np) { 2114 dev_err(svsp->dev, "cannot find %s node\n", node_name); 2115 return ERR_PTR(-ENODEV); 2116 } 2117 2118 pdev = of_find_device_by_node(np); 2119 if (!pdev) { 2120 of_node_put(np); 2121 dev_err(svsp->dev, "cannot find pdev by %s\n", node_name); 2122 return ERR_PTR(-ENXIO); 2123 } 2124 2125 of_node_put(np); 2126 2127 return &pdev->dev; 2128 } 2129 2130 static struct device *svs_add_device_link(struct svs_platform *svsp, 2131 const char *node_name) 2132 { 2133 struct device *dev; 2134 struct device_link *sup_link; 2135 2136 dev = svs_get_subsys_device(svsp, node_name); 2137 if (IS_ERR(dev)) 2138 return dev; 2139 2140 sup_link = device_link_add(svsp->dev, dev, 2141 DL_FLAG_AUTOREMOVE_CONSUMER); 2142 if (!sup_link) { 2143 dev_err(svsp->dev, "sup_link is NULL\n"); 2144 return ERR_PTR(-EINVAL); 2145 } 2146 2147 if (sup_link->supplier->links.status != DL_DEV_DRIVER_BOUND) 2148 return ERR_PTR(-EPROBE_DEFER); 2149 2150 return dev; 2151 } 2152 2153 static int svs_mt8192_platform_probe(struct svs_platform *svsp) 2154 { 2155 struct device *dev; 2156 struct svs_bank *svsb; 2157 u32 idx; 2158 2159 svsp->rst = devm_reset_control_get_optional(svsp->dev, "svs_rst"); 2160 if (IS_ERR(svsp->rst)) 2161 return dev_err_probe(svsp->dev, PTR_ERR(svsp->rst), 2162 "cannot get svs reset control\n"); 2163 2164 dev = svs_add_device_link(svsp, "lvts"); 2165 if (IS_ERR(dev)) 2166 return dev_err_probe(svsp->dev, PTR_ERR(dev), 2167 "failed to get lvts device\n"); 2168 2169 for (idx = 0; idx < svsp->bank_max; idx++) { 2170 svsb = &svsp->banks[idx]; 2171 2172 if (svsb->type == SVSB_HIGH) 2173 svsb->opp_dev = svs_add_device_link(svsp, "gpu"); 2174 else if (svsb->type == SVSB_LOW) 2175 svsb->opp_dev = svs_get_subsys_device(svsp, "gpu"); 2176 2177 if (IS_ERR(svsb->opp_dev)) 2178 return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev), 2179 "failed to get OPP device for bank %d\n", 2180 idx); 2181 } 2182 2183 return 0; 2184 } 2185 2186 static int svs_mt8183_platform_probe(struct svs_platform *svsp) 2187 { 2188 struct device *dev; 2189 struct svs_bank *svsb; 2190 u32 idx; 2191 2192 dev = svs_add_device_link(svsp, "thermal"); 2193 if (IS_ERR(dev)) 2194 return dev_err_probe(svsp->dev, PTR_ERR(dev), 2195 "failed to get thermal device\n"); 2196 2197 for (idx = 0; idx < svsp->bank_max; idx++) { 2198 svsb = &svsp->banks[idx]; 2199 2200 switch (svsb->sw_id) { 2201 case SVSB_CPU_LITTLE: 2202 case SVSB_CPU_BIG: 2203 svsb->opp_dev = get_cpu_device(svsb->cpu_id); 2204 break; 2205 case SVSB_CCI: 2206 svsb->opp_dev = svs_add_device_link(svsp, "cci"); 2207 break; 2208 case SVSB_GPU: 2209 svsb->opp_dev = svs_add_device_link(svsp, "gpu"); 2210 break; 2211 default: 2212 dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); 2213 return -EINVAL; 2214 } 2215 2216 if (IS_ERR(svsb->opp_dev)) 2217 return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev), 2218 "failed to get OPP device for bank %d\n", 2219 idx); 2220 } 2221 2222 return 0; 2223 } 2224 2225 static struct svs_bank svs_mt8192_banks[] = { 2226 { 2227 .sw_id = SVSB_GPU, 2228 .type = SVSB_LOW, 2229 .set_freq_pct = svs_set_bank_freq_pct_v3, 2230 .get_volts = svs_get_bank_volts_v3, 2231 .tzone_name = "gpu1", 2232 .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, 2233 .mode_support = SVSB_MODE_INIT02, 2234 .opp_count = MAX_OPP_ENTRIES, 2235 .freq_base = 688000000, 2236 .turn_freq_base = 688000000, 2237 .volt_step = 6250, 2238 .volt_base = 400000, 2239 .vmax = 0x60, 2240 .vmin = 0x1a, 2241 .age_config = 0x555555, 2242 .dc_config = 0x1, 2243 .dvt_fixed = 0x1, 2244 .vco = 0x18, 2245 .chk_shift = 0x87, 2246 .core_sel = 0x0fff0100, 2247 .int_st = BIT(0), 2248 .ctl0 = 0x00540003, 2249 .tzone_htemp = 85000, 2250 .tzone_htemp_voffset = 0, 2251 .tzone_ltemp = 25000, 2252 .tzone_ltemp_voffset = 7, 2253 }, 2254 { 2255 .sw_id = SVSB_GPU, 2256 .type = SVSB_HIGH, 2257 .set_freq_pct = svs_set_bank_freq_pct_v3, 2258 .get_volts = svs_get_bank_volts_v3, 2259 .tzone_name = "gpu1", 2260 .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | 2261 SVSB_MON_VOLT_IGNORE, 2262 .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, 2263 .opp_count = MAX_OPP_ENTRIES, 2264 .freq_base = 902000000, 2265 .turn_freq_base = 688000000, 2266 .volt_step = 6250, 2267 .volt_base = 400000, 2268 .vmax = 0x60, 2269 .vmin = 0x1a, 2270 .age_config = 0x555555, 2271 .dc_config = 0x1, 2272 .dvt_fixed = 0x6, 2273 .vco = 0x18, 2274 .chk_shift = 0x87, 2275 .core_sel = 0x0fff0101, 2276 .int_st = BIT(1), 2277 .ctl0 = 0x00540003, 2278 .tzone_htemp = 85000, 2279 .tzone_htemp_voffset = 0, 2280 .tzone_ltemp = 25000, 2281 .tzone_ltemp_voffset = 7, 2282 }, 2283 }; 2284 2285 static struct svs_bank svs_mt8188_banks[] = { 2286 { 2287 .sw_id = SVSB_GPU, 2288 .type = SVSB_LOW, 2289 .set_freq_pct = svs_set_bank_freq_pct_v3, 2290 .get_volts = svs_get_bank_volts_v3, 2291 .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, 2292 .mode_support = SVSB_MODE_INIT02, 2293 .opp_count = MAX_OPP_ENTRIES, 2294 .freq_base = 640000000, 2295 .turn_freq_base = 640000000, 2296 .volt_step = 6250, 2297 .volt_base = 400000, 2298 .vmax = 0x38, 2299 .vmin = 0x1c, 2300 .age_config = 0x555555, 2301 .dc_config = 0x555555, 2302 .dvt_fixed = 0x1, 2303 .vco = 0x10, 2304 .chk_shift = 0x87, 2305 .core_sel = 0x0fff0000, 2306 .int_st = BIT(0), 2307 .ctl0 = 0x00100003, 2308 }, 2309 { 2310 .sw_id = SVSB_GPU, 2311 .type = SVSB_HIGH, 2312 .set_freq_pct = svs_set_bank_freq_pct_v3, 2313 .get_volts = svs_get_bank_volts_v3, 2314 .tzone_name = "gpu1", 2315 .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | 2316 SVSB_MON_VOLT_IGNORE, 2317 .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, 2318 .opp_count = MAX_OPP_ENTRIES, 2319 .freq_base = 880000000, 2320 .turn_freq_base = 640000000, 2321 .volt_step = 6250, 2322 .volt_base = 400000, 2323 .vmax = 0x38, 2324 .vmin = 0x1c, 2325 .age_config = 0x555555, 2326 .dc_config = 0x555555, 2327 .dvt_fixed = 0x4, 2328 .vco = 0x10, 2329 .chk_shift = 0x87, 2330 .core_sel = 0x0fff0001, 2331 .int_st = BIT(1), 2332 .ctl0 = 0x00100003, 2333 .tzone_htemp = 85000, 2334 .tzone_htemp_voffset = 0, 2335 .tzone_ltemp = 25000, 2336 .tzone_ltemp_voffset = 7, 2337 }, 2338 }; 2339 2340 static struct svs_bank svs_mt8183_banks[] = { 2341 { 2342 .sw_id = SVSB_CPU_LITTLE, 2343 .set_freq_pct = svs_set_bank_freq_pct_v2, 2344 .get_volts = svs_get_bank_volts_v2, 2345 .cpu_id = 0, 2346 .buck_name = "proc", 2347 .volt_flags = SVSB_INIT01_VOLT_INC_ONLY, 2348 .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02, 2349 .opp_count = MAX_OPP_ENTRIES, 2350 .freq_base = 1989000000, 2351 .vboot = 0x30, 2352 .volt_step = 6250, 2353 .volt_base = 500000, 2354 .vmax = 0x64, 2355 .vmin = 0x18, 2356 .age_config = 0x555555, 2357 .dc_config = 0x555555, 2358 .dvt_fixed = 0x7, 2359 .vco = 0x10, 2360 .chk_shift = 0x77, 2361 .core_sel = 0x8fff0000, 2362 .int_st = BIT(0), 2363 .ctl0 = 0x00010001, 2364 }, 2365 { 2366 .sw_id = SVSB_CPU_BIG, 2367 .set_freq_pct = svs_set_bank_freq_pct_v2, 2368 .get_volts = svs_get_bank_volts_v2, 2369 .cpu_id = 4, 2370 .buck_name = "proc", 2371 .volt_flags = SVSB_INIT01_VOLT_INC_ONLY, 2372 .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02, 2373 .opp_count = MAX_OPP_ENTRIES, 2374 .freq_base = 1989000000, 2375 .vboot = 0x30, 2376 .volt_step = 6250, 2377 .volt_base = 500000, 2378 .vmax = 0x58, 2379 .vmin = 0x10, 2380 .age_config = 0x555555, 2381 .dc_config = 0x555555, 2382 .dvt_fixed = 0x7, 2383 .vco = 0x10, 2384 .chk_shift = 0x77, 2385 .core_sel = 0x8fff0001, 2386 .int_st = BIT(1), 2387 .ctl0 = 0x00000001, 2388 }, 2389 { 2390 .sw_id = SVSB_CCI, 2391 .set_freq_pct = svs_set_bank_freq_pct_v2, 2392 .get_volts = svs_get_bank_volts_v2, 2393 .buck_name = "proc", 2394 .volt_flags = SVSB_INIT01_VOLT_INC_ONLY, 2395 .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02, 2396 .opp_count = MAX_OPP_ENTRIES, 2397 .freq_base = 1196000000, 2398 .vboot = 0x30, 2399 .volt_step = 6250, 2400 .volt_base = 500000, 2401 .vmax = 0x64, 2402 .vmin = 0x18, 2403 .age_config = 0x555555, 2404 .dc_config = 0x555555, 2405 .dvt_fixed = 0x7, 2406 .vco = 0x10, 2407 .chk_shift = 0x77, 2408 .core_sel = 0x8fff0002, 2409 .int_st = BIT(2), 2410 .ctl0 = 0x00100003, 2411 }, 2412 { 2413 .sw_id = SVSB_GPU, 2414 .set_freq_pct = svs_set_bank_freq_pct_v2, 2415 .get_volts = svs_get_bank_volts_v2, 2416 .buck_name = "mali", 2417 .tzone_name = "tzts2", 2418 .volt_flags = SVSB_INIT01_PD_REQ | 2419 SVSB_INIT01_VOLT_INC_ONLY, 2420 .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02 | 2421 SVSB_MODE_MON, 2422 .opp_count = MAX_OPP_ENTRIES, 2423 .freq_base = 900000000, 2424 .vboot = 0x30, 2425 .volt_step = 6250, 2426 .volt_base = 500000, 2427 .vmax = 0x40, 2428 .vmin = 0x14, 2429 .age_config = 0x555555, 2430 .dc_config = 0x555555, 2431 .dvt_fixed = 0x3, 2432 .vco = 0x10, 2433 .chk_shift = 0x77, 2434 .core_sel = 0x8fff0003, 2435 .int_st = BIT(3), 2436 .ctl0 = 0x00050001, 2437 .tzone_htemp = 85000, 2438 .tzone_htemp_voffset = 0, 2439 .tzone_ltemp = 25000, 2440 .tzone_ltemp_voffset = 3, 2441 }, 2442 }; 2443 2444 static const struct svs_platform_data svs_mt8192_platform_data = { 2445 .name = "mt8192-svs", 2446 .banks = svs_mt8192_banks, 2447 .efuse_parsing = svs_mt8192_efuse_parsing, 2448 .probe = svs_mt8192_platform_probe, 2449 .regs = svs_regs_v2, 2450 .bank_max = ARRAY_SIZE(svs_mt8192_banks), 2451 }; 2452 2453 static const struct svs_platform_data svs_mt8188_platform_data = { 2454 .name = "mt8188-svs", 2455 .banks = svs_mt8188_banks, 2456 .efuse_parsing = svs_mt8188_efuse_parsing, 2457 .probe = svs_mt8192_platform_probe, 2458 .regs = svs_regs_v2, 2459 .bank_max = ARRAY_SIZE(svs_mt8188_banks), 2460 }; 2461 2462 static const struct svs_platform_data svs_mt8183_platform_data = { 2463 .name = "mt8183-svs", 2464 .banks = svs_mt8183_banks, 2465 .efuse_parsing = svs_mt8183_efuse_parsing, 2466 .probe = svs_mt8183_platform_probe, 2467 .regs = svs_regs_v2, 2468 .bank_max = ARRAY_SIZE(svs_mt8183_banks), 2469 }; 2470 2471 static const struct of_device_id svs_of_match[] = { 2472 { 2473 .compatible = "mediatek,mt8192-svs", 2474 .data = &svs_mt8192_platform_data, 2475 }, { 2476 .compatible = "mediatek,mt8188-svs", 2477 .data = &svs_mt8188_platform_data, 2478 }, { 2479 .compatible = "mediatek,mt8183-svs", 2480 .data = &svs_mt8183_platform_data, 2481 }, { 2482 /* Sentinel */ 2483 }, 2484 }; 2485 MODULE_DEVICE_TABLE(of, svs_of_match); 2486 2487 static int svs_probe(struct platform_device *pdev) 2488 { 2489 struct svs_platform *svsp; 2490 const struct svs_platform_data *svsp_data; 2491 int ret, svsp_irq; 2492 2493 svsp_data = of_device_get_match_data(&pdev->dev); 2494 2495 svsp = devm_kzalloc(&pdev->dev, sizeof(*svsp), GFP_KERNEL); 2496 if (!svsp) 2497 return -ENOMEM; 2498 2499 svsp->dev = &pdev->dev; 2500 svsp->banks = svsp_data->banks; 2501 svsp->regs = svsp_data->regs; 2502 svsp->bank_max = svsp_data->bank_max; 2503 2504 ret = svsp_data->probe(svsp); 2505 if (ret) 2506 return ret; 2507 2508 ret = svs_get_efuse_data(svsp, "svs-calibration-data", 2509 &svsp->efuse, &svsp->efuse_max); 2510 if (ret) { 2511 ret = -EPERM; 2512 goto svs_probe_free_efuse; 2513 } 2514 2515 if (!svsp_data->efuse_parsing(svsp)) { 2516 dev_err(svsp->dev, "efuse data parsing failed\n"); 2517 ret = -EPERM; 2518 goto svs_probe_free_tefuse; 2519 } 2520 2521 ret = svs_bank_resource_setup(svsp); 2522 if (ret) { 2523 dev_err(svsp->dev, "svs bank resource setup fail: %d\n", ret); 2524 goto svs_probe_free_tefuse; 2525 } 2526 2527 svsp_irq = platform_get_irq(pdev, 0); 2528 if (svsp_irq < 0) { 2529 ret = svsp_irq; 2530 goto svs_probe_free_tefuse; 2531 } 2532 2533 svsp->main_clk = devm_clk_get(svsp->dev, "main"); 2534 if (IS_ERR(svsp->main_clk)) { 2535 dev_err(svsp->dev, "failed to get clock: %ld\n", 2536 PTR_ERR(svsp->main_clk)); 2537 ret = PTR_ERR(svsp->main_clk); 2538 goto svs_probe_free_tefuse; 2539 } 2540 2541 ret = clk_prepare_enable(svsp->main_clk); 2542 if (ret) { 2543 dev_err(svsp->dev, "cannot enable main clk: %d\n", ret); 2544 goto svs_probe_free_tefuse; 2545 } 2546 2547 svsp->base = of_iomap(svsp->dev->of_node, 0); 2548 if (IS_ERR_OR_NULL(svsp->base)) { 2549 dev_err(svsp->dev, "cannot find svs register base\n"); 2550 ret = -EINVAL; 2551 goto svs_probe_clk_disable; 2552 } 2553 2554 ret = devm_request_threaded_irq(svsp->dev, svsp_irq, NULL, svs_isr, 2555 IRQF_ONESHOT, svsp_data->name, svsp); 2556 if (ret) { 2557 dev_err(svsp->dev, "register irq(%d) failed: %d\n", 2558 svsp_irq, ret); 2559 goto svs_probe_iounmap; 2560 } 2561 2562 ret = svs_start(svsp); 2563 if (ret) { 2564 dev_err(svsp->dev, "svs start fail: %d\n", ret); 2565 goto svs_probe_iounmap; 2566 } 2567 2568 #ifdef CONFIG_DEBUG_FS 2569 ret = svs_create_debug_cmds(svsp); 2570 if (ret) { 2571 dev_err(svsp->dev, "svs create debug cmds fail: %d\n", ret); 2572 goto svs_probe_iounmap; 2573 } 2574 #endif 2575 2576 return 0; 2577 2578 svs_probe_iounmap: 2579 iounmap(svsp->base); 2580 2581 svs_probe_clk_disable: 2582 clk_disable_unprepare(svsp->main_clk); 2583 2584 svs_probe_free_tefuse: 2585 if (!IS_ERR_OR_NULL(svsp->tefuse)) 2586 kfree(svsp->tefuse); 2587 2588 svs_probe_free_efuse: 2589 if (!IS_ERR_OR_NULL(svsp->efuse)) 2590 kfree(svsp->efuse); 2591 2592 return ret; 2593 } 2594 2595 static DEFINE_SIMPLE_DEV_PM_OPS(svs_pm_ops, svs_suspend, svs_resume); 2596 2597 static struct platform_driver svs_driver = { 2598 .probe = svs_probe, 2599 .driver = { 2600 .name = "mtk-svs", 2601 .pm = &svs_pm_ops, 2602 .of_match_table = svs_of_match, 2603 }, 2604 }; 2605 2606 module_platform_driver(svs_driver); 2607 2608 MODULE_AUTHOR("Roger Lu <roger.lu@mediatek.com>"); 2609 MODULE_DESCRIPTION("MediaTek SVS driver"); 2610 MODULE_LICENSE("GPL"); 2611