1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Flora Fu, MediaTek 5 */ 6 #include <linux/clk.h> 7 #include <linux/interrupt.h> 8 #include <linux/io.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/of_device.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 #include <linux/reset.h> 15 16 #define PWRAP_POLL_DELAY_US 10 17 #define PWRAP_POLL_TIMEOUT_US 10000 18 19 #define PWRAP_MT8135_BRIDGE_IORD_ARB_EN 0x4 20 #define PWRAP_MT8135_BRIDGE_WACS3_EN 0x10 21 #define PWRAP_MT8135_BRIDGE_INIT_DONE3 0x14 22 #define PWRAP_MT8135_BRIDGE_WACS4_EN 0x24 23 #define PWRAP_MT8135_BRIDGE_INIT_DONE4 0x28 24 #define PWRAP_MT8135_BRIDGE_INT_EN 0x38 25 #define PWRAP_MT8135_BRIDGE_TIMER_EN 0x48 26 #define PWRAP_MT8135_BRIDGE_WDT_UNIT 0x50 27 #define PWRAP_MT8135_BRIDGE_WDT_SRC_EN 0x54 28 29 /* macro for wrapper status */ 30 #define PWRAP_GET_WACS_RDATA(x) (((x) >> 0) & 0x0000ffff) 31 #define PWRAP_GET_WACS_ARB_FSM(x) (((x) >> 1) & 0x00000007) 32 #define PWRAP_GET_WACS_FSM(x) (((x) >> 16) & 0x00000007) 33 #define PWRAP_GET_WACS_REQ(x) (((x) >> 19) & 0x00000001) 34 #define PWRAP_STATE_SYNC_IDLE0 BIT(20) 35 #define PWRAP_STATE_INIT_DONE0 BIT(21) 36 #define PWRAP_STATE_INIT_DONE0_MT8186 BIT(22) 37 #define PWRAP_STATE_INIT_DONE1 BIT(15) 38 39 /* macro for WACS FSM */ 40 #define PWRAP_WACS_FSM_IDLE 0x00 41 #define PWRAP_WACS_FSM_REQ 0x02 42 #define PWRAP_WACS_FSM_WFDLE 0x04 43 #define PWRAP_WACS_FSM_WFVLDCLR 0x06 44 #define PWRAP_WACS_INIT_DONE 0x01 45 #define PWRAP_WACS_WACS_SYNC_IDLE 0x01 46 #define PWRAP_WACS_SYNC_BUSY 0x00 47 48 /* macro for device wrapper default value */ 49 #define PWRAP_DEW_READ_TEST_VAL 0x5aa5 50 #define PWRAP_DEW_WRITE_TEST_VAL 0xa55a 51 52 /* macro for manual command */ 53 #define PWRAP_MAN_CMD_SPI_WRITE_NEW (1 << 14) 54 #define PWRAP_MAN_CMD_SPI_WRITE (1 << 13) 55 #define PWRAP_MAN_CMD_OP_CSH (0x0 << 8) 56 #define PWRAP_MAN_CMD_OP_CSL (0x1 << 8) 57 #define PWRAP_MAN_CMD_OP_CK (0x2 << 8) 58 #define PWRAP_MAN_CMD_OP_OUTS (0x8 << 8) 59 #define PWRAP_MAN_CMD_OP_OUTD (0x9 << 8) 60 #define PWRAP_MAN_CMD_OP_OUTQ (0xa << 8) 61 62 /* macro for Watch Dog Timer Source */ 63 #define PWRAP_WDT_SRC_EN_STAUPD_TRIG (1 << 25) 64 #define PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE (1 << 20) 65 #define PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE (1 << 6) 66 #define PWRAP_WDT_SRC_MASK_ALL 0xffffffff 67 #define PWRAP_WDT_SRC_MASK_NO_STAUPD ~(PWRAP_WDT_SRC_EN_STAUPD_TRIG | \ 68 PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE | \ 69 PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE) 70 71 /* Group of bits used for shown slave capability */ 72 #define PWRAP_SLV_CAP_SPI BIT(0) 73 #define PWRAP_SLV_CAP_DUALIO BIT(1) 74 #define PWRAP_SLV_CAP_SECURITY BIT(2) 75 #define HAS_CAP(_c, _x) (((_c) & (_x)) == (_x)) 76 77 /* Group of bits used for shown pwrap capability */ 78 #define PWRAP_CAP_BRIDGE BIT(0) 79 #define PWRAP_CAP_RESET BIT(1) 80 #define PWRAP_CAP_DCM BIT(2) 81 #define PWRAP_CAP_INT1_EN BIT(3) 82 #define PWRAP_CAP_WDT_SRC1 BIT(4) 83 #define PWRAP_CAP_ARB BIT(5) 84 #define PWRAP_CAP_ARB_MT8186 BIT(8) 85 86 /* defines for slave device wrapper registers */ 87 enum dew_regs { 88 PWRAP_DEW_BASE, 89 PWRAP_DEW_DIO_EN, 90 PWRAP_DEW_READ_TEST, 91 PWRAP_DEW_WRITE_TEST, 92 PWRAP_DEW_CRC_EN, 93 PWRAP_DEW_CRC_VAL, 94 PWRAP_DEW_MON_GRP_SEL, 95 PWRAP_DEW_CIPHER_KEY_SEL, 96 PWRAP_DEW_CIPHER_IV_SEL, 97 PWRAP_DEW_CIPHER_RDY, 98 PWRAP_DEW_CIPHER_MODE, 99 PWRAP_DEW_CIPHER_SWRST, 100 101 /* MT6323 only regs */ 102 PWRAP_DEW_CIPHER_EN, 103 PWRAP_DEW_RDDMY_NO, 104 105 /* MT6358 only regs */ 106 PWRAP_SMT_CON1, 107 PWRAP_DRV_CON1, 108 PWRAP_FILTER_CON0, 109 PWRAP_GPIO_PULLEN0_CLR, 110 PWRAP_RG_SPI_CON0, 111 PWRAP_RG_SPI_RECORD0, 112 PWRAP_RG_SPI_CON2, 113 PWRAP_RG_SPI_CON3, 114 PWRAP_RG_SPI_CON4, 115 PWRAP_RG_SPI_CON5, 116 PWRAP_RG_SPI_CON6, 117 PWRAP_RG_SPI_CON7, 118 PWRAP_RG_SPI_CON8, 119 PWRAP_RG_SPI_CON13, 120 PWRAP_SPISLV_KEY, 121 122 /* MT6359 only regs */ 123 PWRAP_DEW_CRC_SWRST, 124 PWRAP_DEW_RG_EN_RECORD, 125 PWRAP_DEW_RECORD_CMD0, 126 PWRAP_DEW_RECORD_CMD1, 127 PWRAP_DEW_RECORD_CMD2, 128 PWRAP_DEW_RECORD_CMD3, 129 PWRAP_DEW_RECORD_CMD4, 130 PWRAP_DEW_RECORD_CMD5, 131 PWRAP_DEW_RECORD_WDATA0, 132 PWRAP_DEW_RECORD_WDATA1, 133 PWRAP_DEW_RECORD_WDATA2, 134 PWRAP_DEW_RECORD_WDATA3, 135 PWRAP_DEW_RECORD_WDATA4, 136 PWRAP_DEW_RECORD_WDATA5, 137 PWRAP_DEW_RG_ADDR_TARGET, 138 PWRAP_DEW_RG_ADDR_MASK, 139 PWRAP_DEW_RG_WDATA_TARGET, 140 PWRAP_DEW_RG_WDATA_MASK, 141 PWRAP_DEW_RG_SPI_RECORD_CLR, 142 PWRAP_DEW_RG_CMD_ALERT_CLR, 143 144 /* MT6397 only regs */ 145 PWRAP_DEW_EVENT_OUT_EN, 146 PWRAP_DEW_EVENT_SRC_EN, 147 PWRAP_DEW_EVENT_SRC, 148 PWRAP_DEW_EVENT_FLAG, 149 PWRAP_DEW_MON_FLAG_SEL, 150 PWRAP_DEW_EVENT_TEST, 151 PWRAP_DEW_CIPHER_LOAD, 152 PWRAP_DEW_CIPHER_START, 153 }; 154 155 static const u32 mt6323_regs[] = { 156 [PWRAP_DEW_BASE] = 0x0000, 157 [PWRAP_DEW_DIO_EN] = 0x018a, 158 [PWRAP_DEW_READ_TEST] = 0x018c, 159 [PWRAP_DEW_WRITE_TEST] = 0x018e, 160 [PWRAP_DEW_CRC_EN] = 0x0192, 161 [PWRAP_DEW_CRC_VAL] = 0x0194, 162 [PWRAP_DEW_MON_GRP_SEL] = 0x0196, 163 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0198, 164 [PWRAP_DEW_CIPHER_IV_SEL] = 0x019a, 165 [PWRAP_DEW_CIPHER_EN] = 0x019c, 166 [PWRAP_DEW_CIPHER_RDY] = 0x019e, 167 [PWRAP_DEW_CIPHER_MODE] = 0x01a0, 168 [PWRAP_DEW_CIPHER_SWRST] = 0x01a2, 169 [PWRAP_DEW_RDDMY_NO] = 0x01a4, 170 }; 171 172 static const u32 mt6351_regs[] = { 173 [PWRAP_DEW_DIO_EN] = 0x02F2, 174 [PWRAP_DEW_READ_TEST] = 0x02F4, 175 [PWRAP_DEW_WRITE_TEST] = 0x02F6, 176 [PWRAP_DEW_CRC_EN] = 0x02FA, 177 [PWRAP_DEW_CRC_VAL] = 0x02FC, 178 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0300, 179 [PWRAP_DEW_CIPHER_IV_SEL] = 0x0302, 180 [PWRAP_DEW_CIPHER_EN] = 0x0304, 181 [PWRAP_DEW_CIPHER_RDY] = 0x0306, 182 [PWRAP_DEW_CIPHER_MODE] = 0x0308, 183 [PWRAP_DEW_CIPHER_SWRST] = 0x030A, 184 [PWRAP_DEW_RDDMY_NO] = 0x030C, 185 }; 186 187 static const u32 mt6357_regs[] = { 188 [PWRAP_DEW_DIO_EN] = 0x040A, 189 [PWRAP_DEW_READ_TEST] = 0x040C, 190 [PWRAP_DEW_WRITE_TEST] = 0x040E, 191 [PWRAP_DEW_CRC_EN] = 0x0412, 192 [PWRAP_DEW_CRC_VAL] = 0x0414, 193 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0418, 194 [PWRAP_DEW_CIPHER_IV_SEL] = 0x041A, 195 [PWRAP_DEW_CIPHER_EN] = 0x041C, 196 [PWRAP_DEW_CIPHER_RDY] = 0x041E, 197 [PWRAP_DEW_CIPHER_MODE] = 0x0420, 198 [PWRAP_DEW_CIPHER_SWRST] = 0x0422, 199 [PWRAP_DEW_RDDMY_NO] = 0x0424, 200 }; 201 202 static const u32 mt6358_regs[] = { 203 [PWRAP_SMT_CON1] = 0x0030, 204 [PWRAP_DRV_CON1] = 0x0038, 205 [PWRAP_FILTER_CON0] = 0x0040, 206 [PWRAP_GPIO_PULLEN0_CLR] = 0x0098, 207 [PWRAP_RG_SPI_CON0] = 0x0408, 208 [PWRAP_RG_SPI_RECORD0] = 0x040a, 209 [PWRAP_DEW_DIO_EN] = 0x040c, 210 [PWRAP_DEW_READ_TEST] = 0x040e, 211 [PWRAP_DEW_WRITE_TEST] = 0x0410, 212 [PWRAP_DEW_CRC_EN] = 0x0414, 213 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x041a, 214 [PWRAP_DEW_CIPHER_IV_SEL] = 0x041c, 215 [PWRAP_DEW_CIPHER_EN] = 0x041e, 216 [PWRAP_DEW_CIPHER_RDY] = 0x0420, 217 [PWRAP_DEW_CIPHER_MODE] = 0x0422, 218 [PWRAP_DEW_CIPHER_SWRST] = 0x0424, 219 [PWRAP_RG_SPI_CON2] = 0x0432, 220 [PWRAP_RG_SPI_CON3] = 0x0434, 221 [PWRAP_RG_SPI_CON4] = 0x0436, 222 [PWRAP_RG_SPI_CON5] = 0x0438, 223 [PWRAP_RG_SPI_CON6] = 0x043a, 224 [PWRAP_RG_SPI_CON7] = 0x043c, 225 [PWRAP_RG_SPI_CON8] = 0x043e, 226 [PWRAP_RG_SPI_CON13] = 0x0448, 227 [PWRAP_SPISLV_KEY] = 0x044a, 228 }; 229 230 static const u32 mt6359_regs[] = { 231 [PWRAP_DEW_RG_EN_RECORD] = 0x040a, 232 [PWRAP_DEW_DIO_EN] = 0x040c, 233 [PWRAP_DEW_READ_TEST] = 0x040e, 234 [PWRAP_DEW_WRITE_TEST] = 0x0410, 235 [PWRAP_DEW_CRC_SWRST] = 0x0412, 236 [PWRAP_DEW_CRC_EN] = 0x0414, 237 [PWRAP_DEW_CRC_VAL] = 0x0416, 238 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0418, 239 [PWRAP_DEW_CIPHER_IV_SEL] = 0x041a, 240 [PWRAP_DEW_CIPHER_EN] = 0x041c, 241 [PWRAP_DEW_CIPHER_RDY] = 0x041e, 242 [PWRAP_DEW_CIPHER_MODE] = 0x0420, 243 [PWRAP_DEW_CIPHER_SWRST] = 0x0422, 244 [PWRAP_DEW_RDDMY_NO] = 0x0424, 245 [PWRAP_DEW_RECORD_CMD0] = 0x0428, 246 [PWRAP_DEW_RECORD_CMD1] = 0x042a, 247 [PWRAP_DEW_RECORD_CMD2] = 0x042c, 248 [PWRAP_DEW_RECORD_CMD3] = 0x042e, 249 [PWRAP_DEW_RECORD_CMD4] = 0x0430, 250 [PWRAP_DEW_RECORD_CMD5] = 0x0432, 251 [PWRAP_DEW_RECORD_WDATA0] = 0x0434, 252 [PWRAP_DEW_RECORD_WDATA1] = 0x0436, 253 [PWRAP_DEW_RECORD_WDATA2] = 0x0438, 254 [PWRAP_DEW_RECORD_WDATA3] = 0x043a, 255 [PWRAP_DEW_RECORD_WDATA4] = 0x043c, 256 [PWRAP_DEW_RECORD_WDATA5] = 0x043e, 257 [PWRAP_DEW_RG_ADDR_TARGET] = 0x0440, 258 [PWRAP_DEW_RG_ADDR_MASK] = 0x0442, 259 [PWRAP_DEW_RG_WDATA_TARGET] = 0x0444, 260 [PWRAP_DEW_RG_WDATA_MASK] = 0x0446, 261 [PWRAP_DEW_RG_SPI_RECORD_CLR] = 0x0448, 262 [PWRAP_DEW_RG_CMD_ALERT_CLR] = 0x0448, 263 [PWRAP_SPISLV_KEY] = 0x044a, 264 }; 265 266 static const u32 mt6397_regs[] = { 267 [PWRAP_DEW_BASE] = 0xbc00, 268 [PWRAP_DEW_EVENT_OUT_EN] = 0xbc00, 269 [PWRAP_DEW_DIO_EN] = 0xbc02, 270 [PWRAP_DEW_EVENT_SRC_EN] = 0xbc04, 271 [PWRAP_DEW_EVENT_SRC] = 0xbc06, 272 [PWRAP_DEW_EVENT_FLAG] = 0xbc08, 273 [PWRAP_DEW_READ_TEST] = 0xbc0a, 274 [PWRAP_DEW_WRITE_TEST] = 0xbc0c, 275 [PWRAP_DEW_CRC_EN] = 0xbc0e, 276 [PWRAP_DEW_CRC_VAL] = 0xbc10, 277 [PWRAP_DEW_MON_GRP_SEL] = 0xbc12, 278 [PWRAP_DEW_MON_FLAG_SEL] = 0xbc14, 279 [PWRAP_DEW_EVENT_TEST] = 0xbc16, 280 [PWRAP_DEW_CIPHER_KEY_SEL] = 0xbc18, 281 [PWRAP_DEW_CIPHER_IV_SEL] = 0xbc1a, 282 [PWRAP_DEW_CIPHER_LOAD] = 0xbc1c, 283 [PWRAP_DEW_CIPHER_START] = 0xbc1e, 284 [PWRAP_DEW_CIPHER_RDY] = 0xbc20, 285 [PWRAP_DEW_CIPHER_MODE] = 0xbc22, 286 [PWRAP_DEW_CIPHER_SWRST] = 0xbc24, 287 }; 288 289 enum pwrap_regs { 290 PWRAP_MUX_SEL, 291 PWRAP_WRAP_EN, 292 PWRAP_DIO_EN, 293 PWRAP_SIDLY, 294 PWRAP_CSHEXT_WRITE, 295 PWRAP_CSHEXT_READ, 296 PWRAP_CSLEXT_START, 297 PWRAP_CSLEXT_END, 298 PWRAP_STAUPD_PRD, 299 PWRAP_STAUPD_GRPEN, 300 PWRAP_STAUPD_MAN_TRIG, 301 PWRAP_STAUPD_STA, 302 PWRAP_WRAP_STA, 303 PWRAP_HARB_INIT, 304 PWRAP_HARB_HPRIO, 305 PWRAP_HIPRIO_ARB_EN, 306 PWRAP_HARB_STA0, 307 PWRAP_HARB_STA1, 308 PWRAP_MAN_EN, 309 PWRAP_MAN_CMD, 310 PWRAP_MAN_RDATA, 311 PWRAP_MAN_VLDCLR, 312 PWRAP_WACS0_EN, 313 PWRAP_INIT_DONE0, 314 PWRAP_WACS0_CMD, 315 PWRAP_WACS0_RDATA, 316 PWRAP_WACS0_VLDCLR, 317 PWRAP_WACS1_EN, 318 PWRAP_INIT_DONE1, 319 PWRAP_WACS1_CMD, 320 PWRAP_WACS1_RDATA, 321 PWRAP_WACS1_VLDCLR, 322 PWRAP_WACS2_EN, 323 PWRAP_INIT_DONE2, 324 PWRAP_WACS2_CMD, 325 PWRAP_WACS2_RDATA, 326 PWRAP_WACS2_VLDCLR, 327 PWRAP_INT_EN, 328 PWRAP_INT_FLG_RAW, 329 PWRAP_INT_FLG, 330 PWRAP_INT_CLR, 331 PWRAP_SIG_ADR, 332 PWRAP_SIG_MODE, 333 PWRAP_SIG_VALUE, 334 PWRAP_SIG_ERRVAL, 335 PWRAP_CRC_EN, 336 PWRAP_TIMER_EN, 337 PWRAP_TIMER_STA, 338 PWRAP_WDT_UNIT, 339 PWRAP_WDT_SRC_EN, 340 PWRAP_WDT_FLG, 341 PWRAP_DEBUG_INT_SEL, 342 PWRAP_CIPHER_KEY_SEL, 343 PWRAP_CIPHER_IV_SEL, 344 PWRAP_CIPHER_RDY, 345 PWRAP_CIPHER_MODE, 346 PWRAP_CIPHER_SWRST, 347 PWRAP_DCM_EN, 348 PWRAP_DCM_DBC_PRD, 349 PWRAP_EINT_STA0_ADR, 350 PWRAP_EINT_STA1_ADR, 351 PWRAP_SWINF_2_WDATA_31_0, 352 PWRAP_SWINF_2_RDATA_31_0, 353 354 /* MT2701 only regs */ 355 PWRAP_ADC_CMD_ADDR, 356 PWRAP_PWRAP_ADC_CMD, 357 PWRAP_ADC_RDY_ADDR, 358 PWRAP_ADC_RDATA_ADDR1, 359 PWRAP_ADC_RDATA_ADDR2, 360 361 /* MT7622 only regs */ 362 PWRAP_STA, 363 PWRAP_CLR, 364 PWRAP_DVFS_ADR8, 365 PWRAP_DVFS_WDATA8, 366 PWRAP_DVFS_ADR9, 367 PWRAP_DVFS_WDATA9, 368 PWRAP_DVFS_ADR10, 369 PWRAP_DVFS_WDATA10, 370 PWRAP_DVFS_ADR11, 371 PWRAP_DVFS_WDATA11, 372 PWRAP_DVFS_ADR12, 373 PWRAP_DVFS_WDATA12, 374 PWRAP_DVFS_ADR13, 375 PWRAP_DVFS_WDATA13, 376 PWRAP_DVFS_ADR14, 377 PWRAP_DVFS_WDATA14, 378 PWRAP_DVFS_ADR15, 379 PWRAP_DVFS_WDATA15, 380 PWRAP_EXT_CK, 381 PWRAP_ADC_RDATA_ADDR, 382 PWRAP_GPS_STA, 383 PWRAP_SW_RST, 384 PWRAP_DVFS_STEP_CTRL0, 385 PWRAP_DVFS_STEP_CTRL1, 386 PWRAP_DVFS_STEP_CTRL2, 387 PWRAP_SPI2_CTRL, 388 389 /* MT8135 only regs */ 390 PWRAP_CSHEXT, 391 PWRAP_EVENT_IN_EN, 392 PWRAP_EVENT_DST_EN, 393 PWRAP_RRARB_INIT, 394 PWRAP_RRARB_EN, 395 PWRAP_RRARB_STA0, 396 PWRAP_RRARB_STA1, 397 PWRAP_EVENT_STA, 398 PWRAP_EVENT_STACLR, 399 PWRAP_CIPHER_LOAD, 400 PWRAP_CIPHER_START, 401 402 /* MT8173 only regs */ 403 PWRAP_RDDMY, 404 PWRAP_SI_CK_CON, 405 PWRAP_DVFS_ADR0, 406 PWRAP_DVFS_WDATA0, 407 PWRAP_DVFS_ADR1, 408 PWRAP_DVFS_WDATA1, 409 PWRAP_DVFS_ADR2, 410 PWRAP_DVFS_WDATA2, 411 PWRAP_DVFS_ADR3, 412 PWRAP_DVFS_WDATA3, 413 PWRAP_DVFS_ADR4, 414 PWRAP_DVFS_WDATA4, 415 PWRAP_DVFS_ADR5, 416 PWRAP_DVFS_WDATA5, 417 PWRAP_DVFS_ADR6, 418 PWRAP_DVFS_WDATA6, 419 PWRAP_DVFS_ADR7, 420 PWRAP_DVFS_WDATA7, 421 PWRAP_SPMINF_STA, 422 PWRAP_CIPHER_EN, 423 424 /* MT8183 only regs */ 425 PWRAP_SI_SAMPLE_CTRL, 426 PWRAP_CSLEXT_WRITE, 427 PWRAP_CSLEXT_READ, 428 PWRAP_EXT_CK_WRITE, 429 PWRAP_STAUPD_CTRL, 430 PWRAP_WACS_P2P_EN, 431 PWRAP_INIT_DONE_P2P, 432 PWRAP_WACS_MD32_EN, 433 PWRAP_INIT_DONE_MD32, 434 PWRAP_INT1_EN, 435 PWRAP_INT1_FLG, 436 PWRAP_INT1_CLR, 437 PWRAP_WDT_SRC_EN_1, 438 PWRAP_INT_GPS_AUXADC_CMD_ADDR, 439 PWRAP_INT_GPS_AUXADC_CMD, 440 PWRAP_INT_GPS_AUXADC_RDATA_ADDR, 441 PWRAP_EXT_GPS_AUXADC_RDATA_ADDR, 442 PWRAP_GPSINF_0_STA, 443 PWRAP_GPSINF_1_STA, 444 445 /* MT8516 only regs */ 446 PWRAP_OP_TYPE, 447 PWRAP_MSB_FIRST, 448 }; 449 450 static int mt2701_regs[] = { 451 [PWRAP_MUX_SEL] = 0x0, 452 [PWRAP_WRAP_EN] = 0x4, 453 [PWRAP_DIO_EN] = 0x8, 454 [PWRAP_SIDLY] = 0xc, 455 [PWRAP_RDDMY] = 0x18, 456 [PWRAP_SI_CK_CON] = 0x1c, 457 [PWRAP_CSHEXT_WRITE] = 0x20, 458 [PWRAP_CSHEXT_READ] = 0x24, 459 [PWRAP_CSLEXT_START] = 0x28, 460 [PWRAP_CSLEXT_END] = 0x2c, 461 [PWRAP_STAUPD_PRD] = 0x30, 462 [PWRAP_STAUPD_GRPEN] = 0x34, 463 [PWRAP_STAUPD_MAN_TRIG] = 0x38, 464 [PWRAP_STAUPD_STA] = 0x3c, 465 [PWRAP_WRAP_STA] = 0x44, 466 [PWRAP_HARB_INIT] = 0x48, 467 [PWRAP_HARB_HPRIO] = 0x4c, 468 [PWRAP_HIPRIO_ARB_EN] = 0x50, 469 [PWRAP_HARB_STA0] = 0x54, 470 [PWRAP_HARB_STA1] = 0x58, 471 [PWRAP_MAN_EN] = 0x5c, 472 [PWRAP_MAN_CMD] = 0x60, 473 [PWRAP_MAN_RDATA] = 0x64, 474 [PWRAP_MAN_VLDCLR] = 0x68, 475 [PWRAP_WACS0_EN] = 0x6c, 476 [PWRAP_INIT_DONE0] = 0x70, 477 [PWRAP_WACS0_CMD] = 0x74, 478 [PWRAP_WACS0_RDATA] = 0x78, 479 [PWRAP_WACS0_VLDCLR] = 0x7c, 480 [PWRAP_WACS1_EN] = 0x80, 481 [PWRAP_INIT_DONE1] = 0x84, 482 [PWRAP_WACS1_CMD] = 0x88, 483 [PWRAP_WACS1_RDATA] = 0x8c, 484 [PWRAP_WACS1_VLDCLR] = 0x90, 485 [PWRAP_WACS2_EN] = 0x94, 486 [PWRAP_INIT_DONE2] = 0x98, 487 [PWRAP_WACS2_CMD] = 0x9c, 488 [PWRAP_WACS2_RDATA] = 0xa0, 489 [PWRAP_WACS2_VLDCLR] = 0xa4, 490 [PWRAP_INT_EN] = 0xa8, 491 [PWRAP_INT_FLG_RAW] = 0xac, 492 [PWRAP_INT_FLG] = 0xb0, 493 [PWRAP_INT_CLR] = 0xb4, 494 [PWRAP_SIG_ADR] = 0xb8, 495 [PWRAP_SIG_MODE] = 0xbc, 496 [PWRAP_SIG_VALUE] = 0xc0, 497 [PWRAP_SIG_ERRVAL] = 0xc4, 498 [PWRAP_CRC_EN] = 0xc8, 499 [PWRAP_TIMER_EN] = 0xcc, 500 [PWRAP_TIMER_STA] = 0xd0, 501 [PWRAP_WDT_UNIT] = 0xd4, 502 [PWRAP_WDT_SRC_EN] = 0xd8, 503 [PWRAP_WDT_FLG] = 0xdc, 504 [PWRAP_DEBUG_INT_SEL] = 0xe0, 505 [PWRAP_DVFS_ADR0] = 0xe4, 506 [PWRAP_DVFS_WDATA0] = 0xe8, 507 [PWRAP_DVFS_ADR1] = 0xec, 508 [PWRAP_DVFS_WDATA1] = 0xf0, 509 [PWRAP_DVFS_ADR2] = 0xf4, 510 [PWRAP_DVFS_WDATA2] = 0xf8, 511 [PWRAP_DVFS_ADR3] = 0xfc, 512 [PWRAP_DVFS_WDATA3] = 0x100, 513 [PWRAP_DVFS_ADR4] = 0x104, 514 [PWRAP_DVFS_WDATA4] = 0x108, 515 [PWRAP_DVFS_ADR5] = 0x10c, 516 [PWRAP_DVFS_WDATA5] = 0x110, 517 [PWRAP_DVFS_ADR6] = 0x114, 518 [PWRAP_DVFS_WDATA6] = 0x118, 519 [PWRAP_DVFS_ADR7] = 0x11c, 520 [PWRAP_DVFS_WDATA7] = 0x120, 521 [PWRAP_CIPHER_KEY_SEL] = 0x124, 522 [PWRAP_CIPHER_IV_SEL] = 0x128, 523 [PWRAP_CIPHER_EN] = 0x12c, 524 [PWRAP_CIPHER_RDY] = 0x130, 525 [PWRAP_CIPHER_MODE] = 0x134, 526 [PWRAP_CIPHER_SWRST] = 0x138, 527 [PWRAP_DCM_EN] = 0x13c, 528 [PWRAP_DCM_DBC_PRD] = 0x140, 529 [PWRAP_ADC_CMD_ADDR] = 0x144, 530 [PWRAP_PWRAP_ADC_CMD] = 0x148, 531 [PWRAP_ADC_RDY_ADDR] = 0x14c, 532 [PWRAP_ADC_RDATA_ADDR1] = 0x150, 533 [PWRAP_ADC_RDATA_ADDR2] = 0x154, 534 }; 535 536 static int mt6765_regs[] = { 537 [PWRAP_MUX_SEL] = 0x0, 538 [PWRAP_WRAP_EN] = 0x4, 539 [PWRAP_DIO_EN] = 0x8, 540 [PWRAP_RDDMY] = 0x20, 541 [PWRAP_CSHEXT_WRITE] = 0x24, 542 [PWRAP_CSHEXT_READ] = 0x28, 543 [PWRAP_CSLEXT_START] = 0x2C, 544 [PWRAP_CSLEXT_END] = 0x30, 545 [PWRAP_STAUPD_PRD] = 0x3C, 546 [PWRAP_HARB_HPRIO] = 0x68, 547 [PWRAP_HIPRIO_ARB_EN] = 0x6C, 548 [PWRAP_MAN_EN] = 0x7C, 549 [PWRAP_MAN_CMD] = 0x80, 550 [PWRAP_WACS0_EN] = 0x8C, 551 [PWRAP_WACS1_EN] = 0x94, 552 [PWRAP_WACS2_EN] = 0x9C, 553 [PWRAP_INIT_DONE2] = 0xA0, 554 [PWRAP_WACS2_CMD] = 0xC20, 555 [PWRAP_WACS2_RDATA] = 0xC24, 556 [PWRAP_WACS2_VLDCLR] = 0xC28, 557 [PWRAP_INT_EN] = 0xB4, 558 [PWRAP_INT_FLG_RAW] = 0xB8, 559 [PWRAP_INT_FLG] = 0xBC, 560 [PWRAP_INT_CLR] = 0xC0, 561 [PWRAP_TIMER_EN] = 0xE8, 562 [PWRAP_WDT_UNIT] = 0xF0, 563 [PWRAP_WDT_SRC_EN] = 0xF4, 564 [PWRAP_DCM_EN] = 0x1DC, 565 [PWRAP_DCM_DBC_PRD] = 0x1E0, 566 }; 567 568 static int mt6779_regs[] = { 569 [PWRAP_MUX_SEL] = 0x0, 570 [PWRAP_WRAP_EN] = 0x4, 571 [PWRAP_DIO_EN] = 0x8, 572 [PWRAP_RDDMY] = 0x20, 573 [PWRAP_CSHEXT_WRITE] = 0x24, 574 [PWRAP_CSHEXT_READ] = 0x28, 575 [PWRAP_CSLEXT_WRITE] = 0x2C, 576 [PWRAP_CSLEXT_READ] = 0x30, 577 [PWRAP_EXT_CK_WRITE] = 0x34, 578 [PWRAP_STAUPD_CTRL] = 0x3C, 579 [PWRAP_STAUPD_GRPEN] = 0x40, 580 [PWRAP_EINT_STA0_ADR] = 0x44, 581 [PWRAP_HARB_HPRIO] = 0x68, 582 [PWRAP_HIPRIO_ARB_EN] = 0x6C, 583 [PWRAP_MAN_EN] = 0x7C, 584 [PWRAP_MAN_CMD] = 0x80, 585 [PWRAP_WACS0_EN] = 0x8C, 586 [PWRAP_INIT_DONE0] = 0x90, 587 [PWRAP_WACS1_EN] = 0x94, 588 [PWRAP_WACS2_EN] = 0x9C, 589 [PWRAP_INIT_DONE1] = 0x98, 590 [PWRAP_INIT_DONE2] = 0xA0, 591 [PWRAP_INT_EN] = 0xBC, 592 [PWRAP_INT_FLG_RAW] = 0xC0, 593 [PWRAP_INT_FLG] = 0xC4, 594 [PWRAP_INT_CLR] = 0xC8, 595 [PWRAP_INT1_EN] = 0xCC, 596 [PWRAP_INT1_FLG] = 0xD4, 597 [PWRAP_INT1_CLR] = 0xD8, 598 [PWRAP_TIMER_EN] = 0xF0, 599 [PWRAP_WDT_UNIT] = 0xF8, 600 [PWRAP_WDT_SRC_EN] = 0xFC, 601 [PWRAP_WDT_SRC_EN_1] = 0x100, 602 [PWRAP_WACS2_CMD] = 0xC20, 603 [PWRAP_WACS2_RDATA] = 0xC24, 604 [PWRAP_WACS2_VLDCLR] = 0xC28, 605 }; 606 607 static int mt6797_regs[] = { 608 [PWRAP_MUX_SEL] = 0x0, 609 [PWRAP_WRAP_EN] = 0x4, 610 [PWRAP_DIO_EN] = 0x8, 611 [PWRAP_SIDLY] = 0xC, 612 [PWRAP_RDDMY] = 0x10, 613 [PWRAP_CSHEXT_WRITE] = 0x18, 614 [PWRAP_CSHEXT_READ] = 0x1C, 615 [PWRAP_CSLEXT_START] = 0x20, 616 [PWRAP_CSLEXT_END] = 0x24, 617 [PWRAP_STAUPD_PRD] = 0x28, 618 [PWRAP_HARB_HPRIO] = 0x50, 619 [PWRAP_HIPRIO_ARB_EN] = 0x54, 620 [PWRAP_MAN_EN] = 0x60, 621 [PWRAP_MAN_CMD] = 0x64, 622 [PWRAP_WACS0_EN] = 0x70, 623 [PWRAP_WACS1_EN] = 0x84, 624 [PWRAP_WACS2_EN] = 0x98, 625 [PWRAP_INIT_DONE2] = 0x9C, 626 [PWRAP_WACS2_CMD] = 0xA0, 627 [PWRAP_WACS2_RDATA] = 0xA4, 628 [PWRAP_WACS2_VLDCLR] = 0xA8, 629 [PWRAP_INT_EN] = 0xC0, 630 [PWRAP_INT_FLG_RAW] = 0xC4, 631 [PWRAP_INT_FLG] = 0xC8, 632 [PWRAP_INT_CLR] = 0xCC, 633 [PWRAP_TIMER_EN] = 0xF4, 634 [PWRAP_WDT_UNIT] = 0xFC, 635 [PWRAP_WDT_SRC_EN] = 0x100, 636 [PWRAP_DCM_EN] = 0x1CC, 637 [PWRAP_DCM_DBC_PRD] = 0x1D4, 638 }; 639 640 static int mt6873_regs[] = { 641 [PWRAP_INIT_DONE2] = 0x0, 642 [PWRAP_TIMER_EN] = 0x3E0, 643 [PWRAP_INT_EN] = 0x448, 644 [PWRAP_WACS2_CMD] = 0xC80, 645 [PWRAP_SWINF_2_WDATA_31_0] = 0xC84, 646 [PWRAP_SWINF_2_RDATA_31_0] = 0xC94, 647 [PWRAP_WACS2_VLDCLR] = 0xCA4, 648 [PWRAP_WACS2_RDATA] = 0xCA8, 649 }; 650 651 static int mt7622_regs[] = { 652 [PWRAP_MUX_SEL] = 0x0, 653 [PWRAP_WRAP_EN] = 0x4, 654 [PWRAP_DIO_EN] = 0x8, 655 [PWRAP_SIDLY] = 0xC, 656 [PWRAP_RDDMY] = 0x10, 657 [PWRAP_SI_CK_CON] = 0x14, 658 [PWRAP_CSHEXT_WRITE] = 0x18, 659 [PWRAP_CSHEXT_READ] = 0x1C, 660 [PWRAP_CSLEXT_START] = 0x20, 661 [PWRAP_CSLEXT_END] = 0x24, 662 [PWRAP_STAUPD_PRD] = 0x28, 663 [PWRAP_STAUPD_GRPEN] = 0x2C, 664 [PWRAP_EINT_STA0_ADR] = 0x30, 665 [PWRAP_EINT_STA1_ADR] = 0x34, 666 [PWRAP_STA] = 0x38, 667 [PWRAP_CLR] = 0x3C, 668 [PWRAP_STAUPD_MAN_TRIG] = 0x40, 669 [PWRAP_STAUPD_STA] = 0x44, 670 [PWRAP_WRAP_STA] = 0x48, 671 [PWRAP_HARB_INIT] = 0x4C, 672 [PWRAP_HARB_HPRIO] = 0x50, 673 [PWRAP_HIPRIO_ARB_EN] = 0x54, 674 [PWRAP_HARB_STA0] = 0x58, 675 [PWRAP_HARB_STA1] = 0x5C, 676 [PWRAP_MAN_EN] = 0x60, 677 [PWRAP_MAN_CMD] = 0x64, 678 [PWRAP_MAN_RDATA] = 0x68, 679 [PWRAP_MAN_VLDCLR] = 0x6C, 680 [PWRAP_WACS0_EN] = 0x70, 681 [PWRAP_INIT_DONE0] = 0x74, 682 [PWRAP_WACS0_CMD] = 0x78, 683 [PWRAP_WACS0_RDATA] = 0x7C, 684 [PWRAP_WACS0_VLDCLR] = 0x80, 685 [PWRAP_WACS1_EN] = 0x84, 686 [PWRAP_INIT_DONE1] = 0x88, 687 [PWRAP_WACS1_CMD] = 0x8C, 688 [PWRAP_WACS1_RDATA] = 0x90, 689 [PWRAP_WACS1_VLDCLR] = 0x94, 690 [PWRAP_WACS2_EN] = 0x98, 691 [PWRAP_INIT_DONE2] = 0x9C, 692 [PWRAP_WACS2_CMD] = 0xA0, 693 [PWRAP_WACS2_RDATA] = 0xA4, 694 [PWRAP_WACS2_VLDCLR] = 0xA8, 695 [PWRAP_INT_EN] = 0xAC, 696 [PWRAP_INT_FLG_RAW] = 0xB0, 697 [PWRAP_INT_FLG] = 0xB4, 698 [PWRAP_INT_CLR] = 0xB8, 699 [PWRAP_SIG_ADR] = 0xBC, 700 [PWRAP_SIG_MODE] = 0xC0, 701 [PWRAP_SIG_VALUE] = 0xC4, 702 [PWRAP_SIG_ERRVAL] = 0xC8, 703 [PWRAP_CRC_EN] = 0xCC, 704 [PWRAP_TIMER_EN] = 0xD0, 705 [PWRAP_TIMER_STA] = 0xD4, 706 [PWRAP_WDT_UNIT] = 0xD8, 707 [PWRAP_WDT_SRC_EN] = 0xDC, 708 [PWRAP_WDT_FLG] = 0xE0, 709 [PWRAP_DEBUG_INT_SEL] = 0xE4, 710 [PWRAP_DVFS_ADR0] = 0xE8, 711 [PWRAP_DVFS_WDATA0] = 0xEC, 712 [PWRAP_DVFS_ADR1] = 0xF0, 713 [PWRAP_DVFS_WDATA1] = 0xF4, 714 [PWRAP_DVFS_ADR2] = 0xF8, 715 [PWRAP_DVFS_WDATA2] = 0xFC, 716 [PWRAP_DVFS_ADR3] = 0x100, 717 [PWRAP_DVFS_WDATA3] = 0x104, 718 [PWRAP_DVFS_ADR4] = 0x108, 719 [PWRAP_DVFS_WDATA4] = 0x10C, 720 [PWRAP_DVFS_ADR5] = 0x110, 721 [PWRAP_DVFS_WDATA5] = 0x114, 722 [PWRAP_DVFS_ADR6] = 0x118, 723 [PWRAP_DVFS_WDATA6] = 0x11C, 724 [PWRAP_DVFS_ADR7] = 0x120, 725 [PWRAP_DVFS_WDATA7] = 0x124, 726 [PWRAP_DVFS_ADR8] = 0x128, 727 [PWRAP_DVFS_WDATA8] = 0x12C, 728 [PWRAP_DVFS_ADR9] = 0x130, 729 [PWRAP_DVFS_WDATA9] = 0x134, 730 [PWRAP_DVFS_ADR10] = 0x138, 731 [PWRAP_DVFS_WDATA10] = 0x13C, 732 [PWRAP_DVFS_ADR11] = 0x140, 733 [PWRAP_DVFS_WDATA11] = 0x144, 734 [PWRAP_DVFS_ADR12] = 0x148, 735 [PWRAP_DVFS_WDATA12] = 0x14C, 736 [PWRAP_DVFS_ADR13] = 0x150, 737 [PWRAP_DVFS_WDATA13] = 0x154, 738 [PWRAP_DVFS_ADR14] = 0x158, 739 [PWRAP_DVFS_WDATA14] = 0x15C, 740 [PWRAP_DVFS_ADR15] = 0x160, 741 [PWRAP_DVFS_WDATA15] = 0x164, 742 [PWRAP_SPMINF_STA] = 0x168, 743 [PWRAP_CIPHER_KEY_SEL] = 0x16C, 744 [PWRAP_CIPHER_IV_SEL] = 0x170, 745 [PWRAP_CIPHER_EN] = 0x174, 746 [PWRAP_CIPHER_RDY] = 0x178, 747 [PWRAP_CIPHER_MODE] = 0x17C, 748 [PWRAP_CIPHER_SWRST] = 0x180, 749 [PWRAP_DCM_EN] = 0x184, 750 [PWRAP_DCM_DBC_PRD] = 0x188, 751 [PWRAP_EXT_CK] = 0x18C, 752 [PWRAP_ADC_CMD_ADDR] = 0x190, 753 [PWRAP_PWRAP_ADC_CMD] = 0x194, 754 [PWRAP_ADC_RDATA_ADDR] = 0x198, 755 [PWRAP_GPS_STA] = 0x19C, 756 [PWRAP_SW_RST] = 0x1A0, 757 [PWRAP_DVFS_STEP_CTRL0] = 0x238, 758 [PWRAP_DVFS_STEP_CTRL1] = 0x23C, 759 [PWRAP_DVFS_STEP_CTRL2] = 0x240, 760 [PWRAP_SPI2_CTRL] = 0x244, 761 }; 762 763 static int mt8135_regs[] = { 764 [PWRAP_MUX_SEL] = 0x0, 765 [PWRAP_WRAP_EN] = 0x4, 766 [PWRAP_DIO_EN] = 0x8, 767 [PWRAP_SIDLY] = 0xc, 768 [PWRAP_CSHEXT] = 0x10, 769 [PWRAP_CSHEXT_WRITE] = 0x14, 770 [PWRAP_CSHEXT_READ] = 0x18, 771 [PWRAP_CSLEXT_START] = 0x1c, 772 [PWRAP_CSLEXT_END] = 0x20, 773 [PWRAP_STAUPD_PRD] = 0x24, 774 [PWRAP_STAUPD_GRPEN] = 0x28, 775 [PWRAP_STAUPD_MAN_TRIG] = 0x2c, 776 [PWRAP_STAUPD_STA] = 0x30, 777 [PWRAP_EVENT_IN_EN] = 0x34, 778 [PWRAP_EVENT_DST_EN] = 0x38, 779 [PWRAP_WRAP_STA] = 0x3c, 780 [PWRAP_RRARB_INIT] = 0x40, 781 [PWRAP_RRARB_EN] = 0x44, 782 [PWRAP_RRARB_STA0] = 0x48, 783 [PWRAP_RRARB_STA1] = 0x4c, 784 [PWRAP_HARB_INIT] = 0x50, 785 [PWRAP_HARB_HPRIO] = 0x54, 786 [PWRAP_HIPRIO_ARB_EN] = 0x58, 787 [PWRAP_HARB_STA0] = 0x5c, 788 [PWRAP_HARB_STA1] = 0x60, 789 [PWRAP_MAN_EN] = 0x64, 790 [PWRAP_MAN_CMD] = 0x68, 791 [PWRAP_MAN_RDATA] = 0x6c, 792 [PWRAP_MAN_VLDCLR] = 0x70, 793 [PWRAP_WACS0_EN] = 0x74, 794 [PWRAP_INIT_DONE0] = 0x78, 795 [PWRAP_WACS0_CMD] = 0x7c, 796 [PWRAP_WACS0_RDATA] = 0x80, 797 [PWRAP_WACS0_VLDCLR] = 0x84, 798 [PWRAP_WACS1_EN] = 0x88, 799 [PWRAP_INIT_DONE1] = 0x8c, 800 [PWRAP_WACS1_CMD] = 0x90, 801 [PWRAP_WACS1_RDATA] = 0x94, 802 [PWRAP_WACS1_VLDCLR] = 0x98, 803 [PWRAP_WACS2_EN] = 0x9c, 804 [PWRAP_INIT_DONE2] = 0xa0, 805 [PWRAP_WACS2_CMD] = 0xa4, 806 [PWRAP_WACS2_RDATA] = 0xa8, 807 [PWRAP_WACS2_VLDCLR] = 0xac, 808 [PWRAP_INT_EN] = 0xb0, 809 [PWRAP_INT_FLG_RAW] = 0xb4, 810 [PWRAP_INT_FLG] = 0xb8, 811 [PWRAP_INT_CLR] = 0xbc, 812 [PWRAP_SIG_ADR] = 0xc0, 813 [PWRAP_SIG_MODE] = 0xc4, 814 [PWRAP_SIG_VALUE] = 0xc8, 815 [PWRAP_SIG_ERRVAL] = 0xcc, 816 [PWRAP_CRC_EN] = 0xd0, 817 [PWRAP_EVENT_STA] = 0xd4, 818 [PWRAP_EVENT_STACLR] = 0xd8, 819 [PWRAP_TIMER_EN] = 0xdc, 820 [PWRAP_TIMER_STA] = 0xe0, 821 [PWRAP_WDT_UNIT] = 0xe4, 822 [PWRAP_WDT_SRC_EN] = 0xe8, 823 [PWRAP_WDT_FLG] = 0xec, 824 [PWRAP_DEBUG_INT_SEL] = 0xf0, 825 [PWRAP_CIPHER_KEY_SEL] = 0x134, 826 [PWRAP_CIPHER_IV_SEL] = 0x138, 827 [PWRAP_CIPHER_LOAD] = 0x13c, 828 [PWRAP_CIPHER_START] = 0x140, 829 [PWRAP_CIPHER_RDY] = 0x144, 830 [PWRAP_CIPHER_MODE] = 0x148, 831 [PWRAP_CIPHER_SWRST] = 0x14c, 832 [PWRAP_DCM_EN] = 0x15c, 833 [PWRAP_DCM_DBC_PRD] = 0x160, 834 }; 835 836 static int mt8173_regs[] = { 837 [PWRAP_MUX_SEL] = 0x0, 838 [PWRAP_WRAP_EN] = 0x4, 839 [PWRAP_DIO_EN] = 0x8, 840 [PWRAP_SIDLY] = 0xc, 841 [PWRAP_RDDMY] = 0x10, 842 [PWRAP_SI_CK_CON] = 0x14, 843 [PWRAP_CSHEXT_WRITE] = 0x18, 844 [PWRAP_CSHEXT_READ] = 0x1c, 845 [PWRAP_CSLEXT_START] = 0x20, 846 [PWRAP_CSLEXT_END] = 0x24, 847 [PWRAP_STAUPD_PRD] = 0x28, 848 [PWRAP_STAUPD_GRPEN] = 0x2c, 849 [PWRAP_STAUPD_MAN_TRIG] = 0x40, 850 [PWRAP_STAUPD_STA] = 0x44, 851 [PWRAP_WRAP_STA] = 0x48, 852 [PWRAP_HARB_INIT] = 0x4c, 853 [PWRAP_HARB_HPRIO] = 0x50, 854 [PWRAP_HIPRIO_ARB_EN] = 0x54, 855 [PWRAP_HARB_STA0] = 0x58, 856 [PWRAP_HARB_STA1] = 0x5c, 857 [PWRAP_MAN_EN] = 0x60, 858 [PWRAP_MAN_CMD] = 0x64, 859 [PWRAP_MAN_RDATA] = 0x68, 860 [PWRAP_MAN_VLDCLR] = 0x6c, 861 [PWRAP_WACS0_EN] = 0x70, 862 [PWRAP_INIT_DONE0] = 0x74, 863 [PWRAP_WACS0_CMD] = 0x78, 864 [PWRAP_WACS0_RDATA] = 0x7c, 865 [PWRAP_WACS0_VLDCLR] = 0x80, 866 [PWRAP_WACS1_EN] = 0x84, 867 [PWRAP_INIT_DONE1] = 0x88, 868 [PWRAP_WACS1_CMD] = 0x8c, 869 [PWRAP_WACS1_RDATA] = 0x90, 870 [PWRAP_WACS1_VLDCLR] = 0x94, 871 [PWRAP_WACS2_EN] = 0x98, 872 [PWRAP_INIT_DONE2] = 0x9c, 873 [PWRAP_WACS2_CMD] = 0xa0, 874 [PWRAP_WACS2_RDATA] = 0xa4, 875 [PWRAP_WACS2_VLDCLR] = 0xa8, 876 [PWRAP_INT_EN] = 0xac, 877 [PWRAP_INT_FLG_RAW] = 0xb0, 878 [PWRAP_INT_FLG] = 0xb4, 879 [PWRAP_INT_CLR] = 0xb8, 880 [PWRAP_SIG_ADR] = 0xbc, 881 [PWRAP_SIG_MODE] = 0xc0, 882 [PWRAP_SIG_VALUE] = 0xc4, 883 [PWRAP_SIG_ERRVAL] = 0xc8, 884 [PWRAP_CRC_EN] = 0xcc, 885 [PWRAP_TIMER_EN] = 0xd0, 886 [PWRAP_TIMER_STA] = 0xd4, 887 [PWRAP_WDT_UNIT] = 0xd8, 888 [PWRAP_WDT_SRC_EN] = 0xdc, 889 [PWRAP_WDT_FLG] = 0xe0, 890 [PWRAP_DEBUG_INT_SEL] = 0xe4, 891 [PWRAP_DVFS_ADR0] = 0xe8, 892 [PWRAP_DVFS_WDATA0] = 0xec, 893 [PWRAP_DVFS_ADR1] = 0xf0, 894 [PWRAP_DVFS_WDATA1] = 0xf4, 895 [PWRAP_DVFS_ADR2] = 0xf8, 896 [PWRAP_DVFS_WDATA2] = 0xfc, 897 [PWRAP_DVFS_ADR3] = 0x100, 898 [PWRAP_DVFS_WDATA3] = 0x104, 899 [PWRAP_DVFS_ADR4] = 0x108, 900 [PWRAP_DVFS_WDATA4] = 0x10c, 901 [PWRAP_DVFS_ADR5] = 0x110, 902 [PWRAP_DVFS_WDATA5] = 0x114, 903 [PWRAP_DVFS_ADR6] = 0x118, 904 [PWRAP_DVFS_WDATA6] = 0x11c, 905 [PWRAP_DVFS_ADR7] = 0x120, 906 [PWRAP_DVFS_WDATA7] = 0x124, 907 [PWRAP_SPMINF_STA] = 0x128, 908 [PWRAP_CIPHER_KEY_SEL] = 0x12c, 909 [PWRAP_CIPHER_IV_SEL] = 0x130, 910 [PWRAP_CIPHER_EN] = 0x134, 911 [PWRAP_CIPHER_RDY] = 0x138, 912 [PWRAP_CIPHER_MODE] = 0x13c, 913 [PWRAP_CIPHER_SWRST] = 0x140, 914 [PWRAP_DCM_EN] = 0x144, 915 [PWRAP_DCM_DBC_PRD] = 0x148, 916 }; 917 918 static int mt8183_regs[] = { 919 [PWRAP_MUX_SEL] = 0x0, 920 [PWRAP_WRAP_EN] = 0x4, 921 [PWRAP_DIO_EN] = 0x8, 922 [PWRAP_SI_SAMPLE_CTRL] = 0xC, 923 [PWRAP_RDDMY] = 0x14, 924 [PWRAP_CSHEXT_WRITE] = 0x18, 925 [PWRAP_CSHEXT_READ] = 0x1C, 926 [PWRAP_CSLEXT_WRITE] = 0x20, 927 [PWRAP_CSLEXT_READ] = 0x24, 928 [PWRAP_EXT_CK_WRITE] = 0x28, 929 [PWRAP_STAUPD_CTRL] = 0x30, 930 [PWRAP_STAUPD_GRPEN] = 0x34, 931 [PWRAP_EINT_STA0_ADR] = 0x38, 932 [PWRAP_HARB_HPRIO] = 0x5C, 933 [PWRAP_HIPRIO_ARB_EN] = 0x60, 934 [PWRAP_MAN_EN] = 0x70, 935 [PWRAP_MAN_CMD] = 0x74, 936 [PWRAP_WACS0_EN] = 0x80, 937 [PWRAP_INIT_DONE0] = 0x84, 938 [PWRAP_WACS1_EN] = 0x88, 939 [PWRAP_INIT_DONE1] = 0x8C, 940 [PWRAP_WACS2_EN] = 0x90, 941 [PWRAP_INIT_DONE2] = 0x94, 942 [PWRAP_WACS_P2P_EN] = 0xA0, 943 [PWRAP_INIT_DONE_P2P] = 0xA4, 944 [PWRAP_WACS_MD32_EN] = 0xA8, 945 [PWRAP_INIT_DONE_MD32] = 0xAC, 946 [PWRAP_INT_EN] = 0xB0, 947 [PWRAP_INT_FLG] = 0xB8, 948 [PWRAP_INT_CLR] = 0xBC, 949 [PWRAP_INT1_EN] = 0xC0, 950 [PWRAP_INT1_FLG] = 0xC8, 951 [PWRAP_INT1_CLR] = 0xCC, 952 [PWRAP_SIG_ADR] = 0xD0, 953 [PWRAP_CRC_EN] = 0xE0, 954 [PWRAP_TIMER_EN] = 0xE4, 955 [PWRAP_WDT_UNIT] = 0xEC, 956 [PWRAP_WDT_SRC_EN] = 0xF0, 957 [PWRAP_WDT_SRC_EN_1] = 0xF4, 958 [PWRAP_INT_GPS_AUXADC_CMD_ADDR] = 0x1DC, 959 [PWRAP_INT_GPS_AUXADC_CMD] = 0x1E0, 960 [PWRAP_INT_GPS_AUXADC_RDATA_ADDR] = 0x1E4, 961 [PWRAP_EXT_GPS_AUXADC_RDATA_ADDR] = 0x1E8, 962 [PWRAP_GPSINF_0_STA] = 0x1EC, 963 [PWRAP_GPSINF_1_STA] = 0x1F0, 964 [PWRAP_WACS2_CMD] = 0xC20, 965 [PWRAP_WACS2_RDATA] = 0xC24, 966 [PWRAP_WACS2_VLDCLR] = 0xC28, 967 }; 968 969 static int mt8195_regs[] = { 970 [PWRAP_INIT_DONE2] = 0x0, 971 [PWRAP_STAUPD_CTRL] = 0x4C, 972 [PWRAP_TIMER_EN] = 0x3E4, 973 [PWRAP_INT_EN] = 0x420, 974 [PWRAP_INT_FLG] = 0x428, 975 [PWRAP_INT_CLR] = 0x42C, 976 [PWRAP_INT1_EN] = 0x450, 977 [PWRAP_INT1_FLG] = 0x458, 978 [PWRAP_INT1_CLR] = 0x45C, 979 [PWRAP_WACS2_CMD] = 0x880, 980 [PWRAP_SWINF_2_WDATA_31_0] = 0x884, 981 [PWRAP_SWINF_2_RDATA_31_0] = 0x894, 982 [PWRAP_WACS2_VLDCLR] = 0x8A4, 983 [PWRAP_WACS2_RDATA] = 0x8A8, 984 }; 985 986 static int mt8365_regs[] = { 987 [PWRAP_MUX_SEL] = 0x0, 988 [PWRAP_WRAP_EN] = 0x4, 989 [PWRAP_DIO_EN] = 0x8, 990 [PWRAP_CSHEXT_WRITE] = 0x24, 991 [PWRAP_CSHEXT_READ] = 0x28, 992 [PWRAP_STAUPD_PRD] = 0x3c, 993 [PWRAP_STAUPD_GRPEN] = 0x40, 994 [PWRAP_STAUPD_MAN_TRIG] = 0x58, 995 [PWRAP_STAUPD_STA] = 0x5c, 996 [PWRAP_WRAP_STA] = 0x60, 997 [PWRAP_HARB_INIT] = 0x64, 998 [PWRAP_HARB_HPRIO] = 0x68, 999 [PWRAP_HIPRIO_ARB_EN] = 0x6c, 1000 [PWRAP_HARB_STA0] = 0x70, 1001 [PWRAP_HARB_STA1] = 0x74, 1002 [PWRAP_MAN_EN] = 0x7c, 1003 [PWRAP_MAN_CMD] = 0x80, 1004 [PWRAP_MAN_RDATA] = 0x84, 1005 [PWRAP_MAN_VLDCLR] = 0x88, 1006 [PWRAP_WACS0_EN] = 0x8c, 1007 [PWRAP_INIT_DONE0] = 0x90, 1008 [PWRAP_WACS0_CMD] = 0xc00, 1009 [PWRAP_WACS0_RDATA] = 0xc04, 1010 [PWRAP_WACS0_VLDCLR] = 0xc08, 1011 [PWRAP_WACS1_EN] = 0x94, 1012 [PWRAP_INIT_DONE1] = 0x98, 1013 [PWRAP_WACS2_EN] = 0x9c, 1014 [PWRAP_INIT_DONE2] = 0xa0, 1015 [PWRAP_WACS2_CMD] = 0xc20, 1016 [PWRAP_WACS2_RDATA] = 0xc24, 1017 [PWRAP_WACS2_VLDCLR] = 0xc28, 1018 [PWRAP_INT_EN] = 0xb4, 1019 [PWRAP_INT_FLG_RAW] = 0xb8, 1020 [PWRAP_INT_FLG] = 0xbc, 1021 [PWRAP_INT_CLR] = 0xc0, 1022 [PWRAP_SIG_ADR] = 0xd4, 1023 [PWRAP_SIG_MODE] = 0xd8, 1024 [PWRAP_SIG_VALUE] = 0xdc, 1025 [PWRAP_SIG_ERRVAL] = 0xe0, 1026 [PWRAP_CRC_EN] = 0xe4, 1027 [PWRAP_TIMER_EN] = 0xe8, 1028 [PWRAP_TIMER_STA] = 0xec, 1029 [PWRAP_WDT_UNIT] = 0xf0, 1030 [PWRAP_WDT_SRC_EN] = 0xf4, 1031 [PWRAP_WDT_FLG] = 0xfc, 1032 [PWRAP_DEBUG_INT_SEL] = 0x104, 1033 [PWRAP_CIPHER_KEY_SEL] = 0x1c4, 1034 [PWRAP_CIPHER_IV_SEL] = 0x1c8, 1035 [PWRAP_CIPHER_RDY] = 0x1d0, 1036 [PWRAP_CIPHER_MODE] = 0x1d4, 1037 [PWRAP_CIPHER_SWRST] = 0x1d8, 1038 [PWRAP_DCM_EN] = 0x1dc, 1039 [PWRAP_DCM_DBC_PRD] = 0x1e0, 1040 [PWRAP_EINT_STA0_ADR] = 0x44, 1041 [PWRAP_EINT_STA1_ADR] = 0x48, 1042 [PWRAP_INT1_EN] = 0xc4, 1043 [PWRAP_INT1_FLG] = 0xcc, 1044 [PWRAP_INT1_CLR] = 0xd0, 1045 [PWRAP_WDT_SRC_EN_1] = 0xf8, 1046 }; 1047 1048 static int mt8516_regs[] = { 1049 [PWRAP_MUX_SEL] = 0x0, 1050 [PWRAP_WRAP_EN] = 0x4, 1051 [PWRAP_DIO_EN] = 0x8, 1052 [PWRAP_SIDLY] = 0xc, 1053 [PWRAP_RDDMY] = 0x10, 1054 [PWRAP_SI_CK_CON] = 0x14, 1055 [PWRAP_CSHEXT_WRITE] = 0x18, 1056 [PWRAP_CSHEXT_READ] = 0x1c, 1057 [PWRAP_CSLEXT_START] = 0x20, 1058 [PWRAP_CSLEXT_END] = 0x24, 1059 [PWRAP_STAUPD_PRD] = 0x28, 1060 [PWRAP_STAUPD_GRPEN] = 0x2c, 1061 [PWRAP_STAUPD_MAN_TRIG] = 0x40, 1062 [PWRAP_STAUPD_STA] = 0x44, 1063 [PWRAP_WRAP_STA] = 0x48, 1064 [PWRAP_HARB_INIT] = 0x4c, 1065 [PWRAP_HARB_HPRIO] = 0x50, 1066 [PWRAP_HIPRIO_ARB_EN] = 0x54, 1067 [PWRAP_HARB_STA0] = 0x58, 1068 [PWRAP_HARB_STA1] = 0x5c, 1069 [PWRAP_MAN_EN] = 0x60, 1070 [PWRAP_MAN_CMD] = 0x64, 1071 [PWRAP_MAN_RDATA] = 0x68, 1072 [PWRAP_MAN_VLDCLR] = 0x6c, 1073 [PWRAP_WACS0_EN] = 0x70, 1074 [PWRAP_INIT_DONE0] = 0x74, 1075 [PWRAP_WACS0_CMD] = 0x78, 1076 [PWRAP_WACS0_RDATA] = 0x7c, 1077 [PWRAP_WACS0_VLDCLR] = 0x80, 1078 [PWRAP_WACS1_EN] = 0x84, 1079 [PWRAP_INIT_DONE1] = 0x88, 1080 [PWRAP_WACS1_CMD] = 0x8c, 1081 [PWRAP_WACS1_RDATA] = 0x90, 1082 [PWRAP_WACS1_VLDCLR] = 0x94, 1083 [PWRAP_WACS2_EN] = 0x98, 1084 [PWRAP_INIT_DONE2] = 0x9c, 1085 [PWRAP_WACS2_CMD] = 0xa0, 1086 [PWRAP_WACS2_RDATA] = 0xa4, 1087 [PWRAP_WACS2_VLDCLR] = 0xa8, 1088 [PWRAP_INT_EN] = 0xac, 1089 [PWRAP_INT_FLG_RAW] = 0xb0, 1090 [PWRAP_INT_FLG] = 0xb4, 1091 [PWRAP_INT_CLR] = 0xb8, 1092 [PWRAP_SIG_ADR] = 0xbc, 1093 [PWRAP_SIG_MODE] = 0xc0, 1094 [PWRAP_SIG_VALUE] = 0xc4, 1095 [PWRAP_SIG_ERRVAL] = 0xc8, 1096 [PWRAP_CRC_EN] = 0xcc, 1097 [PWRAP_TIMER_EN] = 0xd0, 1098 [PWRAP_TIMER_STA] = 0xd4, 1099 [PWRAP_WDT_UNIT] = 0xd8, 1100 [PWRAP_WDT_SRC_EN] = 0xdc, 1101 [PWRAP_WDT_FLG] = 0xe0, 1102 [PWRAP_DEBUG_INT_SEL] = 0xe4, 1103 [PWRAP_DVFS_ADR0] = 0xe8, 1104 [PWRAP_DVFS_WDATA0] = 0xec, 1105 [PWRAP_DVFS_ADR1] = 0xf0, 1106 [PWRAP_DVFS_WDATA1] = 0xf4, 1107 [PWRAP_DVFS_ADR2] = 0xf8, 1108 [PWRAP_DVFS_WDATA2] = 0xfc, 1109 [PWRAP_DVFS_ADR3] = 0x100, 1110 [PWRAP_DVFS_WDATA3] = 0x104, 1111 [PWRAP_DVFS_ADR4] = 0x108, 1112 [PWRAP_DVFS_WDATA4] = 0x10c, 1113 [PWRAP_DVFS_ADR5] = 0x110, 1114 [PWRAP_DVFS_WDATA5] = 0x114, 1115 [PWRAP_DVFS_ADR6] = 0x118, 1116 [PWRAP_DVFS_WDATA6] = 0x11c, 1117 [PWRAP_DVFS_ADR7] = 0x120, 1118 [PWRAP_DVFS_WDATA7] = 0x124, 1119 [PWRAP_SPMINF_STA] = 0x128, 1120 [PWRAP_CIPHER_KEY_SEL] = 0x12c, 1121 [PWRAP_CIPHER_IV_SEL] = 0x130, 1122 [PWRAP_CIPHER_EN] = 0x134, 1123 [PWRAP_CIPHER_RDY] = 0x138, 1124 [PWRAP_CIPHER_MODE] = 0x13c, 1125 [PWRAP_CIPHER_SWRST] = 0x140, 1126 [PWRAP_DCM_EN] = 0x144, 1127 [PWRAP_DCM_DBC_PRD] = 0x148, 1128 [PWRAP_SW_RST] = 0x168, 1129 [PWRAP_OP_TYPE] = 0x16c, 1130 [PWRAP_MSB_FIRST] = 0x170, 1131 }; 1132 1133 static int mt8186_regs[] = { 1134 [PWRAP_MUX_SEL] = 0x0, 1135 [PWRAP_WRAP_EN] = 0x4, 1136 [PWRAP_DIO_EN] = 0x8, 1137 [PWRAP_RDDMY] = 0x20, 1138 [PWRAP_CSHEXT_WRITE] = 0x24, 1139 [PWRAP_CSHEXT_READ] = 0x28, 1140 [PWRAP_CSLEXT_WRITE] = 0x2C, 1141 [PWRAP_CSLEXT_READ] = 0x30, 1142 [PWRAP_EXT_CK_WRITE] = 0x34, 1143 [PWRAP_STAUPD_CTRL] = 0x3C, 1144 [PWRAP_STAUPD_GRPEN] = 0x40, 1145 [PWRAP_EINT_STA0_ADR] = 0x44, 1146 [PWRAP_EINT_STA1_ADR] = 0x48, 1147 [PWRAP_INT_CLR] = 0xC8, 1148 [PWRAP_INT_FLG] = 0xC4, 1149 [PWRAP_MAN_EN] = 0x7C, 1150 [PWRAP_MAN_CMD] = 0x80, 1151 [PWRAP_WACS0_EN] = 0x8C, 1152 [PWRAP_WACS1_EN] = 0x94, 1153 [PWRAP_WACS2_EN] = 0x9C, 1154 [PWRAP_INIT_DONE0] = 0x90, 1155 [PWRAP_INIT_DONE1] = 0x98, 1156 [PWRAP_INIT_DONE2] = 0xA0, 1157 [PWRAP_INT_EN] = 0xBC, 1158 [PWRAP_INT1_EN] = 0xCC, 1159 [PWRAP_INT1_FLG] = 0xD4, 1160 [PWRAP_INT1_CLR] = 0xD8, 1161 [PWRAP_TIMER_EN] = 0xF0, 1162 [PWRAP_WDT_UNIT] = 0xF8, 1163 [PWRAP_WDT_SRC_EN] = 0xFC, 1164 [PWRAP_WDT_SRC_EN_1] = 0x100, 1165 [PWRAP_WDT_FLG] = 0x104, 1166 [PWRAP_SPMINF_STA] = 0x1B4, 1167 [PWRAP_DCM_EN] = 0x1EC, 1168 [PWRAP_DCM_DBC_PRD] = 0x1F0, 1169 [PWRAP_GPSINF_0_STA] = 0x204, 1170 [PWRAP_GPSINF_1_STA] = 0x208, 1171 [PWRAP_WACS0_CMD] = 0xC00, 1172 [PWRAP_WACS0_RDATA] = 0xC04, 1173 [PWRAP_WACS0_VLDCLR] = 0xC08, 1174 [PWRAP_WACS1_CMD] = 0xC10, 1175 [PWRAP_WACS1_RDATA] = 0xC14, 1176 [PWRAP_WACS1_VLDCLR] = 0xC18, 1177 [PWRAP_WACS2_CMD] = 0xC20, 1178 [PWRAP_WACS2_RDATA] = 0xC24, 1179 [PWRAP_WACS2_VLDCLR] = 0xC28, 1180 }; 1181 1182 enum pmic_type { 1183 PMIC_MT6323, 1184 PMIC_MT6351, 1185 PMIC_MT6357, 1186 PMIC_MT6358, 1187 PMIC_MT6359, 1188 PMIC_MT6380, 1189 PMIC_MT6397, 1190 }; 1191 1192 enum pwrap_type { 1193 PWRAP_MT2701, 1194 PWRAP_MT6765, 1195 PWRAP_MT6779, 1196 PWRAP_MT6797, 1197 PWRAP_MT6873, 1198 PWRAP_MT7622, 1199 PWRAP_MT8135, 1200 PWRAP_MT8173, 1201 PWRAP_MT8183, 1202 PWRAP_MT8186, 1203 PWRAP_MT8195, 1204 PWRAP_MT8365, 1205 PWRAP_MT8516, 1206 }; 1207 1208 struct pmic_wrapper; 1209 1210 struct pwrap_slv_regops { 1211 const struct regmap_config *regmap; 1212 /* 1213 * pwrap operations are highly associated with the PMIC types, 1214 * so the pointers added increases flexibility allowing determination 1215 * which type is used by the detection through device tree. 1216 */ 1217 int (*pwrap_read)(struct pmic_wrapper *wrp, u32 adr, u32 *rdata); 1218 int (*pwrap_write)(struct pmic_wrapper *wrp, u32 adr, u32 wdata); 1219 }; 1220 1221 struct pwrap_slv_type { 1222 const u32 *dew_regs; 1223 enum pmic_type type; 1224 const struct pwrap_slv_regops *regops; 1225 /* Flags indicating the capability for the target slave */ 1226 u32 caps; 1227 }; 1228 1229 struct pmic_wrapper { 1230 struct device *dev; 1231 void __iomem *base; 1232 struct regmap *regmap; 1233 const struct pmic_wrapper_type *master; 1234 const struct pwrap_slv_type *slave; 1235 struct clk *clk_spi; 1236 struct clk *clk_wrap; 1237 struct clk *clk_sys; 1238 struct clk *clk_tmr; 1239 struct reset_control *rstc; 1240 1241 struct reset_control *rstc_bridge; 1242 void __iomem *bridge_base; 1243 }; 1244 1245 struct pmic_wrapper_type { 1246 int *regs; 1247 enum pwrap_type type; 1248 u32 arb_en_all; 1249 u32 int_en_all; 1250 u32 int1_en_all; 1251 u32 spi_w; 1252 u32 wdt_src; 1253 /* Flags indicating the capability for the target pwrap */ 1254 u32 caps; 1255 int (*init_reg_clock)(struct pmic_wrapper *wrp); 1256 int (*init_soc_specific)(struct pmic_wrapper *wrp); 1257 }; 1258 1259 static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg) 1260 { 1261 return readl(wrp->base + wrp->master->regs[reg]); 1262 } 1263 1264 static void pwrap_writel(struct pmic_wrapper *wrp, u32 val, enum pwrap_regs reg) 1265 { 1266 writel(val, wrp->base + wrp->master->regs[reg]); 1267 } 1268 1269 static u32 pwrap_get_fsm_state(struct pmic_wrapper *wrp) 1270 { 1271 u32 val; 1272 1273 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA); 1274 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) 1275 return PWRAP_GET_WACS_ARB_FSM(val); 1276 else 1277 return PWRAP_GET_WACS_FSM(val); 1278 } 1279 1280 static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp) 1281 { 1282 return pwrap_get_fsm_state(wrp) == PWRAP_WACS_FSM_IDLE; 1283 } 1284 1285 static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp) 1286 { 1287 return pwrap_get_fsm_state(wrp) == PWRAP_WACS_FSM_WFVLDCLR; 1288 } 1289 1290 /* 1291 * Timeout issue sometimes caused by the last read command 1292 * failed because pmic wrap could not got the FSM_VLDCLR 1293 * in time after finishing WACS2_CMD. It made state machine 1294 * still on FSM_VLDCLR and timeout next time. 1295 * Check the status of FSM and clear the vldclr to recovery the 1296 * error. 1297 */ 1298 static inline void pwrap_leave_fsm_vldclr(struct pmic_wrapper *wrp) 1299 { 1300 if (pwrap_is_fsm_vldclr(wrp)) 1301 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR); 1302 } 1303 1304 static bool pwrap_is_sync_idle(struct pmic_wrapper *wrp) 1305 { 1306 return pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_SYNC_IDLE0; 1307 } 1308 1309 static bool pwrap_is_fsm_idle_and_sync_idle(struct pmic_wrapper *wrp) 1310 { 1311 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA); 1312 1313 return (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE) && 1314 (val & PWRAP_STATE_SYNC_IDLE0); 1315 } 1316 1317 static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata) 1318 { 1319 bool tmp; 1320 int ret; 1321 u32 val; 1322 1323 ret = readx_poll_timeout(pwrap_is_fsm_idle, wrp, tmp, tmp, 1324 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1325 if (ret) { 1326 pwrap_leave_fsm_vldclr(wrp); 1327 return ret; 1328 } 1329 1330 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) 1331 val = adr; 1332 else 1333 val = (adr >> 1) << 16; 1334 pwrap_writel(wrp, val, PWRAP_WACS2_CMD); 1335 1336 ret = readx_poll_timeout(pwrap_is_fsm_vldclr, wrp, tmp, tmp, 1337 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1338 if (ret) 1339 return ret; 1340 1341 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) 1342 val = pwrap_readl(wrp, PWRAP_SWINF_2_RDATA_31_0); 1343 else 1344 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA); 1345 *rdata = PWRAP_GET_WACS_RDATA(val); 1346 1347 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR); 1348 1349 return 0; 1350 } 1351 1352 static int pwrap_read32(struct pmic_wrapper *wrp, u32 adr, u32 *rdata) 1353 { 1354 bool tmp; 1355 int ret, msb; 1356 1357 *rdata = 0; 1358 for (msb = 0; msb < 2; msb++) { 1359 ret = readx_poll_timeout(pwrap_is_fsm_idle, wrp, tmp, tmp, 1360 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1361 1362 if (ret) { 1363 pwrap_leave_fsm_vldclr(wrp); 1364 return ret; 1365 } 1366 1367 pwrap_writel(wrp, ((msb << 30) | (adr << 16)), 1368 PWRAP_WACS2_CMD); 1369 1370 ret = readx_poll_timeout(pwrap_is_fsm_vldclr, wrp, tmp, tmp, 1371 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1372 if (ret) 1373 return ret; 1374 1375 *rdata += (PWRAP_GET_WACS_RDATA(pwrap_readl(wrp, 1376 PWRAP_WACS2_RDATA)) << (16 * msb)); 1377 1378 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR); 1379 } 1380 1381 return 0; 1382 } 1383 1384 static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata) 1385 { 1386 return wrp->slave->regops->pwrap_read(wrp, adr, rdata); 1387 } 1388 1389 static int pwrap_write16(struct pmic_wrapper *wrp, u32 adr, u32 wdata) 1390 { 1391 bool tmp; 1392 int ret; 1393 1394 ret = readx_poll_timeout(pwrap_is_fsm_idle, wrp, tmp, tmp, 1395 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1396 if (ret) { 1397 pwrap_leave_fsm_vldclr(wrp); 1398 return ret; 1399 } 1400 1401 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) { 1402 pwrap_writel(wrp, wdata, PWRAP_SWINF_2_WDATA_31_0); 1403 pwrap_writel(wrp, BIT(29) | adr, PWRAP_WACS2_CMD); 1404 } else { 1405 pwrap_writel(wrp, BIT(31) | ((adr >> 1) << 16) | wdata, 1406 PWRAP_WACS2_CMD); 1407 } 1408 1409 return 0; 1410 } 1411 1412 static int pwrap_write32(struct pmic_wrapper *wrp, u32 adr, u32 wdata) 1413 { 1414 bool tmp; 1415 int ret, msb, rdata; 1416 1417 for (msb = 0; msb < 2; msb++) { 1418 ret = readx_poll_timeout(pwrap_is_fsm_idle, wrp, tmp, tmp, 1419 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1420 if (ret) { 1421 pwrap_leave_fsm_vldclr(wrp); 1422 return ret; 1423 } 1424 1425 pwrap_writel(wrp, (1 << 31) | (msb << 30) | (adr << 16) | 1426 ((wdata >> (msb * 16)) & 0xffff), 1427 PWRAP_WACS2_CMD); 1428 1429 /* 1430 * The pwrap_read operation is the requirement of hardware used 1431 * for the synchronization between two successive 16-bit 1432 * pwrap_writel operations composing one 32-bit bus writing. 1433 * Otherwise, we'll find the result fails on the lower 16-bit 1434 * pwrap writing. 1435 */ 1436 if (!msb) 1437 pwrap_read(wrp, adr, &rdata); 1438 } 1439 1440 return 0; 1441 } 1442 1443 static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata) 1444 { 1445 return wrp->slave->regops->pwrap_write(wrp, adr, wdata); 1446 } 1447 1448 static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata) 1449 { 1450 return pwrap_read(context, adr, rdata); 1451 } 1452 1453 static int pwrap_regmap_write(void *context, u32 adr, u32 wdata) 1454 { 1455 return pwrap_write(context, adr, wdata); 1456 } 1457 1458 static int pwrap_reset_spislave(struct pmic_wrapper *wrp) 1459 { 1460 bool tmp; 1461 int ret, i; 1462 1463 pwrap_writel(wrp, 0, PWRAP_HIPRIO_ARB_EN); 1464 pwrap_writel(wrp, 0, PWRAP_WRAP_EN); 1465 pwrap_writel(wrp, 1, PWRAP_MUX_SEL); 1466 pwrap_writel(wrp, 1, PWRAP_MAN_EN); 1467 pwrap_writel(wrp, 0, PWRAP_DIO_EN); 1468 1469 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSL, 1470 PWRAP_MAN_CMD); 1471 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS, 1472 PWRAP_MAN_CMD); 1473 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSH, 1474 PWRAP_MAN_CMD); 1475 1476 for (i = 0; i < 4; i++) 1477 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS, 1478 PWRAP_MAN_CMD); 1479 1480 ret = readx_poll_timeout(pwrap_is_sync_idle, wrp, tmp, tmp, 1481 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1482 if (ret) { 1483 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret); 1484 return ret; 1485 } 1486 1487 pwrap_writel(wrp, 0, PWRAP_MAN_EN); 1488 pwrap_writel(wrp, 0, PWRAP_MUX_SEL); 1489 1490 return 0; 1491 } 1492 1493 /* 1494 * pwrap_init_sidly - configure serial input delay 1495 * 1496 * This configures the serial input delay. We can configure 0, 2, 4 or 6ns 1497 * delay. Do a read test with all possible values and chose the best delay. 1498 */ 1499 static int pwrap_init_sidly(struct pmic_wrapper *wrp) 1500 { 1501 u32 rdata; 1502 u32 i; 1503 u32 pass = 0; 1504 signed char dly[16] = { 1505 -1, 0, 1, 0, 2, -1, 1, 1, 3, -1, -1, -1, 3, -1, 2, 1 1506 }; 1507 1508 for (i = 0; i < 4; i++) { 1509 pwrap_writel(wrp, i, PWRAP_SIDLY); 1510 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], 1511 &rdata); 1512 if (rdata == PWRAP_DEW_READ_TEST_VAL) { 1513 dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i); 1514 pass |= 1 << i; 1515 } 1516 } 1517 1518 if (dly[pass] < 0) { 1519 dev_err(wrp->dev, "sidly pass range 0x%x not continuous\n", 1520 pass); 1521 return -EIO; 1522 } 1523 1524 pwrap_writel(wrp, dly[pass], PWRAP_SIDLY); 1525 1526 return 0; 1527 } 1528 1529 static int pwrap_init_dual_io(struct pmic_wrapper *wrp) 1530 { 1531 int ret; 1532 bool tmp; 1533 u32 rdata; 1534 1535 /* Enable dual IO mode */ 1536 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1); 1537 1538 /* Check IDLE & INIT_DONE in advance */ 1539 ret = readx_poll_timeout(pwrap_is_fsm_idle_and_sync_idle, wrp, tmp, tmp, 1540 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1541 if (ret) { 1542 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret); 1543 return ret; 1544 } 1545 1546 pwrap_writel(wrp, 1, PWRAP_DIO_EN); 1547 1548 /* Read Test */ 1549 pwrap_read(wrp, 1550 wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata); 1551 if (rdata != PWRAP_DEW_READ_TEST_VAL) { 1552 dev_err(wrp->dev, 1553 "Read failed on DIO mode: 0x%04x!=0x%04x\n", 1554 PWRAP_DEW_READ_TEST_VAL, rdata); 1555 return -EFAULT; 1556 } 1557 1558 return 0; 1559 } 1560 1561 /* 1562 * pwrap_init_chip_select_ext is used to configure CS extension time for each 1563 * phase during data transactions on the pwrap bus. 1564 */ 1565 static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write, 1566 u8 hext_read, u8 lext_start, 1567 u8 lext_end) 1568 { 1569 /* 1570 * After finishing a write and read transaction, extends CS high time 1571 * to be at least xT of BUS CLK as hext_write and hext_read specifies 1572 * respectively. 1573 */ 1574 pwrap_writel(wrp, hext_write, PWRAP_CSHEXT_WRITE); 1575 pwrap_writel(wrp, hext_read, PWRAP_CSHEXT_READ); 1576 1577 /* 1578 * Extends CS low time after CSL and before CSH command to be at 1579 * least xT of BUS CLK as lext_start and lext_end specifies 1580 * respectively. 1581 */ 1582 pwrap_writel(wrp, lext_start, PWRAP_CSLEXT_START); 1583 pwrap_writel(wrp, lext_end, PWRAP_CSLEXT_END); 1584 } 1585 1586 static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp) 1587 { 1588 switch (wrp->master->type) { 1589 case PWRAP_MT8173: 1590 pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2); 1591 break; 1592 case PWRAP_MT8135: 1593 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT); 1594 pwrap_init_chip_select_ext(wrp, 0, 4, 0, 0); 1595 break; 1596 default: 1597 break; 1598 } 1599 1600 return 0; 1601 } 1602 1603 static int pwrap_mt2701_init_reg_clock(struct pmic_wrapper *wrp) 1604 { 1605 switch (wrp->slave->type) { 1606 case PMIC_MT6397: 1607 pwrap_writel(wrp, 0xc, PWRAP_RDDMY); 1608 pwrap_init_chip_select_ext(wrp, 4, 0, 2, 2); 1609 break; 1610 1611 case PMIC_MT6323: 1612 pwrap_writel(wrp, 0x8, PWRAP_RDDMY); 1613 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO], 1614 0x8); 1615 pwrap_init_chip_select_ext(wrp, 5, 0, 2, 2); 1616 break; 1617 default: 1618 break; 1619 } 1620 1621 return 0; 1622 } 1623 1624 static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp) 1625 { 1626 return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1; 1627 } 1628 1629 static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp) 1630 { 1631 u32 rdata; 1632 int ret; 1633 1634 ret = pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_RDY], 1635 &rdata); 1636 if (ret) 1637 return false; 1638 1639 return rdata == 1; 1640 } 1641 1642 static int pwrap_init_cipher(struct pmic_wrapper *wrp) 1643 { 1644 int ret; 1645 bool tmp; 1646 u32 rdata = 0; 1647 1648 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_SWRST); 1649 pwrap_writel(wrp, 0x0, PWRAP_CIPHER_SWRST); 1650 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_KEY_SEL); 1651 pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL); 1652 1653 switch (wrp->master->type) { 1654 case PWRAP_MT8135: 1655 pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD); 1656 pwrap_writel(wrp, 1, PWRAP_CIPHER_START); 1657 break; 1658 case PWRAP_MT2701: 1659 case PWRAP_MT6765: 1660 case PWRAP_MT6779: 1661 case PWRAP_MT6797: 1662 case PWRAP_MT8173: 1663 case PWRAP_MT8186: 1664 case PWRAP_MT8365: 1665 case PWRAP_MT8516: 1666 pwrap_writel(wrp, 1, PWRAP_CIPHER_EN); 1667 break; 1668 case PWRAP_MT7622: 1669 pwrap_writel(wrp, 0, PWRAP_CIPHER_EN); 1670 break; 1671 case PWRAP_MT6873: 1672 case PWRAP_MT8183: 1673 case PWRAP_MT8195: 1674 break; 1675 } 1676 1677 /* Config cipher mode @PMIC */ 1678 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1); 1679 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0); 1680 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1); 1681 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2); 1682 1683 switch (wrp->slave->type) { 1684 case PMIC_MT6397: 1685 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD], 1686 0x1); 1687 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START], 1688 0x1); 1689 break; 1690 case PMIC_MT6323: 1691 case PMIC_MT6351: 1692 case PMIC_MT6357: 1693 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN], 1694 0x1); 1695 break; 1696 default: 1697 break; 1698 } 1699 1700 /* wait for cipher data ready@AP */ 1701 ret = readx_poll_timeout(pwrap_is_cipher_ready, wrp, tmp, tmp, 1702 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1703 if (ret) { 1704 dev_err(wrp->dev, "cipher data ready@AP fail, ret=%d\n", ret); 1705 return ret; 1706 } 1707 1708 /* wait for cipher data ready@PMIC */ 1709 ret = readx_poll_timeout(pwrap_is_pmic_cipher_ready, wrp, tmp, tmp, 1710 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1711 if (ret) { 1712 dev_err(wrp->dev, 1713 "timeout waiting for cipher data ready@PMIC\n"); 1714 return ret; 1715 } 1716 1717 /* wait for cipher mode idle */ 1718 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_MODE], 0x1); 1719 ret = readx_poll_timeout(pwrap_is_fsm_idle_and_sync_idle, wrp, tmp, tmp, 1720 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1721 if (ret) { 1722 dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret); 1723 return ret; 1724 } 1725 1726 pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE); 1727 1728 /* Write Test */ 1729 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST], 1730 PWRAP_DEW_WRITE_TEST_VAL) || 1731 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST], 1732 &rdata) || 1733 (rdata != PWRAP_DEW_WRITE_TEST_VAL)) { 1734 dev_err(wrp->dev, "rdata=0x%04X\n", rdata); 1735 return -EFAULT; 1736 } 1737 1738 return 0; 1739 } 1740 1741 static int pwrap_init_security(struct pmic_wrapper *wrp) 1742 { 1743 int ret; 1744 1745 /* Enable encryption */ 1746 ret = pwrap_init_cipher(wrp); 1747 if (ret) 1748 return ret; 1749 1750 /* Signature checking - using CRC */ 1751 if (pwrap_write(wrp, 1752 wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1)) 1753 return -EFAULT; 1754 1755 pwrap_writel(wrp, 0x1, PWRAP_CRC_EN); 1756 pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE); 1757 pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL], 1758 PWRAP_SIG_ADR); 1759 pwrap_writel(wrp, 1760 wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN); 1761 1762 return 0; 1763 } 1764 1765 static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp) 1766 { 1767 /* enable pwrap events and pwrap bridge in AP side */ 1768 pwrap_writel(wrp, 0x1, PWRAP_EVENT_IN_EN); 1769 pwrap_writel(wrp, 0xffff, PWRAP_EVENT_DST_EN); 1770 writel(0x7f, wrp->bridge_base + PWRAP_MT8135_BRIDGE_IORD_ARB_EN); 1771 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS3_EN); 1772 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS4_EN); 1773 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_UNIT); 1774 writel(0xffff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_SRC_EN); 1775 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_TIMER_EN); 1776 writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN); 1777 1778 /* enable PMIC event out and sources */ 1779 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN], 1780 0x1) || 1781 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN], 1782 0xffff)) { 1783 dev_err(wrp->dev, "enable dewrap fail\n"); 1784 return -EFAULT; 1785 } 1786 1787 return 0; 1788 } 1789 1790 static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp) 1791 { 1792 /* PMIC_DEWRAP enables */ 1793 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN], 1794 0x1) || 1795 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN], 1796 0xffff)) { 1797 dev_err(wrp->dev, "enable dewrap fail\n"); 1798 return -EFAULT; 1799 } 1800 1801 return 0; 1802 } 1803 1804 static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp) 1805 { 1806 /* GPS_INTF initialization */ 1807 switch (wrp->slave->type) { 1808 case PMIC_MT6323: 1809 pwrap_writel(wrp, 0x076c, PWRAP_ADC_CMD_ADDR); 1810 pwrap_writel(wrp, 0x8000, PWRAP_PWRAP_ADC_CMD); 1811 pwrap_writel(wrp, 0x072c, PWRAP_ADC_RDY_ADDR); 1812 pwrap_writel(wrp, 0x072e, PWRAP_ADC_RDATA_ADDR1); 1813 pwrap_writel(wrp, 0x0730, PWRAP_ADC_RDATA_ADDR2); 1814 break; 1815 default: 1816 break; 1817 } 1818 1819 return 0; 1820 } 1821 1822 static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp) 1823 { 1824 pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD); 1825 /* enable 2wire SPI master */ 1826 pwrap_writel(wrp, 0x8000000, PWRAP_SPI2_CTRL); 1827 1828 return 0; 1829 } 1830 1831 static int pwrap_mt8183_init_soc_specific(struct pmic_wrapper *wrp) 1832 { 1833 pwrap_writel(wrp, 0xf5, PWRAP_STAUPD_GRPEN); 1834 1835 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1); 1836 pwrap_writel(wrp, 1, PWRAP_CRC_EN); 1837 pwrap_writel(wrp, 0x416, PWRAP_SIG_ADR); 1838 pwrap_writel(wrp, 0x42e, PWRAP_EINT_STA0_ADR); 1839 1840 pwrap_writel(wrp, 1, PWRAP_WACS_P2P_EN); 1841 pwrap_writel(wrp, 1, PWRAP_WACS_MD32_EN); 1842 pwrap_writel(wrp, 1, PWRAP_INIT_DONE_P2P); 1843 pwrap_writel(wrp, 1, PWRAP_INIT_DONE_MD32); 1844 1845 return 0; 1846 } 1847 1848 static int pwrap_init(struct pmic_wrapper *wrp) 1849 { 1850 int ret; 1851 1852 if (wrp->rstc) 1853 reset_control_reset(wrp->rstc); 1854 if (wrp->rstc_bridge) 1855 reset_control_reset(wrp->rstc_bridge); 1856 1857 if (wrp->master->type == PWRAP_MT8173) { 1858 /* Enable DCM */ 1859 pwrap_writel(wrp, 3, PWRAP_DCM_EN); 1860 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD); 1861 } 1862 1863 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) { 1864 /* Reset SPI slave */ 1865 ret = pwrap_reset_spislave(wrp); 1866 if (ret) 1867 return ret; 1868 } 1869 1870 pwrap_writel(wrp, 1, PWRAP_WRAP_EN); 1871 1872 pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN); 1873 1874 pwrap_writel(wrp, 1, PWRAP_WACS2_EN); 1875 1876 ret = wrp->master->init_reg_clock(wrp); 1877 if (ret) 1878 return ret; 1879 1880 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) { 1881 /* Setup serial input delay */ 1882 ret = pwrap_init_sidly(wrp); 1883 if (ret) 1884 return ret; 1885 } 1886 1887 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_DUALIO)) { 1888 /* Enable dual I/O mode */ 1889 ret = pwrap_init_dual_io(wrp); 1890 if (ret) 1891 return ret; 1892 } 1893 1894 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SECURITY)) { 1895 /* Enable security on bus */ 1896 ret = pwrap_init_security(wrp); 1897 if (ret) 1898 return ret; 1899 } 1900 1901 if (wrp->master->type == PWRAP_MT8135) 1902 pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN); 1903 1904 pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN); 1905 pwrap_writel(wrp, 0x1, PWRAP_WACS1_EN); 1906 pwrap_writel(wrp, 0x1, PWRAP_WACS2_EN); 1907 pwrap_writel(wrp, 0x5, PWRAP_STAUPD_PRD); 1908 pwrap_writel(wrp, 0xff, PWRAP_STAUPD_GRPEN); 1909 1910 if (wrp->master->init_soc_specific) { 1911 ret = wrp->master->init_soc_specific(wrp); 1912 if (ret) 1913 return ret; 1914 } 1915 1916 /* Setup the init done registers */ 1917 pwrap_writel(wrp, 1, PWRAP_INIT_DONE2); 1918 pwrap_writel(wrp, 1, PWRAP_INIT_DONE0); 1919 pwrap_writel(wrp, 1, PWRAP_INIT_DONE1); 1920 1921 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) { 1922 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3); 1923 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4); 1924 } 1925 1926 return 0; 1927 } 1928 1929 static irqreturn_t pwrap_interrupt(int irqno, void *dev_id) 1930 { 1931 u32 rdata; 1932 struct pmic_wrapper *wrp = dev_id; 1933 1934 rdata = pwrap_readl(wrp, PWRAP_INT_FLG); 1935 dev_err(wrp->dev, "unexpected interrupt int=0x%x\n", rdata); 1936 pwrap_writel(wrp, 0xffffffff, PWRAP_INT_CLR); 1937 1938 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN)) { 1939 rdata = pwrap_readl(wrp, PWRAP_INT1_FLG); 1940 dev_err(wrp->dev, "unexpected interrupt int1=0x%x\n", rdata); 1941 pwrap_writel(wrp, 0xffffffff, PWRAP_INT1_CLR); 1942 } 1943 1944 return IRQ_HANDLED; 1945 } 1946 1947 static const struct regmap_config pwrap_regmap_config16 = { 1948 .reg_bits = 16, 1949 .val_bits = 16, 1950 .reg_stride = 2, 1951 .reg_read = pwrap_regmap_read, 1952 .reg_write = pwrap_regmap_write, 1953 .max_register = 0xffff, 1954 }; 1955 1956 static const struct regmap_config pwrap_regmap_config32 = { 1957 .reg_bits = 32, 1958 .val_bits = 32, 1959 .reg_stride = 4, 1960 .reg_read = pwrap_regmap_read, 1961 .reg_write = pwrap_regmap_write, 1962 .max_register = 0xffff, 1963 }; 1964 1965 static const struct pwrap_slv_regops pwrap_regops16 = { 1966 .pwrap_read = pwrap_read16, 1967 .pwrap_write = pwrap_write16, 1968 .regmap = &pwrap_regmap_config16, 1969 }; 1970 1971 static const struct pwrap_slv_regops pwrap_regops32 = { 1972 .pwrap_read = pwrap_read32, 1973 .pwrap_write = pwrap_write32, 1974 .regmap = &pwrap_regmap_config32, 1975 }; 1976 1977 static const struct pwrap_slv_type pmic_mt6323 = { 1978 .dew_regs = mt6323_regs, 1979 .type = PMIC_MT6323, 1980 .regops = &pwrap_regops16, 1981 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO | 1982 PWRAP_SLV_CAP_SECURITY, 1983 }; 1984 1985 static const struct pwrap_slv_type pmic_mt6351 = { 1986 .dew_regs = mt6351_regs, 1987 .type = PMIC_MT6351, 1988 .regops = &pwrap_regops16, 1989 .caps = 0, 1990 }; 1991 1992 static const struct pwrap_slv_type pmic_mt6357 = { 1993 .dew_regs = mt6357_regs, 1994 .type = PMIC_MT6357, 1995 .regops = &pwrap_regops16, 1996 .caps = 0, 1997 }; 1998 1999 static const struct pwrap_slv_type pmic_mt6358 = { 2000 .dew_regs = mt6358_regs, 2001 .type = PMIC_MT6358, 2002 .regops = &pwrap_regops16, 2003 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO, 2004 }; 2005 2006 static const struct pwrap_slv_type pmic_mt6359 = { 2007 .dew_regs = mt6359_regs, 2008 .type = PMIC_MT6359, 2009 .regops = &pwrap_regops16, 2010 .caps = PWRAP_SLV_CAP_DUALIO, 2011 }; 2012 2013 static const struct pwrap_slv_type pmic_mt6380 = { 2014 .dew_regs = NULL, 2015 .type = PMIC_MT6380, 2016 .regops = &pwrap_regops32, 2017 .caps = 0, 2018 }; 2019 2020 static const struct pwrap_slv_type pmic_mt6397 = { 2021 .dew_regs = mt6397_regs, 2022 .type = PMIC_MT6397, 2023 .regops = &pwrap_regops16, 2024 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO | 2025 PWRAP_SLV_CAP_SECURITY, 2026 }; 2027 2028 static const struct of_device_id of_slave_match_tbl[] = { 2029 { .compatible = "mediatek,mt6323", .data = &pmic_mt6323 }, 2030 { .compatible = "mediatek,mt6351", .data = &pmic_mt6351 }, 2031 { .compatible = "mediatek,mt6357", .data = &pmic_mt6357 }, 2032 { .compatible = "mediatek,mt6358", .data = &pmic_mt6358 }, 2033 { .compatible = "mediatek,mt6359", .data = &pmic_mt6359 }, 2034 2035 /* The MT6380 PMIC only implements a regulator, so we bind it 2036 * directly instead of using a MFD. 2037 */ 2038 { .compatible = "mediatek,mt6380-regulator", .data = &pmic_mt6380 }, 2039 { .compatible = "mediatek,mt6397", .data = &pmic_mt6397 }, 2040 { /* sentinel */ } 2041 }; 2042 MODULE_DEVICE_TABLE(of, of_slave_match_tbl); 2043 2044 static const struct pmic_wrapper_type pwrap_mt2701 = { 2045 .regs = mt2701_regs, 2046 .type = PWRAP_MT2701, 2047 .arb_en_all = 0x3f, 2048 .int_en_all = ~(u32)(BIT(31) | BIT(2)), 2049 .int1_en_all = 0, 2050 .spi_w = PWRAP_MAN_CMD_SPI_WRITE_NEW, 2051 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2052 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM, 2053 .init_reg_clock = pwrap_mt2701_init_reg_clock, 2054 .init_soc_specific = pwrap_mt2701_init_soc_specific, 2055 }; 2056 2057 static const struct pmic_wrapper_type pwrap_mt6765 = { 2058 .regs = mt6765_regs, 2059 .type = PWRAP_MT6765, 2060 .arb_en_all = 0x3fd35, 2061 .int_en_all = 0xffffffff, 2062 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2063 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2064 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM, 2065 .init_reg_clock = pwrap_common_init_reg_clock, 2066 .init_soc_specific = NULL, 2067 }; 2068 2069 static const struct pmic_wrapper_type pwrap_mt6779 = { 2070 .regs = mt6779_regs, 2071 .type = PWRAP_MT6779, 2072 .arb_en_all = 0xfbb7f, 2073 .int_en_all = 0xfffffffe, 2074 .int1_en_all = 0, 2075 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2076 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2077 .caps = 0, 2078 .init_reg_clock = pwrap_common_init_reg_clock, 2079 .init_soc_specific = NULL, 2080 }; 2081 2082 static const struct pmic_wrapper_type pwrap_mt6797 = { 2083 .regs = mt6797_regs, 2084 .type = PWRAP_MT6797, 2085 .arb_en_all = 0x01fff, 2086 .int_en_all = 0xffffffc6, 2087 .int1_en_all = 0, 2088 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2089 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2090 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM, 2091 .init_reg_clock = pwrap_common_init_reg_clock, 2092 .init_soc_specific = NULL, 2093 }; 2094 2095 static const struct pmic_wrapper_type pwrap_mt6873 = { 2096 .regs = mt6873_regs, 2097 .type = PWRAP_MT6873, 2098 .arb_en_all = 0x777f, 2099 .int_en_all = BIT(4) | BIT(5), 2100 .int1_en_all = 0, 2101 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2102 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2103 .caps = PWRAP_CAP_ARB, 2104 .init_reg_clock = pwrap_common_init_reg_clock, 2105 .init_soc_specific = NULL, 2106 }; 2107 2108 static const struct pmic_wrapper_type pwrap_mt7622 = { 2109 .regs = mt7622_regs, 2110 .type = PWRAP_MT7622, 2111 .arb_en_all = 0xff, 2112 .int_en_all = ~(u32)BIT(31), 2113 .int1_en_all = 0, 2114 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2115 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2116 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM, 2117 .init_reg_clock = pwrap_common_init_reg_clock, 2118 .init_soc_specific = pwrap_mt7622_init_soc_specific, 2119 }; 2120 2121 static const struct pmic_wrapper_type pwrap_mt8135 = { 2122 .regs = mt8135_regs, 2123 .type = PWRAP_MT8135, 2124 .arb_en_all = 0x1ff, 2125 .int_en_all = ~(u32)(BIT(31) | BIT(1)), 2126 .int1_en_all = 0, 2127 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2128 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2129 .caps = PWRAP_CAP_BRIDGE | PWRAP_CAP_RESET | PWRAP_CAP_DCM, 2130 .init_reg_clock = pwrap_common_init_reg_clock, 2131 .init_soc_specific = pwrap_mt8135_init_soc_specific, 2132 }; 2133 2134 static const struct pmic_wrapper_type pwrap_mt8173 = { 2135 .regs = mt8173_regs, 2136 .type = PWRAP_MT8173, 2137 .arb_en_all = 0x3f, 2138 .int_en_all = ~(u32)(BIT(31) | BIT(1)), 2139 .int1_en_all = 0, 2140 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2141 .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD, 2142 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM, 2143 .init_reg_clock = pwrap_common_init_reg_clock, 2144 .init_soc_specific = pwrap_mt8173_init_soc_specific, 2145 }; 2146 2147 static const struct pmic_wrapper_type pwrap_mt8183 = { 2148 .regs = mt8183_regs, 2149 .type = PWRAP_MT8183, 2150 .arb_en_all = 0x3fa75, 2151 .int_en_all = 0xffffffff, 2152 .int1_en_all = 0xeef7ffff, 2153 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2154 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2155 .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_WDT_SRC1, 2156 .init_reg_clock = pwrap_common_init_reg_clock, 2157 .init_soc_specific = pwrap_mt8183_init_soc_specific, 2158 }; 2159 2160 static struct pmic_wrapper_type pwrap_mt8195 = { 2161 .regs = mt8195_regs, 2162 .type = PWRAP_MT8195, 2163 .arb_en_all = 0x777f, /* NEED CONFIRM */ 2164 .int_en_all = 0x180000, /* NEED CONFIRM */ 2165 .int1_en_all = 0, 2166 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2167 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2168 .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_ARB, 2169 .init_reg_clock = pwrap_common_init_reg_clock, 2170 .init_soc_specific = NULL, 2171 }; 2172 2173 static const struct pmic_wrapper_type pwrap_mt8365 = { 2174 .regs = mt8365_regs, 2175 .type = PWRAP_MT8365, 2176 .arb_en_all = 0x3ffff, 2177 .int_en_all = 0x7f1fffff, 2178 .int1_en_all = 0x0, 2179 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2180 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2181 .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_WDT_SRC1, 2182 .init_reg_clock = pwrap_common_init_reg_clock, 2183 .init_soc_specific = NULL, 2184 }; 2185 2186 static struct pmic_wrapper_type pwrap_mt8516 = { 2187 .regs = mt8516_regs, 2188 .type = PWRAP_MT8516, 2189 .arb_en_all = 0xff, 2190 .int_en_all = ~(u32)(BIT(31) | BIT(2)), 2191 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2192 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2193 .caps = PWRAP_CAP_DCM, 2194 .init_reg_clock = pwrap_mt2701_init_reg_clock, 2195 .init_soc_specific = NULL, 2196 }; 2197 2198 static struct pmic_wrapper_type pwrap_mt8186 = { 2199 .regs = mt8186_regs, 2200 .type = PWRAP_MT8186, 2201 .arb_en_all = 0xfb27f, 2202 .int_en_all = 0xfffffffe, /* disable WatchDog Timeout for bit 1 */ 2203 .int1_en_all = 0x000017ff, /* disable Matching interrupt for bit 13 */ 2204 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2205 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2206 .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_ARB_MT8186, 2207 .init_reg_clock = pwrap_common_init_reg_clock, 2208 .init_soc_specific = NULL, 2209 }; 2210 2211 static const struct of_device_id of_pwrap_match_tbl[] = { 2212 { .compatible = "mediatek,mt2701-pwrap", .data = &pwrap_mt2701 }, 2213 { .compatible = "mediatek,mt6765-pwrap", .data = &pwrap_mt6765 }, 2214 { .compatible = "mediatek,mt6779-pwrap", .data = &pwrap_mt6779 }, 2215 { .compatible = "mediatek,mt6797-pwrap", .data = &pwrap_mt6797 }, 2216 { .compatible = "mediatek,mt6873-pwrap", .data = &pwrap_mt6873 }, 2217 { .compatible = "mediatek,mt7622-pwrap", .data = &pwrap_mt7622 }, 2218 { .compatible = "mediatek,mt8135-pwrap", .data = &pwrap_mt8135 }, 2219 { .compatible = "mediatek,mt8173-pwrap", .data = &pwrap_mt8173 }, 2220 { .compatible = "mediatek,mt8183-pwrap", .data = &pwrap_mt8183 }, 2221 { .compatible = "mediatek,mt8186-pwrap", .data = &pwrap_mt8186 }, 2222 { .compatible = "mediatek,mt8195-pwrap", .data = &pwrap_mt8195 }, 2223 { .compatible = "mediatek,mt8365-pwrap", .data = &pwrap_mt8365 }, 2224 { .compatible = "mediatek,mt8516-pwrap", .data = &pwrap_mt8516 }, 2225 { /* sentinel */ } 2226 }; 2227 MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl); 2228 2229 static int pwrap_probe(struct platform_device *pdev) 2230 { 2231 int ret, irq; 2232 u32 mask_done; 2233 struct pmic_wrapper *wrp; 2234 struct device_node *np = pdev->dev.of_node; 2235 const struct of_device_id *of_slave_id = NULL; 2236 2237 if (np->child) 2238 of_slave_id = of_match_node(of_slave_match_tbl, np->child); 2239 2240 if (!of_slave_id) { 2241 dev_dbg(&pdev->dev, "slave pmic should be defined in dts\n"); 2242 return -EINVAL; 2243 } 2244 2245 wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL); 2246 if (!wrp) 2247 return -ENOMEM; 2248 2249 platform_set_drvdata(pdev, wrp); 2250 2251 wrp->master = of_device_get_match_data(&pdev->dev); 2252 wrp->slave = of_slave_id->data; 2253 wrp->dev = &pdev->dev; 2254 2255 wrp->base = devm_platform_ioremap_resource_byname(pdev, "pwrap"); 2256 if (IS_ERR(wrp->base)) 2257 return PTR_ERR(wrp->base); 2258 2259 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_RESET)) { 2260 wrp->rstc = devm_reset_control_get(wrp->dev, "pwrap"); 2261 if (IS_ERR(wrp->rstc)) { 2262 ret = PTR_ERR(wrp->rstc); 2263 dev_dbg(wrp->dev, "cannot get pwrap reset: %d\n", ret); 2264 return ret; 2265 } 2266 } 2267 2268 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) { 2269 wrp->bridge_base = devm_platform_ioremap_resource_byname(pdev, "pwrap-bridge"); 2270 if (IS_ERR(wrp->bridge_base)) 2271 return PTR_ERR(wrp->bridge_base); 2272 2273 wrp->rstc_bridge = devm_reset_control_get(wrp->dev, 2274 "pwrap-bridge"); 2275 if (IS_ERR(wrp->rstc_bridge)) { 2276 ret = PTR_ERR(wrp->rstc_bridge); 2277 dev_dbg(wrp->dev, 2278 "cannot get pwrap-bridge reset: %d\n", ret); 2279 return ret; 2280 } 2281 } 2282 2283 wrp->clk_spi = devm_clk_get(wrp->dev, "spi"); 2284 if (IS_ERR(wrp->clk_spi)) { 2285 dev_dbg(wrp->dev, "failed to get clock: %ld\n", 2286 PTR_ERR(wrp->clk_spi)); 2287 return PTR_ERR(wrp->clk_spi); 2288 } 2289 2290 wrp->clk_wrap = devm_clk_get(wrp->dev, "wrap"); 2291 if (IS_ERR(wrp->clk_wrap)) { 2292 dev_dbg(wrp->dev, "failed to get clock: %ld\n", 2293 PTR_ERR(wrp->clk_wrap)); 2294 return PTR_ERR(wrp->clk_wrap); 2295 } 2296 2297 wrp->clk_sys = devm_clk_get_optional(wrp->dev, "sys"); 2298 if (IS_ERR(wrp->clk_sys)) { 2299 return dev_err_probe(wrp->dev, PTR_ERR(wrp->clk_sys), 2300 "failed to get clock: %pe\n", 2301 wrp->clk_sys); 2302 } 2303 2304 wrp->clk_tmr = devm_clk_get_optional(wrp->dev, "tmr"); 2305 if (IS_ERR(wrp->clk_tmr)) { 2306 return dev_err_probe(wrp->dev, PTR_ERR(wrp->clk_tmr), 2307 "failed to get clock: %pe\n", 2308 wrp->clk_tmr); 2309 } 2310 2311 ret = clk_prepare_enable(wrp->clk_spi); 2312 if (ret) 2313 return ret; 2314 2315 ret = clk_prepare_enable(wrp->clk_wrap); 2316 if (ret) 2317 goto err_out1; 2318 2319 ret = clk_prepare_enable(wrp->clk_sys); 2320 if (ret) 2321 goto err_out2; 2322 2323 ret = clk_prepare_enable(wrp->clk_tmr); 2324 if (ret) 2325 goto err_out3; 2326 2327 /* Enable internal dynamic clock */ 2328 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_DCM)) { 2329 pwrap_writel(wrp, 1, PWRAP_DCM_EN); 2330 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD); 2331 } 2332 2333 /* 2334 * The PMIC could already be initialized by the bootloader. 2335 * Skip initialization here in this case. 2336 */ 2337 if (!pwrap_readl(wrp, PWRAP_INIT_DONE2)) { 2338 ret = pwrap_init(wrp); 2339 if (ret) { 2340 dev_dbg(wrp->dev, "init failed with %d\n", ret); 2341 goto err_out4; 2342 } 2343 } 2344 2345 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) 2346 mask_done = PWRAP_STATE_INIT_DONE1; 2347 else if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB_MT8186)) 2348 mask_done = PWRAP_STATE_INIT_DONE0_MT8186; 2349 else 2350 mask_done = PWRAP_STATE_INIT_DONE0; 2351 2352 if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & mask_done)) { 2353 dev_dbg(wrp->dev, "initialization isn't finished\n"); 2354 ret = -ENODEV; 2355 goto err_out4; 2356 } 2357 2358 /* Initialize watchdog, may not be done by the bootloader */ 2359 if (!HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) 2360 pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT); 2361 2362 /* 2363 * Since STAUPD was not used on mt8173 platform, 2364 * so STAUPD of WDT_SRC which should be turned off 2365 */ 2366 pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN); 2367 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_WDT_SRC1)) 2368 pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN_1); 2369 2370 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) 2371 pwrap_writel(wrp, 0x3, PWRAP_TIMER_EN); 2372 else 2373 pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN); 2374 2375 pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN); 2376 /* 2377 * We add INT1 interrupt to handle starvation and request exception 2378 * If we support it, we should enable it here. 2379 */ 2380 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN)) 2381 pwrap_writel(wrp, wrp->master->int1_en_all, PWRAP_INT1_EN); 2382 2383 irq = platform_get_irq(pdev, 0); 2384 if (irq < 0) { 2385 ret = irq; 2386 goto err_out2; 2387 } 2388 2389 ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt, 2390 IRQF_TRIGGER_HIGH, 2391 "mt-pmic-pwrap", wrp); 2392 if (ret) 2393 goto err_out4; 2394 2395 wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, wrp->slave->regops->regmap); 2396 if (IS_ERR(wrp->regmap)) { 2397 ret = PTR_ERR(wrp->regmap); 2398 goto err_out2; 2399 } 2400 2401 ret = of_platform_populate(np, NULL, NULL, wrp->dev); 2402 if (ret) { 2403 dev_dbg(wrp->dev, "failed to create child devices at %pOF\n", 2404 np); 2405 goto err_out4; 2406 } 2407 2408 return 0; 2409 2410 err_out4: 2411 clk_disable_unprepare(wrp->clk_tmr); 2412 err_out3: 2413 clk_disable_unprepare(wrp->clk_sys); 2414 err_out2: 2415 clk_disable_unprepare(wrp->clk_wrap); 2416 err_out1: 2417 clk_disable_unprepare(wrp->clk_spi); 2418 2419 return ret; 2420 } 2421 2422 static struct platform_driver pwrap_drv = { 2423 .driver = { 2424 .name = "mt-pmic-pwrap", 2425 .of_match_table = of_pwrap_match_tbl, 2426 }, 2427 .probe = pwrap_probe, 2428 }; 2429 2430 module_platform_driver(pwrap_drv); 2431 2432 MODULE_AUTHOR("Flora Fu, MediaTek"); 2433 MODULE_DESCRIPTION("MediaTek MT8135 PMIC Wrapper Driver"); 2434 MODULE_LICENSE("GPL v2"); 2435