1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Flora Fu, MediaTek 5 */ 6 #include <linux/clk.h> 7 #include <linux/interrupt.h> 8 #include <linux/io.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/of_device.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 #include <linux/reset.h> 15 16 #define PWRAP_MT8135_BRIDGE_IORD_ARB_EN 0x4 17 #define PWRAP_MT8135_BRIDGE_WACS3_EN 0x10 18 #define PWRAP_MT8135_BRIDGE_INIT_DONE3 0x14 19 #define PWRAP_MT8135_BRIDGE_WACS4_EN 0x24 20 #define PWRAP_MT8135_BRIDGE_INIT_DONE4 0x28 21 #define PWRAP_MT8135_BRIDGE_INT_EN 0x38 22 #define PWRAP_MT8135_BRIDGE_TIMER_EN 0x48 23 #define PWRAP_MT8135_BRIDGE_WDT_UNIT 0x50 24 #define PWRAP_MT8135_BRIDGE_WDT_SRC_EN 0x54 25 26 /* macro for wrapper status */ 27 #define PWRAP_GET_WACS_RDATA(x) (((x) >> 0) & 0x0000ffff) 28 #define PWRAP_GET_WACS_ARB_FSM(x) (((x) >> 1) & 0x00000007) 29 #define PWRAP_GET_WACS_FSM(x) (((x) >> 16) & 0x00000007) 30 #define PWRAP_GET_WACS_REQ(x) (((x) >> 19) & 0x00000001) 31 #define PWRAP_STATE_SYNC_IDLE0 BIT(20) 32 #define PWRAP_STATE_INIT_DONE0 BIT(21) 33 #define PWRAP_STATE_INIT_DONE1 BIT(15) 34 35 /* macro for WACS FSM */ 36 #define PWRAP_WACS_FSM_IDLE 0x00 37 #define PWRAP_WACS_FSM_REQ 0x02 38 #define PWRAP_WACS_FSM_WFDLE 0x04 39 #define PWRAP_WACS_FSM_WFVLDCLR 0x06 40 #define PWRAP_WACS_INIT_DONE 0x01 41 #define PWRAP_WACS_WACS_SYNC_IDLE 0x01 42 #define PWRAP_WACS_SYNC_BUSY 0x00 43 44 /* macro for device wrapper default value */ 45 #define PWRAP_DEW_READ_TEST_VAL 0x5aa5 46 #define PWRAP_DEW_WRITE_TEST_VAL 0xa55a 47 48 /* macro for manual command */ 49 #define PWRAP_MAN_CMD_SPI_WRITE_NEW (1 << 14) 50 #define PWRAP_MAN_CMD_SPI_WRITE (1 << 13) 51 #define PWRAP_MAN_CMD_OP_CSH (0x0 << 8) 52 #define PWRAP_MAN_CMD_OP_CSL (0x1 << 8) 53 #define PWRAP_MAN_CMD_OP_CK (0x2 << 8) 54 #define PWRAP_MAN_CMD_OP_OUTS (0x8 << 8) 55 #define PWRAP_MAN_CMD_OP_OUTD (0x9 << 8) 56 #define PWRAP_MAN_CMD_OP_OUTQ (0xa << 8) 57 58 /* macro for Watch Dog Timer Source */ 59 #define PWRAP_WDT_SRC_EN_STAUPD_TRIG (1 << 25) 60 #define PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE (1 << 20) 61 #define PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE (1 << 6) 62 #define PWRAP_WDT_SRC_MASK_ALL 0xffffffff 63 #define PWRAP_WDT_SRC_MASK_NO_STAUPD ~(PWRAP_WDT_SRC_EN_STAUPD_TRIG | \ 64 PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE | \ 65 PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE) 66 67 /* Group of bits used for shown slave capability */ 68 #define PWRAP_SLV_CAP_SPI BIT(0) 69 #define PWRAP_SLV_CAP_DUALIO BIT(1) 70 #define PWRAP_SLV_CAP_SECURITY BIT(2) 71 #define HAS_CAP(_c, _x) (((_c) & (_x)) == (_x)) 72 73 /* Group of bits used for shown pwrap capability */ 74 #define PWRAP_CAP_BRIDGE BIT(0) 75 #define PWRAP_CAP_RESET BIT(1) 76 #define PWRAP_CAP_DCM BIT(2) 77 #define PWRAP_CAP_INT1_EN BIT(3) 78 #define PWRAP_CAP_WDT_SRC1 BIT(4) 79 #define PWRAP_CAP_ARB BIT(5) 80 81 /* defines for slave device wrapper registers */ 82 enum dew_regs { 83 PWRAP_DEW_BASE, 84 PWRAP_DEW_DIO_EN, 85 PWRAP_DEW_READ_TEST, 86 PWRAP_DEW_WRITE_TEST, 87 PWRAP_DEW_CRC_EN, 88 PWRAP_DEW_CRC_VAL, 89 PWRAP_DEW_MON_GRP_SEL, 90 PWRAP_DEW_CIPHER_KEY_SEL, 91 PWRAP_DEW_CIPHER_IV_SEL, 92 PWRAP_DEW_CIPHER_RDY, 93 PWRAP_DEW_CIPHER_MODE, 94 PWRAP_DEW_CIPHER_SWRST, 95 96 /* MT6323 only regs */ 97 PWRAP_DEW_CIPHER_EN, 98 PWRAP_DEW_RDDMY_NO, 99 100 /* MT6358 only regs */ 101 PWRAP_SMT_CON1, 102 PWRAP_DRV_CON1, 103 PWRAP_FILTER_CON0, 104 PWRAP_GPIO_PULLEN0_CLR, 105 PWRAP_RG_SPI_CON0, 106 PWRAP_RG_SPI_RECORD0, 107 PWRAP_RG_SPI_CON2, 108 PWRAP_RG_SPI_CON3, 109 PWRAP_RG_SPI_CON4, 110 PWRAP_RG_SPI_CON5, 111 PWRAP_RG_SPI_CON6, 112 PWRAP_RG_SPI_CON7, 113 PWRAP_RG_SPI_CON8, 114 PWRAP_RG_SPI_CON13, 115 PWRAP_SPISLV_KEY, 116 117 /* MT6359 only regs */ 118 PWRAP_DEW_CRC_SWRST, 119 PWRAP_DEW_RG_EN_RECORD, 120 PWRAP_DEW_RECORD_CMD0, 121 PWRAP_DEW_RECORD_CMD1, 122 PWRAP_DEW_RECORD_CMD2, 123 PWRAP_DEW_RECORD_CMD3, 124 PWRAP_DEW_RECORD_CMD4, 125 PWRAP_DEW_RECORD_CMD5, 126 PWRAP_DEW_RECORD_WDATA0, 127 PWRAP_DEW_RECORD_WDATA1, 128 PWRAP_DEW_RECORD_WDATA2, 129 PWRAP_DEW_RECORD_WDATA3, 130 PWRAP_DEW_RECORD_WDATA4, 131 PWRAP_DEW_RECORD_WDATA5, 132 PWRAP_DEW_RG_ADDR_TARGET, 133 PWRAP_DEW_RG_ADDR_MASK, 134 PWRAP_DEW_RG_WDATA_TARGET, 135 PWRAP_DEW_RG_WDATA_MASK, 136 PWRAP_DEW_RG_SPI_RECORD_CLR, 137 PWRAP_DEW_RG_CMD_ALERT_CLR, 138 139 /* MT6397 only regs */ 140 PWRAP_DEW_EVENT_OUT_EN, 141 PWRAP_DEW_EVENT_SRC_EN, 142 PWRAP_DEW_EVENT_SRC, 143 PWRAP_DEW_EVENT_FLAG, 144 PWRAP_DEW_MON_FLAG_SEL, 145 PWRAP_DEW_EVENT_TEST, 146 PWRAP_DEW_CIPHER_LOAD, 147 PWRAP_DEW_CIPHER_START, 148 }; 149 150 static const u32 mt6323_regs[] = { 151 [PWRAP_DEW_BASE] = 0x0000, 152 [PWRAP_DEW_DIO_EN] = 0x018a, 153 [PWRAP_DEW_READ_TEST] = 0x018c, 154 [PWRAP_DEW_WRITE_TEST] = 0x018e, 155 [PWRAP_DEW_CRC_EN] = 0x0192, 156 [PWRAP_DEW_CRC_VAL] = 0x0194, 157 [PWRAP_DEW_MON_GRP_SEL] = 0x0196, 158 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0198, 159 [PWRAP_DEW_CIPHER_IV_SEL] = 0x019a, 160 [PWRAP_DEW_CIPHER_EN] = 0x019c, 161 [PWRAP_DEW_CIPHER_RDY] = 0x019e, 162 [PWRAP_DEW_CIPHER_MODE] = 0x01a0, 163 [PWRAP_DEW_CIPHER_SWRST] = 0x01a2, 164 [PWRAP_DEW_RDDMY_NO] = 0x01a4, 165 }; 166 167 static const u32 mt6351_regs[] = { 168 [PWRAP_DEW_DIO_EN] = 0x02F2, 169 [PWRAP_DEW_READ_TEST] = 0x02F4, 170 [PWRAP_DEW_WRITE_TEST] = 0x02F6, 171 [PWRAP_DEW_CRC_EN] = 0x02FA, 172 [PWRAP_DEW_CRC_VAL] = 0x02FC, 173 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0300, 174 [PWRAP_DEW_CIPHER_IV_SEL] = 0x0302, 175 [PWRAP_DEW_CIPHER_EN] = 0x0304, 176 [PWRAP_DEW_CIPHER_RDY] = 0x0306, 177 [PWRAP_DEW_CIPHER_MODE] = 0x0308, 178 [PWRAP_DEW_CIPHER_SWRST] = 0x030A, 179 [PWRAP_DEW_RDDMY_NO] = 0x030C, 180 }; 181 182 static const u32 mt6357_regs[] = { 183 [PWRAP_DEW_DIO_EN] = 0x040A, 184 [PWRAP_DEW_READ_TEST] = 0x040C, 185 [PWRAP_DEW_WRITE_TEST] = 0x040E, 186 [PWRAP_DEW_CRC_EN] = 0x0412, 187 [PWRAP_DEW_CRC_VAL] = 0x0414, 188 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0418, 189 [PWRAP_DEW_CIPHER_IV_SEL] = 0x041A, 190 [PWRAP_DEW_CIPHER_EN] = 0x041C, 191 [PWRAP_DEW_CIPHER_RDY] = 0x041E, 192 [PWRAP_DEW_CIPHER_MODE] = 0x0420, 193 [PWRAP_DEW_CIPHER_SWRST] = 0x0422, 194 [PWRAP_DEW_RDDMY_NO] = 0x0424, 195 }; 196 197 static const u32 mt6358_regs[] = { 198 [PWRAP_SMT_CON1] = 0x0030, 199 [PWRAP_DRV_CON1] = 0x0038, 200 [PWRAP_FILTER_CON0] = 0x0040, 201 [PWRAP_GPIO_PULLEN0_CLR] = 0x0098, 202 [PWRAP_RG_SPI_CON0] = 0x0408, 203 [PWRAP_RG_SPI_RECORD0] = 0x040a, 204 [PWRAP_DEW_DIO_EN] = 0x040c, 205 [PWRAP_DEW_READ_TEST] = 0x040e, 206 [PWRAP_DEW_WRITE_TEST] = 0x0410, 207 [PWRAP_DEW_CRC_EN] = 0x0414, 208 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x041a, 209 [PWRAP_DEW_CIPHER_IV_SEL] = 0x041c, 210 [PWRAP_DEW_CIPHER_EN] = 0x041e, 211 [PWRAP_DEW_CIPHER_RDY] = 0x0420, 212 [PWRAP_DEW_CIPHER_MODE] = 0x0422, 213 [PWRAP_DEW_CIPHER_SWRST] = 0x0424, 214 [PWRAP_RG_SPI_CON2] = 0x0432, 215 [PWRAP_RG_SPI_CON3] = 0x0434, 216 [PWRAP_RG_SPI_CON4] = 0x0436, 217 [PWRAP_RG_SPI_CON5] = 0x0438, 218 [PWRAP_RG_SPI_CON6] = 0x043a, 219 [PWRAP_RG_SPI_CON7] = 0x043c, 220 [PWRAP_RG_SPI_CON8] = 0x043e, 221 [PWRAP_RG_SPI_CON13] = 0x0448, 222 [PWRAP_SPISLV_KEY] = 0x044a, 223 }; 224 225 static const u32 mt6359_regs[] = { 226 [PWRAP_DEW_RG_EN_RECORD] = 0x040a, 227 [PWRAP_DEW_DIO_EN] = 0x040c, 228 [PWRAP_DEW_READ_TEST] = 0x040e, 229 [PWRAP_DEW_WRITE_TEST] = 0x0410, 230 [PWRAP_DEW_CRC_SWRST] = 0x0412, 231 [PWRAP_DEW_CRC_EN] = 0x0414, 232 [PWRAP_DEW_CRC_VAL] = 0x0416, 233 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0418, 234 [PWRAP_DEW_CIPHER_IV_SEL] = 0x041a, 235 [PWRAP_DEW_CIPHER_EN] = 0x041c, 236 [PWRAP_DEW_CIPHER_RDY] = 0x041e, 237 [PWRAP_DEW_CIPHER_MODE] = 0x0420, 238 [PWRAP_DEW_CIPHER_SWRST] = 0x0422, 239 [PWRAP_DEW_RDDMY_NO] = 0x0424, 240 [PWRAP_DEW_RECORD_CMD0] = 0x0428, 241 [PWRAP_DEW_RECORD_CMD1] = 0x042a, 242 [PWRAP_DEW_RECORD_CMD2] = 0x042c, 243 [PWRAP_DEW_RECORD_CMD3] = 0x042e, 244 [PWRAP_DEW_RECORD_CMD4] = 0x0430, 245 [PWRAP_DEW_RECORD_CMD5] = 0x0432, 246 [PWRAP_DEW_RECORD_WDATA0] = 0x0434, 247 [PWRAP_DEW_RECORD_WDATA1] = 0x0436, 248 [PWRAP_DEW_RECORD_WDATA2] = 0x0438, 249 [PWRAP_DEW_RECORD_WDATA3] = 0x043a, 250 [PWRAP_DEW_RECORD_WDATA4] = 0x043c, 251 [PWRAP_DEW_RECORD_WDATA5] = 0x043e, 252 [PWRAP_DEW_RG_ADDR_TARGET] = 0x0440, 253 [PWRAP_DEW_RG_ADDR_MASK] = 0x0442, 254 [PWRAP_DEW_RG_WDATA_TARGET] = 0x0444, 255 [PWRAP_DEW_RG_WDATA_MASK] = 0x0446, 256 [PWRAP_DEW_RG_SPI_RECORD_CLR] = 0x0448, 257 [PWRAP_DEW_RG_CMD_ALERT_CLR] = 0x0448, 258 [PWRAP_SPISLV_KEY] = 0x044a, 259 }; 260 261 static const u32 mt6397_regs[] = { 262 [PWRAP_DEW_BASE] = 0xbc00, 263 [PWRAP_DEW_EVENT_OUT_EN] = 0xbc00, 264 [PWRAP_DEW_DIO_EN] = 0xbc02, 265 [PWRAP_DEW_EVENT_SRC_EN] = 0xbc04, 266 [PWRAP_DEW_EVENT_SRC] = 0xbc06, 267 [PWRAP_DEW_EVENT_FLAG] = 0xbc08, 268 [PWRAP_DEW_READ_TEST] = 0xbc0a, 269 [PWRAP_DEW_WRITE_TEST] = 0xbc0c, 270 [PWRAP_DEW_CRC_EN] = 0xbc0e, 271 [PWRAP_DEW_CRC_VAL] = 0xbc10, 272 [PWRAP_DEW_MON_GRP_SEL] = 0xbc12, 273 [PWRAP_DEW_MON_FLAG_SEL] = 0xbc14, 274 [PWRAP_DEW_EVENT_TEST] = 0xbc16, 275 [PWRAP_DEW_CIPHER_KEY_SEL] = 0xbc18, 276 [PWRAP_DEW_CIPHER_IV_SEL] = 0xbc1a, 277 [PWRAP_DEW_CIPHER_LOAD] = 0xbc1c, 278 [PWRAP_DEW_CIPHER_START] = 0xbc1e, 279 [PWRAP_DEW_CIPHER_RDY] = 0xbc20, 280 [PWRAP_DEW_CIPHER_MODE] = 0xbc22, 281 [PWRAP_DEW_CIPHER_SWRST] = 0xbc24, 282 }; 283 284 enum pwrap_regs { 285 PWRAP_MUX_SEL, 286 PWRAP_WRAP_EN, 287 PWRAP_DIO_EN, 288 PWRAP_SIDLY, 289 PWRAP_CSHEXT_WRITE, 290 PWRAP_CSHEXT_READ, 291 PWRAP_CSLEXT_START, 292 PWRAP_CSLEXT_END, 293 PWRAP_STAUPD_PRD, 294 PWRAP_STAUPD_GRPEN, 295 PWRAP_STAUPD_MAN_TRIG, 296 PWRAP_STAUPD_STA, 297 PWRAP_WRAP_STA, 298 PWRAP_HARB_INIT, 299 PWRAP_HARB_HPRIO, 300 PWRAP_HIPRIO_ARB_EN, 301 PWRAP_HARB_STA0, 302 PWRAP_HARB_STA1, 303 PWRAP_MAN_EN, 304 PWRAP_MAN_CMD, 305 PWRAP_MAN_RDATA, 306 PWRAP_MAN_VLDCLR, 307 PWRAP_WACS0_EN, 308 PWRAP_INIT_DONE0, 309 PWRAP_WACS0_CMD, 310 PWRAP_WACS0_RDATA, 311 PWRAP_WACS0_VLDCLR, 312 PWRAP_WACS1_EN, 313 PWRAP_INIT_DONE1, 314 PWRAP_WACS1_CMD, 315 PWRAP_WACS1_RDATA, 316 PWRAP_WACS1_VLDCLR, 317 PWRAP_WACS2_EN, 318 PWRAP_INIT_DONE2, 319 PWRAP_WACS2_CMD, 320 PWRAP_WACS2_RDATA, 321 PWRAP_WACS2_VLDCLR, 322 PWRAP_INT_EN, 323 PWRAP_INT_FLG_RAW, 324 PWRAP_INT_FLG, 325 PWRAP_INT_CLR, 326 PWRAP_SIG_ADR, 327 PWRAP_SIG_MODE, 328 PWRAP_SIG_VALUE, 329 PWRAP_SIG_ERRVAL, 330 PWRAP_CRC_EN, 331 PWRAP_TIMER_EN, 332 PWRAP_TIMER_STA, 333 PWRAP_WDT_UNIT, 334 PWRAP_WDT_SRC_EN, 335 PWRAP_WDT_FLG, 336 PWRAP_DEBUG_INT_SEL, 337 PWRAP_CIPHER_KEY_SEL, 338 PWRAP_CIPHER_IV_SEL, 339 PWRAP_CIPHER_RDY, 340 PWRAP_CIPHER_MODE, 341 PWRAP_CIPHER_SWRST, 342 PWRAP_DCM_EN, 343 PWRAP_DCM_DBC_PRD, 344 PWRAP_EINT_STA0_ADR, 345 PWRAP_EINT_STA1_ADR, 346 PWRAP_SWINF_2_WDATA_31_0, 347 PWRAP_SWINF_2_RDATA_31_0, 348 349 /* MT2701 only regs */ 350 PWRAP_ADC_CMD_ADDR, 351 PWRAP_PWRAP_ADC_CMD, 352 PWRAP_ADC_RDY_ADDR, 353 PWRAP_ADC_RDATA_ADDR1, 354 PWRAP_ADC_RDATA_ADDR2, 355 356 /* MT7622 only regs */ 357 PWRAP_STA, 358 PWRAP_CLR, 359 PWRAP_DVFS_ADR8, 360 PWRAP_DVFS_WDATA8, 361 PWRAP_DVFS_ADR9, 362 PWRAP_DVFS_WDATA9, 363 PWRAP_DVFS_ADR10, 364 PWRAP_DVFS_WDATA10, 365 PWRAP_DVFS_ADR11, 366 PWRAP_DVFS_WDATA11, 367 PWRAP_DVFS_ADR12, 368 PWRAP_DVFS_WDATA12, 369 PWRAP_DVFS_ADR13, 370 PWRAP_DVFS_WDATA13, 371 PWRAP_DVFS_ADR14, 372 PWRAP_DVFS_WDATA14, 373 PWRAP_DVFS_ADR15, 374 PWRAP_DVFS_WDATA15, 375 PWRAP_EXT_CK, 376 PWRAP_ADC_RDATA_ADDR, 377 PWRAP_GPS_STA, 378 PWRAP_SW_RST, 379 PWRAP_DVFS_STEP_CTRL0, 380 PWRAP_DVFS_STEP_CTRL1, 381 PWRAP_DVFS_STEP_CTRL2, 382 PWRAP_SPI2_CTRL, 383 384 /* MT8135 only regs */ 385 PWRAP_CSHEXT, 386 PWRAP_EVENT_IN_EN, 387 PWRAP_EVENT_DST_EN, 388 PWRAP_RRARB_INIT, 389 PWRAP_RRARB_EN, 390 PWRAP_RRARB_STA0, 391 PWRAP_RRARB_STA1, 392 PWRAP_EVENT_STA, 393 PWRAP_EVENT_STACLR, 394 PWRAP_CIPHER_LOAD, 395 PWRAP_CIPHER_START, 396 397 /* MT8173 only regs */ 398 PWRAP_RDDMY, 399 PWRAP_SI_CK_CON, 400 PWRAP_DVFS_ADR0, 401 PWRAP_DVFS_WDATA0, 402 PWRAP_DVFS_ADR1, 403 PWRAP_DVFS_WDATA1, 404 PWRAP_DVFS_ADR2, 405 PWRAP_DVFS_WDATA2, 406 PWRAP_DVFS_ADR3, 407 PWRAP_DVFS_WDATA3, 408 PWRAP_DVFS_ADR4, 409 PWRAP_DVFS_WDATA4, 410 PWRAP_DVFS_ADR5, 411 PWRAP_DVFS_WDATA5, 412 PWRAP_DVFS_ADR6, 413 PWRAP_DVFS_WDATA6, 414 PWRAP_DVFS_ADR7, 415 PWRAP_DVFS_WDATA7, 416 PWRAP_SPMINF_STA, 417 PWRAP_CIPHER_EN, 418 419 /* MT8183 only regs */ 420 PWRAP_SI_SAMPLE_CTRL, 421 PWRAP_CSLEXT_WRITE, 422 PWRAP_CSLEXT_READ, 423 PWRAP_EXT_CK_WRITE, 424 PWRAP_STAUPD_CTRL, 425 PWRAP_WACS_P2P_EN, 426 PWRAP_INIT_DONE_P2P, 427 PWRAP_WACS_MD32_EN, 428 PWRAP_INIT_DONE_MD32, 429 PWRAP_INT1_EN, 430 PWRAP_INT1_FLG, 431 PWRAP_INT1_CLR, 432 PWRAP_WDT_SRC_EN_1, 433 PWRAP_INT_GPS_AUXADC_CMD_ADDR, 434 PWRAP_INT_GPS_AUXADC_CMD, 435 PWRAP_INT_GPS_AUXADC_RDATA_ADDR, 436 PWRAP_EXT_GPS_AUXADC_RDATA_ADDR, 437 PWRAP_GPSINF_0_STA, 438 PWRAP_GPSINF_1_STA, 439 440 /* MT8516 only regs */ 441 PWRAP_OP_TYPE, 442 PWRAP_MSB_FIRST, 443 }; 444 445 static int mt2701_regs[] = { 446 [PWRAP_MUX_SEL] = 0x0, 447 [PWRAP_WRAP_EN] = 0x4, 448 [PWRAP_DIO_EN] = 0x8, 449 [PWRAP_SIDLY] = 0xc, 450 [PWRAP_RDDMY] = 0x18, 451 [PWRAP_SI_CK_CON] = 0x1c, 452 [PWRAP_CSHEXT_WRITE] = 0x20, 453 [PWRAP_CSHEXT_READ] = 0x24, 454 [PWRAP_CSLEXT_START] = 0x28, 455 [PWRAP_CSLEXT_END] = 0x2c, 456 [PWRAP_STAUPD_PRD] = 0x30, 457 [PWRAP_STAUPD_GRPEN] = 0x34, 458 [PWRAP_STAUPD_MAN_TRIG] = 0x38, 459 [PWRAP_STAUPD_STA] = 0x3c, 460 [PWRAP_WRAP_STA] = 0x44, 461 [PWRAP_HARB_INIT] = 0x48, 462 [PWRAP_HARB_HPRIO] = 0x4c, 463 [PWRAP_HIPRIO_ARB_EN] = 0x50, 464 [PWRAP_HARB_STA0] = 0x54, 465 [PWRAP_HARB_STA1] = 0x58, 466 [PWRAP_MAN_EN] = 0x5c, 467 [PWRAP_MAN_CMD] = 0x60, 468 [PWRAP_MAN_RDATA] = 0x64, 469 [PWRAP_MAN_VLDCLR] = 0x68, 470 [PWRAP_WACS0_EN] = 0x6c, 471 [PWRAP_INIT_DONE0] = 0x70, 472 [PWRAP_WACS0_CMD] = 0x74, 473 [PWRAP_WACS0_RDATA] = 0x78, 474 [PWRAP_WACS0_VLDCLR] = 0x7c, 475 [PWRAP_WACS1_EN] = 0x80, 476 [PWRAP_INIT_DONE1] = 0x84, 477 [PWRAP_WACS1_CMD] = 0x88, 478 [PWRAP_WACS1_RDATA] = 0x8c, 479 [PWRAP_WACS1_VLDCLR] = 0x90, 480 [PWRAP_WACS2_EN] = 0x94, 481 [PWRAP_INIT_DONE2] = 0x98, 482 [PWRAP_WACS2_CMD] = 0x9c, 483 [PWRAP_WACS2_RDATA] = 0xa0, 484 [PWRAP_WACS2_VLDCLR] = 0xa4, 485 [PWRAP_INT_EN] = 0xa8, 486 [PWRAP_INT_FLG_RAW] = 0xac, 487 [PWRAP_INT_FLG] = 0xb0, 488 [PWRAP_INT_CLR] = 0xb4, 489 [PWRAP_SIG_ADR] = 0xb8, 490 [PWRAP_SIG_MODE] = 0xbc, 491 [PWRAP_SIG_VALUE] = 0xc0, 492 [PWRAP_SIG_ERRVAL] = 0xc4, 493 [PWRAP_CRC_EN] = 0xc8, 494 [PWRAP_TIMER_EN] = 0xcc, 495 [PWRAP_TIMER_STA] = 0xd0, 496 [PWRAP_WDT_UNIT] = 0xd4, 497 [PWRAP_WDT_SRC_EN] = 0xd8, 498 [PWRAP_WDT_FLG] = 0xdc, 499 [PWRAP_DEBUG_INT_SEL] = 0xe0, 500 [PWRAP_DVFS_ADR0] = 0xe4, 501 [PWRAP_DVFS_WDATA0] = 0xe8, 502 [PWRAP_DVFS_ADR1] = 0xec, 503 [PWRAP_DVFS_WDATA1] = 0xf0, 504 [PWRAP_DVFS_ADR2] = 0xf4, 505 [PWRAP_DVFS_WDATA2] = 0xf8, 506 [PWRAP_DVFS_ADR3] = 0xfc, 507 [PWRAP_DVFS_WDATA3] = 0x100, 508 [PWRAP_DVFS_ADR4] = 0x104, 509 [PWRAP_DVFS_WDATA4] = 0x108, 510 [PWRAP_DVFS_ADR5] = 0x10c, 511 [PWRAP_DVFS_WDATA5] = 0x110, 512 [PWRAP_DVFS_ADR6] = 0x114, 513 [PWRAP_DVFS_WDATA6] = 0x118, 514 [PWRAP_DVFS_ADR7] = 0x11c, 515 [PWRAP_DVFS_WDATA7] = 0x120, 516 [PWRAP_CIPHER_KEY_SEL] = 0x124, 517 [PWRAP_CIPHER_IV_SEL] = 0x128, 518 [PWRAP_CIPHER_EN] = 0x12c, 519 [PWRAP_CIPHER_RDY] = 0x130, 520 [PWRAP_CIPHER_MODE] = 0x134, 521 [PWRAP_CIPHER_SWRST] = 0x138, 522 [PWRAP_DCM_EN] = 0x13c, 523 [PWRAP_DCM_DBC_PRD] = 0x140, 524 [PWRAP_ADC_CMD_ADDR] = 0x144, 525 [PWRAP_PWRAP_ADC_CMD] = 0x148, 526 [PWRAP_ADC_RDY_ADDR] = 0x14c, 527 [PWRAP_ADC_RDATA_ADDR1] = 0x150, 528 [PWRAP_ADC_RDATA_ADDR2] = 0x154, 529 }; 530 531 static int mt6765_regs[] = { 532 [PWRAP_MUX_SEL] = 0x0, 533 [PWRAP_WRAP_EN] = 0x4, 534 [PWRAP_DIO_EN] = 0x8, 535 [PWRAP_RDDMY] = 0x20, 536 [PWRAP_CSHEXT_WRITE] = 0x24, 537 [PWRAP_CSHEXT_READ] = 0x28, 538 [PWRAP_CSLEXT_START] = 0x2C, 539 [PWRAP_CSLEXT_END] = 0x30, 540 [PWRAP_STAUPD_PRD] = 0x3C, 541 [PWRAP_HARB_HPRIO] = 0x68, 542 [PWRAP_HIPRIO_ARB_EN] = 0x6C, 543 [PWRAP_MAN_EN] = 0x7C, 544 [PWRAP_MAN_CMD] = 0x80, 545 [PWRAP_WACS0_EN] = 0x8C, 546 [PWRAP_WACS1_EN] = 0x94, 547 [PWRAP_WACS2_EN] = 0x9C, 548 [PWRAP_INIT_DONE2] = 0xA0, 549 [PWRAP_WACS2_CMD] = 0xC20, 550 [PWRAP_WACS2_RDATA] = 0xC24, 551 [PWRAP_WACS2_VLDCLR] = 0xC28, 552 [PWRAP_INT_EN] = 0xB4, 553 [PWRAP_INT_FLG_RAW] = 0xB8, 554 [PWRAP_INT_FLG] = 0xBC, 555 [PWRAP_INT_CLR] = 0xC0, 556 [PWRAP_TIMER_EN] = 0xE8, 557 [PWRAP_WDT_UNIT] = 0xF0, 558 [PWRAP_WDT_SRC_EN] = 0xF4, 559 [PWRAP_DCM_EN] = 0x1DC, 560 [PWRAP_DCM_DBC_PRD] = 0x1E0, 561 }; 562 563 static int mt6779_regs[] = { 564 [PWRAP_MUX_SEL] = 0x0, 565 [PWRAP_WRAP_EN] = 0x4, 566 [PWRAP_DIO_EN] = 0x8, 567 [PWRAP_RDDMY] = 0x20, 568 [PWRAP_CSHEXT_WRITE] = 0x24, 569 [PWRAP_CSHEXT_READ] = 0x28, 570 [PWRAP_CSLEXT_WRITE] = 0x2C, 571 [PWRAP_CSLEXT_READ] = 0x30, 572 [PWRAP_EXT_CK_WRITE] = 0x34, 573 [PWRAP_STAUPD_CTRL] = 0x3C, 574 [PWRAP_STAUPD_GRPEN] = 0x40, 575 [PWRAP_EINT_STA0_ADR] = 0x44, 576 [PWRAP_HARB_HPRIO] = 0x68, 577 [PWRAP_HIPRIO_ARB_EN] = 0x6C, 578 [PWRAP_MAN_EN] = 0x7C, 579 [PWRAP_MAN_CMD] = 0x80, 580 [PWRAP_WACS0_EN] = 0x8C, 581 [PWRAP_INIT_DONE0] = 0x90, 582 [PWRAP_WACS1_EN] = 0x94, 583 [PWRAP_WACS2_EN] = 0x9C, 584 [PWRAP_INIT_DONE1] = 0x98, 585 [PWRAP_INIT_DONE2] = 0xA0, 586 [PWRAP_INT_EN] = 0xBC, 587 [PWRAP_INT_FLG_RAW] = 0xC0, 588 [PWRAP_INT_FLG] = 0xC4, 589 [PWRAP_INT_CLR] = 0xC8, 590 [PWRAP_INT1_EN] = 0xCC, 591 [PWRAP_INT1_FLG] = 0xD4, 592 [PWRAP_INT1_CLR] = 0xD8, 593 [PWRAP_TIMER_EN] = 0xF0, 594 [PWRAP_WDT_UNIT] = 0xF8, 595 [PWRAP_WDT_SRC_EN] = 0xFC, 596 [PWRAP_WDT_SRC_EN_1] = 0x100, 597 [PWRAP_WACS2_CMD] = 0xC20, 598 [PWRAP_WACS2_RDATA] = 0xC24, 599 [PWRAP_WACS2_VLDCLR] = 0xC28, 600 }; 601 602 static int mt6797_regs[] = { 603 [PWRAP_MUX_SEL] = 0x0, 604 [PWRAP_WRAP_EN] = 0x4, 605 [PWRAP_DIO_EN] = 0x8, 606 [PWRAP_SIDLY] = 0xC, 607 [PWRAP_RDDMY] = 0x10, 608 [PWRAP_CSHEXT_WRITE] = 0x18, 609 [PWRAP_CSHEXT_READ] = 0x1C, 610 [PWRAP_CSLEXT_START] = 0x20, 611 [PWRAP_CSLEXT_END] = 0x24, 612 [PWRAP_STAUPD_PRD] = 0x28, 613 [PWRAP_HARB_HPRIO] = 0x50, 614 [PWRAP_HIPRIO_ARB_EN] = 0x54, 615 [PWRAP_MAN_EN] = 0x60, 616 [PWRAP_MAN_CMD] = 0x64, 617 [PWRAP_WACS0_EN] = 0x70, 618 [PWRAP_WACS1_EN] = 0x84, 619 [PWRAP_WACS2_EN] = 0x98, 620 [PWRAP_INIT_DONE2] = 0x9C, 621 [PWRAP_WACS2_CMD] = 0xA0, 622 [PWRAP_WACS2_RDATA] = 0xA4, 623 [PWRAP_WACS2_VLDCLR] = 0xA8, 624 [PWRAP_INT_EN] = 0xC0, 625 [PWRAP_INT_FLG_RAW] = 0xC4, 626 [PWRAP_INT_FLG] = 0xC8, 627 [PWRAP_INT_CLR] = 0xCC, 628 [PWRAP_TIMER_EN] = 0xF4, 629 [PWRAP_WDT_UNIT] = 0xFC, 630 [PWRAP_WDT_SRC_EN] = 0x100, 631 [PWRAP_DCM_EN] = 0x1CC, 632 [PWRAP_DCM_DBC_PRD] = 0x1D4, 633 }; 634 635 static int mt6873_regs[] = { 636 [PWRAP_INIT_DONE2] = 0x0, 637 [PWRAP_TIMER_EN] = 0x3E0, 638 [PWRAP_INT_EN] = 0x448, 639 [PWRAP_WACS2_CMD] = 0xC80, 640 [PWRAP_SWINF_2_WDATA_31_0] = 0xC84, 641 [PWRAP_SWINF_2_RDATA_31_0] = 0xC94, 642 [PWRAP_WACS2_VLDCLR] = 0xCA4, 643 [PWRAP_WACS2_RDATA] = 0xCA8, 644 }; 645 646 static int mt7622_regs[] = { 647 [PWRAP_MUX_SEL] = 0x0, 648 [PWRAP_WRAP_EN] = 0x4, 649 [PWRAP_DIO_EN] = 0x8, 650 [PWRAP_SIDLY] = 0xC, 651 [PWRAP_RDDMY] = 0x10, 652 [PWRAP_SI_CK_CON] = 0x14, 653 [PWRAP_CSHEXT_WRITE] = 0x18, 654 [PWRAP_CSHEXT_READ] = 0x1C, 655 [PWRAP_CSLEXT_START] = 0x20, 656 [PWRAP_CSLEXT_END] = 0x24, 657 [PWRAP_STAUPD_PRD] = 0x28, 658 [PWRAP_STAUPD_GRPEN] = 0x2C, 659 [PWRAP_EINT_STA0_ADR] = 0x30, 660 [PWRAP_EINT_STA1_ADR] = 0x34, 661 [PWRAP_STA] = 0x38, 662 [PWRAP_CLR] = 0x3C, 663 [PWRAP_STAUPD_MAN_TRIG] = 0x40, 664 [PWRAP_STAUPD_STA] = 0x44, 665 [PWRAP_WRAP_STA] = 0x48, 666 [PWRAP_HARB_INIT] = 0x4C, 667 [PWRAP_HARB_HPRIO] = 0x50, 668 [PWRAP_HIPRIO_ARB_EN] = 0x54, 669 [PWRAP_HARB_STA0] = 0x58, 670 [PWRAP_HARB_STA1] = 0x5C, 671 [PWRAP_MAN_EN] = 0x60, 672 [PWRAP_MAN_CMD] = 0x64, 673 [PWRAP_MAN_RDATA] = 0x68, 674 [PWRAP_MAN_VLDCLR] = 0x6C, 675 [PWRAP_WACS0_EN] = 0x70, 676 [PWRAP_INIT_DONE0] = 0x74, 677 [PWRAP_WACS0_CMD] = 0x78, 678 [PWRAP_WACS0_RDATA] = 0x7C, 679 [PWRAP_WACS0_VLDCLR] = 0x80, 680 [PWRAP_WACS1_EN] = 0x84, 681 [PWRAP_INIT_DONE1] = 0x88, 682 [PWRAP_WACS1_CMD] = 0x8C, 683 [PWRAP_WACS1_RDATA] = 0x90, 684 [PWRAP_WACS1_VLDCLR] = 0x94, 685 [PWRAP_WACS2_EN] = 0x98, 686 [PWRAP_INIT_DONE2] = 0x9C, 687 [PWRAP_WACS2_CMD] = 0xA0, 688 [PWRAP_WACS2_RDATA] = 0xA4, 689 [PWRAP_WACS2_VLDCLR] = 0xA8, 690 [PWRAP_INT_EN] = 0xAC, 691 [PWRAP_INT_FLG_RAW] = 0xB0, 692 [PWRAP_INT_FLG] = 0xB4, 693 [PWRAP_INT_CLR] = 0xB8, 694 [PWRAP_SIG_ADR] = 0xBC, 695 [PWRAP_SIG_MODE] = 0xC0, 696 [PWRAP_SIG_VALUE] = 0xC4, 697 [PWRAP_SIG_ERRVAL] = 0xC8, 698 [PWRAP_CRC_EN] = 0xCC, 699 [PWRAP_TIMER_EN] = 0xD0, 700 [PWRAP_TIMER_STA] = 0xD4, 701 [PWRAP_WDT_UNIT] = 0xD8, 702 [PWRAP_WDT_SRC_EN] = 0xDC, 703 [PWRAP_WDT_FLG] = 0xE0, 704 [PWRAP_DEBUG_INT_SEL] = 0xE4, 705 [PWRAP_DVFS_ADR0] = 0xE8, 706 [PWRAP_DVFS_WDATA0] = 0xEC, 707 [PWRAP_DVFS_ADR1] = 0xF0, 708 [PWRAP_DVFS_WDATA1] = 0xF4, 709 [PWRAP_DVFS_ADR2] = 0xF8, 710 [PWRAP_DVFS_WDATA2] = 0xFC, 711 [PWRAP_DVFS_ADR3] = 0x100, 712 [PWRAP_DVFS_WDATA3] = 0x104, 713 [PWRAP_DVFS_ADR4] = 0x108, 714 [PWRAP_DVFS_WDATA4] = 0x10C, 715 [PWRAP_DVFS_ADR5] = 0x110, 716 [PWRAP_DVFS_WDATA5] = 0x114, 717 [PWRAP_DVFS_ADR6] = 0x118, 718 [PWRAP_DVFS_WDATA6] = 0x11C, 719 [PWRAP_DVFS_ADR7] = 0x120, 720 [PWRAP_DVFS_WDATA7] = 0x124, 721 [PWRAP_DVFS_ADR8] = 0x128, 722 [PWRAP_DVFS_WDATA8] = 0x12C, 723 [PWRAP_DVFS_ADR9] = 0x130, 724 [PWRAP_DVFS_WDATA9] = 0x134, 725 [PWRAP_DVFS_ADR10] = 0x138, 726 [PWRAP_DVFS_WDATA10] = 0x13C, 727 [PWRAP_DVFS_ADR11] = 0x140, 728 [PWRAP_DVFS_WDATA11] = 0x144, 729 [PWRAP_DVFS_ADR12] = 0x148, 730 [PWRAP_DVFS_WDATA12] = 0x14C, 731 [PWRAP_DVFS_ADR13] = 0x150, 732 [PWRAP_DVFS_WDATA13] = 0x154, 733 [PWRAP_DVFS_ADR14] = 0x158, 734 [PWRAP_DVFS_WDATA14] = 0x15C, 735 [PWRAP_DVFS_ADR15] = 0x160, 736 [PWRAP_DVFS_WDATA15] = 0x164, 737 [PWRAP_SPMINF_STA] = 0x168, 738 [PWRAP_CIPHER_KEY_SEL] = 0x16C, 739 [PWRAP_CIPHER_IV_SEL] = 0x170, 740 [PWRAP_CIPHER_EN] = 0x174, 741 [PWRAP_CIPHER_RDY] = 0x178, 742 [PWRAP_CIPHER_MODE] = 0x17C, 743 [PWRAP_CIPHER_SWRST] = 0x180, 744 [PWRAP_DCM_EN] = 0x184, 745 [PWRAP_DCM_DBC_PRD] = 0x188, 746 [PWRAP_EXT_CK] = 0x18C, 747 [PWRAP_ADC_CMD_ADDR] = 0x190, 748 [PWRAP_PWRAP_ADC_CMD] = 0x194, 749 [PWRAP_ADC_RDATA_ADDR] = 0x198, 750 [PWRAP_GPS_STA] = 0x19C, 751 [PWRAP_SW_RST] = 0x1A0, 752 [PWRAP_DVFS_STEP_CTRL0] = 0x238, 753 [PWRAP_DVFS_STEP_CTRL1] = 0x23C, 754 [PWRAP_DVFS_STEP_CTRL2] = 0x240, 755 [PWRAP_SPI2_CTRL] = 0x244, 756 }; 757 758 static int mt8135_regs[] = { 759 [PWRAP_MUX_SEL] = 0x0, 760 [PWRAP_WRAP_EN] = 0x4, 761 [PWRAP_DIO_EN] = 0x8, 762 [PWRAP_SIDLY] = 0xc, 763 [PWRAP_CSHEXT] = 0x10, 764 [PWRAP_CSHEXT_WRITE] = 0x14, 765 [PWRAP_CSHEXT_READ] = 0x18, 766 [PWRAP_CSLEXT_START] = 0x1c, 767 [PWRAP_CSLEXT_END] = 0x20, 768 [PWRAP_STAUPD_PRD] = 0x24, 769 [PWRAP_STAUPD_GRPEN] = 0x28, 770 [PWRAP_STAUPD_MAN_TRIG] = 0x2c, 771 [PWRAP_STAUPD_STA] = 0x30, 772 [PWRAP_EVENT_IN_EN] = 0x34, 773 [PWRAP_EVENT_DST_EN] = 0x38, 774 [PWRAP_WRAP_STA] = 0x3c, 775 [PWRAP_RRARB_INIT] = 0x40, 776 [PWRAP_RRARB_EN] = 0x44, 777 [PWRAP_RRARB_STA0] = 0x48, 778 [PWRAP_RRARB_STA1] = 0x4c, 779 [PWRAP_HARB_INIT] = 0x50, 780 [PWRAP_HARB_HPRIO] = 0x54, 781 [PWRAP_HIPRIO_ARB_EN] = 0x58, 782 [PWRAP_HARB_STA0] = 0x5c, 783 [PWRAP_HARB_STA1] = 0x60, 784 [PWRAP_MAN_EN] = 0x64, 785 [PWRAP_MAN_CMD] = 0x68, 786 [PWRAP_MAN_RDATA] = 0x6c, 787 [PWRAP_MAN_VLDCLR] = 0x70, 788 [PWRAP_WACS0_EN] = 0x74, 789 [PWRAP_INIT_DONE0] = 0x78, 790 [PWRAP_WACS0_CMD] = 0x7c, 791 [PWRAP_WACS0_RDATA] = 0x80, 792 [PWRAP_WACS0_VLDCLR] = 0x84, 793 [PWRAP_WACS1_EN] = 0x88, 794 [PWRAP_INIT_DONE1] = 0x8c, 795 [PWRAP_WACS1_CMD] = 0x90, 796 [PWRAP_WACS1_RDATA] = 0x94, 797 [PWRAP_WACS1_VLDCLR] = 0x98, 798 [PWRAP_WACS2_EN] = 0x9c, 799 [PWRAP_INIT_DONE2] = 0xa0, 800 [PWRAP_WACS2_CMD] = 0xa4, 801 [PWRAP_WACS2_RDATA] = 0xa8, 802 [PWRAP_WACS2_VLDCLR] = 0xac, 803 [PWRAP_INT_EN] = 0xb0, 804 [PWRAP_INT_FLG_RAW] = 0xb4, 805 [PWRAP_INT_FLG] = 0xb8, 806 [PWRAP_INT_CLR] = 0xbc, 807 [PWRAP_SIG_ADR] = 0xc0, 808 [PWRAP_SIG_MODE] = 0xc4, 809 [PWRAP_SIG_VALUE] = 0xc8, 810 [PWRAP_SIG_ERRVAL] = 0xcc, 811 [PWRAP_CRC_EN] = 0xd0, 812 [PWRAP_EVENT_STA] = 0xd4, 813 [PWRAP_EVENT_STACLR] = 0xd8, 814 [PWRAP_TIMER_EN] = 0xdc, 815 [PWRAP_TIMER_STA] = 0xe0, 816 [PWRAP_WDT_UNIT] = 0xe4, 817 [PWRAP_WDT_SRC_EN] = 0xe8, 818 [PWRAP_WDT_FLG] = 0xec, 819 [PWRAP_DEBUG_INT_SEL] = 0xf0, 820 [PWRAP_CIPHER_KEY_SEL] = 0x134, 821 [PWRAP_CIPHER_IV_SEL] = 0x138, 822 [PWRAP_CIPHER_LOAD] = 0x13c, 823 [PWRAP_CIPHER_START] = 0x140, 824 [PWRAP_CIPHER_RDY] = 0x144, 825 [PWRAP_CIPHER_MODE] = 0x148, 826 [PWRAP_CIPHER_SWRST] = 0x14c, 827 [PWRAP_DCM_EN] = 0x15c, 828 [PWRAP_DCM_DBC_PRD] = 0x160, 829 }; 830 831 static int mt8173_regs[] = { 832 [PWRAP_MUX_SEL] = 0x0, 833 [PWRAP_WRAP_EN] = 0x4, 834 [PWRAP_DIO_EN] = 0x8, 835 [PWRAP_SIDLY] = 0xc, 836 [PWRAP_RDDMY] = 0x10, 837 [PWRAP_SI_CK_CON] = 0x14, 838 [PWRAP_CSHEXT_WRITE] = 0x18, 839 [PWRAP_CSHEXT_READ] = 0x1c, 840 [PWRAP_CSLEXT_START] = 0x20, 841 [PWRAP_CSLEXT_END] = 0x24, 842 [PWRAP_STAUPD_PRD] = 0x28, 843 [PWRAP_STAUPD_GRPEN] = 0x2c, 844 [PWRAP_STAUPD_MAN_TRIG] = 0x40, 845 [PWRAP_STAUPD_STA] = 0x44, 846 [PWRAP_WRAP_STA] = 0x48, 847 [PWRAP_HARB_INIT] = 0x4c, 848 [PWRAP_HARB_HPRIO] = 0x50, 849 [PWRAP_HIPRIO_ARB_EN] = 0x54, 850 [PWRAP_HARB_STA0] = 0x58, 851 [PWRAP_HARB_STA1] = 0x5c, 852 [PWRAP_MAN_EN] = 0x60, 853 [PWRAP_MAN_CMD] = 0x64, 854 [PWRAP_MAN_RDATA] = 0x68, 855 [PWRAP_MAN_VLDCLR] = 0x6c, 856 [PWRAP_WACS0_EN] = 0x70, 857 [PWRAP_INIT_DONE0] = 0x74, 858 [PWRAP_WACS0_CMD] = 0x78, 859 [PWRAP_WACS0_RDATA] = 0x7c, 860 [PWRAP_WACS0_VLDCLR] = 0x80, 861 [PWRAP_WACS1_EN] = 0x84, 862 [PWRAP_INIT_DONE1] = 0x88, 863 [PWRAP_WACS1_CMD] = 0x8c, 864 [PWRAP_WACS1_RDATA] = 0x90, 865 [PWRAP_WACS1_VLDCLR] = 0x94, 866 [PWRAP_WACS2_EN] = 0x98, 867 [PWRAP_INIT_DONE2] = 0x9c, 868 [PWRAP_WACS2_CMD] = 0xa0, 869 [PWRAP_WACS2_RDATA] = 0xa4, 870 [PWRAP_WACS2_VLDCLR] = 0xa8, 871 [PWRAP_INT_EN] = 0xac, 872 [PWRAP_INT_FLG_RAW] = 0xb0, 873 [PWRAP_INT_FLG] = 0xb4, 874 [PWRAP_INT_CLR] = 0xb8, 875 [PWRAP_SIG_ADR] = 0xbc, 876 [PWRAP_SIG_MODE] = 0xc0, 877 [PWRAP_SIG_VALUE] = 0xc4, 878 [PWRAP_SIG_ERRVAL] = 0xc8, 879 [PWRAP_CRC_EN] = 0xcc, 880 [PWRAP_TIMER_EN] = 0xd0, 881 [PWRAP_TIMER_STA] = 0xd4, 882 [PWRAP_WDT_UNIT] = 0xd8, 883 [PWRAP_WDT_SRC_EN] = 0xdc, 884 [PWRAP_WDT_FLG] = 0xe0, 885 [PWRAP_DEBUG_INT_SEL] = 0xe4, 886 [PWRAP_DVFS_ADR0] = 0xe8, 887 [PWRAP_DVFS_WDATA0] = 0xec, 888 [PWRAP_DVFS_ADR1] = 0xf0, 889 [PWRAP_DVFS_WDATA1] = 0xf4, 890 [PWRAP_DVFS_ADR2] = 0xf8, 891 [PWRAP_DVFS_WDATA2] = 0xfc, 892 [PWRAP_DVFS_ADR3] = 0x100, 893 [PWRAP_DVFS_WDATA3] = 0x104, 894 [PWRAP_DVFS_ADR4] = 0x108, 895 [PWRAP_DVFS_WDATA4] = 0x10c, 896 [PWRAP_DVFS_ADR5] = 0x110, 897 [PWRAP_DVFS_WDATA5] = 0x114, 898 [PWRAP_DVFS_ADR6] = 0x118, 899 [PWRAP_DVFS_WDATA6] = 0x11c, 900 [PWRAP_DVFS_ADR7] = 0x120, 901 [PWRAP_DVFS_WDATA7] = 0x124, 902 [PWRAP_SPMINF_STA] = 0x128, 903 [PWRAP_CIPHER_KEY_SEL] = 0x12c, 904 [PWRAP_CIPHER_IV_SEL] = 0x130, 905 [PWRAP_CIPHER_EN] = 0x134, 906 [PWRAP_CIPHER_RDY] = 0x138, 907 [PWRAP_CIPHER_MODE] = 0x13c, 908 [PWRAP_CIPHER_SWRST] = 0x140, 909 [PWRAP_DCM_EN] = 0x144, 910 [PWRAP_DCM_DBC_PRD] = 0x148, 911 }; 912 913 static int mt8183_regs[] = { 914 [PWRAP_MUX_SEL] = 0x0, 915 [PWRAP_WRAP_EN] = 0x4, 916 [PWRAP_DIO_EN] = 0x8, 917 [PWRAP_SI_SAMPLE_CTRL] = 0xC, 918 [PWRAP_RDDMY] = 0x14, 919 [PWRAP_CSHEXT_WRITE] = 0x18, 920 [PWRAP_CSHEXT_READ] = 0x1C, 921 [PWRAP_CSLEXT_WRITE] = 0x20, 922 [PWRAP_CSLEXT_READ] = 0x24, 923 [PWRAP_EXT_CK_WRITE] = 0x28, 924 [PWRAP_STAUPD_CTRL] = 0x30, 925 [PWRAP_STAUPD_GRPEN] = 0x34, 926 [PWRAP_EINT_STA0_ADR] = 0x38, 927 [PWRAP_HARB_HPRIO] = 0x5C, 928 [PWRAP_HIPRIO_ARB_EN] = 0x60, 929 [PWRAP_MAN_EN] = 0x70, 930 [PWRAP_MAN_CMD] = 0x74, 931 [PWRAP_WACS0_EN] = 0x80, 932 [PWRAP_INIT_DONE0] = 0x84, 933 [PWRAP_WACS1_EN] = 0x88, 934 [PWRAP_INIT_DONE1] = 0x8C, 935 [PWRAP_WACS2_EN] = 0x90, 936 [PWRAP_INIT_DONE2] = 0x94, 937 [PWRAP_WACS_P2P_EN] = 0xA0, 938 [PWRAP_INIT_DONE_P2P] = 0xA4, 939 [PWRAP_WACS_MD32_EN] = 0xA8, 940 [PWRAP_INIT_DONE_MD32] = 0xAC, 941 [PWRAP_INT_EN] = 0xB0, 942 [PWRAP_INT_FLG] = 0xB8, 943 [PWRAP_INT_CLR] = 0xBC, 944 [PWRAP_INT1_EN] = 0xC0, 945 [PWRAP_INT1_FLG] = 0xC8, 946 [PWRAP_INT1_CLR] = 0xCC, 947 [PWRAP_SIG_ADR] = 0xD0, 948 [PWRAP_CRC_EN] = 0xE0, 949 [PWRAP_TIMER_EN] = 0xE4, 950 [PWRAP_WDT_UNIT] = 0xEC, 951 [PWRAP_WDT_SRC_EN] = 0xF0, 952 [PWRAP_WDT_SRC_EN_1] = 0xF4, 953 [PWRAP_INT_GPS_AUXADC_CMD_ADDR] = 0x1DC, 954 [PWRAP_INT_GPS_AUXADC_CMD] = 0x1E0, 955 [PWRAP_INT_GPS_AUXADC_RDATA_ADDR] = 0x1E4, 956 [PWRAP_EXT_GPS_AUXADC_RDATA_ADDR] = 0x1E8, 957 [PWRAP_GPSINF_0_STA] = 0x1EC, 958 [PWRAP_GPSINF_1_STA] = 0x1F0, 959 [PWRAP_WACS2_CMD] = 0xC20, 960 [PWRAP_WACS2_RDATA] = 0xC24, 961 [PWRAP_WACS2_VLDCLR] = 0xC28, 962 }; 963 964 static int mt8195_regs[] = { 965 [PWRAP_INIT_DONE2] = 0x0, 966 [PWRAP_STAUPD_CTRL] = 0x4C, 967 [PWRAP_TIMER_EN] = 0x3E4, 968 [PWRAP_INT_EN] = 0x420, 969 [PWRAP_INT_FLG] = 0x428, 970 [PWRAP_INT_CLR] = 0x42C, 971 [PWRAP_INT1_EN] = 0x450, 972 [PWRAP_INT1_FLG] = 0x458, 973 [PWRAP_INT1_CLR] = 0x45C, 974 [PWRAP_WACS2_CMD] = 0x880, 975 [PWRAP_SWINF_2_WDATA_31_0] = 0x884, 976 [PWRAP_SWINF_2_RDATA_31_0] = 0x894, 977 [PWRAP_WACS2_VLDCLR] = 0x8A4, 978 [PWRAP_WACS2_RDATA] = 0x8A8, 979 }; 980 981 static int mt8516_regs[] = { 982 [PWRAP_MUX_SEL] = 0x0, 983 [PWRAP_WRAP_EN] = 0x4, 984 [PWRAP_DIO_EN] = 0x8, 985 [PWRAP_SIDLY] = 0xc, 986 [PWRAP_RDDMY] = 0x10, 987 [PWRAP_SI_CK_CON] = 0x14, 988 [PWRAP_CSHEXT_WRITE] = 0x18, 989 [PWRAP_CSHEXT_READ] = 0x1c, 990 [PWRAP_CSLEXT_START] = 0x20, 991 [PWRAP_CSLEXT_END] = 0x24, 992 [PWRAP_STAUPD_PRD] = 0x28, 993 [PWRAP_STAUPD_GRPEN] = 0x2c, 994 [PWRAP_STAUPD_MAN_TRIG] = 0x40, 995 [PWRAP_STAUPD_STA] = 0x44, 996 [PWRAP_WRAP_STA] = 0x48, 997 [PWRAP_HARB_INIT] = 0x4c, 998 [PWRAP_HARB_HPRIO] = 0x50, 999 [PWRAP_HIPRIO_ARB_EN] = 0x54, 1000 [PWRAP_HARB_STA0] = 0x58, 1001 [PWRAP_HARB_STA1] = 0x5c, 1002 [PWRAP_MAN_EN] = 0x60, 1003 [PWRAP_MAN_CMD] = 0x64, 1004 [PWRAP_MAN_RDATA] = 0x68, 1005 [PWRAP_MAN_VLDCLR] = 0x6c, 1006 [PWRAP_WACS0_EN] = 0x70, 1007 [PWRAP_INIT_DONE0] = 0x74, 1008 [PWRAP_WACS0_CMD] = 0x78, 1009 [PWRAP_WACS0_RDATA] = 0x7c, 1010 [PWRAP_WACS0_VLDCLR] = 0x80, 1011 [PWRAP_WACS1_EN] = 0x84, 1012 [PWRAP_INIT_DONE1] = 0x88, 1013 [PWRAP_WACS1_CMD] = 0x8c, 1014 [PWRAP_WACS1_RDATA] = 0x90, 1015 [PWRAP_WACS1_VLDCLR] = 0x94, 1016 [PWRAP_WACS2_EN] = 0x98, 1017 [PWRAP_INIT_DONE2] = 0x9c, 1018 [PWRAP_WACS2_CMD] = 0xa0, 1019 [PWRAP_WACS2_RDATA] = 0xa4, 1020 [PWRAP_WACS2_VLDCLR] = 0xa8, 1021 [PWRAP_INT_EN] = 0xac, 1022 [PWRAP_INT_FLG_RAW] = 0xb0, 1023 [PWRAP_INT_FLG] = 0xb4, 1024 [PWRAP_INT_CLR] = 0xb8, 1025 [PWRAP_SIG_ADR] = 0xbc, 1026 [PWRAP_SIG_MODE] = 0xc0, 1027 [PWRAP_SIG_VALUE] = 0xc4, 1028 [PWRAP_SIG_ERRVAL] = 0xc8, 1029 [PWRAP_CRC_EN] = 0xcc, 1030 [PWRAP_TIMER_EN] = 0xd0, 1031 [PWRAP_TIMER_STA] = 0xd4, 1032 [PWRAP_WDT_UNIT] = 0xd8, 1033 [PWRAP_WDT_SRC_EN] = 0xdc, 1034 [PWRAP_WDT_FLG] = 0xe0, 1035 [PWRAP_DEBUG_INT_SEL] = 0xe4, 1036 [PWRAP_DVFS_ADR0] = 0xe8, 1037 [PWRAP_DVFS_WDATA0] = 0xec, 1038 [PWRAP_DVFS_ADR1] = 0xf0, 1039 [PWRAP_DVFS_WDATA1] = 0xf4, 1040 [PWRAP_DVFS_ADR2] = 0xf8, 1041 [PWRAP_DVFS_WDATA2] = 0xfc, 1042 [PWRAP_DVFS_ADR3] = 0x100, 1043 [PWRAP_DVFS_WDATA3] = 0x104, 1044 [PWRAP_DVFS_ADR4] = 0x108, 1045 [PWRAP_DVFS_WDATA4] = 0x10c, 1046 [PWRAP_DVFS_ADR5] = 0x110, 1047 [PWRAP_DVFS_WDATA5] = 0x114, 1048 [PWRAP_DVFS_ADR6] = 0x118, 1049 [PWRAP_DVFS_WDATA6] = 0x11c, 1050 [PWRAP_DVFS_ADR7] = 0x120, 1051 [PWRAP_DVFS_WDATA7] = 0x124, 1052 [PWRAP_SPMINF_STA] = 0x128, 1053 [PWRAP_CIPHER_KEY_SEL] = 0x12c, 1054 [PWRAP_CIPHER_IV_SEL] = 0x130, 1055 [PWRAP_CIPHER_EN] = 0x134, 1056 [PWRAP_CIPHER_RDY] = 0x138, 1057 [PWRAP_CIPHER_MODE] = 0x13c, 1058 [PWRAP_CIPHER_SWRST] = 0x140, 1059 [PWRAP_DCM_EN] = 0x144, 1060 [PWRAP_DCM_DBC_PRD] = 0x148, 1061 [PWRAP_SW_RST] = 0x168, 1062 [PWRAP_OP_TYPE] = 0x16c, 1063 [PWRAP_MSB_FIRST] = 0x170, 1064 }; 1065 1066 enum pmic_type { 1067 PMIC_MT6323, 1068 PMIC_MT6351, 1069 PMIC_MT6357, 1070 PMIC_MT6358, 1071 PMIC_MT6359, 1072 PMIC_MT6380, 1073 PMIC_MT6397, 1074 }; 1075 1076 enum pwrap_type { 1077 PWRAP_MT2701, 1078 PWRAP_MT6765, 1079 PWRAP_MT6779, 1080 PWRAP_MT6797, 1081 PWRAP_MT6873, 1082 PWRAP_MT7622, 1083 PWRAP_MT8135, 1084 PWRAP_MT8173, 1085 PWRAP_MT8183, 1086 PWRAP_MT8195, 1087 PWRAP_MT8516, 1088 }; 1089 1090 struct pmic_wrapper; 1091 struct pwrap_slv_type { 1092 const u32 *dew_regs; 1093 enum pmic_type type; 1094 const struct regmap_config *regmap; 1095 /* Flags indicating the capability for the target slave */ 1096 u32 caps; 1097 /* 1098 * pwrap operations are highly associated with the PMIC types, 1099 * so the pointers added increases flexibility allowing determination 1100 * which type is used by the detection through device tree. 1101 */ 1102 int (*pwrap_read)(struct pmic_wrapper *wrp, u32 adr, u32 *rdata); 1103 int (*pwrap_write)(struct pmic_wrapper *wrp, u32 adr, u32 wdata); 1104 }; 1105 1106 struct pmic_wrapper { 1107 struct device *dev; 1108 void __iomem *base; 1109 struct regmap *regmap; 1110 const struct pmic_wrapper_type *master; 1111 const struct pwrap_slv_type *slave; 1112 struct clk *clk_spi; 1113 struct clk *clk_wrap; 1114 struct reset_control *rstc; 1115 1116 struct reset_control *rstc_bridge; 1117 void __iomem *bridge_base; 1118 }; 1119 1120 struct pmic_wrapper_type { 1121 int *regs; 1122 enum pwrap_type type; 1123 u32 arb_en_all; 1124 u32 int_en_all; 1125 u32 int1_en_all; 1126 u32 spi_w; 1127 u32 wdt_src; 1128 /* Flags indicating the capability for the target pwrap */ 1129 u32 caps; 1130 int (*init_reg_clock)(struct pmic_wrapper *wrp); 1131 int (*init_soc_specific)(struct pmic_wrapper *wrp); 1132 }; 1133 1134 static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg) 1135 { 1136 return readl(wrp->base + wrp->master->regs[reg]); 1137 } 1138 1139 static void pwrap_writel(struct pmic_wrapper *wrp, u32 val, enum pwrap_regs reg) 1140 { 1141 writel(val, wrp->base + wrp->master->regs[reg]); 1142 } 1143 1144 static u32 pwrap_get_fsm_state(struct pmic_wrapper *wrp) 1145 { 1146 u32 val; 1147 1148 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA); 1149 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) 1150 return PWRAP_GET_WACS_ARB_FSM(val); 1151 else 1152 return PWRAP_GET_WACS_FSM(val); 1153 } 1154 1155 static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp) 1156 { 1157 return pwrap_get_fsm_state(wrp) == PWRAP_WACS_FSM_IDLE; 1158 } 1159 1160 static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp) 1161 { 1162 return pwrap_get_fsm_state(wrp) == PWRAP_WACS_FSM_WFVLDCLR; 1163 } 1164 1165 /* 1166 * Timeout issue sometimes caused by the last read command 1167 * failed because pmic wrap could not got the FSM_VLDCLR 1168 * in time after finishing WACS2_CMD. It made state machine 1169 * still on FSM_VLDCLR and timeout next time. 1170 * Check the status of FSM and clear the vldclr to recovery the 1171 * error. 1172 */ 1173 static inline void pwrap_leave_fsm_vldclr(struct pmic_wrapper *wrp) 1174 { 1175 if (pwrap_is_fsm_vldclr(wrp)) 1176 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR); 1177 } 1178 1179 static bool pwrap_is_sync_idle(struct pmic_wrapper *wrp) 1180 { 1181 return pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_SYNC_IDLE0; 1182 } 1183 1184 static bool pwrap_is_fsm_idle_and_sync_idle(struct pmic_wrapper *wrp) 1185 { 1186 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA); 1187 1188 return (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE) && 1189 (val & PWRAP_STATE_SYNC_IDLE0); 1190 } 1191 1192 static int pwrap_wait_for_state(struct pmic_wrapper *wrp, 1193 bool (*fp)(struct pmic_wrapper *)) 1194 { 1195 unsigned long timeout; 1196 1197 timeout = jiffies + usecs_to_jiffies(10000); 1198 1199 do { 1200 if (time_after(jiffies, timeout)) 1201 return fp(wrp) ? 0 : -ETIMEDOUT; 1202 if (fp(wrp)) 1203 return 0; 1204 } while (1); 1205 } 1206 1207 static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata) 1208 { 1209 int ret; 1210 u32 val; 1211 1212 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle); 1213 if (ret) { 1214 pwrap_leave_fsm_vldclr(wrp); 1215 return ret; 1216 } 1217 1218 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) 1219 val = adr; 1220 else 1221 val = (adr >> 1) << 16; 1222 pwrap_writel(wrp, val, PWRAP_WACS2_CMD); 1223 1224 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr); 1225 if (ret) 1226 return ret; 1227 1228 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) 1229 val = pwrap_readl(wrp, PWRAP_SWINF_2_RDATA_31_0); 1230 else 1231 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA); 1232 *rdata = PWRAP_GET_WACS_RDATA(val); 1233 1234 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR); 1235 1236 return 0; 1237 } 1238 1239 static int pwrap_read32(struct pmic_wrapper *wrp, u32 adr, u32 *rdata) 1240 { 1241 int ret, msb; 1242 1243 *rdata = 0; 1244 for (msb = 0; msb < 2; msb++) { 1245 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle); 1246 if (ret) { 1247 pwrap_leave_fsm_vldclr(wrp); 1248 return ret; 1249 } 1250 1251 pwrap_writel(wrp, ((msb << 30) | (adr << 16)), 1252 PWRAP_WACS2_CMD); 1253 1254 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr); 1255 if (ret) 1256 return ret; 1257 1258 *rdata += (PWRAP_GET_WACS_RDATA(pwrap_readl(wrp, 1259 PWRAP_WACS2_RDATA)) << (16 * msb)); 1260 1261 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR); 1262 } 1263 1264 return 0; 1265 } 1266 1267 static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata) 1268 { 1269 return wrp->slave->pwrap_read(wrp, adr, rdata); 1270 } 1271 1272 static int pwrap_write16(struct pmic_wrapper *wrp, u32 adr, u32 wdata) 1273 { 1274 int ret; 1275 1276 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle); 1277 if (ret) { 1278 pwrap_leave_fsm_vldclr(wrp); 1279 return ret; 1280 } 1281 1282 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) { 1283 pwrap_writel(wrp, wdata, PWRAP_SWINF_2_WDATA_31_0); 1284 pwrap_writel(wrp, BIT(29) | adr, PWRAP_WACS2_CMD); 1285 } else { 1286 pwrap_writel(wrp, BIT(31) | ((adr >> 1) << 16) | wdata, 1287 PWRAP_WACS2_CMD); 1288 } 1289 1290 return 0; 1291 } 1292 1293 static int pwrap_write32(struct pmic_wrapper *wrp, u32 adr, u32 wdata) 1294 { 1295 int ret, msb, rdata; 1296 1297 for (msb = 0; msb < 2; msb++) { 1298 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle); 1299 if (ret) { 1300 pwrap_leave_fsm_vldclr(wrp); 1301 return ret; 1302 } 1303 1304 pwrap_writel(wrp, (1 << 31) | (msb << 30) | (adr << 16) | 1305 ((wdata >> (msb * 16)) & 0xffff), 1306 PWRAP_WACS2_CMD); 1307 1308 /* 1309 * The pwrap_read operation is the requirement of hardware used 1310 * for the synchronization between two successive 16-bit 1311 * pwrap_writel operations composing one 32-bit bus writing. 1312 * Otherwise, we'll find the result fails on the lower 16-bit 1313 * pwrap writing. 1314 */ 1315 if (!msb) 1316 pwrap_read(wrp, adr, &rdata); 1317 } 1318 1319 return 0; 1320 } 1321 1322 static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata) 1323 { 1324 return wrp->slave->pwrap_write(wrp, adr, wdata); 1325 } 1326 1327 static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata) 1328 { 1329 return pwrap_read(context, adr, rdata); 1330 } 1331 1332 static int pwrap_regmap_write(void *context, u32 adr, u32 wdata) 1333 { 1334 return pwrap_write(context, adr, wdata); 1335 } 1336 1337 static int pwrap_reset_spislave(struct pmic_wrapper *wrp) 1338 { 1339 int ret, i; 1340 1341 pwrap_writel(wrp, 0, PWRAP_HIPRIO_ARB_EN); 1342 pwrap_writel(wrp, 0, PWRAP_WRAP_EN); 1343 pwrap_writel(wrp, 1, PWRAP_MUX_SEL); 1344 pwrap_writel(wrp, 1, PWRAP_MAN_EN); 1345 pwrap_writel(wrp, 0, PWRAP_DIO_EN); 1346 1347 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSL, 1348 PWRAP_MAN_CMD); 1349 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS, 1350 PWRAP_MAN_CMD); 1351 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSH, 1352 PWRAP_MAN_CMD); 1353 1354 for (i = 0; i < 4; i++) 1355 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS, 1356 PWRAP_MAN_CMD); 1357 1358 ret = pwrap_wait_for_state(wrp, pwrap_is_sync_idle); 1359 if (ret) { 1360 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret); 1361 return ret; 1362 } 1363 1364 pwrap_writel(wrp, 0, PWRAP_MAN_EN); 1365 pwrap_writel(wrp, 0, PWRAP_MUX_SEL); 1366 1367 return 0; 1368 } 1369 1370 /* 1371 * pwrap_init_sidly - configure serial input delay 1372 * 1373 * This configures the serial input delay. We can configure 0, 2, 4 or 6ns 1374 * delay. Do a read test with all possible values and chose the best delay. 1375 */ 1376 static int pwrap_init_sidly(struct pmic_wrapper *wrp) 1377 { 1378 u32 rdata; 1379 u32 i; 1380 u32 pass = 0; 1381 signed char dly[16] = { 1382 -1, 0, 1, 0, 2, -1, 1, 1, 3, -1, -1, -1, 3, -1, 2, 1 1383 }; 1384 1385 for (i = 0; i < 4; i++) { 1386 pwrap_writel(wrp, i, PWRAP_SIDLY); 1387 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], 1388 &rdata); 1389 if (rdata == PWRAP_DEW_READ_TEST_VAL) { 1390 dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i); 1391 pass |= 1 << i; 1392 } 1393 } 1394 1395 if (dly[pass] < 0) { 1396 dev_err(wrp->dev, "sidly pass range 0x%x not continuous\n", 1397 pass); 1398 return -EIO; 1399 } 1400 1401 pwrap_writel(wrp, dly[pass], PWRAP_SIDLY); 1402 1403 return 0; 1404 } 1405 1406 static int pwrap_init_dual_io(struct pmic_wrapper *wrp) 1407 { 1408 int ret; 1409 u32 rdata; 1410 1411 /* Enable dual IO mode */ 1412 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1); 1413 1414 /* Check IDLE & INIT_DONE in advance */ 1415 ret = pwrap_wait_for_state(wrp, 1416 pwrap_is_fsm_idle_and_sync_idle); 1417 if (ret) { 1418 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret); 1419 return ret; 1420 } 1421 1422 pwrap_writel(wrp, 1, PWRAP_DIO_EN); 1423 1424 /* Read Test */ 1425 pwrap_read(wrp, 1426 wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata); 1427 if (rdata != PWRAP_DEW_READ_TEST_VAL) { 1428 dev_err(wrp->dev, 1429 "Read failed on DIO mode: 0x%04x!=0x%04x\n", 1430 PWRAP_DEW_READ_TEST_VAL, rdata); 1431 return -EFAULT; 1432 } 1433 1434 return 0; 1435 } 1436 1437 /* 1438 * pwrap_init_chip_select_ext is used to configure CS extension time for each 1439 * phase during data transactions on the pwrap bus. 1440 */ 1441 static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write, 1442 u8 hext_read, u8 lext_start, 1443 u8 lext_end) 1444 { 1445 /* 1446 * After finishing a write and read transaction, extends CS high time 1447 * to be at least xT of BUS CLK as hext_write and hext_read specifies 1448 * respectively. 1449 */ 1450 pwrap_writel(wrp, hext_write, PWRAP_CSHEXT_WRITE); 1451 pwrap_writel(wrp, hext_read, PWRAP_CSHEXT_READ); 1452 1453 /* 1454 * Extends CS low time after CSL and before CSH command to be at 1455 * least xT of BUS CLK as lext_start and lext_end specifies 1456 * respectively. 1457 */ 1458 pwrap_writel(wrp, lext_start, PWRAP_CSLEXT_START); 1459 pwrap_writel(wrp, lext_end, PWRAP_CSLEXT_END); 1460 } 1461 1462 static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp) 1463 { 1464 switch (wrp->master->type) { 1465 case PWRAP_MT8173: 1466 pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2); 1467 break; 1468 case PWRAP_MT8135: 1469 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT); 1470 pwrap_init_chip_select_ext(wrp, 0, 4, 0, 0); 1471 break; 1472 default: 1473 break; 1474 } 1475 1476 return 0; 1477 } 1478 1479 static int pwrap_mt2701_init_reg_clock(struct pmic_wrapper *wrp) 1480 { 1481 switch (wrp->slave->type) { 1482 case PMIC_MT6397: 1483 pwrap_writel(wrp, 0xc, PWRAP_RDDMY); 1484 pwrap_init_chip_select_ext(wrp, 4, 0, 2, 2); 1485 break; 1486 1487 case PMIC_MT6323: 1488 pwrap_writel(wrp, 0x8, PWRAP_RDDMY); 1489 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO], 1490 0x8); 1491 pwrap_init_chip_select_ext(wrp, 5, 0, 2, 2); 1492 break; 1493 default: 1494 break; 1495 } 1496 1497 return 0; 1498 } 1499 1500 static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp) 1501 { 1502 return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1; 1503 } 1504 1505 static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp) 1506 { 1507 u32 rdata; 1508 int ret; 1509 1510 ret = pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_RDY], 1511 &rdata); 1512 if (ret) 1513 return false; 1514 1515 return rdata == 1; 1516 } 1517 1518 static int pwrap_init_cipher(struct pmic_wrapper *wrp) 1519 { 1520 int ret; 1521 u32 rdata = 0; 1522 1523 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_SWRST); 1524 pwrap_writel(wrp, 0x0, PWRAP_CIPHER_SWRST); 1525 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_KEY_SEL); 1526 pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL); 1527 1528 switch (wrp->master->type) { 1529 case PWRAP_MT8135: 1530 pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD); 1531 pwrap_writel(wrp, 1, PWRAP_CIPHER_START); 1532 break; 1533 case PWRAP_MT2701: 1534 case PWRAP_MT6765: 1535 case PWRAP_MT6779: 1536 case PWRAP_MT6797: 1537 case PWRAP_MT8173: 1538 case PWRAP_MT8516: 1539 pwrap_writel(wrp, 1, PWRAP_CIPHER_EN); 1540 break; 1541 case PWRAP_MT7622: 1542 pwrap_writel(wrp, 0, PWRAP_CIPHER_EN); 1543 break; 1544 case PWRAP_MT6873: 1545 case PWRAP_MT8183: 1546 case PWRAP_MT8195: 1547 break; 1548 } 1549 1550 /* Config cipher mode @PMIC */ 1551 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1); 1552 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0); 1553 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1); 1554 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2); 1555 1556 switch (wrp->slave->type) { 1557 case PMIC_MT6397: 1558 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD], 1559 0x1); 1560 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START], 1561 0x1); 1562 break; 1563 case PMIC_MT6323: 1564 case PMIC_MT6351: 1565 case PMIC_MT6357: 1566 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN], 1567 0x1); 1568 break; 1569 default: 1570 break; 1571 } 1572 1573 /* wait for cipher data ready@AP */ 1574 ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready); 1575 if (ret) { 1576 dev_err(wrp->dev, "cipher data ready@AP fail, ret=%d\n", ret); 1577 return ret; 1578 } 1579 1580 /* wait for cipher data ready@PMIC */ 1581 ret = pwrap_wait_for_state(wrp, pwrap_is_pmic_cipher_ready); 1582 if (ret) { 1583 dev_err(wrp->dev, 1584 "timeout waiting for cipher data ready@PMIC\n"); 1585 return ret; 1586 } 1587 1588 /* wait for cipher mode idle */ 1589 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_MODE], 0x1); 1590 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle); 1591 if (ret) { 1592 dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret); 1593 return ret; 1594 } 1595 1596 pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE); 1597 1598 /* Write Test */ 1599 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST], 1600 PWRAP_DEW_WRITE_TEST_VAL) || 1601 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST], 1602 &rdata) || 1603 (rdata != PWRAP_DEW_WRITE_TEST_VAL)) { 1604 dev_err(wrp->dev, "rdata=0x%04X\n", rdata); 1605 return -EFAULT; 1606 } 1607 1608 return 0; 1609 } 1610 1611 static int pwrap_init_security(struct pmic_wrapper *wrp) 1612 { 1613 int ret; 1614 1615 /* Enable encryption */ 1616 ret = pwrap_init_cipher(wrp); 1617 if (ret) 1618 return ret; 1619 1620 /* Signature checking - using CRC */ 1621 if (pwrap_write(wrp, 1622 wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1)) 1623 return -EFAULT; 1624 1625 pwrap_writel(wrp, 0x1, PWRAP_CRC_EN); 1626 pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE); 1627 pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL], 1628 PWRAP_SIG_ADR); 1629 pwrap_writel(wrp, 1630 wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN); 1631 1632 return 0; 1633 } 1634 1635 static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp) 1636 { 1637 /* enable pwrap events and pwrap bridge in AP side */ 1638 pwrap_writel(wrp, 0x1, PWRAP_EVENT_IN_EN); 1639 pwrap_writel(wrp, 0xffff, PWRAP_EVENT_DST_EN); 1640 writel(0x7f, wrp->bridge_base + PWRAP_MT8135_BRIDGE_IORD_ARB_EN); 1641 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS3_EN); 1642 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS4_EN); 1643 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_UNIT); 1644 writel(0xffff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_SRC_EN); 1645 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_TIMER_EN); 1646 writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN); 1647 1648 /* enable PMIC event out and sources */ 1649 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN], 1650 0x1) || 1651 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN], 1652 0xffff)) { 1653 dev_err(wrp->dev, "enable dewrap fail\n"); 1654 return -EFAULT; 1655 } 1656 1657 return 0; 1658 } 1659 1660 static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp) 1661 { 1662 /* PMIC_DEWRAP enables */ 1663 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN], 1664 0x1) || 1665 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN], 1666 0xffff)) { 1667 dev_err(wrp->dev, "enable dewrap fail\n"); 1668 return -EFAULT; 1669 } 1670 1671 return 0; 1672 } 1673 1674 static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp) 1675 { 1676 /* GPS_INTF initialization */ 1677 switch (wrp->slave->type) { 1678 case PMIC_MT6323: 1679 pwrap_writel(wrp, 0x076c, PWRAP_ADC_CMD_ADDR); 1680 pwrap_writel(wrp, 0x8000, PWRAP_PWRAP_ADC_CMD); 1681 pwrap_writel(wrp, 0x072c, PWRAP_ADC_RDY_ADDR); 1682 pwrap_writel(wrp, 0x072e, PWRAP_ADC_RDATA_ADDR1); 1683 pwrap_writel(wrp, 0x0730, PWRAP_ADC_RDATA_ADDR2); 1684 break; 1685 default: 1686 break; 1687 } 1688 1689 return 0; 1690 } 1691 1692 static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp) 1693 { 1694 pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD); 1695 /* enable 2wire SPI master */ 1696 pwrap_writel(wrp, 0x8000000, PWRAP_SPI2_CTRL); 1697 1698 return 0; 1699 } 1700 1701 static int pwrap_mt8183_init_soc_specific(struct pmic_wrapper *wrp) 1702 { 1703 pwrap_writel(wrp, 0xf5, PWRAP_STAUPD_GRPEN); 1704 1705 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1); 1706 pwrap_writel(wrp, 1, PWRAP_CRC_EN); 1707 pwrap_writel(wrp, 0x416, PWRAP_SIG_ADR); 1708 pwrap_writel(wrp, 0x42e, PWRAP_EINT_STA0_ADR); 1709 1710 pwrap_writel(wrp, 1, PWRAP_WACS_P2P_EN); 1711 pwrap_writel(wrp, 1, PWRAP_WACS_MD32_EN); 1712 pwrap_writel(wrp, 1, PWRAP_INIT_DONE_P2P); 1713 pwrap_writel(wrp, 1, PWRAP_INIT_DONE_MD32); 1714 1715 return 0; 1716 } 1717 1718 static int pwrap_init(struct pmic_wrapper *wrp) 1719 { 1720 int ret; 1721 1722 if (wrp->rstc) 1723 reset_control_reset(wrp->rstc); 1724 if (wrp->rstc_bridge) 1725 reset_control_reset(wrp->rstc_bridge); 1726 1727 if (wrp->master->type == PWRAP_MT8173) { 1728 /* Enable DCM */ 1729 pwrap_writel(wrp, 3, PWRAP_DCM_EN); 1730 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD); 1731 } 1732 1733 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) { 1734 /* Reset SPI slave */ 1735 ret = pwrap_reset_spislave(wrp); 1736 if (ret) 1737 return ret; 1738 } 1739 1740 pwrap_writel(wrp, 1, PWRAP_WRAP_EN); 1741 1742 pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN); 1743 1744 pwrap_writel(wrp, 1, PWRAP_WACS2_EN); 1745 1746 ret = wrp->master->init_reg_clock(wrp); 1747 if (ret) 1748 return ret; 1749 1750 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) { 1751 /* Setup serial input delay */ 1752 ret = pwrap_init_sidly(wrp); 1753 if (ret) 1754 return ret; 1755 } 1756 1757 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_DUALIO)) { 1758 /* Enable dual I/O mode */ 1759 ret = pwrap_init_dual_io(wrp); 1760 if (ret) 1761 return ret; 1762 } 1763 1764 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SECURITY)) { 1765 /* Enable security on bus */ 1766 ret = pwrap_init_security(wrp); 1767 if (ret) 1768 return ret; 1769 } 1770 1771 if (wrp->master->type == PWRAP_MT8135) 1772 pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN); 1773 1774 pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN); 1775 pwrap_writel(wrp, 0x1, PWRAP_WACS1_EN); 1776 pwrap_writel(wrp, 0x1, PWRAP_WACS2_EN); 1777 pwrap_writel(wrp, 0x5, PWRAP_STAUPD_PRD); 1778 pwrap_writel(wrp, 0xff, PWRAP_STAUPD_GRPEN); 1779 1780 if (wrp->master->init_soc_specific) { 1781 ret = wrp->master->init_soc_specific(wrp); 1782 if (ret) 1783 return ret; 1784 } 1785 1786 /* Setup the init done registers */ 1787 pwrap_writel(wrp, 1, PWRAP_INIT_DONE2); 1788 pwrap_writel(wrp, 1, PWRAP_INIT_DONE0); 1789 pwrap_writel(wrp, 1, PWRAP_INIT_DONE1); 1790 1791 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) { 1792 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3); 1793 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4); 1794 } 1795 1796 return 0; 1797 } 1798 1799 static irqreturn_t pwrap_interrupt(int irqno, void *dev_id) 1800 { 1801 u32 rdata; 1802 struct pmic_wrapper *wrp = dev_id; 1803 1804 rdata = pwrap_readl(wrp, PWRAP_INT_FLG); 1805 dev_err(wrp->dev, "unexpected interrupt int=0x%x\n", rdata); 1806 pwrap_writel(wrp, 0xffffffff, PWRAP_INT_CLR); 1807 1808 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN)) { 1809 rdata = pwrap_readl(wrp, PWRAP_INT1_FLG); 1810 dev_err(wrp->dev, "unexpected interrupt int1=0x%x\n", rdata); 1811 pwrap_writel(wrp, 0xffffffff, PWRAP_INT1_CLR); 1812 } 1813 1814 return IRQ_HANDLED; 1815 } 1816 1817 static const struct regmap_config pwrap_regmap_config16 = { 1818 .reg_bits = 16, 1819 .val_bits = 16, 1820 .reg_stride = 2, 1821 .reg_read = pwrap_regmap_read, 1822 .reg_write = pwrap_regmap_write, 1823 .max_register = 0xffff, 1824 }; 1825 1826 static const struct regmap_config pwrap_regmap_config32 = { 1827 .reg_bits = 32, 1828 .val_bits = 32, 1829 .reg_stride = 4, 1830 .reg_read = pwrap_regmap_read, 1831 .reg_write = pwrap_regmap_write, 1832 .max_register = 0xffff, 1833 }; 1834 1835 static const struct pwrap_slv_type pmic_mt6323 = { 1836 .dew_regs = mt6323_regs, 1837 .type = PMIC_MT6323, 1838 .regmap = &pwrap_regmap_config16, 1839 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO | 1840 PWRAP_SLV_CAP_SECURITY, 1841 .pwrap_read = pwrap_read16, 1842 .pwrap_write = pwrap_write16, 1843 }; 1844 1845 static const struct pwrap_slv_type pmic_mt6351 = { 1846 .dew_regs = mt6351_regs, 1847 .type = PMIC_MT6351, 1848 .regmap = &pwrap_regmap_config16, 1849 .caps = 0, 1850 .pwrap_read = pwrap_read16, 1851 .pwrap_write = pwrap_write16, 1852 }; 1853 1854 static const struct pwrap_slv_type pmic_mt6357 = { 1855 .dew_regs = mt6357_regs, 1856 .type = PMIC_MT6357, 1857 .regmap = &pwrap_regmap_config16, 1858 .caps = 0, 1859 .pwrap_read = pwrap_read16, 1860 .pwrap_write = pwrap_write16, 1861 }; 1862 1863 static const struct pwrap_slv_type pmic_mt6358 = { 1864 .dew_regs = mt6358_regs, 1865 .type = PMIC_MT6358, 1866 .regmap = &pwrap_regmap_config16, 1867 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO, 1868 .pwrap_read = pwrap_read16, 1869 .pwrap_write = pwrap_write16, 1870 }; 1871 1872 static const struct pwrap_slv_type pmic_mt6359 = { 1873 .dew_regs = mt6359_regs, 1874 .type = PMIC_MT6359, 1875 .regmap = &pwrap_regmap_config16, 1876 .caps = PWRAP_SLV_CAP_DUALIO, 1877 .pwrap_read = pwrap_read16, 1878 .pwrap_write = pwrap_write16, 1879 }; 1880 1881 static const struct pwrap_slv_type pmic_mt6380 = { 1882 .dew_regs = NULL, 1883 .type = PMIC_MT6380, 1884 .regmap = &pwrap_regmap_config32, 1885 .caps = 0, 1886 .pwrap_read = pwrap_read32, 1887 .pwrap_write = pwrap_write32, 1888 }; 1889 1890 static const struct pwrap_slv_type pmic_mt6397 = { 1891 .dew_regs = mt6397_regs, 1892 .type = PMIC_MT6397, 1893 .regmap = &pwrap_regmap_config16, 1894 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO | 1895 PWRAP_SLV_CAP_SECURITY, 1896 .pwrap_read = pwrap_read16, 1897 .pwrap_write = pwrap_write16, 1898 }; 1899 1900 static const struct of_device_id of_slave_match_tbl[] = { 1901 { 1902 .compatible = "mediatek,mt6323", 1903 .data = &pmic_mt6323, 1904 }, { 1905 .compatible = "mediatek,mt6351", 1906 .data = &pmic_mt6351, 1907 }, { 1908 .compatible = "mediatek,mt6357", 1909 .data = &pmic_mt6357, 1910 }, { 1911 .compatible = "mediatek,mt6358", 1912 .data = &pmic_mt6358, 1913 }, { 1914 .compatible = "mediatek,mt6359", 1915 .data = &pmic_mt6359, 1916 }, { 1917 /* The MT6380 PMIC only implements a regulator, so we bind it 1918 * directly instead of using a MFD. 1919 */ 1920 .compatible = "mediatek,mt6380-regulator", 1921 .data = &pmic_mt6380, 1922 }, { 1923 .compatible = "mediatek,mt6397", 1924 .data = &pmic_mt6397, 1925 }, { 1926 /* sentinel */ 1927 } 1928 }; 1929 MODULE_DEVICE_TABLE(of, of_slave_match_tbl); 1930 1931 static const struct pmic_wrapper_type pwrap_mt2701 = { 1932 .regs = mt2701_regs, 1933 .type = PWRAP_MT2701, 1934 .arb_en_all = 0x3f, 1935 .int_en_all = ~(u32)(BIT(31) | BIT(2)), 1936 .int1_en_all = 0, 1937 .spi_w = PWRAP_MAN_CMD_SPI_WRITE_NEW, 1938 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 1939 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM, 1940 .init_reg_clock = pwrap_mt2701_init_reg_clock, 1941 .init_soc_specific = pwrap_mt2701_init_soc_specific, 1942 }; 1943 1944 static const struct pmic_wrapper_type pwrap_mt6765 = { 1945 .regs = mt6765_regs, 1946 .type = PWRAP_MT6765, 1947 .arb_en_all = 0x3fd35, 1948 .int_en_all = 0xffffffff, 1949 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 1950 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 1951 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM, 1952 .init_reg_clock = pwrap_common_init_reg_clock, 1953 .init_soc_specific = NULL, 1954 }; 1955 1956 static const struct pmic_wrapper_type pwrap_mt6779 = { 1957 .regs = mt6779_regs, 1958 .type = PWRAP_MT6779, 1959 .arb_en_all = 0xfbb7f, 1960 .int_en_all = 0xfffffffe, 1961 .int1_en_all = 0, 1962 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 1963 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 1964 .caps = 0, 1965 .init_reg_clock = pwrap_common_init_reg_clock, 1966 .init_soc_specific = NULL, 1967 }; 1968 1969 static const struct pmic_wrapper_type pwrap_mt6797 = { 1970 .regs = mt6797_regs, 1971 .type = PWRAP_MT6797, 1972 .arb_en_all = 0x01fff, 1973 .int_en_all = 0xffffffc6, 1974 .int1_en_all = 0, 1975 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 1976 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 1977 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM, 1978 .init_reg_clock = pwrap_common_init_reg_clock, 1979 .init_soc_specific = NULL, 1980 }; 1981 1982 static const struct pmic_wrapper_type pwrap_mt6873 = { 1983 .regs = mt6873_regs, 1984 .type = PWRAP_MT6873, 1985 .arb_en_all = 0x777f, 1986 .int_en_all = BIT(4) | BIT(5), 1987 .int1_en_all = 0, 1988 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 1989 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 1990 .caps = PWRAP_CAP_ARB, 1991 .init_reg_clock = pwrap_common_init_reg_clock, 1992 .init_soc_specific = NULL, 1993 }; 1994 1995 static const struct pmic_wrapper_type pwrap_mt7622 = { 1996 .regs = mt7622_regs, 1997 .type = PWRAP_MT7622, 1998 .arb_en_all = 0xff, 1999 .int_en_all = ~(u32)BIT(31), 2000 .int1_en_all = 0, 2001 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2002 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2003 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM, 2004 .init_reg_clock = pwrap_common_init_reg_clock, 2005 .init_soc_specific = pwrap_mt7622_init_soc_specific, 2006 }; 2007 2008 static const struct pmic_wrapper_type pwrap_mt8135 = { 2009 .regs = mt8135_regs, 2010 .type = PWRAP_MT8135, 2011 .arb_en_all = 0x1ff, 2012 .int_en_all = ~(u32)(BIT(31) | BIT(1)), 2013 .int1_en_all = 0, 2014 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2015 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2016 .caps = PWRAP_CAP_BRIDGE | PWRAP_CAP_RESET | PWRAP_CAP_DCM, 2017 .init_reg_clock = pwrap_common_init_reg_clock, 2018 .init_soc_specific = pwrap_mt8135_init_soc_specific, 2019 }; 2020 2021 static const struct pmic_wrapper_type pwrap_mt8173 = { 2022 .regs = mt8173_regs, 2023 .type = PWRAP_MT8173, 2024 .arb_en_all = 0x3f, 2025 .int_en_all = ~(u32)(BIT(31) | BIT(1)), 2026 .int1_en_all = 0, 2027 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2028 .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD, 2029 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM, 2030 .init_reg_clock = pwrap_common_init_reg_clock, 2031 .init_soc_specific = pwrap_mt8173_init_soc_specific, 2032 }; 2033 2034 static const struct pmic_wrapper_type pwrap_mt8183 = { 2035 .regs = mt8183_regs, 2036 .type = PWRAP_MT8183, 2037 .arb_en_all = 0x3fa75, 2038 .int_en_all = 0xffffffff, 2039 .int1_en_all = 0xeef7ffff, 2040 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2041 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2042 .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_WDT_SRC1, 2043 .init_reg_clock = pwrap_common_init_reg_clock, 2044 .init_soc_specific = pwrap_mt8183_init_soc_specific, 2045 }; 2046 2047 static struct pmic_wrapper_type pwrap_mt8195 = { 2048 .regs = mt8195_regs, 2049 .type = PWRAP_MT8195, 2050 .arb_en_all = 0x777f, /* NEED CONFIRM */ 2051 .int_en_all = 0x180000, /* NEED CONFIRM */ 2052 .int1_en_all = 0, 2053 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2054 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2055 .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_ARB, 2056 .init_reg_clock = pwrap_common_init_reg_clock, 2057 .init_soc_specific = NULL, 2058 }; 2059 2060 static struct pmic_wrapper_type pwrap_mt8516 = { 2061 .regs = mt8516_regs, 2062 .type = PWRAP_MT8516, 2063 .arb_en_all = 0xff, 2064 .int_en_all = ~(u32)(BIT(31) | BIT(2)), 2065 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2066 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2067 .caps = PWRAP_CAP_DCM, 2068 .init_reg_clock = pwrap_mt2701_init_reg_clock, 2069 .init_soc_specific = NULL, 2070 }; 2071 2072 static const struct of_device_id of_pwrap_match_tbl[] = { 2073 { 2074 .compatible = "mediatek,mt2701-pwrap", 2075 .data = &pwrap_mt2701, 2076 }, { 2077 .compatible = "mediatek,mt6765-pwrap", 2078 .data = &pwrap_mt6765, 2079 }, { 2080 .compatible = "mediatek,mt6779-pwrap", 2081 .data = &pwrap_mt6779, 2082 }, { 2083 .compatible = "mediatek,mt6797-pwrap", 2084 .data = &pwrap_mt6797, 2085 }, { 2086 .compatible = "mediatek,mt6873-pwrap", 2087 .data = &pwrap_mt6873, 2088 }, { 2089 .compatible = "mediatek,mt7622-pwrap", 2090 .data = &pwrap_mt7622, 2091 }, { 2092 .compatible = "mediatek,mt8135-pwrap", 2093 .data = &pwrap_mt8135, 2094 }, { 2095 .compatible = "mediatek,mt8173-pwrap", 2096 .data = &pwrap_mt8173, 2097 }, { 2098 .compatible = "mediatek,mt8183-pwrap", 2099 .data = &pwrap_mt8183, 2100 }, { 2101 .compatible = "mediatek,mt8195-pwrap", 2102 .data = &pwrap_mt8195, 2103 }, { 2104 .compatible = "mediatek,mt8516-pwrap", 2105 .data = &pwrap_mt8516, 2106 }, { 2107 /* sentinel */ 2108 } 2109 }; 2110 MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl); 2111 2112 static int pwrap_probe(struct platform_device *pdev) 2113 { 2114 int ret, irq; 2115 u32 mask_done; 2116 struct pmic_wrapper *wrp; 2117 struct device_node *np = pdev->dev.of_node; 2118 const struct of_device_id *of_slave_id = NULL; 2119 struct resource *res; 2120 2121 if (np->child) 2122 of_slave_id = of_match_node(of_slave_match_tbl, np->child); 2123 2124 if (!of_slave_id) { 2125 dev_dbg(&pdev->dev, "slave pmic should be defined in dts\n"); 2126 return -EINVAL; 2127 } 2128 2129 wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL); 2130 if (!wrp) 2131 return -ENOMEM; 2132 2133 platform_set_drvdata(pdev, wrp); 2134 2135 wrp->master = of_device_get_match_data(&pdev->dev); 2136 wrp->slave = of_slave_id->data; 2137 wrp->dev = &pdev->dev; 2138 2139 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrap"); 2140 wrp->base = devm_ioremap_resource(wrp->dev, res); 2141 if (IS_ERR(wrp->base)) 2142 return PTR_ERR(wrp->base); 2143 2144 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_RESET)) { 2145 wrp->rstc = devm_reset_control_get(wrp->dev, "pwrap"); 2146 if (IS_ERR(wrp->rstc)) { 2147 ret = PTR_ERR(wrp->rstc); 2148 dev_dbg(wrp->dev, "cannot get pwrap reset: %d\n", ret); 2149 return ret; 2150 } 2151 } 2152 2153 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) { 2154 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 2155 "pwrap-bridge"); 2156 wrp->bridge_base = devm_ioremap_resource(wrp->dev, res); 2157 if (IS_ERR(wrp->bridge_base)) 2158 return PTR_ERR(wrp->bridge_base); 2159 2160 wrp->rstc_bridge = devm_reset_control_get(wrp->dev, 2161 "pwrap-bridge"); 2162 if (IS_ERR(wrp->rstc_bridge)) { 2163 ret = PTR_ERR(wrp->rstc_bridge); 2164 dev_dbg(wrp->dev, 2165 "cannot get pwrap-bridge reset: %d\n", ret); 2166 return ret; 2167 } 2168 } 2169 2170 wrp->clk_spi = devm_clk_get(wrp->dev, "spi"); 2171 if (IS_ERR(wrp->clk_spi)) { 2172 dev_dbg(wrp->dev, "failed to get clock: %ld\n", 2173 PTR_ERR(wrp->clk_spi)); 2174 return PTR_ERR(wrp->clk_spi); 2175 } 2176 2177 wrp->clk_wrap = devm_clk_get(wrp->dev, "wrap"); 2178 if (IS_ERR(wrp->clk_wrap)) { 2179 dev_dbg(wrp->dev, "failed to get clock: %ld\n", 2180 PTR_ERR(wrp->clk_wrap)); 2181 return PTR_ERR(wrp->clk_wrap); 2182 } 2183 2184 ret = clk_prepare_enable(wrp->clk_spi); 2185 if (ret) 2186 return ret; 2187 2188 ret = clk_prepare_enable(wrp->clk_wrap); 2189 if (ret) 2190 goto err_out1; 2191 2192 /* Enable internal dynamic clock */ 2193 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_DCM)) { 2194 pwrap_writel(wrp, 1, PWRAP_DCM_EN); 2195 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD); 2196 } 2197 2198 /* 2199 * The PMIC could already be initialized by the bootloader. 2200 * Skip initialization here in this case. 2201 */ 2202 if (!pwrap_readl(wrp, PWRAP_INIT_DONE2)) { 2203 ret = pwrap_init(wrp); 2204 if (ret) { 2205 dev_dbg(wrp->dev, "init failed with %d\n", ret); 2206 goto err_out2; 2207 } 2208 } 2209 2210 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) 2211 mask_done = PWRAP_STATE_INIT_DONE1; 2212 else 2213 mask_done = PWRAP_STATE_INIT_DONE0; 2214 2215 if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & mask_done)) { 2216 dev_dbg(wrp->dev, "initialization isn't finished\n"); 2217 ret = -ENODEV; 2218 goto err_out2; 2219 } 2220 2221 /* Initialize watchdog, may not be done by the bootloader */ 2222 if (!HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) 2223 pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT); 2224 2225 /* 2226 * Since STAUPD was not used on mt8173 platform, 2227 * so STAUPD of WDT_SRC which should be turned off 2228 */ 2229 pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN); 2230 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_WDT_SRC1)) 2231 pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN_1); 2232 2233 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) 2234 pwrap_writel(wrp, 0x3, PWRAP_TIMER_EN); 2235 else 2236 pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN); 2237 2238 pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN); 2239 /* 2240 * We add INT1 interrupt to handle starvation and request exception 2241 * If we support it, we should enable it here. 2242 */ 2243 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN)) 2244 pwrap_writel(wrp, wrp->master->int1_en_all, PWRAP_INT1_EN); 2245 2246 irq = platform_get_irq(pdev, 0); 2247 ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt, 2248 IRQF_TRIGGER_HIGH, 2249 "mt-pmic-pwrap", wrp); 2250 if (ret) 2251 goto err_out2; 2252 2253 wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, wrp->slave->regmap); 2254 if (IS_ERR(wrp->regmap)) { 2255 ret = PTR_ERR(wrp->regmap); 2256 goto err_out2; 2257 } 2258 2259 ret = of_platform_populate(np, NULL, NULL, wrp->dev); 2260 if (ret) { 2261 dev_dbg(wrp->dev, "failed to create child devices at %pOF\n", 2262 np); 2263 goto err_out2; 2264 } 2265 2266 return 0; 2267 2268 err_out2: 2269 clk_disable_unprepare(wrp->clk_wrap); 2270 err_out1: 2271 clk_disable_unprepare(wrp->clk_spi); 2272 2273 return ret; 2274 } 2275 2276 static struct platform_driver pwrap_drv = { 2277 .driver = { 2278 .name = "mt-pmic-pwrap", 2279 .of_match_table = of_match_ptr(of_pwrap_match_tbl), 2280 }, 2281 .probe = pwrap_probe, 2282 }; 2283 2284 module_platform_driver(pwrap_drv); 2285 2286 MODULE_AUTHOR("Flora Fu, MediaTek"); 2287 MODULE_DESCRIPTION("MediaTek MT8135 PMIC Wrapper Driver"); 2288 MODULE_LICENSE("GPL v2"); 2289