1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/iopoll.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/platform_device.h> 11 #include <linux/regmap.h> 12 #include <linux/soc/mediatek/mtk-mmsys.h> 13 #include <linux/soc/mediatek/mtk-mutex.h> 14 #include <linux/soc/mediatek/mtk-cmdq.h> 15 16 #define MTK_MUTEX_MAX_HANDLES 10 17 18 #define MT2701_MUTEX0_MOD0 0x2c 19 #define MT2701_MUTEX0_SOF0 0x30 20 #define MT8183_MUTEX0_MOD0 0x30 21 #define MT8183_MUTEX0_SOF0 0x2c 22 23 #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) 24 #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) 25 #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n)) 26 #define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) (mutex_mod_reg + 0x20 * (n)) 27 #define DISP_REG_MUTEX_MOD1(mutex_mod_reg, n) ((mutex_mod_reg) + 0x20 * (n) + 0x4) 28 #define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) (mutex_sof_reg + 0x20 * (n)) 29 #define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n)) 30 31 #define INT_MUTEX BIT(1) 32 33 #define MT8186_MUTEX_MOD_DISP_OVL0 0 34 #define MT8186_MUTEX_MOD_DISP_OVL0_2L 1 35 #define MT8186_MUTEX_MOD_DISP_RDMA0 2 36 #define MT8186_MUTEX_MOD_DISP_COLOR0 4 37 #define MT8186_MUTEX_MOD_DISP_CCORR0 5 38 #define MT8186_MUTEX_MOD_DISP_AAL0 7 39 #define MT8186_MUTEX_MOD_DISP_GAMMA0 8 40 #define MT8186_MUTEX_MOD_DISP_POSTMASK0 9 41 #define MT8186_MUTEX_MOD_DISP_DITHER0 10 42 #define MT8186_MUTEX_MOD_DISP_RDMA1 17 43 44 #define MT8186_MUTEX_SOF_SINGLE_MODE 0 45 #define MT8186_MUTEX_SOF_DSI0 1 46 #define MT8186_MUTEX_SOF_DPI0 2 47 #define MT8186_MUTEX_EOF_DSI0 (MT8186_MUTEX_SOF_DSI0 << 6) 48 #define MT8186_MUTEX_EOF_DPI0 (MT8186_MUTEX_SOF_DPI0 << 6) 49 50 #define MT8167_MUTEX_MOD_DISP_PWM 1 51 #define MT8167_MUTEX_MOD_DISP_OVL0 6 52 #define MT8167_MUTEX_MOD_DISP_OVL1 7 53 #define MT8167_MUTEX_MOD_DISP_RDMA0 8 54 #define MT8167_MUTEX_MOD_DISP_RDMA1 9 55 #define MT8167_MUTEX_MOD_DISP_WDMA0 10 56 #define MT8167_MUTEX_MOD_DISP_CCORR 11 57 #define MT8167_MUTEX_MOD_DISP_COLOR 12 58 #define MT8167_MUTEX_MOD_DISP_AAL 13 59 #define MT8167_MUTEX_MOD_DISP_GAMMA 14 60 #define MT8167_MUTEX_MOD_DISP_DITHER 15 61 #define MT8167_MUTEX_MOD_DISP_UFOE 16 62 63 #define MT8192_MUTEX_MOD_DISP_OVL0 0 64 #define MT8192_MUTEX_MOD_DISP_OVL0_2L 1 65 #define MT8192_MUTEX_MOD_DISP_RDMA0 2 66 #define MT8192_MUTEX_MOD_DISP_COLOR0 4 67 #define MT8192_MUTEX_MOD_DISP_CCORR0 5 68 #define MT8192_MUTEX_MOD_DISP_AAL0 6 69 #define MT8192_MUTEX_MOD_DISP_GAMMA0 7 70 #define MT8192_MUTEX_MOD_DISP_POSTMASK0 8 71 #define MT8192_MUTEX_MOD_DISP_DITHER0 9 72 #define MT8192_MUTEX_MOD_DISP_OVL2_2L 16 73 #define MT8192_MUTEX_MOD_DISP_RDMA4 17 74 75 #define MT8183_MUTEX_MOD_DISP_RDMA0 0 76 #define MT8183_MUTEX_MOD_DISP_RDMA1 1 77 #define MT8183_MUTEX_MOD_DISP_OVL0 9 78 #define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 79 #define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 80 #define MT8183_MUTEX_MOD_DISP_WDMA0 12 81 #define MT8183_MUTEX_MOD_DISP_COLOR0 13 82 #define MT8183_MUTEX_MOD_DISP_CCORR0 14 83 #define MT8183_MUTEX_MOD_DISP_AAL0 15 84 #define MT8183_MUTEX_MOD_DISP_GAMMA0 16 85 #define MT8183_MUTEX_MOD_DISP_DITHER0 17 86 87 #define MT8183_MUTEX_MOD_MDP_RDMA0 2 88 #define MT8183_MUTEX_MOD_MDP_RSZ0 4 89 #define MT8183_MUTEX_MOD_MDP_RSZ1 5 90 #define MT8183_MUTEX_MOD_MDP_TDSHP0 6 91 #define MT8183_MUTEX_MOD_MDP_WROT0 7 92 #define MT8183_MUTEX_MOD_MDP_WDMA 8 93 #define MT8183_MUTEX_MOD_MDP_AAL0 23 94 #define MT8183_MUTEX_MOD_MDP_CCORR0 24 95 96 #define MT8186_MUTEX_MOD_MDP_RDMA0 0 97 #define MT8186_MUTEX_MOD_MDP_AAL0 2 98 #define MT8186_MUTEX_MOD_MDP_HDR0 4 99 #define MT8186_MUTEX_MOD_MDP_RSZ0 5 100 #define MT8186_MUTEX_MOD_MDP_RSZ1 6 101 #define MT8186_MUTEX_MOD_MDP_WROT0 7 102 #define MT8186_MUTEX_MOD_MDP_TDSHP0 9 103 #define MT8186_MUTEX_MOD_MDP_COLOR0 14 104 105 #define MT8173_MUTEX_MOD_DISP_OVL0 11 106 #define MT8173_MUTEX_MOD_DISP_OVL1 12 107 #define MT8173_MUTEX_MOD_DISP_RDMA0 13 108 #define MT8173_MUTEX_MOD_DISP_RDMA1 14 109 #define MT8173_MUTEX_MOD_DISP_RDMA2 15 110 #define MT8173_MUTEX_MOD_DISP_WDMA0 16 111 #define MT8173_MUTEX_MOD_DISP_WDMA1 17 112 #define MT8173_MUTEX_MOD_DISP_COLOR0 18 113 #define MT8173_MUTEX_MOD_DISP_COLOR1 19 114 #define MT8173_MUTEX_MOD_DISP_AAL 20 115 #define MT8173_MUTEX_MOD_DISP_GAMMA 21 116 #define MT8173_MUTEX_MOD_DISP_UFOE 22 117 #define MT8173_MUTEX_MOD_DISP_PWM0 23 118 #define MT8173_MUTEX_MOD_DISP_PWM1 24 119 #define MT8173_MUTEX_MOD_DISP_OD 25 120 121 #define MT8188_MUTEX_MOD_DISP_OVL0 0 122 #define MT8188_MUTEX_MOD_DISP_WDMA0 1 123 #define MT8188_MUTEX_MOD_DISP_RDMA0 2 124 #define MT8188_MUTEX_MOD_DISP_COLOR0 3 125 #define MT8188_MUTEX_MOD_DISP_CCORR0 4 126 #define MT8188_MUTEX_MOD_DISP_AAL0 5 127 #define MT8188_MUTEX_MOD_DISP_GAMMA0 6 128 #define MT8188_MUTEX_MOD_DISP_DITHER0 7 129 #define MT8188_MUTEX_MOD_DISP_DSI0 8 130 #define MT8188_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9 131 #define MT8188_MUTEX_MOD_DISP_VPP_MERGE 20 132 #define MT8188_MUTEX_MOD_DISP_DP_INTF0 21 133 #define MT8188_MUTEX_MOD_DISP_POSTMASK0 24 134 #define MT8188_MUTEX_MOD2_DISP_PWM0 33 135 136 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA0 0 137 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA1 1 138 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA2 2 139 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA3 3 140 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA4 4 141 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA5 5 142 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA6 6 143 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA7 7 144 #define MT8188_MUTEX_MOD_DISP1_PADDING0 8 145 #define MT8188_MUTEX_MOD_DISP1_PADDING1 9 146 #define MT8188_MUTEX_MOD_DISP1_PADDING2 10 147 #define MT8188_MUTEX_MOD_DISP1_PADDING3 11 148 #define MT8188_MUTEX_MOD_DISP1_PADDING4 12 149 #define MT8188_MUTEX_MOD_DISP1_PADDING5 13 150 #define MT8188_MUTEX_MOD_DISP1_PADDING6 14 151 #define MT8188_MUTEX_MOD_DISP1_PADDING7 15 152 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE0 20 153 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE1 21 154 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE2 22 155 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE3 23 156 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE4 24 157 #define MT8188_MUTEX_MOD_DISP1_DISP_MIXER 30 158 #define MT8188_MUTEX_MOD_DISP1_DPI1 38 159 #define MT8188_MUTEX_MOD_DISP1_DP_INTF1 39 160 161 #define MT8195_MUTEX_MOD_DISP_OVL0 0 162 #define MT8195_MUTEX_MOD_DISP_WDMA0 1 163 #define MT8195_MUTEX_MOD_DISP_RDMA0 2 164 #define MT8195_MUTEX_MOD_DISP_COLOR0 3 165 #define MT8195_MUTEX_MOD_DISP_CCORR0 4 166 #define MT8195_MUTEX_MOD_DISP_AAL0 5 167 #define MT8195_MUTEX_MOD_DISP_GAMMA0 6 168 #define MT8195_MUTEX_MOD_DISP_DITHER0 7 169 #define MT8195_MUTEX_MOD_DISP_DSI0 8 170 #define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9 171 #define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20 172 #define MT8195_MUTEX_MOD_DISP_DP_INTF0 21 173 #define MT8195_MUTEX_MOD_DISP_PWM0 27 174 175 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 0 176 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 1 177 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 2 178 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 3 179 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 4 180 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 5 181 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 6 182 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 7 183 #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 8 184 #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 9 185 #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 10 186 #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 11 187 #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 12 188 #define MT8195_MUTEX_MOD_DISP1_DISP_MIXER 18 189 #define MT8195_MUTEX_MOD_DISP1_DPI0 25 190 #define MT8195_MUTEX_MOD_DISP1_DPI1 26 191 #define MT8195_MUTEX_MOD_DISP1_DP_INTF0 27 192 193 /* VPPSYS0 */ 194 #define MT8195_MUTEX_MOD_MDP_RDMA0 0 195 #define MT8195_MUTEX_MOD_MDP_FG0 1 196 #define MT8195_MUTEX_MOD_MDP_STITCH0 2 197 #define MT8195_MUTEX_MOD_MDP_HDR0 3 198 #define MT8195_MUTEX_MOD_MDP_AAL0 4 199 #define MT8195_MUTEX_MOD_MDP_RSZ0 5 200 #define MT8195_MUTEX_MOD_MDP_TDSHP0 6 201 #define MT8195_MUTEX_MOD_MDP_COLOR0 7 202 #define MT8195_MUTEX_MOD_MDP_OVL0 8 203 #define MT8195_MUTEX_MOD_MDP_PAD0 9 204 #define MT8195_MUTEX_MOD_MDP_TCC0 10 205 #define MT8195_MUTEX_MOD_MDP_WROT0 11 206 207 /* VPPSYS1 */ 208 #define MT8195_MUTEX_MOD_MDP_TCC1 3 209 #define MT8195_MUTEX_MOD_MDP_RDMA1 4 210 #define MT8195_MUTEX_MOD_MDP_RDMA2 5 211 #define MT8195_MUTEX_MOD_MDP_RDMA3 6 212 #define MT8195_MUTEX_MOD_MDP_FG1 7 213 #define MT8195_MUTEX_MOD_MDP_FG2 8 214 #define MT8195_MUTEX_MOD_MDP_FG3 9 215 #define MT8195_MUTEX_MOD_MDP_HDR1 10 216 #define MT8195_MUTEX_MOD_MDP_HDR2 11 217 #define MT8195_MUTEX_MOD_MDP_HDR3 12 218 #define MT8195_MUTEX_MOD_MDP_AAL1 13 219 #define MT8195_MUTEX_MOD_MDP_AAL2 14 220 #define MT8195_MUTEX_MOD_MDP_AAL3 15 221 #define MT8195_MUTEX_MOD_MDP_RSZ1 16 222 #define MT8195_MUTEX_MOD_MDP_RSZ2 17 223 #define MT8195_MUTEX_MOD_MDP_RSZ3 18 224 #define MT8195_MUTEX_MOD_MDP_TDSHP1 19 225 #define MT8195_MUTEX_MOD_MDP_TDSHP2 20 226 #define MT8195_MUTEX_MOD_MDP_TDSHP3 21 227 #define MT8195_MUTEX_MOD_MDP_MERGE2 22 228 #define MT8195_MUTEX_MOD_MDP_MERGE3 23 229 #define MT8195_MUTEX_MOD_MDP_COLOR1 24 230 #define MT8195_MUTEX_MOD_MDP_COLOR2 25 231 #define MT8195_MUTEX_MOD_MDP_COLOR3 26 232 #define MT8195_MUTEX_MOD_MDP_OVL1 27 233 #define MT8195_MUTEX_MOD_MDP_PAD1 28 234 #define MT8195_MUTEX_MOD_MDP_PAD2 29 235 #define MT8195_MUTEX_MOD_MDP_PAD3 30 236 #define MT8195_MUTEX_MOD_MDP_WROT1 31 237 #define MT8195_MUTEX_MOD_MDP_WROT2 32 238 #define MT8195_MUTEX_MOD_MDP_WROT3 33 239 240 #define MT8365_MUTEX_MOD_DISP_OVL0 7 241 #define MT8365_MUTEX_MOD_DISP_OVL0_2L 8 242 #define MT8365_MUTEX_MOD_DISP_RDMA0 9 243 #define MT8365_MUTEX_MOD_DISP_RDMA1 10 244 #define MT8365_MUTEX_MOD_DISP_WDMA0 11 245 #define MT8365_MUTEX_MOD_DISP_COLOR0 12 246 #define MT8365_MUTEX_MOD_DISP_CCORR 13 247 #define MT8365_MUTEX_MOD_DISP_AAL 14 248 #define MT8365_MUTEX_MOD_DISP_GAMMA 15 249 #define MT8365_MUTEX_MOD_DISP_DITHER 16 250 #define MT8365_MUTEX_MOD_DISP_DSI0 17 251 #define MT8365_MUTEX_MOD_DISP_PWM0 20 252 #define MT8365_MUTEX_MOD_DISP_DPI0 22 253 254 #define MT2712_MUTEX_MOD_DISP_PWM2 10 255 #define MT2712_MUTEX_MOD_DISP_OVL0 11 256 #define MT2712_MUTEX_MOD_DISP_OVL1 12 257 #define MT2712_MUTEX_MOD_DISP_RDMA0 13 258 #define MT2712_MUTEX_MOD_DISP_RDMA1 14 259 #define MT2712_MUTEX_MOD_DISP_RDMA2 15 260 #define MT2712_MUTEX_MOD_DISP_WDMA0 16 261 #define MT2712_MUTEX_MOD_DISP_WDMA1 17 262 #define MT2712_MUTEX_MOD_DISP_COLOR0 18 263 #define MT2712_MUTEX_MOD_DISP_COLOR1 19 264 #define MT2712_MUTEX_MOD_DISP_AAL0 20 265 #define MT2712_MUTEX_MOD_DISP_UFOE 22 266 #define MT2712_MUTEX_MOD_DISP_PWM0 23 267 #define MT2712_MUTEX_MOD_DISP_PWM1 24 268 #define MT2712_MUTEX_MOD_DISP_OD0 25 269 #define MT2712_MUTEX_MOD2_DISP_AAL1 33 270 #define MT2712_MUTEX_MOD2_DISP_OD1 34 271 272 #define MT2701_MUTEX_MOD_DISP_OVL 3 273 #define MT2701_MUTEX_MOD_DISP_WDMA 6 274 #define MT2701_MUTEX_MOD_DISP_COLOR 7 275 #define MT2701_MUTEX_MOD_DISP_BLS 9 276 #define MT2701_MUTEX_MOD_DISP_RDMA0 10 277 #define MT2701_MUTEX_MOD_DISP_RDMA1 12 278 279 #define MT2712_MUTEX_SOF_SINGLE_MODE 0 280 #define MT2712_MUTEX_SOF_DSI0 1 281 #define MT2712_MUTEX_SOF_DSI1 2 282 #define MT2712_MUTEX_SOF_DPI0 3 283 #define MT2712_MUTEX_SOF_DPI1 4 284 #define MT2712_MUTEX_SOF_DSI2 5 285 #define MT2712_MUTEX_SOF_DSI3 6 286 #define MT8167_MUTEX_SOF_DPI0 2 287 #define MT8167_MUTEX_SOF_DPI1 3 288 #define MT8183_MUTEX_SOF_DSI0 1 289 #define MT8183_MUTEX_SOF_DPI0 2 290 #define MT8188_MUTEX_SOF_DSI0 1 291 #define MT8188_MUTEX_SOF_DP_INTF0 3 292 #define MT8188_MUTEX_SOF_DP_INTF1 4 293 #define MT8188_MUTEX_SOF_DPI1 5 294 #define MT8195_MUTEX_SOF_DSI0 1 295 #define MT8195_MUTEX_SOF_DSI1 2 296 #define MT8195_MUTEX_SOF_DP_INTF0 3 297 #define MT8195_MUTEX_SOF_DP_INTF1 4 298 #define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */ 299 #define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */ 300 301 #define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6) 302 #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) 303 #define MT8188_MUTEX_EOF_DSI0 (MT8188_MUTEX_SOF_DSI0 << 7) 304 #define MT8188_MUTEX_EOF_DP_INTF0 (MT8188_MUTEX_SOF_DP_INTF0 << 7) 305 #define MT8188_MUTEX_EOF_DP_INTF1 (MT8188_MUTEX_SOF_DP_INTF1 << 7) 306 #define MT8188_MUTEX_EOF_DPI1 (MT8188_MUTEX_SOF_DPI1 << 7) 307 #define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7) 308 #define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7) 309 #define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7) 310 #define MT8195_MUTEX_EOF_DP_INTF1 (MT8195_MUTEX_SOF_DP_INTF1 << 7) 311 #define MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_SOF_DPI0 << 7) 312 #define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7) 313 314 struct mtk_mutex { 315 u8 id; 316 bool claimed; 317 }; 318 319 enum mtk_mutex_sof_id { 320 MUTEX_SOF_SINGLE_MODE, 321 MUTEX_SOF_DSI0, 322 MUTEX_SOF_DSI1, 323 MUTEX_SOF_DPI0, 324 MUTEX_SOF_DPI1, 325 MUTEX_SOF_DSI2, 326 MUTEX_SOF_DSI3, 327 MUTEX_SOF_DP_INTF0, 328 MUTEX_SOF_DP_INTF1, 329 DDP_MUTEX_SOF_MAX, 330 }; 331 332 struct mtk_mutex_data { 333 const u8 *mutex_mod; 334 const u8 *mutex_table_mod; 335 const u16 *mutex_sof; 336 const u16 mutex_mod_reg; 337 const u16 mutex_sof_reg; 338 const bool no_clk; 339 }; 340 341 struct mtk_mutex_ctx { 342 struct device *dev; 343 struct clk *clk; 344 void __iomem *regs; 345 struct mtk_mutex mutex[MTK_MUTEX_MAX_HANDLES]; 346 const struct mtk_mutex_data *data; 347 phys_addr_t addr; 348 struct cmdq_client_reg cmdq_reg; 349 }; 350 351 static const u8 mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { 352 [DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS, 353 [DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR, 354 [DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL, 355 [DDP_COMPONENT_RDMA0] = MT2701_MUTEX_MOD_DISP_RDMA0, 356 [DDP_COMPONENT_RDMA1] = MT2701_MUTEX_MOD_DISP_RDMA1, 357 [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA, 358 }; 359 360 static const u8 mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { 361 [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0, 362 [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1, 363 [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0, 364 [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1, 365 [DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0, 366 [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1, 367 [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0, 368 [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1, 369 [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0, 370 [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1, 371 [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2, 372 [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0, 373 [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1, 374 [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2, 375 [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE, 376 [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0, 377 [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1, 378 }; 379 380 static const u8 mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = { 381 [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL, 382 [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR, 383 [DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR, 384 [DDP_COMPONENT_DITHER0] = MT8167_MUTEX_MOD_DISP_DITHER, 385 [DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA, 386 [DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0, 387 [DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1, 388 [DDP_COMPONENT_PWM0] = MT8167_MUTEX_MOD_DISP_PWM, 389 [DDP_COMPONENT_RDMA0] = MT8167_MUTEX_MOD_DISP_RDMA0, 390 [DDP_COMPONENT_RDMA1] = MT8167_MUTEX_MOD_DISP_RDMA1, 391 [DDP_COMPONENT_UFOE] = MT8167_MUTEX_MOD_DISP_UFOE, 392 [DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0, 393 }; 394 395 static const u8 mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { 396 [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL, 397 [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0, 398 [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1, 399 [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA, 400 [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD, 401 [DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0, 402 [DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1, 403 [DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0, 404 [DDP_COMPONENT_PWM1] = MT8173_MUTEX_MOD_DISP_PWM1, 405 [DDP_COMPONENT_RDMA0] = MT8173_MUTEX_MOD_DISP_RDMA0, 406 [DDP_COMPONENT_RDMA1] = MT8173_MUTEX_MOD_DISP_RDMA1, 407 [DDP_COMPONENT_RDMA2] = MT8173_MUTEX_MOD_DISP_RDMA2, 408 [DDP_COMPONENT_UFOE] = MT8173_MUTEX_MOD_DISP_UFOE, 409 [DDP_COMPONENT_WDMA0] = MT8173_MUTEX_MOD_DISP_WDMA0, 410 [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, 411 }; 412 413 static const u8 mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { 414 [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, 415 [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, 416 [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, 417 [DDP_COMPONENT_DITHER0] = MT8183_MUTEX_MOD_DISP_DITHER0, 418 [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, 419 [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, 420 [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, 421 [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, 422 [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, 423 [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, 424 [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, 425 }; 426 427 static const u8 mt8183_mutex_table_mod[MUTEX_MOD_IDX_MAX] = { 428 [MUTEX_MOD_IDX_MDP_RDMA0] = MT8183_MUTEX_MOD_MDP_RDMA0, 429 [MUTEX_MOD_IDX_MDP_RSZ0] = MT8183_MUTEX_MOD_MDP_RSZ0, 430 [MUTEX_MOD_IDX_MDP_RSZ1] = MT8183_MUTEX_MOD_MDP_RSZ1, 431 [MUTEX_MOD_IDX_MDP_TDSHP0] = MT8183_MUTEX_MOD_MDP_TDSHP0, 432 [MUTEX_MOD_IDX_MDP_WROT0] = MT8183_MUTEX_MOD_MDP_WROT0, 433 [MUTEX_MOD_IDX_MDP_WDMA] = MT8183_MUTEX_MOD_MDP_WDMA, 434 [MUTEX_MOD_IDX_MDP_AAL0] = MT8183_MUTEX_MOD_MDP_AAL0, 435 [MUTEX_MOD_IDX_MDP_CCORR0] = MT8183_MUTEX_MOD_MDP_CCORR0, 436 }; 437 438 static const u8 mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = { 439 [DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0, 440 [DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0, 441 [DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0, 442 [DDP_COMPONENT_DITHER0] = MT8186_MUTEX_MOD_DISP_DITHER0, 443 [DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0, 444 [DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0, 445 [DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L, 446 [DDP_COMPONENT_POSTMASK0] = MT8186_MUTEX_MOD_DISP_POSTMASK0, 447 [DDP_COMPONENT_RDMA0] = MT8186_MUTEX_MOD_DISP_RDMA0, 448 [DDP_COMPONENT_RDMA1] = MT8186_MUTEX_MOD_DISP_RDMA1, 449 }; 450 451 static const u8 mt8186_mdp_mutex_table_mod[MUTEX_MOD_IDX_MAX] = { 452 [MUTEX_MOD_IDX_MDP_RDMA0] = MT8186_MUTEX_MOD_MDP_RDMA0, 453 [MUTEX_MOD_IDX_MDP_RSZ0] = MT8186_MUTEX_MOD_MDP_RSZ0, 454 [MUTEX_MOD_IDX_MDP_RSZ1] = MT8186_MUTEX_MOD_MDP_RSZ1, 455 [MUTEX_MOD_IDX_MDP_TDSHP0] = MT8186_MUTEX_MOD_MDP_TDSHP0, 456 [MUTEX_MOD_IDX_MDP_WROT0] = MT8186_MUTEX_MOD_MDP_WROT0, 457 [MUTEX_MOD_IDX_MDP_HDR0] = MT8186_MUTEX_MOD_MDP_HDR0, 458 [MUTEX_MOD_IDX_MDP_AAL0] = MT8186_MUTEX_MOD_MDP_AAL0, 459 [MUTEX_MOD_IDX_MDP_COLOR0] = MT8186_MUTEX_MOD_MDP_COLOR0, 460 }; 461 462 static const u8 mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = { 463 [DDP_COMPONENT_OVL0] = MT8188_MUTEX_MOD_DISP_OVL0, 464 [DDP_COMPONENT_WDMA0] = MT8188_MUTEX_MOD_DISP_WDMA0, 465 [DDP_COMPONENT_RDMA0] = MT8188_MUTEX_MOD_DISP_RDMA0, 466 [DDP_COMPONENT_COLOR0] = MT8188_MUTEX_MOD_DISP_COLOR0, 467 [DDP_COMPONENT_CCORR] = MT8188_MUTEX_MOD_DISP_CCORR0, 468 [DDP_COMPONENT_AAL0] = MT8188_MUTEX_MOD_DISP_AAL0, 469 [DDP_COMPONENT_GAMMA] = MT8188_MUTEX_MOD_DISP_GAMMA0, 470 [DDP_COMPONENT_POSTMASK0] = MT8188_MUTEX_MOD_DISP_POSTMASK0, 471 [DDP_COMPONENT_DITHER0] = MT8188_MUTEX_MOD_DISP_DITHER0, 472 [DDP_COMPONENT_MERGE0] = MT8188_MUTEX_MOD_DISP_VPP_MERGE, 473 [DDP_COMPONENT_DSC0] = MT8188_MUTEX_MOD_DISP_DSC_WRAP0_CORE0, 474 [DDP_COMPONENT_DSI0] = MT8188_MUTEX_MOD_DISP_DSI0, 475 [DDP_COMPONENT_PWM0] = MT8188_MUTEX_MOD2_DISP_PWM0, 476 [DDP_COMPONENT_DP_INTF0] = MT8188_MUTEX_MOD_DISP_DP_INTF0, 477 [DDP_COMPONENT_DP_INTF1] = MT8188_MUTEX_MOD_DISP1_DP_INTF1, 478 [DDP_COMPONENT_DPI1] = MT8188_MUTEX_MOD_DISP1_DPI1, 479 [DDP_COMPONENT_ETHDR_MIXER] = MT8188_MUTEX_MOD_DISP1_DISP_MIXER, 480 [DDP_COMPONENT_MDP_RDMA0] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA0, 481 [DDP_COMPONENT_MDP_RDMA1] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA1, 482 [DDP_COMPONENT_MDP_RDMA2] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA2, 483 [DDP_COMPONENT_MDP_RDMA3] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA3, 484 [DDP_COMPONENT_MDP_RDMA4] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA4, 485 [DDP_COMPONENT_MDP_RDMA5] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA5, 486 [DDP_COMPONENT_MDP_RDMA6] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA6, 487 [DDP_COMPONENT_MDP_RDMA7] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA7, 488 [DDP_COMPONENT_PADDING0] = MT8188_MUTEX_MOD_DISP1_PADDING0, 489 [DDP_COMPONENT_PADDING1] = MT8188_MUTEX_MOD_DISP1_PADDING1, 490 [DDP_COMPONENT_PADDING2] = MT8188_MUTEX_MOD_DISP1_PADDING2, 491 [DDP_COMPONENT_PADDING3] = MT8188_MUTEX_MOD_DISP1_PADDING3, 492 [DDP_COMPONENT_PADDING4] = MT8188_MUTEX_MOD_DISP1_PADDING4, 493 [DDP_COMPONENT_PADDING5] = MT8188_MUTEX_MOD_DISP1_PADDING5, 494 [DDP_COMPONENT_PADDING6] = MT8188_MUTEX_MOD_DISP1_PADDING6, 495 [DDP_COMPONENT_PADDING7] = MT8188_MUTEX_MOD_DISP1_PADDING7, 496 [DDP_COMPONENT_MERGE1] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE0, 497 [DDP_COMPONENT_MERGE2] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE1, 498 [DDP_COMPONENT_MERGE3] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE2, 499 [DDP_COMPONENT_MERGE4] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE3, 500 [DDP_COMPONENT_MERGE5] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE4, 501 }; 502 503 static const u8 mt8188_mdp_mutex_table_mod[MUTEX_MOD_IDX_MAX] = { 504 [MUTEX_MOD_IDX_MDP_RDMA0] = MT8195_MUTEX_MOD_MDP_RDMA0, 505 [MUTEX_MOD_IDX_MDP_RDMA2] = MT8195_MUTEX_MOD_MDP_RDMA2, 506 [MUTEX_MOD_IDX_MDP_RDMA3] = MT8195_MUTEX_MOD_MDP_RDMA3, 507 [MUTEX_MOD_IDX_MDP_FG0] = MT8195_MUTEX_MOD_MDP_FG0, 508 [MUTEX_MOD_IDX_MDP_FG2] = MT8195_MUTEX_MOD_MDP_FG2, 509 [MUTEX_MOD_IDX_MDP_FG3] = MT8195_MUTEX_MOD_MDP_FG3, 510 [MUTEX_MOD_IDX_MDP_HDR0] = MT8195_MUTEX_MOD_MDP_HDR0, 511 [MUTEX_MOD_IDX_MDP_HDR2] = MT8195_MUTEX_MOD_MDP_HDR2, 512 [MUTEX_MOD_IDX_MDP_HDR3] = MT8195_MUTEX_MOD_MDP_HDR3, 513 [MUTEX_MOD_IDX_MDP_AAL0] = MT8195_MUTEX_MOD_MDP_AAL0, 514 [MUTEX_MOD_IDX_MDP_AAL2] = MT8195_MUTEX_MOD_MDP_AAL2, 515 [MUTEX_MOD_IDX_MDP_AAL3] = MT8195_MUTEX_MOD_MDP_AAL3, 516 [MUTEX_MOD_IDX_MDP_RSZ0] = MT8195_MUTEX_MOD_MDP_RSZ0, 517 [MUTEX_MOD_IDX_MDP_RSZ2] = MT8195_MUTEX_MOD_MDP_RSZ2, 518 [MUTEX_MOD_IDX_MDP_RSZ3] = MT8195_MUTEX_MOD_MDP_RSZ3, 519 [MUTEX_MOD_IDX_MDP_MERGE2] = MT8195_MUTEX_MOD_MDP_MERGE2, 520 [MUTEX_MOD_IDX_MDP_MERGE3] = MT8195_MUTEX_MOD_MDP_MERGE3, 521 [MUTEX_MOD_IDX_MDP_TDSHP0] = MT8195_MUTEX_MOD_MDP_TDSHP0, 522 [MUTEX_MOD_IDX_MDP_TDSHP2] = MT8195_MUTEX_MOD_MDP_TDSHP2, 523 [MUTEX_MOD_IDX_MDP_TDSHP3] = MT8195_MUTEX_MOD_MDP_TDSHP3, 524 [MUTEX_MOD_IDX_MDP_COLOR0] = MT8195_MUTEX_MOD_MDP_COLOR0, 525 [MUTEX_MOD_IDX_MDP_COLOR2] = MT8195_MUTEX_MOD_MDP_COLOR2, 526 [MUTEX_MOD_IDX_MDP_COLOR3] = MT8195_MUTEX_MOD_MDP_COLOR3, 527 [MUTEX_MOD_IDX_MDP_OVL0] = MT8195_MUTEX_MOD_MDP_OVL0, 528 [MUTEX_MOD_IDX_MDP_PAD0] = MT8195_MUTEX_MOD_MDP_PAD0, 529 [MUTEX_MOD_IDX_MDP_PAD2] = MT8195_MUTEX_MOD_MDP_PAD2, 530 [MUTEX_MOD_IDX_MDP_PAD3] = MT8195_MUTEX_MOD_MDP_PAD3, 531 [MUTEX_MOD_IDX_MDP_TCC0] = MT8195_MUTEX_MOD_MDP_TCC0, 532 [MUTEX_MOD_IDX_MDP_WROT0] = MT8195_MUTEX_MOD_MDP_WROT0, 533 [MUTEX_MOD_IDX_MDP_WROT2] = MT8195_MUTEX_MOD_MDP_WROT2, 534 [MUTEX_MOD_IDX_MDP_WROT3] = MT8195_MUTEX_MOD_MDP_WROT3, 535 }; 536 537 static const u8 mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = { 538 [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0, 539 [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0, 540 [DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0, 541 [DDP_COMPONENT_DITHER0] = MT8192_MUTEX_MOD_DISP_DITHER0, 542 [DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0, 543 [DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0, 544 [DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0, 545 [DDP_COMPONENT_OVL_2L0] = MT8192_MUTEX_MOD_DISP_OVL0_2L, 546 [DDP_COMPONENT_OVL_2L2] = MT8192_MUTEX_MOD_DISP_OVL2_2L, 547 [DDP_COMPONENT_RDMA0] = MT8192_MUTEX_MOD_DISP_RDMA0, 548 [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4, 549 }; 550 551 static const u8 mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = { 552 [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0, 553 [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0, 554 [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0, 555 [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0, 556 [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0, 557 [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0, 558 [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0, 559 [DDP_COMPONENT_DITHER0] = MT8195_MUTEX_MOD_DISP_DITHER0, 560 [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE, 561 [DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0, 562 [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0, 563 [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0, 564 [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0, 565 [DDP_COMPONENT_MDP_RDMA0] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA0, 566 [DDP_COMPONENT_MDP_RDMA1] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA1, 567 [DDP_COMPONENT_MDP_RDMA2] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA2, 568 [DDP_COMPONENT_MDP_RDMA3] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA3, 569 [DDP_COMPONENT_MDP_RDMA4] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA4, 570 [DDP_COMPONENT_MDP_RDMA5] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA5, 571 [DDP_COMPONENT_MDP_RDMA6] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA6, 572 [DDP_COMPONENT_MDP_RDMA7] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA7, 573 [DDP_COMPONENT_MERGE1] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE0, 574 [DDP_COMPONENT_MERGE2] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE1, 575 [DDP_COMPONENT_MERGE3] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE2, 576 [DDP_COMPONENT_MERGE4] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE3, 577 [DDP_COMPONENT_ETHDR_MIXER] = MT8195_MUTEX_MOD_DISP1_DISP_MIXER, 578 [DDP_COMPONENT_MERGE5] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE4, 579 [DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0, 580 }; 581 582 static const u8 mt8195_mutex_table_mod[MUTEX_MOD_IDX_MAX] = { 583 [MUTEX_MOD_IDX_MDP_RDMA0] = MT8195_MUTEX_MOD_MDP_RDMA0, 584 [MUTEX_MOD_IDX_MDP_RDMA1] = MT8195_MUTEX_MOD_MDP_RDMA1, 585 [MUTEX_MOD_IDX_MDP_RDMA2] = MT8195_MUTEX_MOD_MDP_RDMA2, 586 [MUTEX_MOD_IDX_MDP_RDMA3] = MT8195_MUTEX_MOD_MDP_RDMA3, 587 [MUTEX_MOD_IDX_MDP_STITCH0] = MT8195_MUTEX_MOD_MDP_STITCH0, 588 [MUTEX_MOD_IDX_MDP_FG0] = MT8195_MUTEX_MOD_MDP_FG0, 589 [MUTEX_MOD_IDX_MDP_FG1] = MT8195_MUTEX_MOD_MDP_FG1, 590 [MUTEX_MOD_IDX_MDP_FG2] = MT8195_MUTEX_MOD_MDP_FG2, 591 [MUTEX_MOD_IDX_MDP_FG3] = MT8195_MUTEX_MOD_MDP_FG3, 592 [MUTEX_MOD_IDX_MDP_HDR0] = MT8195_MUTEX_MOD_MDP_HDR0, 593 [MUTEX_MOD_IDX_MDP_HDR1] = MT8195_MUTEX_MOD_MDP_HDR1, 594 [MUTEX_MOD_IDX_MDP_HDR2] = MT8195_MUTEX_MOD_MDP_HDR2, 595 [MUTEX_MOD_IDX_MDP_HDR3] = MT8195_MUTEX_MOD_MDP_HDR3, 596 [MUTEX_MOD_IDX_MDP_AAL0] = MT8195_MUTEX_MOD_MDP_AAL0, 597 [MUTEX_MOD_IDX_MDP_AAL1] = MT8195_MUTEX_MOD_MDP_AAL1, 598 [MUTEX_MOD_IDX_MDP_AAL2] = MT8195_MUTEX_MOD_MDP_AAL2, 599 [MUTEX_MOD_IDX_MDP_AAL3] = MT8195_MUTEX_MOD_MDP_AAL3, 600 [MUTEX_MOD_IDX_MDP_RSZ0] = MT8195_MUTEX_MOD_MDP_RSZ0, 601 [MUTEX_MOD_IDX_MDP_RSZ1] = MT8195_MUTEX_MOD_MDP_RSZ1, 602 [MUTEX_MOD_IDX_MDP_RSZ2] = MT8195_MUTEX_MOD_MDP_RSZ2, 603 [MUTEX_MOD_IDX_MDP_RSZ3] = MT8195_MUTEX_MOD_MDP_RSZ3, 604 [MUTEX_MOD_IDX_MDP_MERGE2] = MT8195_MUTEX_MOD_MDP_MERGE2, 605 [MUTEX_MOD_IDX_MDP_MERGE3] = MT8195_MUTEX_MOD_MDP_MERGE3, 606 [MUTEX_MOD_IDX_MDP_TDSHP0] = MT8195_MUTEX_MOD_MDP_TDSHP0, 607 [MUTEX_MOD_IDX_MDP_TDSHP1] = MT8195_MUTEX_MOD_MDP_TDSHP1, 608 [MUTEX_MOD_IDX_MDP_TDSHP2] = MT8195_MUTEX_MOD_MDP_TDSHP2, 609 [MUTEX_MOD_IDX_MDP_TDSHP3] = MT8195_MUTEX_MOD_MDP_TDSHP3, 610 [MUTEX_MOD_IDX_MDP_COLOR0] = MT8195_MUTEX_MOD_MDP_COLOR0, 611 [MUTEX_MOD_IDX_MDP_COLOR1] = MT8195_MUTEX_MOD_MDP_COLOR1, 612 [MUTEX_MOD_IDX_MDP_COLOR2] = MT8195_MUTEX_MOD_MDP_COLOR2, 613 [MUTEX_MOD_IDX_MDP_COLOR3] = MT8195_MUTEX_MOD_MDP_COLOR3, 614 [MUTEX_MOD_IDX_MDP_OVL0] = MT8195_MUTEX_MOD_MDP_OVL0, 615 [MUTEX_MOD_IDX_MDP_OVL1] = MT8195_MUTEX_MOD_MDP_OVL1, 616 [MUTEX_MOD_IDX_MDP_PAD0] = MT8195_MUTEX_MOD_MDP_PAD0, 617 [MUTEX_MOD_IDX_MDP_PAD1] = MT8195_MUTEX_MOD_MDP_PAD1, 618 [MUTEX_MOD_IDX_MDP_PAD2] = MT8195_MUTEX_MOD_MDP_PAD2, 619 [MUTEX_MOD_IDX_MDP_PAD3] = MT8195_MUTEX_MOD_MDP_PAD3, 620 [MUTEX_MOD_IDX_MDP_TCC0] = MT8195_MUTEX_MOD_MDP_TCC0, 621 [MUTEX_MOD_IDX_MDP_TCC1] = MT8195_MUTEX_MOD_MDP_TCC1, 622 [MUTEX_MOD_IDX_MDP_WROT0] = MT8195_MUTEX_MOD_MDP_WROT0, 623 [MUTEX_MOD_IDX_MDP_WROT1] = MT8195_MUTEX_MOD_MDP_WROT1, 624 [MUTEX_MOD_IDX_MDP_WROT2] = MT8195_MUTEX_MOD_MDP_WROT2, 625 [MUTEX_MOD_IDX_MDP_WROT3] = MT8195_MUTEX_MOD_MDP_WROT3, 626 }; 627 628 static const u8 mt8365_mutex_mod[DDP_COMPONENT_ID_MAX] = { 629 [DDP_COMPONENT_AAL0] = MT8365_MUTEX_MOD_DISP_AAL, 630 [DDP_COMPONENT_CCORR] = MT8365_MUTEX_MOD_DISP_CCORR, 631 [DDP_COMPONENT_COLOR0] = MT8365_MUTEX_MOD_DISP_COLOR0, 632 [DDP_COMPONENT_DITHER0] = MT8365_MUTEX_MOD_DISP_DITHER, 633 [DDP_COMPONENT_DPI0] = MT8365_MUTEX_MOD_DISP_DPI0, 634 [DDP_COMPONENT_DSI0] = MT8365_MUTEX_MOD_DISP_DSI0, 635 [DDP_COMPONENT_GAMMA] = MT8365_MUTEX_MOD_DISP_GAMMA, 636 [DDP_COMPONENT_OVL0] = MT8365_MUTEX_MOD_DISP_OVL0, 637 [DDP_COMPONENT_OVL_2L0] = MT8365_MUTEX_MOD_DISP_OVL0_2L, 638 [DDP_COMPONENT_PWM0] = MT8365_MUTEX_MOD_DISP_PWM0, 639 [DDP_COMPONENT_RDMA0] = MT8365_MUTEX_MOD_DISP_RDMA0, 640 [DDP_COMPONENT_RDMA1] = MT8365_MUTEX_MOD_DISP_RDMA1, 641 [DDP_COMPONENT_WDMA0] = MT8365_MUTEX_MOD_DISP_WDMA0, 642 }; 643 644 static const u16 mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = { 645 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, 646 [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, 647 [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1, 648 [MUTEX_SOF_DPI0] = MUTEX_SOF_DPI0, 649 [MUTEX_SOF_DPI1] = MUTEX_SOF_DPI1, 650 [MUTEX_SOF_DSI2] = MUTEX_SOF_DSI2, 651 [MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, 652 }; 653 654 static const u16 mt6795_mutex_sof[DDP_MUTEX_SOF_MAX] = { 655 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, 656 [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, 657 [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1, 658 [MUTEX_SOF_DPI0] = MUTEX_SOF_DPI0, 659 }; 660 661 static const u16 mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = { 662 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, 663 [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, 664 [MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0, 665 [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1, 666 }; 667 668 /* Add EOF setting so overlay hardware can receive frame done irq */ 669 static const u16 mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = { 670 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, 671 [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, 672 [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, 673 }; 674 675 static const u16 mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = { 676 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, 677 [MUTEX_SOF_DSI0] = MT8186_MUTEX_SOF_DSI0 | MT8186_MUTEX_EOF_DSI0, 678 [MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0, 679 }; 680 681 /* 682 * To support refresh mode(video mode), DISP_REG_MUTEX_SOF should 683 * select the EOF source and configure the EOF plus timing from the 684 * module that provides the timing signal. 685 * So that MUTEX can not only send a STREAM_DONE event to GCE 686 * but also detect the error at end of frame(EAEOF) when EOF signal 687 * arrives. 688 */ 689 static const u16 mt8188_mutex_sof[DDP_MUTEX_SOF_MAX] = { 690 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, 691 [MUTEX_SOF_DSI0] = 692 MT8188_MUTEX_SOF_DSI0 | MT8188_MUTEX_EOF_DSI0, 693 [MUTEX_SOF_DPI1] = 694 MT8188_MUTEX_SOF_DPI1 | MT8188_MUTEX_EOF_DPI1, 695 [MUTEX_SOF_DP_INTF0] = 696 MT8188_MUTEX_SOF_DP_INTF0 | MT8188_MUTEX_EOF_DP_INTF0, 697 [MUTEX_SOF_DP_INTF1] = 698 MT8188_MUTEX_SOF_DP_INTF1 | MT8188_MUTEX_EOF_DP_INTF1, 699 }; 700 701 static const u16 mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = { 702 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, 703 [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0, 704 [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1, 705 [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0, 706 [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1, 707 [MUTEX_SOF_DP_INTF0] = 708 MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0, 709 [MUTEX_SOF_DP_INTF1] = 710 MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1, 711 }; 712 713 static const struct mtk_mutex_data mt2701_mutex_driver_data = { 714 .mutex_mod = mt2701_mutex_mod, 715 .mutex_sof = mt2712_mutex_sof, 716 .mutex_mod_reg = MT2701_MUTEX0_MOD0, 717 .mutex_sof_reg = MT2701_MUTEX0_SOF0, 718 }; 719 720 static const struct mtk_mutex_data mt2712_mutex_driver_data = { 721 .mutex_mod = mt2712_mutex_mod, 722 .mutex_sof = mt2712_mutex_sof, 723 .mutex_mod_reg = MT2701_MUTEX0_MOD0, 724 .mutex_sof_reg = MT2701_MUTEX0_SOF0, 725 }; 726 727 static const struct mtk_mutex_data mt6795_mutex_driver_data = { 728 .mutex_mod = mt8173_mutex_mod, 729 .mutex_sof = mt6795_mutex_sof, 730 .mutex_mod_reg = MT2701_MUTEX0_MOD0, 731 .mutex_sof_reg = MT2701_MUTEX0_SOF0, 732 }; 733 734 static const struct mtk_mutex_data mt8167_mutex_driver_data = { 735 .mutex_mod = mt8167_mutex_mod, 736 .mutex_sof = mt8167_mutex_sof, 737 .mutex_mod_reg = MT2701_MUTEX0_MOD0, 738 .mutex_sof_reg = MT2701_MUTEX0_SOF0, 739 .no_clk = true, 740 }; 741 742 static const struct mtk_mutex_data mt8173_mutex_driver_data = { 743 .mutex_mod = mt8173_mutex_mod, 744 .mutex_sof = mt2712_mutex_sof, 745 .mutex_mod_reg = MT2701_MUTEX0_MOD0, 746 .mutex_sof_reg = MT2701_MUTEX0_SOF0, 747 }; 748 749 static const struct mtk_mutex_data mt8183_mutex_driver_data = { 750 .mutex_mod = mt8183_mutex_mod, 751 .mutex_sof = mt8183_mutex_sof, 752 .mutex_mod_reg = MT8183_MUTEX0_MOD0, 753 .mutex_sof_reg = MT8183_MUTEX0_SOF0, 754 .mutex_table_mod = mt8183_mutex_table_mod, 755 .no_clk = true, 756 }; 757 758 static const struct mtk_mutex_data mt8186_mdp_mutex_driver_data = { 759 .mutex_mod_reg = MT8183_MUTEX0_MOD0, 760 .mutex_sof_reg = MT8183_MUTEX0_SOF0, 761 .mutex_table_mod = mt8186_mdp_mutex_table_mod, 762 }; 763 764 static const struct mtk_mutex_data mt8186_mutex_driver_data = { 765 .mutex_mod = mt8186_mutex_mod, 766 .mutex_sof = mt8186_mutex_sof, 767 .mutex_mod_reg = MT8183_MUTEX0_MOD0, 768 .mutex_sof_reg = MT8183_MUTEX0_SOF0, 769 }; 770 771 static const struct mtk_mutex_data mt8188_mutex_driver_data = { 772 .mutex_mod = mt8188_mutex_mod, 773 .mutex_sof = mt8188_mutex_sof, 774 .mutex_mod_reg = MT8183_MUTEX0_MOD0, 775 .mutex_sof_reg = MT8183_MUTEX0_SOF0, 776 }; 777 778 static const struct mtk_mutex_data mt8188_vpp_mutex_driver_data = { 779 .mutex_sof = mt8188_mutex_sof, 780 .mutex_mod_reg = MT8183_MUTEX0_MOD0, 781 .mutex_sof_reg = MT8183_MUTEX0_SOF0, 782 .mutex_table_mod = mt8188_mdp_mutex_table_mod, 783 }; 784 785 static const struct mtk_mutex_data mt8192_mutex_driver_data = { 786 .mutex_mod = mt8192_mutex_mod, 787 .mutex_sof = mt8183_mutex_sof, 788 .mutex_mod_reg = MT8183_MUTEX0_MOD0, 789 .mutex_sof_reg = MT8183_MUTEX0_SOF0, 790 }; 791 792 static const struct mtk_mutex_data mt8195_mutex_driver_data = { 793 .mutex_mod = mt8195_mutex_mod, 794 .mutex_sof = mt8195_mutex_sof, 795 .mutex_mod_reg = MT8183_MUTEX0_MOD0, 796 .mutex_sof_reg = MT8183_MUTEX0_SOF0, 797 }; 798 799 static const struct mtk_mutex_data mt8195_vpp_mutex_driver_data = { 800 .mutex_sof = mt8195_mutex_sof, 801 .mutex_mod_reg = MT8183_MUTEX0_MOD0, 802 .mutex_sof_reg = MT8183_MUTEX0_SOF0, 803 .mutex_table_mod = mt8195_mutex_table_mod, 804 }; 805 806 static const struct mtk_mutex_data mt8365_mutex_driver_data = { 807 .mutex_mod = mt8365_mutex_mod, 808 .mutex_sof = mt8183_mutex_sof, 809 .mutex_mod_reg = MT8183_MUTEX0_MOD0, 810 .mutex_sof_reg = MT8183_MUTEX0_SOF0, 811 .no_clk = true, 812 }; 813 814 struct mtk_mutex *mtk_mutex_get(struct device *dev) 815 { 816 struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); 817 int i; 818 819 for (i = 0; i < MTK_MUTEX_MAX_HANDLES; i++) 820 if (!mtx->mutex[i].claimed) { 821 mtx->mutex[i].claimed = true; 822 return &mtx->mutex[i]; 823 } 824 825 return ERR_PTR(-EBUSY); 826 } 827 EXPORT_SYMBOL_GPL(mtk_mutex_get); 828 829 void mtk_mutex_put(struct mtk_mutex *mutex) 830 { 831 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 832 mutex[mutex->id]); 833 834 WARN_ON(&mtx->mutex[mutex->id] != mutex); 835 836 mutex->claimed = false; 837 } 838 EXPORT_SYMBOL_GPL(mtk_mutex_put); 839 840 int mtk_mutex_prepare(struct mtk_mutex *mutex) 841 { 842 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 843 mutex[mutex->id]); 844 return clk_prepare_enable(mtx->clk); 845 } 846 EXPORT_SYMBOL_GPL(mtk_mutex_prepare); 847 848 void mtk_mutex_unprepare(struct mtk_mutex *mutex) 849 { 850 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 851 mutex[mutex->id]); 852 clk_disable_unprepare(mtx->clk); 853 } 854 EXPORT_SYMBOL_GPL(mtk_mutex_unprepare); 855 856 void mtk_mutex_add_comp(struct mtk_mutex *mutex, 857 enum mtk_ddp_comp_id id) 858 { 859 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 860 mutex[mutex->id]); 861 unsigned int reg; 862 unsigned int sof_id; 863 unsigned int offset; 864 865 WARN_ON(&mtx->mutex[mutex->id] != mutex); 866 867 switch (id) { 868 case DDP_COMPONENT_DSI0: 869 sof_id = MUTEX_SOF_DSI0; 870 break; 871 case DDP_COMPONENT_DSI1: 872 sof_id = MUTEX_SOF_DSI0; 873 break; 874 case DDP_COMPONENT_DSI2: 875 sof_id = MUTEX_SOF_DSI2; 876 break; 877 case DDP_COMPONENT_DSI3: 878 sof_id = MUTEX_SOF_DSI3; 879 break; 880 case DDP_COMPONENT_DPI0: 881 sof_id = MUTEX_SOF_DPI0; 882 break; 883 case DDP_COMPONENT_DPI1: 884 sof_id = MUTEX_SOF_DPI1; 885 break; 886 case DDP_COMPONENT_DP_INTF0: 887 sof_id = MUTEX_SOF_DP_INTF0; 888 break; 889 case DDP_COMPONENT_DP_INTF1: 890 sof_id = MUTEX_SOF_DP_INTF1; 891 break; 892 default: 893 if (mtx->data->mutex_mod[id] < 32) { 894 offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, 895 mutex->id); 896 reg = readl_relaxed(mtx->regs + offset); 897 reg |= 1 << mtx->data->mutex_mod[id]; 898 writel_relaxed(reg, mtx->regs + offset); 899 } else { 900 offset = DISP_REG_MUTEX_MOD2(mutex->id); 901 reg = readl_relaxed(mtx->regs + offset); 902 reg |= 1 << (mtx->data->mutex_mod[id] - 32); 903 writel_relaxed(reg, mtx->regs + offset); 904 } 905 return; 906 } 907 908 writel_relaxed(mtx->data->mutex_sof[sof_id], 909 mtx->regs + 910 DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id)); 911 } 912 EXPORT_SYMBOL_GPL(mtk_mutex_add_comp); 913 914 void mtk_mutex_remove_comp(struct mtk_mutex *mutex, 915 enum mtk_ddp_comp_id id) 916 { 917 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 918 mutex[mutex->id]); 919 unsigned int reg; 920 unsigned int offset; 921 922 WARN_ON(&mtx->mutex[mutex->id] != mutex); 923 924 switch (id) { 925 case DDP_COMPONENT_DSI0: 926 case DDP_COMPONENT_DSI1: 927 case DDP_COMPONENT_DSI2: 928 case DDP_COMPONENT_DSI3: 929 case DDP_COMPONENT_DPI0: 930 case DDP_COMPONENT_DPI1: 931 case DDP_COMPONENT_DP_INTF0: 932 case DDP_COMPONENT_DP_INTF1: 933 writel_relaxed(MUTEX_SOF_SINGLE_MODE, 934 mtx->regs + 935 DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, 936 mutex->id)); 937 break; 938 default: 939 if (mtx->data->mutex_mod[id] < 32) { 940 offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, 941 mutex->id); 942 reg = readl_relaxed(mtx->regs + offset); 943 reg &= ~(1 << mtx->data->mutex_mod[id]); 944 writel_relaxed(reg, mtx->regs + offset); 945 } else { 946 offset = DISP_REG_MUTEX_MOD2(mutex->id); 947 reg = readl_relaxed(mtx->regs + offset); 948 reg &= ~(1 << (mtx->data->mutex_mod[id] - 32)); 949 writel_relaxed(reg, mtx->regs + offset); 950 } 951 break; 952 } 953 } 954 EXPORT_SYMBOL_GPL(mtk_mutex_remove_comp); 955 956 void mtk_mutex_enable(struct mtk_mutex *mutex) 957 { 958 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 959 mutex[mutex->id]); 960 961 WARN_ON(&mtx->mutex[mutex->id] != mutex); 962 963 writel(1, mtx->regs + DISP_REG_MUTEX_EN(mutex->id)); 964 } 965 EXPORT_SYMBOL_GPL(mtk_mutex_enable); 966 967 int mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex, void *pkt) 968 { 969 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 970 mutex[mutex->id]); 971 struct cmdq_pkt *cmdq_pkt = (struct cmdq_pkt *)pkt; 972 973 WARN_ON(&mtx->mutex[mutex->id] != mutex); 974 975 if (!mtx->cmdq_reg.size) { 976 dev_err(mtx->dev, "mediatek,gce-client-reg hasn't been set"); 977 return -ENODEV; 978 } 979 980 cmdq_pkt_write(cmdq_pkt, mtx->cmdq_reg.subsys, 981 mtx->addr + DISP_REG_MUTEX_EN(mutex->id), 1); 982 return 0; 983 } 984 EXPORT_SYMBOL_GPL(mtk_mutex_enable_by_cmdq); 985 986 void mtk_mutex_disable(struct mtk_mutex *mutex) 987 { 988 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 989 mutex[mutex->id]); 990 991 WARN_ON(&mtx->mutex[mutex->id] != mutex); 992 993 writel(0, mtx->regs + DISP_REG_MUTEX_EN(mutex->id)); 994 } 995 EXPORT_SYMBOL_GPL(mtk_mutex_disable); 996 997 void mtk_mutex_acquire(struct mtk_mutex *mutex) 998 { 999 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 1000 mutex[mutex->id]); 1001 u32 tmp; 1002 1003 writel(1, mtx->regs + DISP_REG_MUTEX_EN(mutex->id)); 1004 writel(1, mtx->regs + DISP_REG_MUTEX(mutex->id)); 1005 if (readl_poll_timeout_atomic(mtx->regs + DISP_REG_MUTEX(mutex->id), 1006 tmp, tmp & INT_MUTEX, 1, 10000)) 1007 pr_err("could not acquire mutex %d\n", mutex->id); 1008 } 1009 EXPORT_SYMBOL_GPL(mtk_mutex_acquire); 1010 1011 void mtk_mutex_release(struct mtk_mutex *mutex) 1012 { 1013 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 1014 mutex[mutex->id]); 1015 1016 writel(0, mtx->regs + DISP_REG_MUTEX(mutex->id)); 1017 } 1018 EXPORT_SYMBOL_GPL(mtk_mutex_release); 1019 1020 int mtk_mutex_write_mod(struct mtk_mutex *mutex, 1021 enum mtk_mutex_mod_index idx, bool clear) 1022 { 1023 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 1024 mutex[mutex->id]); 1025 unsigned int reg; 1026 u32 reg_offset, id_offset = 0; 1027 1028 WARN_ON(&mtx->mutex[mutex->id] != mutex); 1029 1030 if (idx < MUTEX_MOD_IDX_MDP_RDMA0 || 1031 idx >= MUTEX_MOD_IDX_MAX) { 1032 dev_err(mtx->dev, "Not supported MOD table index : %d", idx); 1033 return -EINVAL; 1034 } 1035 1036 /* 1037 * Some SoCs may have multiple MUTEX_MOD registers as more than 32 mods 1038 * are present, hence requiring multiple 32-bits registers. 1039 * 1040 * The mutex_table_mod fully represents that by defining the number of 1041 * the mod sequentially, later used as a bit number, which can be more 1042 * than 0..31. 1043 * 1044 * In order to retain compatibility with older SoCs, we perform R/W on 1045 * the single 32 bits registers, but this requires us to translate the 1046 * mutex ID bit accordingly. 1047 */ 1048 if (mtx->data->mutex_table_mod[idx] < 32) { 1049 reg_offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, 1050 mutex->id); 1051 } else { 1052 reg_offset = DISP_REG_MUTEX_MOD1(mtx->data->mutex_mod_reg, 1053 mutex->id); 1054 id_offset = 32; 1055 } 1056 1057 reg = readl_relaxed(mtx->regs + reg_offset); 1058 if (clear) 1059 reg &= ~BIT(mtx->data->mutex_table_mod[idx] - id_offset); 1060 else 1061 reg |= BIT(mtx->data->mutex_table_mod[idx] - id_offset); 1062 1063 writel_relaxed(reg, mtx->regs + reg_offset); 1064 1065 return 0; 1066 } 1067 EXPORT_SYMBOL_GPL(mtk_mutex_write_mod); 1068 1069 int mtk_mutex_write_sof(struct mtk_mutex *mutex, 1070 enum mtk_mutex_sof_index idx) 1071 { 1072 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 1073 mutex[mutex->id]); 1074 1075 WARN_ON(&mtx->mutex[mutex->id] != mutex); 1076 1077 if (idx < MUTEX_SOF_IDX_SINGLE_MODE || 1078 idx >= MUTEX_SOF_IDX_MAX) { 1079 dev_err(mtx->dev, "Not supported SOF index : %d", idx); 1080 return -EINVAL; 1081 } 1082 1083 writel_relaxed(idx, mtx->regs + 1084 DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id)); 1085 1086 return 0; 1087 } 1088 EXPORT_SYMBOL_GPL(mtk_mutex_write_sof); 1089 1090 static int mtk_mutex_probe(struct platform_device *pdev) 1091 { 1092 struct device *dev = &pdev->dev; 1093 struct mtk_mutex_ctx *mtx; 1094 struct resource *regs; 1095 int i, ret; 1096 1097 mtx = devm_kzalloc(dev, sizeof(*mtx), GFP_KERNEL); 1098 if (!mtx) 1099 return -ENOMEM; 1100 1101 for (i = 0; i < MTK_MUTEX_MAX_HANDLES; i++) 1102 mtx->mutex[i].id = i; 1103 1104 mtx->data = of_device_get_match_data(dev); 1105 1106 if (!mtx->data->no_clk) { 1107 mtx->clk = devm_clk_get(dev, NULL); 1108 if (IS_ERR(mtx->clk)) 1109 return dev_err_probe(dev, PTR_ERR(mtx->clk), "Failed to get clock\n"); 1110 } 1111 1112 mtx->regs = devm_platform_get_and_ioremap_resource(pdev, 0, ®s); 1113 if (IS_ERR(mtx->regs)) { 1114 dev_err(dev, "Failed to map mutex registers\n"); 1115 return PTR_ERR(mtx->regs); 1116 } 1117 mtx->addr = regs->start; 1118 1119 /* CMDQ is optional */ 1120 ret = cmdq_dev_get_client_reg(dev, &mtx->cmdq_reg, 0); 1121 if (ret) 1122 dev_dbg(dev, "No mediatek,gce-client-reg!\n"); 1123 1124 platform_set_drvdata(pdev, mtx); 1125 1126 return 0; 1127 } 1128 1129 static const struct of_device_id mutex_driver_dt_match[] = { 1130 { .compatible = "mediatek,mt2701-disp-mutex", .data = &mt2701_mutex_driver_data }, 1131 { .compatible = "mediatek,mt2712-disp-mutex", .data = &mt2712_mutex_driver_data }, 1132 { .compatible = "mediatek,mt6795-disp-mutex", .data = &mt6795_mutex_driver_data }, 1133 { .compatible = "mediatek,mt8167-disp-mutex", .data = &mt8167_mutex_driver_data }, 1134 { .compatible = "mediatek,mt8173-disp-mutex", .data = &mt8173_mutex_driver_data }, 1135 { .compatible = "mediatek,mt8183-disp-mutex", .data = &mt8183_mutex_driver_data }, 1136 { .compatible = "mediatek,mt8186-disp-mutex", .data = &mt8186_mutex_driver_data }, 1137 { .compatible = "mediatek,mt8186-mdp3-mutex", .data = &mt8186_mdp_mutex_driver_data }, 1138 { .compatible = "mediatek,mt8188-disp-mutex", .data = &mt8188_mutex_driver_data }, 1139 { .compatible = "mediatek,mt8188-vpp-mutex", .data = &mt8188_vpp_mutex_driver_data }, 1140 { .compatible = "mediatek,mt8192-disp-mutex", .data = &mt8192_mutex_driver_data }, 1141 { .compatible = "mediatek,mt8195-disp-mutex", .data = &mt8195_mutex_driver_data }, 1142 { .compatible = "mediatek,mt8195-vpp-mutex", .data = &mt8195_vpp_mutex_driver_data }, 1143 { .compatible = "mediatek,mt8365-disp-mutex", .data = &mt8365_mutex_driver_data }, 1144 { /* sentinel */ }, 1145 }; 1146 MODULE_DEVICE_TABLE(of, mutex_driver_dt_match); 1147 1148 static struct platform_driver mtk_mutex_driver = { 1149 .probe = mtk_mutex_probe, 1150 .driver = { 1151 .name = "mediatek-mutex", 1152 .of_match_table = mutex_driver_dt_match, 1153 }, 1154 }; 1155 module_platform_driver(mtk_mutex_driver); 1156 1157 MODULE_AUTHOR("Yongqiang Niu <yongqiang.niu@mediatek.com>"); 1158 MODULE_DESCRIPTION("MediaTek SoC MUTEX driver"); 1159 MODULE_LICENSE("GPL"); 1160