1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/iopoll.h> 8 #include <linux/module.h> 9 #include <linux/of_device.h> 10 #include <linux/platform_device.h> 11 #include <linux/regmap.h> 12 #include <linux/soc/mediatek/mtk-mmsys.h> 13 #include <linux/soc/mediatek/mtk-mutex.h> 14 15 #define MT2701_MUTEX0_MOD0 0x2c 16 #define MT2701_MUTEX0_SOF0 0x30 17 18 #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) 19 #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) 20 #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n)) 21 #define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) (mutex_mod_reg + 0x20 * (n)) 22 #define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) (mutex_sof_reg + 0x20 * (n)) 23 #define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n)) 24 25 #define INT_MUTEX BIT(1) 26 27 #define MT8167_MUTEX_MOD_DISP_PWM 1 28 #define MT8167_MUTEX_MOD_DISP_OVL0 6 29 #define MT8167_MUTEX_MOD_DISP_OVL1 7 30 #define MT8167_MUTEX_MOD_DISP_RDMA0 8 31 #define MT8167_MUTEX_MOD_DISP_RDMA1 9 32 #define MT8167_MUTEX_MOD_DISP_WDMA0 10 33 #define MT8167_MUTEX_MOD_DISP_CCORR 11 34 #define MT8167_MUTEX_MOD_DISP_COLOR 12 35 #define MT8167_MUTEX_MOD_DISP_AAL 13 36 #define MT8167_MUTEX_MOD_DISP_GAMMA 14 37 #define MT8167_MUTEX_MOD_DISP_DITHER 15 38 #define MT8167_MUTEX_MOD_DISP_UFOE 16 39 40 #define MT8173_MUTEX_MOD_DISP_OVL0 11 41 #define MT8173_MUTEX_MOD_DISP_OVL1 12 42 #define MT8173_MUTEX_MOD_DISP_RDMA0 13 43 #define MT8173_MUTEX_MOD_DISP_RDMA1 14 44 #define MT8173_MUTEX_MOD_DISP_RDMA2 15 45 #define MT8173_MUTEX_MOD_DISP_WDMA0 16 46 #define MT8173_MUTEX_MOD_DISP_WDMA1 17 47 #define MT8173_MUTEX_MOD_DISP_COLOR0 18 48 #define MT8173_MUTEX_MOD_DISP_COLOR1 19 49 #define MT8173_MUTEX_MOD_DISP_AAL 20 50 #define MT8173_MUTEX_MOD_DISP_GAMMA 21 51 #define MT8173_MUTEX_MOD_DISP_UFOE 22 52 #define MT8173_MUTEX_MOD_DISP_PWM0 23 53 #define MT8173_MUTEX_MOD_DISP_PWM1 24 54 #define MT8173_MUTEX_MOD_DISP_OD 25 55 56 #define MT2712_MUTEX_MOD_DISP_PWM2 10 57 #define MT2712_MUTEX_MOD_DISP_OVL0 11 58 #define MT2712_MUTEX_MOD_DISP_OVL1 12 59 #define MT2712_MUTEX_MOD_DISP_RDMA0 13 60 #define MT2712_MUTEX_MOD_DISP_RDMA1 14 61 #define MT2712_MUTEX_MOD_DISP_RDMA2 15 62 #define MT2712_MUTEX_MOD_DISP_WDMA0 16 63 #define MT2712_MUTEX_MOD_DISP_WDMA1 17 64 #define MT2712_MUTEX_MOD_DISP_COLOR0 18 65 #define MT2712_MUTEX_MOD_DISP_COLOR1 19 66 #define MT2712_MUTEX_MOD_DISP_AAL0 20 67 #define MT2712_MUTEX_MOD_DISP_UFOE 22 68 #define MT2712_MUTEX_MOD_DISP_PWM0 23 69 #define MT2712_MUTEX_MOD_DISP_PWM1 24 70 #define MT2712_MUTEX_MOD_DISP_OD0 25 71 #define MT2712_MUTEX_MOD2_DISP_AAL1 33 72 #define MT2712_MUTEX_MOD2_DISP_OD1 34 73 74 #define MT2701_MUTEX_MOD_DISP_OVL 3 75 #define MT2701_MUTEX_MOD_DISP_WDMA 6 76 #define MT2701_MUTEX_MOD_DISP_COLOR 7 77 #define MT2701_MUTEX_MOD_DISP_BLS 9 78 #define MT2701_MUTEX_MOD_DISP_RDMA0 10 79 #define MT2701_MUTEX_MOD_DISP_RDMA1 12 80 81 #define MT2712_MUTEX_SOF_SINGLE_MODE 0 82 #define MT2712_MUTEX_SOF_DSI0 1 83 #define MT2712_MUTEX_SOF_DSI1 2 84 #define MT2712_MUTEX_SOF_DPI0 3 85 #define MT2712_MUTEX_SOF_DPI1 4 86 #define MT2712_MUTEX_SOF_DSI2 5 87 #define MT2712_MUTEX_SOF_DSI3 6 88 #define MT8167_MUTEX_SOF_DPI0 2 89 #define MT8167_MUTEX_SOF_DPI1 3 90 91 struct mtk_mutex { 92 int id; 93 bool claimed; 94 }; 95 96 enum mtk_mutex_sof_id { 97 MUTEX_SOF_SINGLE_MODE, 98 MUTEX_SOF_DSI0, 99 MUTEX_SOF_DSI1, 100 MUTEX_SOF_DPI0, 101 MUTEX_SOF_DPI1, 102 MUTEX_SOF_DSI2, 103 MUTEX_SOF_DSI3, 104 }; 105 106 struct mtk_mutex_data { 107 const unsigned int *mutex_mod; 108 const unsigned int *mutex_sof; 109 const unsigned int mutex_mod_reg; 110 const unsigned int mutex_sof_reg; 111 const bool no_clk; 112 }; 113 114 struct mtk_mutex_ctx { 115 struct device *dev; 116 struct clk *clk; 117 void __iomem *regs; 118 struct mtk_mutex mutex[10]; 119 const struct mtk_mutex_data *data; 120 }; 121 122 static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { 123 [DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS, 124 [DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR, 125 [DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL, 126 [DDP_COMPONENT_RDMA0] = MT2701_MUTEX_MOD_DISP_RDMA0, 127 [DDP_COMPONENT_RDMA1] = MT2701_MUTEX_MOD_DISP_RDMA1, 128 [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA, 129 }; 130 131 static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { 132 [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0, 133 [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1, 134 [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0, 135 [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1, 136 [DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0, 137 [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1, 138 [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0, 139 [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1, 140 [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0, 141 [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1, 142 [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2, 143 [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0, 144 [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1, 145 [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2, 146 [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE, 147 [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0, 148 [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1, 149 }; 150 151 static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = { 152 [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL, 153 [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR, 154 [DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR, 155 [DDP_COMPONENT_DITHER] = MT8167_MUTEX_MOD_DISP_DITHER, 156 [DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA, 157 [DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0, 158 [DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1, 159 [DDP_COMPONENT_PWM0] = MT8167_MUTEX_MOD_DISP_PWM, 160 [DDP_COMPONENT_RDMA0] = MT8167_MUTEX_MOD_DISP_RDMA0, 161 [DDP_COMPONENT_RDMA1] = MT8167_MUTEX_MOD_DISP_RDMA1, 162 [DDP_COMPONENT_UFOE] = MT8167_MUTEX_MOD_DISP_UFOE, 163 [DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0, 164 }; 165 166 static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { 167 [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL, 168 [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0, 169 [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1, 170 [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA, 171 [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD, 172 [DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0, 173 [DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1, 174 [DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0, 175 [DDP_COMPONENT_PWM1] = MT8173_MUTEX_MOD_DISP_PWM1, 176 [DDP_COMPONENT_RDMA0] = MT8173_MUTEX_MOD_DISP_RDMA0, 177 [DDP_COMPONENT_RDMA1] = MT8173_MUTEX_MOD_DISP_RDMA1, 178 [DDP_COMPONENT_RDMA2] = MT8173_MUTEX_MOD_DISP_RDMA2, 179 [DDP_COMPONENT_UFOE] = MT8173_MUTEX_MOD_DISP_UFOE, 180 [DDP_COMPONENT_WDMA0] = MT8173_MUTEX_MOD_DISP_WDMA0, 181 [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, 182 }; 183 184 static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { 185 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, 186 [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, 187 [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1, 188 [MUTEX_SOF_DPI0] = MUTEX_SOF_DPI0, 189 [MUTEX_SOF_DPI1] = MUTEX_SOF_DPI1, 190 [MUTEX_SOF_DSI2] = MUTEX_SOF_DSI2, 191 [MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, 192 }; 193 194 static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = { 195 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, 196 [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, 197 [MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0, 198 [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1, 199 }; 200 201 static const struct mtk_mutex_data mt2701_mutex_driver_data = { 202 .mutex_mod = mt2701_mutex_mod, 203 .mutex_sof = mt2712_mutex_sof, 204 .mutex_mod_reg = MT2701_MUTEX0_MOD0, 205 .mutex_sof_reg = MT2701_MUTEX0_SOF0, 206 }; 207 208 static const struct mtk_mutex_data mt2712_mutex_driver_data = { 209 .mutex_mod = mt2712_mutex_mod, 210 .mutex_sof = mt2712_mutex_sof, 211 .mutex_mod_reg = MT2701_MUTEX0_MOD0, 212 .mutex_sof_reg = MT2701_MUTEX0_SOF0, 213 }; 214 215 static const struct mtk_mutex_data mt8167_mutex_driver_data = { 216 .mutex_mod = mt8167_mutex_mod, 217 .mutex_sof = mt8167_mutex_sof, 218 .mutex_mod_reg = MT2701_MUTEX0_MOD0, 219 .mutex_sof_reg = MT2701_MUTEX0_SOF0, 220 .no_clk = true, 221 }; 222 223 static const struct mtk_mutex_data mt8173_mutex_driver_data = { 224 .mutex_mod = mt8173_mutex_mod, 225 .mutex_sof = mt2712_mutex_sof, 226 .mutex_mod_reg = MT2701_MUTEX0_MOD0, 227 .mutex_sof_reg = MT2701_MUTEX0_SOF0, 228 }; 229 230 struct mtk_mutex *mtk_mutex_get(struct device *dev) 231 { 232 struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); 233 int i; 234 235 for (i = 0; i < 10; i++) 236 if (!mtx->mutex[i].claimed) { 237 mtx->mutex[i].claimed = true; 238 return &mtx->mutex[i]; 239 } 240 241 return ERR_PTR(-EBUSY); 242 } 243 EXPORT_SYMBOL_GPL(mtk_mutex_get); 244 245 void mtk_mutex_put(struct mtk_mutex *mutex) 246 { 247 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 248 mutex[mutex->id]); 249 250 WARN_ON(&mtx->mutex[mutex->id] != mutex); 251 252 mutex->claimed = false; 253 } 254 EXPORT_SYMBOL_GPL(mtk_mutex_put); 255 256 int mtk_mutex_prepare(struct mtk_mutex *mutex) 257 { 258 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 259 mutex[mutex->id]); 260 return clk_prepare_enable(mtx->clk); 261 } 262 EXPORT_SYMBOL_GPL(mtk_mutex_prepare); 263 264 void mtk_mutex_unprepare(struct mtk_mutex *mutex) 265 { 266 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 267 mutex[mutex->id]); 268 clk_disable_unprepare(mtx->clk); 269 } 270 EXPORT_SYMBOL_GPL(mtk_mutex_unprepare); 271 272 void mtk_mutex_add_comp(struct mtk_mutex *mutex, 273 enum mtk_ddp_comp_id id) 274 { 275 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 276 mutex[mutex->id]); 277 unsigned int reg; 278 unsigned int sof_id; 279 unsigned int offset; 280 281 WARN_ON(&mtx->mutex[mutex->id] != mutex); 282 283 switch (id) { 284 case DDP_COMPONENT_DSI0: 285 sof_id = MUTEX_SOF_DSI0; 286 break; 287 case DDP_COMPONENT_DSI1: 288 sof_id = MUTEX_SOF_DSI0; 289 break; 290 case DDP_COMPONENT_DSI2: 291 sof_id = MUTEX_SOF_DSI2; 292 break; 293 case DDP_COMPONENT_DSI3: 294 sof_id = MUTEX_SOF_DSI3; 295 break; 296 case DDP_COMPONENT_DPI0: 297 sof_id = MUTEX_SOF_DPI0; 298 break; 299 case DDP_COMPONENT_DPI1: 300 sof_id = MUTEX_SOF_DPI1; 301 break; 302 default: 303 if (mtx->data->mutex_mod[id] < 32) { 304 offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, 305 mutex->id); 306 reg = readl_relaxed(mtx->regs + offset); 307 reg |= 1 << mtx->data->mutex_mod[id]; 308 writel_relaxed(reg, mtx->regs + offset); 309 } else { 310 offset = DISP_REG_MUTEX_MOD2(mutex->id); 311 reg = readl_relaxed(mtx->regs + offset); 312 reg |= 1 << (mtx->data->mutex_mod[id] - 32); 313 writel_relaxed(reg, mtx->regs + offset); 314 } 315 return; 316 } 317 318 writel_relaxed(mtx->data->mutex_sof[sof_id], 319 mtx->regs + 320 DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id)); 321 } 322 EXPORT_SYMBOL_GPL(mtk_mutex_add_comp); 323 324 void mtk_mutex_remove_comp(struct mtk_mutex *mutex, 325 enum mtk_ddp_comp_id id) 326 { 327 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 328 mutex[mutex->id]); 329 unsigned int reg; 330 unsigned int offset; 331 332 WARN_ON(&mtx->mutex[mutex->id] != mutex); 333 334 switch (id) { 335 case DDP_COMPONENT_DSI0: 336 case DDP_COMPONENT_DSI1: 337 case DDP_COMPONENT_DSI2: 338 case DDP_COMPONENT_DSI3: 339 case DDP_COMPONENT_DPI0: 340 case DDP_COMPONENT_DPI1: 341 writel_relaxed(MUTEX_SOF_SINGLE_MODE, 342 mtx->regs + 343 DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, 344 mutex->id)); 345 break; 346 default: 347 if (mtx->data->mutex_mod[id] < 32) { 348 offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, 349 mutex->id); 350 reg = readl_relaxed(mtx->regs + offset); 351 reg &= ~(1 << mtx->data->mutex_mod[id]); 352 writel_relaxed(reg, mtx->regs + offset); 353 } else { 354 offset = DISP_REG_MUTEX_MOD2(mutex->id); 355 reg = readl_relaxed(mtx->regs + offset); 356 reg &= ~(1 << (mtx->data->mutex_mod[id] - 32)); 357 writel_relaxed(reg, mtx->regs + offset); 358 } 359 break; 360 } 361 } 362 EXPORT_SYMBOL_GPL(mtk_mutex_remove_comp); 363 364 void mtk_mutex_enable(struct mtk_mutex *mutex) 365 { 366 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 367 mutex[mutex->id]); 368 369 WARN_ON(&mtx->mutex[mutex->id] != mutex); 370 371 writel(1, mtx->regs + DISP_REG_MUTEX_EN(mutex->id)); 372 } 373 EXPORT_SYMBOL_GPL(mtk_mutex_enable); 374 375 void mtk_mutex_disable(struct mtk_mutex *mutex) 376 { 377 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 378 mutex[mutex->id]); 379 380 WARN_ON(&mtx->mutex[mutex->id] != mutex); 381 382 writel(0, mtx->regs + DISP_REG_MUTEX_EN(mutex->id)); 383 } 384 EXPORT_SYMBOL_GPL(mtk_mutex_disable); 385 386 void mtk_mutex_acquire(struct mtk_mutex *mutex) 387 { 388 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 389 mutex[mutex->id]); 390 u32 tmp; 391 392 writel(1, mtx->regs + DISP_REG_MUTEX_EN(mutex->id)); 393 writel(1, mtx->regs + DISP_REG_MUTEX(mutex->id)); 394 if (readl_poll_timeout_atomic(mtx->regs + DISP_REG_MUTEX(mutex->id), 395 tmp, tmp & INT_MUTEX, 1, 10000)) 396 pr_err("could not acquire mutex %d\n", mutex->id); 397 } 398 EXPORT_SYMBOL_GPL(mtk_mutex_acquire); 399 400 void mtk_mutex_release(struct mtk_mutex *mutex) 401 { 402 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 403 mutex[mutex->id]); 404 405 writel(0, mtx->regs + DISP_REG_MUTEX(mutex->id)); 406 } 407 EXPORT_SYMBOL_GPL(mtk_mutex_release); 408 409 static int mtk_mutex_probe(struct platform_device *pdev) 410 { 411 struct device *dev = &pdev->dev; 412 struct mtk_mutex_ctx *mtx; 413 struct resource *regs; 414 int i; 415 416 mtx = devm_kzalloc(dev, sizeof(*mtx), GFP_KERNEL); 417 if (!mtx) 418 return -ENOMEM; 419 420 for (i = 0; i < 10; i++) 421 mtx->mutex[i].id = i; 422 423 mtx->data = of_device_get_match_data(dev); 424 425 if (!mtx->data->no_clk) { 426 mtx->clk = devm_clk_get(dev, NULL); 427 if (IS_ERR(mtx->clk)) { 428 if (PTR_ERR(mtx->clk) != -EPROBE_DEFER) 429 dev_err(dev, "Failed to get clock\n"); 430 return PTR_ERR(mtx->clk); 431 } 432 } 433 434 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 435 mtx->regs = devm_ioremap_resource(dev, regs); 436 if (IS_ERR(mtx->regs)) { 437 dev_err(dev, "Failed to map mutex registers\n"); 438 return PTR_ERR(mtx->regs); 439 } 440 441 platform_set_drvdata(pdev, mtx); 442 443 return 0; 444 } 445 446 static int mtk_mutex_remove(struct platform_device *pdev) 447 { 448 return 0; 449 } 450 451 static const struct of_device_id mutex_driver_dt_match[] = { 452 { .compatible = "mediatek,mt2701-disp-mutex", 453 .data = &mt2701_mutex_driver_data}, 454 { .compatible = "mediatek,mt2712-disp-mutex", 455 .data = &mt2712_mutex_driver_data}, 456 { .compatible = "mediatek,mt8167-disp-mutex", 457 .data = &mt8167_mutex_driver_data}, 458 { .compatible = "mediatek,mt8173-disp-mutex", 459 .data = &mt8173_mutex_driver_data}, 460 {}, 461 }; 462 MODULE_DEVICE_TABLE(of, mutex_driver_dt_match); 463 464 struct platform_driver mtk_mutex_driver = { 465 .probe = mtk_mutex_probe, 466 .remove = mtk_mutex_remove, 467 .driver = { 468 .name = "mediatek-mutex", 469 .owner = THIS_MODULE, 470 .of_match_table = mutex_driver_dt_match, 471 }, 472 }; 473 474 builtin_platform_driver(mtk_mutex_driver); 475