1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_MEDIATEK_MTK_MMSYS_H 4 #define __SOC_MEDIATEK_MTK_MMSYS_H 5 6 #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 7 #define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 8 #define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 9 #define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c 10 #define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 11 #define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 12 #define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 13 #define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 14 #define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 15 #define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac 16 #define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 17 #define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 18 #define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 19 #define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 20 21 #define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 22 #define DISP_REG_CONFIG_OUT_SEL 0x04c 23 #define DISP_REG_CONFIG_DSI_SEL 0x050 24 #define DISP_REG_CONFIG_DPI_SEL 0x064 25 26 #define OVL0_MOUT_EN_COLOR0 0x1 27 #define OD_MOUT_EN_RDMA0 0x1 28 #define OD1_MOUT_EN_RDMA1 BIT(16) 29 #define UFOE_MOUT_EN_DSI0 0x1 30 #define COLOR0_SEL_IN_OVL0 0x1 31 #define OVL1_MOUT_EN_COLOR1 0x1 32 #define GAMMA_MOUT_EN_RDMA1 0x1 33 #define RDMA0_SOUT_DPI0 0x2 34 #define RDMA0_SOUT_DPI1 0x3 35 #define RDMA0_SOUT_DSI1 0x1 36 #define RDMA0_SOUT_DSI2 0x4 37 #define RDMA0_SOUT_DSI3 0x5 38 #define RDMA0_SOUT_MASK 0x7 39 #define RDMA1_SOUT_DPI0 0x2 40 #define RDMA1_SOUT_DPI1 0x3 41 #define RDMA1_SOUT_DSI1 0x1 42 #define RDMA1_SOUT_DSI2 0x4 43 #define RDMA1_SOUT_DSI3 0x5 44 #define RDMA1_SOUT_MASK 0x7 45 #define RDMA2_SOUT_DPI0 0x2 46 #define RDMA2_SOUT_DPI1 0x3 47 #define RDMA2_SOUT_DSI1 0x1 48 #define RDMA2_SOUT_DSI2 0x4 49 #define RDMA2_SOUT_DSI3 0x5 50 #define RDMA2_SOUT_MASK 0x7 51 #define DPI0_SEL_IN_RDMA1 0x1 52 #define DPI0_SEL_IN_RDMA2 0x3 53 #define DPI0_SEL_IN_MASK 0x3 54 #define DPI1_SEL_IN_RDMA1 (0x1 << 8) 55 #define DPI1_SEL_IN_RDMA2 (0x3 << 8) 56 #define DPI1_SEL_IN_MASK (0x3 << 8) 57 #define DSI0_SEL_IN_RDMA1 0x1 58 #define DSI0_SEL_IN_RDMA2 0x4 59 #define DSI0_SEL_IN_MASK 0x7 60 #define DSI1_SEL_IN_RDMA1 0x1 61 #define DSI1_SEL_IN_RDMA2 0x4 62 #define DSI1_SEL_IN_MASK 0x7 63 #define DSI2_SEL_IN_RDMA1 (0x1 << 16) 64 #define DSI2_SEL_IN_RDMA2 (0x4 << 16) 65 #define DSI2_SEL_IN_MASK (0x7 << 16) 66 #define DSI3_SEL_IN_RDMA1 (0x1 << 16) 67 #define DSI3_SEL_IN_RDMA2 (0x4 << 16) 68 #define DSI3_SEL_IN_MASK (0x7 << 16) 69 #define COLOR1_SEL_IN_OVL1 0x1 70 71 #define OVL_MOUT_EN_RDMA 0x1 72 #define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 73 #define BLS_TO_DPI_RDMA1_TO_DSI 0x2 74 #define BLS_RDMA1_DSI_DPI_MASK 0xf 75 #define DSI_SEL_IN_BLS 0x0 76 #define DPI_SEL_IN_BLS 0x0 77 #define DPI_SEL_IN_MASK 0x1 78 #define DSI_SEL_IN_RDMA 0x1 79 #define DSI_SEL_IN_MASK 0x1 80 81 #define MMSYS_RST_NR(bank, bit) (((bank) * 32) + (bit)) 82 83 struct mtk_mmsys_routes { 84 u32 from_comp; 85 u32 to_comp; 86 u32 addr; 87 u32 mask; 88 u32 val; 89 }; 90 91 /** 92 * struct mtk_mmsys_driver_data - Settings of the mmsys 93 * @clk_driver: Clock driver name that the mmsys is using 94 * (defined in drivers/clk/mediatek/clk-*.c). 95 * @routes: Routing table of the mmsys. 96 * It provides mux settings from one module to another. 97 * @num_routes: Array size of the routes. 98 * @sw0_rst_offset: Register offset for the reset control. 99 * @num_resets: Number of reset bits that are defined 100 * @is_vppsys: Whether the mmsys is VPPSYS (Video Processing Pipe) 101 * or VDOSYS (Video). Only VDOSYS needs to be added to drm driver. 102 * @vsync_len: VSYNC length of the MIXER. 103 * VSYNC is usually triggered by the connector, so its length is a 104 * fixed value when the frame rate is decided, but ETHDR and 105 * MIXER generate their own VSYNC due to hardware design, therefore 106 * MIXER has to sync with ETHDR by adjusting VSYNC length. 107 * On MT8195, there is no such setting so we use the gap between 108 * falling edge and rising edge of SOF (Start of Frame) signal to 109 * do the job, but since MT8188, VSYNC_LEN setting is introduced to 110 * solve the problem and is given 0x40 (ticks) as the default value. 111 * Please notice that this value has to be set to 1 (minimum) if 112 * ETHDR is bypassed, otherwise MIXER could wait too long and causing 113 * underflow. 114 * 115 * Each MMSYS (multi-media system) may have different settings, they may use 116 * different clock sources, mux settings, reset control ...etc., and these 117 * differences are all stored here. 118 */ 119 struct mtk_mmsys_driver_data { 120 const char *clk_driver; 121 const struct mtk_mmsys_routes *routes; 122 const unsigned int num_routes; 123 const u16 sw0_rst_offset; 124 const u8 *rst_tb; 125 const u32 num_resets; 126 const bool is_vppsys; 127 const u8 vsync_len; 128 }; 129 130 /* 131 * Routes in mt2701 and mt2712 are different. That means 132 * in the same register address, it controls different input/output 133 * selection for each SoC. But, right now, they use the same table as 134 * default routes meet their requirements. But we don't have the complete 135 * route information for these three SoC, so just keep them in the same 136 * table. After we've more information, we could separate mt2701, mt2712 137 * to an independent table. 138 */ 139 static const struct mtk_mmsys_routes mmsys_default_routing_table[] = { 140 { 141 DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0, 142 DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK, 143 BLS_TO_DSI_RDMA1_TO_DPI1 144 }, { 145 DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0, 146 DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK, 147 DSI_SEL_IN_BLS 148 }, { 149 DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0, 150 DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK, 151 BLS_TO_DPI_RDMA1_TO_DSI 152 }, { 153 DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0, 154 DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK, 155 DSI_SEL_IN_RDMA 156 }, { 157 DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0, 158 DISP_REG_CONFIG_DPI_SEL, DPI_SEL_IN_MASK, 159 DPI_SEL_IN_BLS 160 }, { 161 DDP_COMPONENT_GAMMA, DDP_COMPONENT_RDMA1, 162 DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, GAMMA_MOUT_EN_RDMA1, 163 GAMMA_MOUT_EN_RDMA1 164 }, { 165 DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0, 166 DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD_MOUT_EN_RDMA0, 167 OD_MOUT_EN_RDMA0 168 }, { 169 DDP_COMPONENT_OD1, DDP_COMPONENT_RDMA1, 170 DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD1_MOUT_EN_RDMA1, 171 OD1_MOUT_EN_RDMA1 172 }, { 173 DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, 174 DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0, 175 OVL0_MOUT_EN_COLOR0 176 }, { 177 DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, 178 DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0, 179 COLOR0_SEL_IN_OVL0 180 }, { 181 DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, 182 DISP_REG_CONFIG_DISP_OVL_MOUT_EN, OVL_MOUT_EN_RDMA, 183 OVL_MOUT_EN_RDMA 184 }, { 185 DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1, 186 DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, OVL1_MOUT_EN_COLOR1, 187 OVL1_MOUT_EN_COLOR1 188 }, { 189 DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1, 190 DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1, 191 COLOR1_SEL_IN_OVL1 192 }, { 193 DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI0, 194 DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK, 195 RDMA0_SOUT_DPI0 196 }, { 197 DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI1, 198 DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK, 199 RDMA0_SOUT_DPI1 200 }, { 201 DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI1, 202 DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK, 203 RDMA0_SOUT_DSI1 204 }, { 205 DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI2, 206 DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK, 207 RDMA0_SOUT_DSI2 208 }, { 209 DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI3, 210 DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK, 211 RDMA0_SOUT_DSI3 212 }, { 213 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, 214 DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK, 215 RDMA1_SOUT_DPI0 216 }, { 217 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, 218 DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK, 219 DPI0_SEL_IN_RDMA1 220 }, { 221 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1, 222 DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK, 223 RDMA1_SOUT_DPI1 224 }, { 225 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1, 226 DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK, 227 DPI1_SEL_IN_RDMA1 228 }, { 229 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI0, 230 DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK, 231 DSI0_SEL_IN_RDMA1 232 }, { 233 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1, 234 DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK, 235 RDMA1_SOUT_DSI1 236 }, { 237 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1, 238 DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK, 239 DSI1_SEL_IN_RDMA1 240 }, { 241 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2, 242 DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK, 243 RDMA1_SOUT_DSI2 244 }, { 245 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2, 246 DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK, 247 DSI2_SEL_IN_RDMA1 248 }, { 249 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3, 250 DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK, 251 RDMA1_SOUT_DSI3 252 }, { 253 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3, 254 DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK, 255 DSI3_SEL_IN_RDMA1 256 }, { 257 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0, 258 DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK, 259 RDMA2_SOUT_DPI0 260 }, { 261 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0, 262 DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK, 263 DPI0_SEL_IN_RDMA2 264 }, { 265 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1, 266 DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK, 267 RDMA2_SOUT_DPI1 268 }, { 269 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1, 270 DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK, 271 DPI1_SEL_IN_RDMA2 272 }, { 273 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI0, 274 DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK, 275 DSI0_SEL_IN_RDMA2 276 }, { 277 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1, 278 DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK, 279 RDMA2_SOUT_DSI1 280 }, { 281 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1, 282 DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK, 283 DSI1_SEL_IN_RDMA2 284 }, { 285 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2, 286 DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK, 287 RDMA2_SOUT_DSI2 288 }, { 289 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2, 290 DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK, 291 DSI2_SEL_IN_RDMA2 292 }, { 293 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3, 294 DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK, 295 RDMA2_SOUT_DSI3 296 }, { 297 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3, 298 DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK, 299 DSI3_SEL_IN_RDMA2 300 }, { 301 DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0, 302 DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, UFOE_MOUT_EN_DSI0, 303 UFOE_MOUT_EN_DSI0 304 } 305 }; 306 307 #endif /* __SOC_MEDIATEK_MTK_MMSYS_H */ 308