1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: James Liao <jamesjj.liao@mediatek.com> 5 */ 6 7 #include <linux/delay.h> 8 #include <linux/device.h> 9 #include <linux/io.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 #include <linux/reset-controller.h> 14 #include <linux/soc/mediatek/mtk-mmsys.h> 15 16 #include "mtk-mmsys.h" 17 #include "mt8167-mmsys.h" 18 #include "mt8173-mmsys.h" 19 #include "mt8183-mmsys.h" 20 #include "mt8186-mmsys.h" 21 #include "mt8188-mmsys.h" 22 #include "mt8192-mmsys.h" 23 #include "mt8195-mmsys.h" 24 #include "mt8365-mmsys.h" 25 26 #define MMSYS_SW_RESET_PER_REG 32 27 28 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { 29 .clk_driver = "clk-mt2701-mm", 30 .routes = mmsys_default_routing_table, 31 .num_routes = ARRAY_SIZE(mmsys_default_routing_table), 32 }; 33 34 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { 35 .clk_driver = "clk-mt2712-mm", 36 .routes = mmsys_default_routing_table, 37 .num_routes = ARRAY_SIZE(mmsys_default_routing_table), 38 }; 39 40 static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { 41 .clk_driver = "clk-mt6779-mm", 42 }; 43 44 static const struct mtk_mmsys_driver_data mt6795_mmsys_driver_data = { 45 .clk_driver = "clk-mt6795-mm", 46 .routes = mt8173_mmsys_routing_table, 47 .num_routes = ARRAY_SIZE(mt8173_mmsys_routing_table), 48 .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, 49 .num_resets = 64, 50 }; 51 52 static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { 53 .clk_driver = "clk-mt6797-mm", 54 }; 55 56 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { 57 .clk_driver = "clk-mt8167-mm", 58 .routes = mt8167_mmsys_routing_table, 59 .num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table), 60 }; 61 62 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { 63 .clk_driver = "clk-mt8173-mm", 64 .routes = mt8173_mmsys_routing_table, 65 .num_routes = ARRAY_SIZE(mt8173_mmsys_routing_table), 66 .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, 67 .num_resets = 64, 68 }; 69 70 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { 71 .clk_driver = "clk-mt8183-mm", 72 .routes = mmsys_mt8183_routing_table, 73 .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table), 74 .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, 75 .num_resets = 32, 76 }; 77 78 static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { 79 .clk_driver = "clk-mt8186-mm", 80 .routes = mmsys_mt8186_routing_table, 81 .num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table), 82 .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, 83 .num_resets = 32, 84 }; 85 86 static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = { 87 .clk_driver = "clk-mt8188-vdo0", 88 .routes = mmsys_mt8188_routing_table, 89 .num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table), 90 .sw0_rst_offset = MT8188_VDO0_SW0_RST_B, 91 .rst_tb = mmsys_mt8188_vdo0_rst_tb, 92 .num_resets = ARRAY_SIZE(mmsys_mt8188_vdo0_rst_tb), 93 }; 94 95 static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data = { 96 .clk_driver = "clk-mt8188-vdo1", 97 .routes = mmsys_mt8188_vdo1_routing_table, 98 .num_routes = ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table), 99 .sw0_rst_offset = MT8188_VDO1_SW0_RST_B, 100 .rst_tb = mmsys_mt8188_vdo1_rst_tb, 101 .num_resets = ARRAY_SIZE(mmsys_mt8188_vdo1_rst_tb), 102 .vsync_len = 1, 103 }; 104 105 static const struct mtk_mmsys_driver_data mt8188_vppsys0_driver_data = { 106 .clk_driver = "clk-mt8188-vpp0", 107 .is_vppsys = true, 108 }; 109 110 static const struct mtk_mmsys_driver_data mt8188_vppsys1_driver_data = { 111 .clk_driver = "clk-mt8188-vpp1", 112 .is_vppsys = true, 113 }; 114 115 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { 116 .clk_driver = "clk-mt8192-mm", 117 .routes = mmsys_mt8192_routing_table, 118 .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table), 119 .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, 120 .num_resets = 32, 121 }; 122 123 static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { 124 .clk_driver = "clk-mt8195-vdo0", 125 .routes = mmsys_mt8195_routing_table, 126 .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table), 127 }; 128 129 static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { 130 .clk_driver = "clk-mt8195-vdo1", 131 .routes = mmsys_mt8195_vdo1_routing_table, 132 .num_routes = ARRAY_SIZE(mmsys_mt8195_vdo1_routing_table), 133 .sw0_rst_offset = MT8195_VDO1_SW0_RST_B, 134 .num_resets = 64, 135 }; 136 137 static const struct mtk_mmsys_driver_data mt8195_vppsys0_driver_data = { 138 .clk_driver = "clk-mt8195-vpp0", 139 .is_vppsys = true, 140 }; 141 142 static const struct mtk_mmsys_driver_data mt8195_vppsys1_driver_data = { 143 .clk_driver = "clk-mt8195-vpp1", 144 .is_vppsys = true, 145 }; 146 147 static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { 148 .clk_driver = "clk-mt8365-mm", 149 .routes = mt8365_mmsys_routing_table, 150 .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table), 151 }; 152 153 struct mtk_mmsys { 154 void __iomem *regs; 155 const struct mtk_mmsys_driver_data *data; 156 struct platform_device *clks_pdev; 157 struct platform_device *drm_pdev; 158 spinlock_t lock; /* protects mmsys_sw_rst_b reg */ 159 struct reset_controller_dev rcdev; 160 struct cmdq_client_reg cmdq_base; 161 }; 162 163 static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val, 164 struct cmdq_pkt *cmdq_pkt) 165 { 166 int ret; 167 u32 tmp; 168 169 if (mmsys->cmdq_base.size && cmdq_pkt) { 170 ret = mmsys->cmdq_base.pkt_write_mask(cmdq_pkt, 171 mmsys->cmdq_base.subsys, 172 mmsys->cmdq_base.pa_base, 173 mmsys->cmdq_base.offset + offset, 174 val, mask); 175 if (ret) 176 pr_debug("CMDQ unavailable: using CPU write\n"); 177 else 178 return; 179 } 180 tmp = readl_relaxed(mmsys->regs + offset); 181 tmp = (tmp & ~mask) | (val & mask); 182 writel_relaxed(tmp, mmsys->regs + offset); 183 } 184 185 void mtk_mmsys_ddp_connect(struct device *dev, 186 enum mtk_ddp_comp_id cur, 187 enum mtk_ddp_comp_id next) 188 { 189 struct mtk_mmsys *mmsys = dev_get_drvdata(dev); 190 const struct mtk_mmsys_routes *routes = mmsys->data->routes; 191 int i; 192 193 for (i = 0; i < mmsys->data->num_routes; i++) 194 if (cur == routes[i].from_comp && next == routes[i].to_comp) 195 mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask, 196 routes[i].val, NULL); 197 198 if (mmsys->data->vsync_len) 199 mtk_mmsys_update_bits(mmsys, MT8188_VDO1_MIXER_VSYNC_LEN, GENMASK(31, 0), 200 mmsys->data->vsync_len, NULL); 201 } 202 EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); 203 204 void mtk_mmsys_ddp_disconnect(struct device *dev, 205 enum mtk_ddp_comp_id cur, 206 enum mtk_ddp_comp_id next) 207 { 208 struct mtk_mmsys *mmsys = dev_get_drvdata(dev); 209 const struct mtk_mmsys_routes *routes = mmsys->data->routes; 210 int i; 211 212 for (i = 0; i < mmsys->data->num_routes; i++) 213 if (cur == routes[i].from_comp && next == routes[i].to_comp) 214 mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask, 0, NULL); 215 } 216 EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); 217 218 void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width, int height, 219 struct cmdq_pkt *cmdq_pkt) 220 { 221 mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_MERGE0_ASYNC_CFG_WD + 0x10 * idx, 222 ~0, height << 16 | width, cmdq_pkt); 223 } 224 EXPORT_SYMBOL_GPL(mtk_mmsys_merge_async_config); 225 226 void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height, 227 struct cmdq_pkt *cmdq_pkt) 228 { 229 mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_HDRBE_ASYNC_CFG_WD, ~0, 230 be_height << 16 | be_width, cmdq_pkt); 231 } 232 EXPORT_SYMBOL_GPL(mtk_mmsys_hdr_config); 233 234 void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 alpha, 235 u8 mode, u32 biwidth, struct cmdq_pkt *cmdq_pkt) 236 { 237 struct mtk_mmsys *mmsys = dev_get_drvdata(dev); 238 239 mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_ALPHA + (idx - 1) * 4, ~0, 240 alpha << 16 | alpha, cmdq_pkt); 241 mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(15 + idx), 0, cmdq_pkt); 242 mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(19 + idx), 243 alpha_sel << (19 + idx), cmdq_pkt); 244 mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4, 245 GENMASK(31, 16) | GENMASK(1, 0), biwidth << 16 | mode, cmdq_pkt); 246 } 247 EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_config); 248 249 void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap, 250 struct cmdq_pkt *cmdq_pkt) 251 { 252 mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4, 253 BIT(4), channel_swap << 4, cmdq_pkt); 254 } 255 EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_channel_swap); 256 257 void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val) 258 { 259 struct mtk_mmsys *mmsys = dev_get_drvdata(dev); 260 261 switch (val) { 262 case MTK_DPI_RGB888_SDR_CON: 263 mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT, 264 MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB888_SDR_CON, NULL); 265 break; 266 case MTK_DPI_RGB565_SDR_CON: 267 mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT, 268 MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB565_SDR_CON, NULL); 269 break; 270 case MTK_DPI_RGB565_DDR_CON: 271 mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT, 272 MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB565_DDR_CON, NULL); 273 break; 274 case MTK_DPI_RGB888_DDR_CON: 275 default: 276 mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT, 277 MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB888_DDR_CON, NULL); 278 break; 279 } 280 } 281 EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_dpi_fmt_config); 282 283 void mtk_mmsys_vpp_rsz_merge_config(struct device *dev, u32 id, bool enable, 284 struct cmdq_pkt *cmdq_pkt) 285 { 286 u32 reg; 287 288 switch (id) { 289 case 2: 290 reg = MT8195_SVPP2_BUF_BF_RSZ_SWITCH; 291 break; 292 case 3: 293 reg = MT8195_SVPP3_BUF_BF_RSZ_SWITCH; 294 break; 295 default: 296 dev_err(dev, "Invalid id %d\n", id); 297 return; 298 } 299 300 mtk_mmsys_update_bits(dev_get_drvdata(dev), reg, ~0, enable, cmdq_pkt); 301 } 302 EXPORT_SYMBOL_GPL(mtk_mmsys_vpp_rsz_merge_config); 303 304 void mtk_mmsys_vpp_rsz_dcm_config(struct device *dev, bool enable, 305 struct cmdq_pkt *cmdq_pkt) 306 { 307 u32 client; 308 309 client = MT8195_SVPP1_MDP_RSZ; 310 mtk_mmsys_update_bits(dev_get_drvdata(dev), 311 MT8195_VPP1_HW_DCM_1ST_DIS0, client, 312 ((enable) ? client : 0), cmdq_pkt); 313 mtk_mmsys_update_bits(dev_get_drvdata(dev), 314 MT8195_VPP1_HW_DCM_2ND_DIS0, client, 315 ((enable) ? client : 0), cmdq_pkt); 316 317 client = MT8195_SVPP2_MDP_RSZ | MT8195_SVPP3_MDP_RSZ; 318 mtk_mmsys_update_bits(dev_get_drvdata(dev), 319 MT8195_VPP1_HW_DCM_1ST_DIS1, client, 320 ((enable) ? client : 0), cmdq_pkt); 321 mtk_mmsys_update_bits(dev_get_drvdata(dev), 322 MT8195_VPP1_HW_DCM_2ND_DIS1, client, 323 ((enable) ? client : 0), cmdq_pkt); 324 } 325 EXPORT_SYMBOL_GPL(mtk_mmsys_vpp_rsz_dcm_config); 326 327 static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id, 328 bool assert) 329 { 330 struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev); 331 unsigned long flags; 332 u32 offset; 333 u32 reg; 334 335 if (mmsys->data->rst_tb) { 336 if (id >= mmsys->data->num_resets) { 337 dev_err(rcdev->dev, "Invalid reset ID: %lu (>=%u)\n", 338 id, mmsys->data->num_resets); 339 return -EINVAL; 340 } 341 id = mmsys->data->rst_tb[id]; 342 } 343 344 offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32); 345 id = id % MMSYS_SW_RESET_PER_REG; 346 reg = mmsys->data->sw0_rst_offset + offset; 347 348 spin_lock_irqsave(&mmsys->lock, flags); 349 350 if (assert) 351 mtk_mmsys_update_bits(mmsys, reg, BIT(id), 0, NULL); 352 else 353 mtk_mmsys_update_bits(mmsys, reg, BIT(id), BIT(id), NULL); 354 355 spin_unlock_irqrestore(&mmsys->lock, flags); 356 357 return 0; 358 } 359 360 static int mtk_mmsys_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) 361 { 362 return mtk_mmsys_reset_update(rcdev, id, true); 363 } 364 365 static int mtk_mmsys_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) 366 { 367 return mtk_mmsys_reset_update(rcdev, id, false); 368 } 369 370 static int mtk_mmsys_reset(struct reset_controller_dev *rcdev, unsigned long id) 371 { 372 int ret; 373 374 ret = mtk_mmsys_reset_assert(rcdev, id); 375 if (ret) 376 return ret; 377 378 usleep_range(1000, 1100); 379 380 return mtk_mmsys_reset_deassert(rcdev, id); 381 } 382 383 static const struct reset_control_ops mtk_mmsys_reset_ops = { 384 .assert = mtk_mmsys_reset_assert, 385 .deassert = mtk_mmsys_reset_deassert, 386 .reset = mtk_mmsys_reset, 387 }; 388 389 static int mtk_mmsys_probe(struct platform_device *pdev) 390 { 391 struct device *dev = &pdev->dev; 392 struct platform_device *clks; 393 struct platform_device *drm; 394 struct mtk_mmsys *mmsys; 395 int ret; 396 397 mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL); 398 if (!mmsys) 399 return -ENOMEM; 400 401 mmsys->regs = devm_platform_ioremap_resource(pdev, 0); 402 if (IS_ERR(mmsys->regs)) { 403 ret = PTR_ERR(mmsys->regs); 404 dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret); 405 return ret; 406 } 407 408 mmsys->data = of_device_get_match_data(&pdev->dev); 409 410 if (mmsys->data->num_resets > 0) { 411 spin_lock_init(&mmsys->lock); 412 413 mmsys->rcdev.owner = THIS_MODULE; 414 mmsys->rcdev.nr_resets = mmsys->data->num_resets; 415 mmsys->rcdev.ops = &mtk_mmsys_reset_ops; 416 mmsys->rcdev.of_node = pdev->dev.of_node; 417 ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev); 418 if (ret) { 419 dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret); 420 return ret; 421 } 422 } 423 424 /* CMDQ is optional */ 425 ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0); 426 if (ret) 427 dev_dbg(dev, "No mediatek,gce-client-reg!\n"); 428 429 platform_set_drvdata(pdev, mmsys); 430 431 clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver, 432 PLATFORM_DEVID_AUTO, NULL, 0); 433 if (IS_ERR(clks)) 434 return PTR_ERR(clks); 435 mmsys->clks_pdev = clks; 436 437 if (mmsys->data->is_vppsys) 438 goto out_probe_done; 439 440 drm = platform_device_register_data(&pdev->dev, "mediatek-drm", 441 PLATFORM_DEVID_AUTO, NULL, 0); 442 if (IS_ERR(drm)) { 443 platform_device_unregister(clks); 444 return PTR_ERR(drm); 445 } 446 mmsys->drm_pdev = drm; 447 448 out_probe_done: 449 return 0; 450 } 451 452 static void mtk_mmsys_remove(struct platform_device *pdev) 453 { 454 struct mtk_mmsys *mmsys = platform_get_drvdata(pdev); 455 456 platform_device_unregister(mmsys->drm_pdev); 457 platform_device_unregister(mmsys->clks_pdev); 458 } 459 460 static const struct of_device_id of_match_mtk_mmsys[] = { 461 { .compatible = "mediatek,mt2701-mmsys", .data = &mt2701_mmsys_driver_data }, 462 { .compatible = "mediatek,mt2712-mmsys", .data = &mt2712_mmsys_driver_data }, 463 { .compatible = "mediatek,mt6779-mmsys", .data = &mt6779_mmsys_driver_data }, 464 { .compatible = "mediatek,mt6795-mmsys", .data = &mt6795_mmsys_driver_data }, 465 { .compatible = "mediatek,mt6797-mmsys", .data = &mt6797_mmsys_driver_data }, 466 { .compatible = "mediatek,mt8167-mmsys", .data = &mt8167_mmsys_driver_data }, 467 { .compatible = "mediatek,mt8173-mmsys", .data = &mt8173_mmsys_driver_data }, 468 { .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data }, 469 { .compatible = "mediatek,mt8186-mmsys", .data = &mt8186_mmsys_driver_data }, 470 { .compatible = "mediatek,mt8188-vdosys0", .data = &mt8188_vdosys0_driver_data }, 471 { .compatible = "mediatek,mt8188-vdosys1", .data = &mt8188_vdosys1_driver_data }, 472 { .compatible = "mediatek,mt8188-vppsys0", .data = &mt8188_vppsys0_driver_data }, 473 { .compatible = "mediatek,mt8188-vppsys1", .data = &mt8188_vppsys1_driver_data }, 474 { .compatible = "mediatek,mt8192-mmsys", .data = &mt8192_mmsys_driver_data }, 475 /* "mediatek,mt8195-mmsys" compatible is deprecated */ 476 { .compatible = "mediatek,mt8195-mmsys", .data = &mt8195_vdosys0_driver_data }, 477 { .compatible = "mediatek,mt8195-vdosys0", .data = &mt8195_vdosys0_driver_data }, 478 { .compatible = "mediatek,mt8195-vdosys1", .data = &mt8195_vdosys1_driver_data }, 479 { .compatible = "mediatek,mt8195-vppsys0", .data = &mt8195_vppsys0_driver_data }, 480 { .compatible = "mediatek,mt8195-vppsys1", .data = &mt8195_vppsys1_driver_data }, 481 { .compatible = "mediatek,mt8365-mmsys", .data = &mt8365_mmsys_driver_data }, 482 { /* sentinel */ } 483 }; 484 MODULE_DEVICE_TABLE(of, of_match_mtk_mmsys); 485 486 static struct platform_driver mtk_mmsys_drv = { 487 .driver = { 488 .name = "mtk-mmsys", 489 .of_match_table = of_match_mtk_mmsys, 490 }, 491 .probe = mtk_mmsys_probe, 492 .remove = mtk_mmsys_remove, 493 }; 494 module_platform_driver(mtk_mmsys_drv); 495 496 MODULE_AUTHOR("Yongqiang Niu <yongqiang.niu@mediatek.com>"); 497 MODULE_DESCRIPTION("MediaTek SoC MMSYS driver"); 498 MODULE_LICENSE("GPL"); 499