1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: James Liao <jamesjj.liao@mediatek.com> 5 */ 6 7 #include <linux/delay.h> 8 #include <linux/device.h> 9 #include <linux/io.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 #include <linux/reset-controller.h> 14 #include <linux/soc/mediatek/mtk-mmsys.h> 15 16 #include "mtk-mmsys.h" 17 #include "mt8167-mmsys.h" 18 #include "mt8173-mmsys.h" 19 #include "mt8183-mmsys.h" 20 #include "mt8186-mmsys.h" 21 #include "mt8188-mmsys.h" 22 #include "mt8192-mmsys.h" 23 #include "mt8195-mmsys.h" 24 #include "mt8365-mmsys.h" 25 26 #define MMSYS_SW_RESET_PER_REG 32 27 28 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { 29 .clk_driver = "clk-mt2701-mm", 30 .routes = mmsys_default_routing_table, 31 .num_routes = ARRAY_SIZE(mmsys_default_routing_table), 32 }; 33 34 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { 35 .clk_driver = "clk-mt2712-mm", 36 .routes = mmsys_default_routing_table, 37 .num_routes = ARRAY_SIZE(mmsys_default_routing_table), 38 }; 39 40 static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { 41 .clk_driver = "clk-mt6779-mm", 42 }; 43 44 static const struct mtk_mmsys_driver_data mt6795_mmsys_driver_data = { 45 .clk_driver = "clk-mt6795-mm", 46 .routes = mt8173_mmsys_routing_table, 47 .num_routes = ARRAY_SIZE(mt8173_mmsys_routing_table), 48 .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, 49 .num_resets = 64, 50 }; 51 52 static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { 53 .clk_driver = "clk-mt6797-mm", 54 }; 55 56 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { 57 .clk_driver = "clk-mt8167-mm", 58 .routes = mt8167_mmsys_routing_table, 59 .num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table), 60 }; 61 62 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { 63 .clk_driver = "clk-mt8173-mm", 64 .routes = mt8173_mmsys_routing_table, 65 .num_routes = ARRAY_SIZE(mt8173_mmsys_routing_table), 66 .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, 67 .num_resets = 64, 68 }; 69 70 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { 71 .clk_driver = "clk-mt8183-mm", 72 .routes = mmsys_mt8183_routing_table, 73 .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table), 74 .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, 75 .num_resets = 32, 76 }; 77 78 static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { 79 .clk_driver = "clk-mt8186-mm", 80 .routes = mmsys_mt8186_routing_table, 81 .num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table), 82 .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, 83 .num_resets = 32, 84 }; 85 86 static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = { 87 .clk_driver = "clk-mt8188-vdo0", 88 .routes = mmsys_mt8188_routing_table, 89 .num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table), 90 .sw0_rst_offset = MT8188_VDO0_SW0_RST_B, 91 .rst_tb = mmsys_mt8188_vdo0_rst_tb, 92 .num_resets = ARRAY_SIZE(mmsys_mt8188_vdo0_rst_tb), 93 }; 94 95 static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data = { 96 .clk_driver = "clk-mt8188-vdo1", 97 .routes = mmsys_mt8188_vdo1_routing_table, 98 .num_routes = ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table), 99 .sw0_rst_offset = MT8188_VDO1_SW0_RST_B, 100 .rst_tb = mmsys_mt8188_vdo1_rst_tb, 101 .num_resets = ARRAY_SIZE(mmsys_mt8188_vdo1_rst_tb), 102 .vsync_len = 1, 103 }; 104 105 static const struct mtk_mmsys_driver_data mt8188_vppsys0_driver_data = { 106 .clk_driver = "clk-mt8188-vpp0", 107 .is_vppsys = true, 108 }; 109 110 static const struct mtk_mmsys_driver_data mt8188_vppsys1_driver_data = { 111 .clk_driver = "clk-mt8188-vpp1", 112 .is_vppsys = true, 113 }; 114 115 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { 116 .clk_driver = "clk-mt8192-mm", 117 .routes = mmsys_mt8192_routing_table, 118 .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table), 119 .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, 120 .num_resets = 32, 121 }; 122 123 static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { 124 .clk_driver = "clk-mt8195-vdo0", 125 .routes = mmsys_mt8195_routing_table, 126 .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table), 127 }; 128 129 static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { 130 .clk_driver = "clk-mt8195-vdo1", 131 .routes = mmsys_mt8195_vdo1_routing_table, 132 .num_routes = ARRAY_SIZE(mmsys_mt8195_vdo1_routing_table), 133 .sw0_rst_offset = MT8195_VDO1_SW0_RST_B, 134 .num_resets = 64, 135 }; 136 137 static const struct mtk_mmsys_driver_data mt8195_vppsys0_driver_data = { 138 .clk_driver = "clk-mt8195-vpp0", 139 .is_vppsys = true, 140 }; 141 142 static const struct mtk_mmsys_driver_data mt8195_vppsys1_driver_data = { 143 .clk_driver = "clk-mt8195-vpp1", 144 .is_vppsys = true, 145 }; 146 147 static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { 148 .clk_driver = "clk-mt8365-mm", 149 .routes = mt8365_mmsys_routing_table, 150 .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table), 151 }; 152 153 struct mtk_mmsys { 154 void __iomem *regs; 155 const struct mtk_mmsys_driver_data *data; 156 struct platform_device *clks_pdev; 157 struct platform_device *drm_pdev; 158 spinlock_t lock; /* protects mmsys_sw_rst_b reg */ 159 struct reset_controller_dev rcdev; 160 struct cmdq_client_reg cmdq_base; 161 }; 162 163 static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val, 164 struct cmdq_pkt *cmdq_pkt) 165 { 166 int ret; 167 u32 tmp; 168 169 if (mmsys->cmdq_base.size && cmdq_pkt) { 170 ret = cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys, 171 mmsys->cmdq_base.offset + offset, val, 172 mask); 173 if (ret) 174 pr_debug("CMDQ unavailable: using CPU write\n"); 175 else 176 return; 177 } 178 tmp = readl_relaxed(mmsys->regs + offset); 179 tmp = (tmp & ~mask) | (val & mask); 180 writel_relaxed(tmp, mmsys->regs + offset); 181 } 182 183 void mtk_mmsys_ddp_connect(struct device *dev, 184 enum mtk_ddp_comp_id cur, 185 enum mtk_ddp_comp_id next) 186 { 187 struct mtk_mmsys *mmsys = dev_get_drvdata(dev); 188 const struct mtk_mmsys_routes *routes = mmsys->data->routes; 189 int i; 190 191 for (i = 0; i < mmsys->data->num_routes; i++) 192 if (cur == routes[i].from_comp && next == routes[i].to_comp) 193 mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask, 194 routes[i].val, NULL); 195 196 if (mmsys->data->vsync_len) 197 mtk_mmsys_update_bits(mmsys, MT8188_VDO1_MIXER_VSYNC_LEN, GENMASK(31, 0), 198 mmsys->data->vsync_len, NULL); 199 } 200 EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); 201 202 void mtk_mmsys_ddp_disconnect(struct device *dev, 203 enum mtk_ddp_comp_id cur, 204 enum mtk_ddp_comp_id next) 205 { 206 struct mtk_mmsys *mmsys = dev_get_drvdata(dev); 207 const struct mtk_mmsys_routes *routes = mmsys->data->routes; 208 int i; 209 210 for (i = 0; i < mmsys->data->num_routes; i++) 211 if (cur == routes[i].from_comp && next == routes[i].to_comp) 212 mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask, 0, NULL); 213 } 214 EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); 215 216 void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width, int height, 217 struct cmdq_pkt *cmdq_pkt) 218 { 219 mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_MERGE0_ASYNC_CFG_WD + 0x10 * idx, 220 ~0, height << 16 | width, cmdq_pkt); 221 } 222 EXPORT_SYMBOL_GPL(mtk_mmsys_merge_async_config); 223 224 void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height, 225 struct cmdq_pkt *cmdq_pkt) 226 { 227 mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_HDRBE_ASYNC_CFG_WD, ~0, 228 be_height << 16 | be_width, cmdq_pkt); 229 } 230 EXPORT_SYMBOL_GPL(mtk_mmsys_hdr_config); 231 232 void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 alpha, 233 u8 mode, u32 biwidth, struct cmdq_pkt *cmdq_pkt) 234 { 235 struct mtk_mmsys *mmsys = dev_get_drvdata(dev); 236 237 mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_ALPHA + (idx - 1) * 4, ~0, 238 alpha << 16 | alpha, cmdq_pkt); 239 mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(19 + idx), 240 alpha_sel << (19 + idx), cmdq_pkt); 241 mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4, 242 GENMASK(31, 16) | GENMASK(1, 0), biwidth << 16 | mode, cmdq_pkt); 243 } 244 EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_config); 245 246 void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap, 247 struct cmdq_pkt *cmdq_pkt) 248 { 249 mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4, 250 BIT(4), channel_swap << 4, cmdq_pkt); 251 } 252 EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_channel_swap); 253 254 void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val) 255 { 256 struct mtk_mmsys *mmsys = dev_get_drvdata(dev); 257 258 switch (val) { 259 case MTK_DPI_RGB888_SDR_CON: 260 mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT, 261 MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB888_SDR_CON, NULL); 262 break; 263 case MTK_DPI_RGB565_SDR_CON: 264 mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT, 265 MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB565_SDR_CON, NULL); 266 break; 267 case MTK_DPI_RGB565_DDR_CON: 268 mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT, 269 MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB565_DDR_CON, NULL); 270 break; 271 case MTK_DPI_RGB888_DDR_CON: 272 default: 273 mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT, 274 MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB888_DDR_CON, NULL); 275 break; 276 } 277 } 278 EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_dpi_fmt_config); 279 280 void mtk_mmsys_vpp_rsz_merge_config(struct device *dev, u32 id, bool enable, 281 struct cmdq_pkt *cmdq_pkt) 282 { 283 u32 reg; 284 285 switch (id) { 286 case 2: 287 reg = MT8195_SVPP2_BUF_BF_RSZ_SWITCH; 288 break; 289 case 3: 290 reg = MT8195_SVPP3_BUF_BF_RSZ_SWITCH; 291 break; 292 default: 293 dev_err(dev, "Invalid id %d\n", id); 294 return; 295 } 296 297 mtk_mmsys_update_bits(dev_get_drvdata(dev), reg, ~0, enable, cmdq_pkt); 298 } 299 EXPORT_SYMBOL_GPL(mtk_mmsys_vpp_rsz_merge_config); 300 301 void mtk_mmsys_vpp_rsz_dcm_config(struct device *dev, bool enable, 302 struct cmdq_pkt *cmdq_pkt) 303 { 304 u32 client; 305 306 client = MT8195_SVPP1_MDP_RSZ; 307 mtk_mmsys_update_bits(dev_get_drvdata(dev), 308 MT8195_VPP1_HW_DCM_1ST_DIS0, client, 309 ((enable) ? client : 0), cmdq_pkt); 310 mtk_mmsys_update_bits(dev_get_drvdata(dev), 311 MT8195_VPP1_HW_DCM_2ND_DIS0, client, 312 ((enable) ? client : 0), cmdq_pkt); 313 314 client = MT8195_SVPP2_MDP_RSZ | MT8195_SVPP3_MDP_RSZ; 315 mtk_mmsys_update_bits(dev_get_drvdata(dev), 316 MT8195_VPP1_HW_DCM_1ST_DIS1, client, 317 ((enable) ? client : 0), cmdq_pkt); 318 mtk_mmsys_update_bits(dev_get_drvdata(dev), 319 MT8195_VPP1_HW_DCM_2ND_DIS1, client, 320 ((enable) ? client : 0), cmdq_pkt); 321 } 322 EXPORT_SYMBOL_GPL(mtk_mmsys_vpp_rsz_dcm_config); 323 324 static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id, 325 bool assert) 326 { 327 struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev); 328 unsigned long flags; 329 u32 offset; 330 u32 reg; 331 332 if (mmsys->data->rst_tb) { 333 if (id >= mmsys->data->num_resets) { 334 dev_err(rcdev->dev, "Invalid reset ID: %lu (>=%u)\n", 335 id, mmsys->data->num_resets); 336 return -EINVAL; 337 } 338 id = mmsys->data->rst_tb[id]; 339 } 340 341 offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32); 342 id = id % MMSYS_SW_RESET_PER_REG; 343 reg = mmsys->data->sw0_rst_offset + offset; 344 345 spin_lock_irqsave(&mmsys->lock, flags); 346 347 if (assert) 348 mtk_mmsys_update_bits(mmsys, reg, BIT(id), 0, NULL); 349 else 350 mtk_mmsys_update_bits(mmsys, reg, BIT(id), BIT(id), NULL); 351 352 spin_unlock_irqrestore(&mmsys->lock, flags); 353 354 return 0; 355 } 356 357 static int mtk_mmsys_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) 358 { 359 return mtk_mmsys_reset_update(rcdev, id, true); 360 } 361 362 static int mtk_mmsys_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) 363 { 364 return mtk_mmsys_reset_update(rcdev, id, false); 365 } 366 367 static int mtk_mmsys_reset(struct reset_controller_dev *rcdev, unsigned long id) 368 { 369 int ret; 370 371 ret = mtk_mmsys_reset_assert(rcdev, id); 372 if (ret) 373 return ret; 374 375 usleep_range(1000, 1100); 376 377 return mtk_mmsys_reset_deassert(rcdev, id); 378 } 379 380 static const struct reset_control_ops mtk_mmsys_reset_ops = { 381 .assert = mtk_mmsys_reset_assert, 382 .deassert = mtk_mmsys_reset_deassert, 383 .reset = mtk_mmsys_reset, 384 }; 385 386 static int mtk_mmsys_probe(struct platform_device *pdev) 387 { 388 struct device *dev = &pdev->dev; 389 struct platform_device *clks; 390 struct platform_device *drm; 391 struct mtk_mmsys *mmsys; 392 int ret; 393 394 mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL); 395 if (!mmsys) 396 return -ENOMEM; 397 398 mmsys->regs = devm_platform_ioremap_resource(pdev, 0); 399 if (IS_ERR(mmsys->regs)) { 400 ret = PTR_ERR(mmsys->regs); 401 dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret); 402 return ret; 403 } 404 405 mmsys->data = of_device_get_match_data(&pdev->dev); 406 407 if (mmsys->data->num_resets > 0) { 408 spin_lock_init(&mmsys->lock); 409 410 mmsys->rcdev.owner = THIS_MODULE; 411 mmsys->rcdev.nr_resets = mmsys->data->num_resets; 412 mmsys->rcdev.ops = &mtk_mmsys_reset_ops; 413 mmsys->rcdev.of_node = pdev->dev.of_node; 414 ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev); 415 if (ret) { 416 dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret); 417 return ret; 418 } 419 } 420 421 /* CMDQ is optional */ 422 ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0); 423 if (ret) 424 dev_dbg(dev, "No mediatek,gce-client-reg!\n"); 425 426 platform_set_drvdata(pdev, mmsys); 427 428 clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver, 429 PLATFORM_DEVID_AUTO, NULL, 0); 430 if (IS_ERR(clks)) 431 return PTR_ERR(clks); 432 mmsys->clks_pdev = clks; 433 434 if (mmsys->data->is_vppsys) 435 goto out_probe_done; 436 437 drm = platform_device_register_data(&pdev->dev, "mediatek-drm", 438 PLATFORM_DEVID_AUTO, NULL, 0); 439 if (IS_ERR(drm)) { 440 platform_device_unregister(clks); 441 return PTR_ERR(drm); 442 } 443 mmsys->drm_pdev = drm; 444 445 out_probe_done: 446 return 0; 447 } 448 449 static void mtk_mmsys_remove(struct platform_device *pdev) 450 { 451 struct mtk_mmsys *mmsys = platform_get_drvdata(pdev); 452 453 platform_device_unregister(mmsys->drm_pdev); 454 platform_device_unregister(mmsys->clks_pdev); 455 } 456 457 static const struct of_device_id of_match_mtk_mmsys[] = { 458 { .compatible = "mediatek,mt2701-mmsys", .data = &mt2701_mmsys_driver_data }, 459 { .compatible = "mediatek,mt2712-mmsys", .data = &mt2712_mmsys_driver_data }, 460 { .compatible = "mediatek,mt6779-mmsys", .data = &mt6779_mmsys_driver_data }, 461 { .compatible = "mediatek,mt6795-mmsys", .data = &mt6795_mmsys_driver_data }, 462 { .compatible = "mediatek,mt6797-mmsys", .data = &mt6797_mmsys_driver_data }, 463 { .compatible = "mediatek,mt8167-mmsys", .data = &mt8167_mmsys_driver_data }, 464 { .compatible = "mediatek,mt8173-mmsys", .data = &mt8173_mmsys_driver_data }, 465 { .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data }, 466 { .compatible = "mediatek,mt8186-mmsys", .data = &mt8186_mmsys_driver_data }, 467 { .compatible = "mediatek,mt8188-vdosys0", .data = &mt8188_vdosys0_driver_data }, 468 { .compatible = "mediatek,mt8188-vdosys1", .data = &mt8188_vdosys1_driver_data }, 469 { .compatible = "mediatek,mt8188-vppsys0", .data = &mt8188_vppsys0_driver_data }, 470 { .compatible = "mediatek,mt8188-vppsys1", .data = &mt8188_vppsys1_driver_data }, 471 { .compatible = "mediatek,mt8192-mmsys", .data = &mt8192_mmsys_driver_data }, 472 /* "mediatek,mt8195-mmsys" compatible is deprecated */ 473 { .compatible = "mediatek,mt8195-mmsys", .data = &mt8195_vdosys0_driver_data }, 474 { .compatible = "mediatek,mt8195-vdosys0", .data = &mt8195_vdosys0_driver_data }, 475 { .compatible = "mediatek,mt8195-vdosys1", .data = &mt8195_vdosys1_driver_data }, 476 { .compatible = "mediatek,mt8195-vppsys0", .data = &mt8195_vppsys0_driver_data }, 477 { .compatible = "mediatek,mt8195-vppsys1", .data = &mt8195_vppsys1_driver_data }, 478 { .compatible = "mediatek,mt8365-mmsys", .data = &mt8365_mmsys_driver_data }, 479 { /* sentinel */ } 480 }; 481 MODULE_DEVICE_TABLE(of, of_match_mtk_mmsys); 482 483 static struct platform_driver mtk_mmsys_drv = { 484 .driver = { 485 .name = "mtk-mmsys", 486 .of_match_table = of_match_mtk_mmsys, 487 }, 488 .probe = mtk_mmsys_probe, 489 .remove_new = mtk_mmsys_remove, 490 }; 491 module_platform_driver(mtk_mmsys_drv); 492 493 MODULE_AUTHOR("Yongqiang Niu <yongqiang.niu@mediatek.com>"); 494 MODULE_DESCRIPTION("MediaTek SoC MMSYS driver"); 495 MODULE_LICENSE("GPL"); 496