1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_MEDIATEK_MT8192_MMSYS_H 4 #define __SOC_MEDIATEK_MT8192_MMSYS_H 5 6 #define MT8192_MMSYS_OVL_MOUT_EN 0xf04 7 #define MT8192_DISP_OVL1_2L_MOUT_EN 0xf08 8 #define MT8192_DISP_OVL0_2L_MOUT_EN 0xf18 9 #define MT8192_DISP_OVL0_MOUT_EN 0xf1c 10 #define MT8192_DISP_RDMA0_SEL_IN 0xf2c 11 #define MT8192_DISP_RDMA0_SOUT_SEL 0xf30 12 #define MT8192_DISP_CCORR0_SOUT_SEL 0xf34 13 #define MT8192_DISP_AAL0_SEL_IN 0xf38 14 #define MT8192_DISP_DITHER0_MOUT_EN 0xf3c 15 #define MT8192_DISP_DSI0_SEL_IN 0xf40 16 #define MT8192_DISP_OVL2_2L_MOUT_EN 0xf4c 17 18 #define MT8192_DISP_OVL0_GO_BLEND BIT(0) 19 #define MT8192_DITHER0_MOUT_IN_DSI0 BIT(0) 20 #define MT8192_OVL0_MOUT_EN_DISP_RDMA0 BIT(0) 21 #define MT8192_OVL2_2L_MOUT_EN_RDMA4 BIT(0) 22 #define MT8192_DISP_OVL0_GO_BG BIT(1) 23 #define MT8192_DISP_OVL0_2L_GO_BLEND BIT(2) 24 #define MT8192_DISP_OVL0_2L_GO_BG BIT(3) 25 #define MT8192_OVL1_2L_MOUT_EN_RDMA1 BIT(4) 26 #define MT8192_OVL0_MOUT_EN_OVL0_2L BIT(4) 27 #define MT8192_RDMA0_SEL_IN_OVL0_2L 0x3 28 #define MT8192_RDMA0_SOUT_COLOR0 0x1 29 #define MT8192_CCORR0_SOUT_AAL0 0x1 30 #define MT8192_AAL0_SEL_IN_CCORR0 0x1 31 #define MT8192_DSI0_SEL_IN_DITHER0 0x1 32 33 static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = { 34 { 35 DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, 36 MT8192_DISP_OVL0_2L_MOUT_EN, MT8192_OVL0_MOUT_EN_DISP_RDMA0, 37 MT8192_OVL0_MOUT_EN_DISP_RDMA0 38 }, { 39 DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_RDMA4, 40 MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4, 41 MT8192_OVL2_2L_MOUT_EN_RDMA4 42 }, { 43 DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, 44 MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0, 45 MT8192_DITHER0_MOUT_IN_DSI0 46 }, { 47 DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, 48 MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L, 49 MT8192_RDMA0_SEL_IN_OVL0_2L 50 }, { 51 DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0, 52 MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0, 53 MT8192_AAL0_SEL_IN_CCORR0 54 }, { 55 DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, 56 MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0, 57 MT8192_DSI0_SEL_IN_DITHER0 58 }, { 59 DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, 60 MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0, 61 MT8192_RDMA0_SOUT_COLOR0 62 }, { 63 DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0, 64 MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0, 65 MT8192_CCORR0_SOUT_AAL0 66 }, { 67 DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, 68 MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_GO_BG, 69 MT8192_DISP_OVL0_GO_BG 70 }, { 71 DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, 72 MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_2L_GO_BLEND, 73 MT8192_DISP_OVL0_2L_GO_BLEND 74 } 75 }; 76 77 #endif /* __SOC_MEDIATEK_MT8192_MMSYS_H */ 78