1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * LiteX SoC Controller Driver 4 * 5 * Copyright (C) 2020 Antmicro <www.antmicro.com> 6 * 7 */ 8 9 #include <linux/litex.h> 10 #include <linux/device.h> 11 #include <linux/errno.h> 12 #include <linux/of.h> 13 #include <linux/platform_device.h> 14 #include <linux/printk.h> 15 #include <linux/module.h> 16 #include <linux/io.h> 17 #include <linux/reboot.h> 18 19 /* reset register located at the base address */ 20 #define RESET_REG_OFF 0x00 21 #define RESET_REG_VALUE 0x00000001 22 23 #define SCRATCH_REG_OFF 0x04 24 #define SCRATCH_REG_VALUE 0x12345678 25 #define SCRATCH_TEST_VALUE 0xdeadbeef 26 27 /* 28 * Check LiteX CSR read/write access 29 * 30 * This function reads and writes a scratch register in order to verify if CSR 31 * access works. 32 * 33 * In case any problems are detected, the driver should panic. 34 * 35 * Access to the LiteX CSR is, by design, done in CPU native endianness. 36 * The driver should not dynamically configure access functions when 37 * the endianness mismatch is detected. Such situation indicates problems in 38 * the soft SoC design and should be solved at the LiteX generator level, 39 * not in the software. 40 */ 41 static int litex_check_csr_access(void __iomem *reg_addr) 42 { 43 unsigned long reg; 44 45 reg = litex_read32(reg_addr + SCRATCH_REG_OFF); 46 47 if (reg != SCRATCH_REG_VALUE) { 48 panic("Scratch register read error - the system is probably broken! Expected: 0x%x but got: 0x%lx", 49 SCRATCH_REG_VALUE, reg); 50 return -EINVAL; 51 } 52 53 litex_write32(reg_addr + SCRATCH_REG_OFF, SCRATCH_TEST_VALUE); 54 reg = litex_read32(reg_addr + SCRATCH_REG_OFF); 55 56 if (reg != SCRATCH_TEST_VALUE) { 57 panic("Scratch register write error - the system is probably broken! Expected: 0x%x but got: 0x%lx", 58 SCRATCH_TEST_VALUE, reg); 59 return -EINVAL; 60 } 61 62 /* restore original value of the SCRATCH register */ 63 litex_write32(reg_addr + SCRATCH_REG_OFF, SCRATCH_REG_VALUE); 64 65 pr_info("LiteX SoC Controller driver initialized"); 66 67 return 0; 68 } 69 70 struct litex_soc_ctrl_device { 71 void __iomem *base; 72 }; 73 74 static int litex_reset_handler(struct sys_off_data *data) 75 { 76 struct litex_soc_ctrl_device *soc_ctrl_dev = data->cb_data; 77 78 litex_write32(soc_ctrl_dev->base + RESET_REG_OFF, RESET_REG_VALUE); 79 return NOTIFY_DONE; 80 } 81 82 static const struct of_device_id litex_soc_ctrl_of_match[] = { 83 {.compatible = "litex,soc-controller"}, 84 {}, 85 }; 86 MODULE_DEVICE_TABLE(of, litex_soc_ctrl_of_match); 87 88 static int litex_soc_ctrl_probe(struct platform_device *pdev) 89 { 90 struct litex_soc_ctrl_device *soc_ctrl_dev; 91 int error; 92 93 soc_ctrl_dev = devm_kzalloc(&pdev->dev, sizeof(*soc_ctrl_dev), GFP_KERNEL); 94 if (!soc_ctrl_dev) 95 return -ENOMEM; 96 97 soc_ctrl_dev->base = devm_platform_ioremap_resource(pdev, 0); 98 if (IS_ERR(soc_ctrl_dev->base)) 99 return PTR_ERR(soc_ctrl_dev->base); 100 101 error = litex_check_csr_access(soc_ctrl_dev->base); 102 if (error) 103 return error; 104 105 error = devm_register_restart_handler(&pdev->dev, 106 litex_reset_handler, 107 soc_ctrl_dev); 108 if (error) { 109 dev_warn(&pdev->dev, "cannot register restart handler: %d\n", 110 error); 111 } 112 113 return 0; 114 } 115 116 static struct platform_driver litex_soc_ctrl_driver = { 117 .driver = { 118 .name = "litex-soc-controller", 119 .of_match_table = litex_soc_ctrl_of_match, 120 }, 121 .probe = litex_soc_ctrl_probe, 122 }; 123 124 module_platform_driver(litex_soc_ctrl_driver); 125 MODULE_DESCRIPTION("LiteX SoC Controller driver"); 126 MODULE_AUTHOR("Antmicro <www.antmicro.com>"); 127 MODULE_LICENSE("GPL v2"); 128