1 /* 2 * Intel IXP4xx Network Processor Engine driver for Linux 3 * 4 * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License 8 * as published by the Free Software Foundation. 9 * 10 * The code is based on publicly available information: 11 * - Intel IXP4xx Developer's Manual and other e-papers 12 * - Intel IXP400 Access Library Software (BSD license) 13 * - previous works by Christian Hohnstaedt <chohnstaedt@innominate.com> 14 * Thanks, Christian. 15 */ 16 17 #include <linux/delay.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/firmware.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/of.h> 24 #include <mach/npe.h> 25 26 #define DEBUG_MSG 0 27 #define DEBUG_FW 0 28 29 #define NPE_COUNT 3 30 #define MAX_RETRIES 1000 /* microseconds */ 31 #define NPE_42X_DATA_SIZE 0x800 /* in dwords */ 32 #define NPE_46X_DATA_SIZE 0x1000 33 #define NPE_A_42X_INSTR_SIZE 0x1000 34 #define NPE_B_AND_C_42X_INSTR_SIZE 0x800 35 #define NPE_46X_INSTR_SIZE 0x1000 36 #define REGS_SIZE 0x1000 37 38 #define NPE_PHYS_REG 32 39 40 #define FW_MAGIC 0xFEEDF00D 41 #define FW_BLOCK_TYPE_INSTR 0x0 42 #define FW_BLOCK_TYPE_DATA 0x1 43 #define FW_BLOCK_TYPE_EOF 0xF 44 45 /* NPE exec status (read) and command (write) */ 46 #define CMD_NPE_STEP 0x01 47 #define CMD_NPE_START 0x02 48 #define CMD_NPE_STOP 0x03 49 #define CMD_NPE_CLR_PIPE 0x04 50 #define CMD_CLR_PROFILE_CNT 0x0C 51 #define CMD_RD_INS_MEM 0x10 /* instruction memory */ 52 #define CMD_WR_INS_MEM 0x11 53 #define CMD_RD_DATA_MEM 0x12 /* data memory */ 54 #define CMD_WR_DATA_MEM 0x13 55 #define CMD_RD_ECS_REG 0x14 /* exec access register */ 56 #define CMD_WR_ECS_REG 0x15 57 58 #define STAT_RUN 0x80000000 59 #define STAT_STOP 0x40000000 60 #define STAT_CLEAR 0x20000000 61 #define STAT_ECS_K 0x00800000 /* pipeline clean */ 62 63 #define NPE_STEVT 0x1B 64 #define NPE_STARTPC 0x1C 65 #define NPE_REGMAP 0x1E 66 #define NPE_CINDEX 0x1F 67 68 #define INSTR_WR_REG_SHORT 0x0000C000 69 #define INSTR_WR_REG_BYTE 0x00004000 70 #define INSTR_RD_FIFO 0x0F888220 71 #define INSTR_RESET_MBOX 0x0FAC8210 72 73 #define ECS_BG_CTXT_REG_0 0x00 /* Background Executing Context */ 74 #define ECS_BG_CTXT_REG_1 0x01 /* Stack level */ 75 #define ECS_BG_CTXT_REG_2 0x02 76 #define ECS_PRI_1_CTXT_REG_0 0x04 /* Priority 1 Executing Context */ 77 #define ECS_PRI_1_CTXT_REG_1 0x05 /* Stack level */ 78 #define ECS_PRI_1_CTXT_REG_2 0x06 79 #define ECS_PRI_2_CTXT_REG_0 0x08 /* Priority 2 Executing Context */ 80 #define ECS_PRI_2_CTXT_REG_1 0x09 /* Stack level */ 81 #define ECS_PRI_2_CTXT_REG_2 0x0A 82 #define ECS_DBG_CTXT_REG_0 0x0C /* Debug Executing Context */ 83 #define ECS_DBG_CTXT_REG_1 0x0D /* Stack level */ 84 #define ECS_DBG_CTXT_REG_2 0x0E 85 #define ECS_INSTRUCT_REG 0x11 /* NPE Instruction Register */ 86 87 #define ECS_REG_0_ACTIVE 0x80000000 /* all levels */ 88 #define ECS_REG_0_NEXTPC_MASK 0x1FFF0000 /* BG/PRI1/PRI2 levels */ 89 #define ECS_REG_0_LDUR_BITS 8 90 #define ECS_REG_0_LDUR_MASK 0x00000700 /* all levels */ 91 #define ECS_REG_1_CCTXT_BITS 16 92 #define ECS_REG_1_CCTXT_MASK 0x000F0000 /* all levels */ 93 #define ECS_REG_1_SELCTXT_BITS 0 94 #define ECS_REG_1_SELCTXT_MASK 0x0000000F /* all levels */ 95 #define ECS_DBG_REG_2_IF 0x00100000 /* debug level */ 96 #define ECS_DBG_REG_2_IE 0x00080000 /* debug level */ 97 98 /* NPE watchpoint_fifo register bit */ 99 #define WFIFO_VALID 0x80000000 100 101 /* NPE messaging_status register bit definitions */ 102 #define MSGSTAT_OFNE 0x00010000 /* OutFifoNotEmpty */ 103 #define MSGSTAT_IFNF 0x00020000 /* InFifoNotFull */ 104 #define MSGSTAT_OFNF 0x00040000 /* OutFifoNotFull */ 105 #define MSGSTAT_IFNE 0x00080000 /* InFifoNotEmpty */ 106 #define MSGSTAT_MBINT 0x00100000 /* Mailbox interrupt */ 107 #define MSGSTAT_IFINT 0x00200000 /* InFifo interrupt */ 108 #define MSGSTAT_OFINT 0x00400000 /* OutFifo interrupt */ 109 #define MSGSTAT_WFINT 0x00800000 /* WatchFifo interrupt */ 110 111 /* NPE messaging_control register bit definitions */ 112 #define MSGCTL_OUT_FIFO 0x00010000 /* enable output FIFO */ 113 #define MSGCTL_IN_FIFO 0x00020000 /* enable input FIFO */ 114 #define MSGCTL_OUT_FIFO_WRITE 0x01000000 /* enable FIFO + WRITE */ 115 #define MSGCTL_IN_FIFO_WRITE 0x02000000 116 117 /* NPE mailbox_status value for reset */ 118 #define RESET_MBOX_STAT 0x0000F0F0 119 120 #define NPE_A_FIRMWARE "NPE-A" 121 #define NPE_B_FIRMWARE "NPE-B" 122 #define NPE_C_FIRMWARE "NPE-C" 123 124 const char *npe_names[] = { NPE_A_FIRMWARE, NPE_B_FIRMWARE, NPE_C_FIRMWARE }; 125 126 #define print_npe(pri, npe, fmt, ...) \ 127 printk(pri "%s: " fmt, npe_name(npe), ## __VA_ARGS__) 128 129 #if DEBUG_MSG 130 #define debug_msg(npe, fmt, ...) \ 131 print_npe(KERN_DEBUG, npe, fmt, ## __VA_ARGS__) 132 #else 133 #define debug_msg(npe, fmt, ...) 134 #endif 135 136 static struct { 137 u32 reg, val; 138 } ecs_reset[] = { 139 { ECS_BG_CTXT_REG_0, 0xA0000000 }, 140 { ECS_BG_CTXT_REG_1, 0x01000000 }, 141 { ECS_BG_CTXT_REG_2, 0x00008000 }, 142 { ECS_PRI_1_CTXT_REG_0, 0x20000080 }, 143 { ECS_PRI_1_CTXT_REG_1, 0x01000000 }, 144 { ECS_PRI_1_CTXT_REG_2, 0x00008000 }, 145 { ECS_PRI_2_CTXT_REG_0, 0x20000080 }, 146 { ECS_PRI_2_CTXT_REG_1, 0x01000000 }, 147 { ECS_PRI_2_CTXT_REG_2, 0x00008000 }, 148 { ECS_DBG_CTXT_REG_0, 0x20000000 }, 149 { ECS_DBG_CTXT_REG_1, 0x00000000 }, 150 { ECS_DBG_CTXT_REG_2, 0x001E0000 }, 151 { ECS_INSTRUCT_REG, 0x1003C00F }, 152 }; 153 154 static struct npe npe_tab[NPE_COUNT] = { 155 { 156 .id = 0, 157 .regs = (struct npe_regs __iomem *)IXP4XX_NPEA_BASE_VIRT, 158 .regs_phys = IXP4XX_NPEA_BASE_PHYS, 159 }, { 160 .id = 1, 161 .regs = (struct npe_regs __iomem *)IXP4XX_NPEB_BASE_VIRT, 162 .regs_phys = IXP4XX_NPEB_BASE_PHYS, 163 }, { 164 .id = 2, 165 .regs = (struct npe_regs __iomem *)IXP4XX_NPEC_BASE_VIRT, 166 .regs_phys = IXP4XX_NPEC_BASE_PHYS, 167 } 168 }; 169 170 int npe_running(struct npe *npe) 171 { 172 return (__raw_readl(&npe->regs->exec_status_cmd) & STAT_RUN) != 0; 173 } 174 175 static void npe_cmd_write(struct npe *npe, u32 addr, int cmd, u32 data) 176 { 177 __raw_writel(data, &npe->regs->exec_data); 178 __raw_writel(addr, &npe->regs->exec_addr); 179 __raw_writel(cmd, &npe->regs->exec_status_cmd); 180 } 181 182 static u32 npe_cmd_read(struct npe *npe, u32 addr, int cmd) 183 { 184 __raw_writel(addr, &npe->regs->exec_addr); 185 __raw_writel(cmd, &npe->regs->exec_status_cmd); 186 /* Iintroduce extra read cycles after issuing read command to NPE 187 so that we read the register after the NPE has updated it. 188 This is to overcome race condition between XScale and NPE */ 189 __raw_readl(&npe->regs->exec_data); 190 __raw_readl(&npe->regs->exec_data); 191 return __raw_readl(&npe->regs->exec_data); 192 } 193 194 static void npe_clear_active(struct npe *npe, u32 reg) 195 { 196 u32 val = npe_cmd_read(npe, reg, CMD_RD_ECS_REG); 197 npe_cmd_write(npe, reg, CMD_WR_ECS_REG, val & ~ECS_REG_0_ACTIVE); 198 } 199 200 static void npe_start(struct npe *npe) 201 { 202 /* ensure only Background Context Stack Level is active */ 203 npe_clear_active(npe, ECS_PRI_1_CTXT_REG_0); 204 npe_clear_active(npe, ECS_PRI_2_CTXT_REG_0); 205 npe_clear_active(npe, ECS_DBG_CTXT_REG_0); 206 207 __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); 208 __raw_writel(CMD_NPE_START, &npe->regs->exec_status_cmd); 209 } 210 211 static void npe_stop(struct npe *npe) 212 { 213 __raw_writel(CMD_NPE_STOP, &npe->regs->exec_status_cmd); 214 __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); /*FIXME?*/ 215 } 216 217 static int __must_check npe_debug_instr(struct npe *npe, u32 instr, u32 ctx, 218 u32 ldur) 219 { 220 u32 wc; 221 int i; 222 223 /* set the Active bit, and the LDUR, in the debug level */ 224 npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG, 225 ECS_REG_0_ACTIVE | (ldur << ECS_REG_0_LDUR_BITS)); 226 227 /* set CCTXT at ECS DEBUG L3 to specify in which context to execute 228 the instruction, and set SELCTXT at ECS DEBUG Level to specify 229 which context store to access. 230 Debug ECS Level Reg 1 has form 0x000n000n, where n = context number 231 */ 232 npe_cmd_write(npe, ECS_DBG_CTXT_REG_1, CMD_WR_ECS_REG, 233 (ctx << ECS_REG_1_CCTXT_BITS) | 234 (ctx << ECS_REG_1_SELCTXT_BITS)); 235 236 /* clear the pipeline */ 237 __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); 238 239 /* load NPE instruction into the instruction register */ 240 npe_cmd_write(npe, ECS_INSTRUCT_REG, CMD_WR_ECS_REG, instr); 241 242 /* we need this value later to wait for completion of NPE execution 243 step */ 244 wc = __raw_readl(&npe->regs->watch_count); 245 246 /* issue a Step One command via the Execution Control register */ 247 __raw_writel(CMD_NPE_STEP, &npe->regs->exec_status_cmd); 248 249 /* Watch Count register increments when NPE completes an instruction */ 250 for (i = 0; i < MAX_RETRIES; i++) { 251 if (wc != __raw_readl(&npe->regs->watch_count)) 252 return 0; 253 udelay(1); 254 } 255 256 print_npe(KERN_ERR, npe, "reset: npe_debug_instr(): timeout\n"); 257 return -ETIMEDOUT; 258 } 259 260 static int __must_check npe_logical_reg_write8(struct npe *npe, u32 addr, 261 u8 val, u32 ctx) 262 { 263 /* here we build the NPE assembler instruction: mov8 d0, #0 */ 264 u32 instr = INSTR_WR_REG_BYTE | /* OpCode */ 265 addr << 9 | /* base Operand */ 266 (val & 0x1F) << 4 | /* lower 5 bits to immediate data */ 267 (val & ~0x1F) << (18 - 5);/* higher 3 bits to CoProc instr. */ 268 return npe_debug_instr(npe, instr, ctx, 1); /* execute it */ 269 } 270 271 static int __must_check npe_logical_reg_write16(struct npe *npe, u32 addr, 272 u16 val, u32 ctx) 273 { 274 /* here we build the NPE assembler instruction: mov16 d0, #0 */ 275 u32 instr = INSTR_WR_REG_SHORT | /* OpCode */ 276 addr << 9 | /* base Operand */ 277 (val & 0x1F) << 4 | /* lower 5 bits to immediate data */ 278 (val & ~0x1F) << (18 - 5);/* higher 11 bits to CoProc instr. */ 279 return npe_debug_instr(npe, instr, ctx, 1); /* execute it */ 280 } 281 282 static int __must_check npe_logical_reg_write32(struct npe *npe, u32 addr, 283 u32 val, u32 ctx) 284 { 285 /* write in 16 bit steps first the high and then the low value */ 286 if (npe_logical_reg_write16(npe, addr, val >> 16, ctx)) 287 return -ETIMEDOUT; 288 return npe_logical_reg_write16(npe, addr + 2, val & 0xFFFF, ctx); 289 } 290 291 static int npe_reset(struct npe *npe) 292 { 293 u32 val, ctl, exec_count, ctx_reg2; 294 int i; 295 296 ctl = (__raw_readl(&npe->regs->messaging_control) | 0x3F000000) & 297 0x3F3FFFFF; 298 299 /* disable parity interrupt */ 300 __raw_writel(ctl & 0x3F00FFFF, &npe->regs->messaging_control); 301 302 /* pre exec - debug instruction */ 303 /* turn off the halt bit by clearing Execution Count register. */ 304 exec_count = __raw_readl(&npe->regs->exec_count); 305 __raw_writel(0, &npe->regs->exec_count); 306 /* ensure that IF and IE are on (temporarily), so that we don't end up 307 stepping forever */ 308 ctx_reg2 = npe_cmd_read(npe, ECS_DBG_CTXT_REG_2, CMD_RD_ECS_REG); 309 npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2 | 310 ECS_DBG_REG_2_IF | ECS_DBG_REG_2_IE); 311 312 /* clear the FIFOs */ 313 while (__raw_readl(&npe->regs->watchpoint_fifo) & WFIFO_VALID) 314 ; 315 while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE) 316 /* read from the outFIFO until empty */ 317 print_npe(KERN_DEBUG, npe, "npe_reset: read FIFO = 0x%X\n", 318 __raw_readl(&npe->regs->in_out_fifo)); 319 320 while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE) 321 /* step execution of the NPE intruction to read inFIFO using 322 the Debug Executing Context stack */ 323 if (npe_debug_instr(npe, INSTR_RD_FIFO, 0, 0)) 324 return -ETIMEDOUT; 325 326 /* reset the mailbox reg from the XScale side */ 327 __raw_writel(RESET_MBOX_STAT, &npe->regs->mailbox_status); 328 /* from NPE side */ 329 if (npe_debug_instr(npe, INSTR_RESET_MBOX, 0, 0)) 330 return -ETIMEDOUT; 331 332 /* Reset the physical registers in the NPE register file */ 333 for (val = 0; val < NPE_PHYS_REG; val++) { 334 if (npe_logical_reg_write16(npe, NPE_REGMAP, val >> 1, 0)) 335 return -ETIMEDOUT; 336 /* address is either 0 or 4 */ 337 if (npe_logical_reg_write32(npe, (val & 1) * 4, 0, 0)) 338 return -ETIMEDOUT; 339 } 340 341 /* Reset the context store = each context's Context Store registers */ 342 343 /* Context 0 has no STARTPC. Instead, this value is used to set NextPC 344 for Background ECS, to set where NPE starts executing code */ 345 val = npe_cmd_read(npe, ECS_BG_CTXT_REG_0, CMD_RD_ECS_REG); 346 val &= ~ECS_REG_0_NEXTPC_MASK; 347 val |= (0 /* NextPC */ << 16) & ECS_REG_0_NEXTPC_MASK; 348 npe_cmd_write(npe, ECS_BG_CTXT_REG_0, CMD_WR_ECS_REG, val); 349 350 for (i = 0; i < 16; i++) { 351 if (i) { /* Context 0 has no STEVT nor STARTPC */ 352 /* STEVT = off, 0x80 */ 353 if (npe_logical_reg_write8(npe, NPE_STEVT, 0x80, i)) 354 return -ETIMEDOUT; 355 if (npe_logical_reg_write16(npe, NPE_STARTPC, 0, i)) 356 return -ETIMEDOUT; 357 } 358 /* REGMAP = d0->p0, d8->p2, d16->p4 */ 359 if (npe_logical_reg_write16(npe, NPE_REGMAP, 0x820, i)) 360 return -ETIMEDOUT; 361 if (npe_logical_reg_write8(npe, NPE_CINDEX, 0, i)) 362 return -ETIMEDOUT; 363 } 364 365 /* post exec */ 366 /* clear active bit in debug level */ 367 npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG, 0); 368 /* clear the pipeline */ 369 __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); 370 /* restore previous values */ 371 __raw_writel(exec_count, &npe->regs->exec_count); 372 npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2); 373 374 /* write reset values to Execution Context Stack registers */ 375 for (val = 0; val < ARRAY_SIZE(ecs_reset); val++) 376 npe_cmd_write(npe, ecs_reset[val].reg, CMD_WR_ECS_REG, 377 ecs_reset[val].val); 378 379 /* clear the profile counter */ 380 __raw_writel(CMD_CLR_PROFILE_CNT, &npe->regs->exec_status_cmd); 381 382 __raw_writel(0, &npe->regs->exec_count); 383 __raw_writel(0, &npe->regs->action_points[0]); 384 __raw_writel(0, &npe->regs->action_points[1]); 385 __raw_writel(0, &npe->regs->action_points[2]); 386 __raw_writel(0, &npe->regs->action_points[3]); 387 __raw_writel(0, &npe->regs->watch_count); 388 389 val = ixp4xx_read_feature_bits(); 390 /* reset the NPE */ 391 ixp4xx_write_feature_bits(val & 392 ~(IXP4XX_FEATURE_RESET_NPEA << npe->id)); 393 /* deassert reset */ 394 ixp4xx_write_feature_bits(val | 395 (IXP4XX_FEATURE_RESET_NPEA << npe->id)); 396 for (i = 0; i < MAX_RETRIES; i++) { 397 if (ixp4xx_read_feature_bits() & 398 (IXP4XX_FEATURE_RESET_NPEA << npe->id)) 399 break; /* NPE is back alive */ 400 udelay(1); 401 } 402 if (i == MAX_RETRIES) 403 return -ETIMEDOUT; 404 405 npe_stop(npe); 406 407 /* restore NPE configuration bus Control Register - parity settings */ 408 __raw_writel(ctl, &npe->regs->messaging_control); 409 return 0; 410 } 411 412 413 int npe_send_message(struct npe *npe, const void *msg, const char *what) 414 { 415 const u32 *send = msg; 416 int cycles = 0; 417 418 debug_msg(npe, "Trying to send message %s [%08X:%08X]\n", 419 what, send[0], send[1]); 420 421 if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE) { 422 debug_msg(npe, "NPE input FIFO not empty\n"); 423 return -EIO; 424 } 425 426 __raw_writel(send[0], &npe->regs->in_out_fifo); 427 428 if (!(__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNF)) { 429 debug_msg(npe, "NPE input FIFO full\n"); 430 return -EIO; 431 } 432 433 __raw_writel(send[1], &npe->regs->in_out_fifo); 434 435 while ((cycles < MAX_RETRIES) && 436 (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)) { 437 udelay(1); 438 cycles++; 439 } 440 441 if (cycles == MAX_RETRIES) { 442 debug_msg(npe, "Timeout sending message\n"); 443 return -ETIMEDOUT; 444 } 445 446 #if DEBUG_MSG > 1 447 debug_msg(npe, "Sending a message took %i cycles\n", cycles); 448 #endif 449 return 0; 450 } 451 452 int npe_recv_message(struct npe *npe, void *msg, const char *what) 453 { 454 u32 *recv = msg; 455 int cycles = 0, cnt = 0; 456 457 debug_msg(npe, "Trying to receive message %s\n", what); 458 459 while (cycles < MAX_RETRIES) { 460 if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE) { 461 recv[cnt++] = __raw_readl(&npe->regs->in_out_fifo); 462 if (cnt == 2) 463 break; 464 } else { 465 udelay(1); 466 cycles++; 467 } 468 } 469 470 switch(cnt) { 471 case 1: 472 debug_msg(npe, "Received [%08X]\n", recv[0]); 473 break; 474 case 2: 475 debug_msg(npe, "Received [%08X:%08X]\n", recv[0], recv[1]); 476 break; 477 } 478 479 if (cycles == MAX_RETRIES) { 480 debug_msg(npe, "Timeout waiting for message\n"); 481 return -ETIMEDOUT; 482 } 483 484 #if DEBUG_MSG > 1 485 debug_msg(npe, "Receiving a message took %i cycles\n", cycles); 486 #endif 487 return 0; 488 } 489 490 int npe_send_recv_message(struct npe *npe, void *msg, const char *what) 491 { 492 int result; 493 u32 *send = msg, recv[2]; 494 495 if ((result = npe_send_message(npe, msg, what)) != 0) 496 return result; 497 if ((result = npe_recv_message(npe, recv, what)) != 0) 498 return result; 499 500 if ((recv[0] != send[0]) || (recv[1] != send[1])) { 501 debug_msg(npe, "Message %s: unexpected message received\n", 502 what); 503 return -EIO; 504 } 505 return 0; 506 } 507 508 509 int npe_load_firmware(struct npe *npe, const char *name, struct device *dev) 510 { 511 const struct firmware *fw_entry; 512 513 struct dl_block { 514 u32 type; 515 u32 offset; 516 } *blk; 517 518 struct dl_image { 519 u32 magic; 520 u32 id; 521 u32 size; 522 union { 523 u32 data[0]; 524 struct dl_block blocks[0]; 525 }; 526 } *image; 527 528 struct dl_codeblock { 529 u32 npe_addr; 530 u32 size; 531 u32 data[0]; 532 } *cb; 533 534 int i, j, err, data_size, instr_size, blocks, table_end; 535 u32 cmd; 536 537 if ((err = request_firmware(&fw_entry, name, dev)) != 0) 538 return err; 539 540 err = -EINVAL; 541 if (fw_entry->size < sizeof(struct dl_image)) { 542 print_npe(KERN_ERR, npe, "incomplete firmware file\n"); 543 goto err; 544 } 545 image = (struct dl_image*)fw_entry->data; 546 547 #if DEBUG_FW 548 print_npe(KERN_DEBUG, npe, "firmware: %08X %08X %08X (0x%X bytes)\n", 549 image->magic, image->id, image->size, image->size * 4); 550 #endif 551 552 if (image->magic == swab32(FW_MAGIC)) { /* swapped file */ 553 image->id = swab32(image->id); 554 image->size = swab32(image->size); 555 } else if (image->magic != FW_MAGIC) { 556 print_npe(KERN_ERR, npe, "bad firmware file magic: 0x%X\n", 557 image->magic); 558 goto err; 559 } 560 if ((image->size * 4 + sizeof(struct dl_image)) != fw_entry->size) { 561 print_npe(KERN_ERR, npe, 562 "inconsistent size of firmware file\n"); 563 goto err; 564 } 565 if (((image->id >> 24) & 0xF /* NPE ID */) != npe->id) { 566 print_npe(KERN_ERR, npe, "firmware file NPE ID mismatch\n"); 567 goto err; 568 } 569 if (image->magic == swab32(FW_MAGIC)) 570 for (i = 0; i < image->size; i++) 571 image->data[i] = swab32(image->data[i]); 572 573 if (cpu_is_ixp42x() && ((image->id >> 28) & 0xF /* device ID */)) { 574 print_npe(KERN_INFO, npe, "IXP43x/IXP46x firmware ignored on " 575 "IXP42x\n"); 576 goto err; 577 } 578 579 if (npe_running(npe)) { 580 print_npe(KERN_INFO, npe, "unable to load firmware, NPE is " 581 "already running\n"); 582 err = -EBUSY; 583 goto err; 584 } 585 #if 0 586 npe_stop(npe); 587 npe_reset(npe); 588 #endif 589 590 print_npe(KERN_INFO, npe, "firmware functionality 0x%X, " 591 "revision 0x%X:%X\n", (image->id >> 16) & 0xFF, 592 (image->id >> 8) & 0xFF, image->id & 0xFF); 593 594 if (cpu_is_ixp42x()) { 595 if (!npe->id) 596 instr_size = NPE_A_42X_INSTR_SIZE; 597 else 598 instr_size = NPE_B_AND_C_42X_INSTR_SIZE; 599 data_size = NPE_42X_DATA_SIZE; 600 } else { 601 instr_size = NPE_46X_INSTR_SIZE; 602 data_size = NPE_46X_DATA_SIZE; 603 } 604 605 for (blocks = 0; blocks * sizeof(struct dl_block) / 4 < image->size; 606 blocks++) 607 if (image->blocks[blocks].type == FW_BLOCK_TYPE_EOF) 608 break; 609 if (blocks * sizeof(struct dl_block) / 4 >= image->size) { 610 print_npe(KERN_INFO, npe, "firmware EOF block marker not " 611 "found\n"); 612 goto err; 613 } 614 615 #if DEBUG_FW 616 print_npe(KERN_DEBUG, npe, "%i firmware blocks found\n", blocks); 617 #endif 618 619 table_end = blocks * sizeof(struct dl_block) / 4 + 1 /* EOF marker */; 620 for (i = 0, blk = image->blocks; i < blocks; i++, blk++) { 621 if (blk->offset > image->size - sizeof(struct dl_codeblock) / 4 622 || blk->offset < table_end) { 623 print_npe(KERN_INFO, npe, "invalid offset 0x%X of " 624 "firmware block #%i\n", blk->offset, i); 625 goto err; 626 } 627 628 cb = (struct dl_codeblock*)&image->data[blk->offset]; 629 if (blk->type == FW_BLOCK_TYPE_INSTR) { 630 if (cb->npe_addr + cb->size > instr_size) 631 goto too_big; 632 cmd = CMD_WR_INS_MEM; 633 } else if (blk->type == FW_BLOCK_TYPE_DATA) { 634 if (cb->npe_addr + cb->size > data_size) 635 goto too_big; 636 cmd = CMD_WR_DATA_MEM; 637 } else { 638 print_npe(KERN_INFO, npe, "invalid firmware block #%i " 639 "type 0x%X\n", i, blk->type); 640 goto err; 641 } 642 if (blk->offset + sizeof(*cb) / 4 + cb->size > image->size) { 643 print_npe(KERN_INFO, npe, "firmware block #%i doesn't " 644 "fit in firmware image: type %c, start 0x%X," 645 " length 0x%X\n", i, 646 blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D', 647 cb->npe_addr, cb->size); 648 goto err; 649 } 650 651 for (j = 0; j < cb->size; j++) 652 npe_cmd_write(npe, cb->npe_addr + j, cmd, cb->data[j]); 653 } 654 655 npe_start(npe); 656 if (!npe_running(npe)) 657 print_npe(KERN_ERR, npe, "unable to start\n"); 658 release_firmware(fw_entry); 659 return 0; 660 661 too_big: 662 print_npe(KERN_INFO, npe, "firmware block #%i doesn't fit in NPE " 663 "memory: type %c, start 0x%X, length 0x%X\n", i, 664 blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D', 665 cb->npe_addr, cb->size); 666 err: 667 release_firmware(fw_entry); 668 return err; 669 } 670 671 672 struct npe *npe_request(unsigned id) 673 { 674 if (id < NPE_COUNT) 675 if (npe_tab[id].valid) 676 if (try_module_get(THIS_MODULE)) 677 return &npe_tab[id]; 678 return NULL; 679 } 680 681 void npe_release(struct npe *npe) 682 { 683 module_put(THIS_MODULE); 684 } 685 686 687 static int __init npe_init_module(void) 688 { 689 690 int i, found = 0; 691 692 /* This driver does not work with device tree */ 693 if (of_have_populated_dt()) 694 return -ENODEV; 695 696 for (i = 0; i < NPE_COUNT; i++) { 697 struct npe *npe = &npe_tab[i]; 698 if (!(ixp4xx_read_feature_bits() & 699 (IXP4XX_FEATURE_RESET_NPEA << i))) 700 continue; /* NPE already disabled or not present */ 701 if (!(npe->mem_res = request_mem_region(npe->regs_phys, 702 REGS_SIZE, 703 npe_name(npe)))) { 704 print_npe(KERN_ERR, npe, 705 "failed to request memory region\n"); 706 continue; 707 } 708 709 if (npe_reset(npe)) 710 continue; 711 npe->valid = 1; 712 found++; 713 } 714 715 if (!found) 716 return -ENODEV; 717 return 0; 718 } 719 720 static void __exit npe_cleanup_module(void) 721 { 722 int i; 723 724 for (i = 0; i < NPE_COUNT; i++) 725 if (npe_tab[i].mem_res) { 726 npe_reset(&npe_tab[i]); 727 release_resource(npe_tab[i].mem_res); 728 } 729 } 730 731 module_init(npe_init_module); 732 module_exit(npe_cleanup_module); 733 734 MODULE_AUTHOR("Krzysztof Halasa"); 735 MODULE_LICENSE("GPL v2"); 736 MODULE_FIRMWARE(NPE_A_FIRMWARE); 737 MODULE_FIRMWARE(NPE_B_FIRMWARE); 738 MODULE_FIRMWARE(NPE_C_FIRMWARE); 739 740 EXPORT_SYMBOL(npe_names); 741 EXPORT_SYMBOL(npe_running); 742 EXPORT_SYMBOL(npe_request); 743 EXPORT_SYMBOL(npe_release); 744 EXPORT_SYMBOL(npe_load_firmware); 745 EXPORT_SYMBOL(npe_send_message); 746 EXPORT_SYMBOL(npe_recv_message); 747 EXPORT_SYMBOL(npe_send_recv_message); 748