1 /* 2 * Intel IXP4xx Network Processor Engine driver for Linux 3 * 4 * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License 8 * as published by the Free Software Foundation. 9 * 10 * The code is based on publicly available information: 11 * - Intel IXP4xx Developer's Manual and other e-papers 12 * - Intel IXP400 Access Library Software (BSD license) 13 * - previous works by Christian Hohnstaedt <chohnstaedt@innominate.com> 14 * Thanks, Christian. 15 */ 16 17 #include <linux/delay.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/firmware.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/of.h> 24 #include <linux/platform_device.h> 25 #include <linux/soc/ixp4xx/npe.h> 26 27 #define DEBUG_MSG 0 28 #define DEBUG_FW 0 29 30 #define NPE_COUNT 3 31 #define MAX_RETRIES 1000 /* microseconds */ 32 #define NPE_42X_DATA_SIZE 0x800 /* in dwords */ 33 #define NPE_46X_DATA_SIZE 0x1000 34 #define NPE_A_42X_INSTR_SIZE 0x1000 35 #define NPE_B_AND_C_42X_INSTR_SIZE 0x800 36 #define NPE_46X_INSTR_SIZE 0x1000 37 #define REGS_SIZE 0x1000 38 39 #define NPE_PHYS_REG 32 40 41 #define FW_MAGIC 0xFEEDF00D 42 #define FW_BLOCK_TYPE_INSTR 0x0 43 #define FW_BLOCK_TYPE_DATA 0x1 44 #define FW_BLOCK_TYPE_EOF 0xF 45 46 /* NPE exec status (read) and command (write) */ 47 #define CMD_NPE_STEP 0x01 48 #define CMD_NPE_START 0x02 49 #define CMD_NPE_STOP 0x03 50 #define CMD_NPE_CLR_PIPE 0x04 51 #define CMD_CLR_PROFILE_CNT 0x0C 52 #define CMD_RD_INS_MEM 0x10 /* instruction memory */ 53 #define CMD_WR_INS_MEM 0x11 54 #define CMD_RD_DATA_MEM 0x12 /* data memory */ 55 #define CMD_WR_DATA_MEM 0x13 56 #define CMD_RD_ECS_REG 0x14 /* exec access register */ 57 #define CMD_WR_ECS_REG 0x15 58 59 #define STAT_RUN 0x80000000 60 #define STAT_STOP 0x40000000 61 #define STAT_CLEAR 0x20000000 62 #define STAT_ECS_K 0x00800000 /* pipeline clean */ 63 64 #define NPE_STEVT 0x1B 65 #define NPE_STARTPC 0x1C 66 #define NPE_REGMAP 0x1E 67 #define NPE_CINDEX 0x1F 68 69 #define INSTR_WR_REG_SHORT 0x0000C000 70 #define INSTR_WR_REG_BYTE 0x00004000 71 #define INSTR_RD_FIFO 0x0F888220 72 #define INSTR_RESET_MBOX 0x0FAC8210 73 74 #define ECS_BG_CTXT_REG_0 0x00 /* Background Executing Context */ 75 #define ECS_BG_CTXT_REG_1 0x01 /* Stack level */ 76 #define ECS_BG_CTXT_REG_2 0x02 77 #define ECS_PRI_1_CTXT_REG_0 0x04 /* Priority 1 Executing Context */ 78 #define ECS_PRI_1_CTXT_REG_1 0x05 /* Stack level */ 79 #define ECS_PRI_1_CTXT_REG_2 0x06 80 #define ECS_PRI_2_CTXT_REG_0 0x08 /* Priority 2 Executing Context */ 81 #define ECS_PRI_2_CTXT_REG_1 0x09 /* Stack level */ 82 #define ECS_PRI_2_CTXT_REG_2 0x0A 83 #define ECS_DBG_CTXT_REG_0 0x0C /* Debug Executing Context */ 84 #define ECS_DBG_CTXT_REG_1 0x0D /* Stack level */ 85 #define ECS_DBG_CTXT_REG_2 0x0E 86 #define ECS_INSTRUCT_REG 0x11 /* NPE Instruction Register */ 87 88 #define ECS_REG_0_ACTIVE 0x80000000 /* all levels */ 89 #define ECS_REG_0_NEXTPC_MASK 0x1FFF0000 /* BG/PRI1/PRI2 levels */ 90 #define ECS_REG_0_LDUR_BITS 8 91 #define ECS_REG_0_LDUR_MASK 0x00000700 /* all levels */ 92 #define ECS_REG_1_CCTXT_BITS 16 93 #define ECS_REG_1_CCTXT_MASK 0x000F0000 /* all levels */ 94 #define ECS_REG_1_SELCTXT_BITS 0 95 #define ECS_REG_1_SELCTXT_MASK 0x0000000F /* all levels */ 96 #define ECS_DBG_REG_2_IF 0x00100000 /* debug level */ 97 #define ECS_DBG_REG_2_IE 0x00080000 /* debug level */ 98 99 /* NPE watchpoint_fifo register bit */ 100 #define WFIFO_VALID 0x80000000 101 102 /* NPE messaging_status register bit definitions */ 103 #define MSGSTAT_OFNE 0x00010000 /* OutFifoNotEmpty */ 104 #define MSGSTAT_IFNF 0x00020000 /* InFifoNotFull */ 105 #define MSGSTAT_OFNF 0x00040000 /* OutFifoNotFull */ 106 #define MSGSTAT_IFNE 0x00080000 /* InFifoNotEmpty */ 107 #define MSGSTAT_MBINT 0x00100000 /* Mailbox interrupt */ 108 #define MSGSTAT_IFINT 0x00200000 /* InFifo interrupt */ 109 #define MSGSTAT_OFINT 0x00400000 /* OutFifo interrupt */ 110 #define MSGSTAT_WFINT 0x00800000 /* WatchFifo interrupt */ 111 112 /* NPE messaging_control register bit definitions */ 113 #define MSGCTL_OUT_FIFO 0x00010000 /* enable output FIFO */ 114 #define MSGCTL_IN_FIFO 0x00020000 /* enable input FIFO */ 115 #define MSGCTL_OUT_FIFO_WRITE 0x01000000 /* enable FIFO + WRITE */ 116 #define MSGCTL_IN_FIFO_WRITE 0x02000000 117 118 /* NPE mailbox_status value for reset */ 119 #define RESET_MBOX_STAT 0x0000F0F0 120 121 #define NPE_A_FIRMWARE "NPE-A" 122 #define NPE_B_FIRMWARE "NPE-B" 123 #define NPE_C_FIRMWARE "NPE-C" 124 125 const char *npe_names[] = { NPE_A_FIRMWARE, NPE_B_FIRMWARE, NPE_C_FIRMWARE }; 126 127 #define print_npe(pri, npe, fmt, ...) \ 128 printk(pri "%s: " fmt, npe_name(npe), ## __VA_ARGS__) 129 130 #if DEBUG_MSG 131 #define debug_msg(npe, fmt, ...) \ 132 print_npe(KERN_DEBUG, npe, fmt, ## __VA_ARGS__) 133 #else 134 #define debug_msg(npe, fmt, ...) 135 #endif 136 137 static struct { 138 u32 reg, val; 139 } ecs_reset[] = { 140 { ECS_BG_CTXT_REG_0, 0xA0000000 }, 141 { ECS_BG_CTXT_REG_1, 0x01000000 }, 142 { ECS_BG_CTXT_REG_2, 0x00008000 }, 143 { ECS_PRI_1_CTXT_REG_0, 0x20000080 }, 144 { ECS_PRI_1_CTXT_REG_1, 0x01000000 }, 145 { ECS_PRI_1_CTXT_REG_2, 0x00008000 }, 146 { ECS_PRI_2_CTXT_REG_0, 0x20000080 }, 147 { ECS_PRI_2_CTXT_REG_1, 0x01000000 }, 148 { ECS_PRI_2_CTXT_REG_2, 0x00008000 }, 149 { ECS_DBG_CTXT_REG_0, 0x20000000 }, 150 { ECS_DBG_CTXT_REG_1, 0x00000000 }, 151 { ECS_DBG_CTXT_REG_2, 0x001E0000 }, 152 { ECS_INSTRUCT_REG, 0x1003C00F }, 153 }; 154 155 static struct npe npe_tab[NPE_COUNT] = { 156 { 157 .id = 0, 158 .regs = (struct npe_regs __iomem *)IXP4XX_NPEA_BASE_VIRT, 159 .regs_phys = IXP4XX_NPEA_BASE_PHYS, 160 }, { 161 .id = 1, 162 .regs = (struct npe_regs __iomem *)IXP4XX_NPEB_BASE_VIRT, 163 .regs_phys = IXP4XX_NPEB_BASE_PHYS, 164 }, { 165 .id = 2, 166 .regs = (struct npe_regs __iomem *)IXP4XX_NPEC_BASE_VIRT, 167 .regs_phys = IXP4XX_NPEC_BASE_PHYS, 168 } 169 }; 170 171 int npe_running(struct npe *npe) 172 { 173 return (__raw_readl(&npe->regs->exec_status_cmd) & STAT_RUN) != 0; 174 } 175 176 static void npe_cmd_write(struct npe *npe, u32 addr, int cmd, u32 data) 177 { 178 __raw_writel(data, &npe->regs->exec_data); 179 __raw_writel(addr, &npe->regs->exec_addr); 180 __raw_writel(cmd, &npe->regs->exec_status_cmd); 181 } 182 183 static u32 npe_cmd_read(struct npe *npe, u32 addr, int cmd) 184 { 185 __raw_writel(addr, &npe->regs->exec_addr); 186 __raw_writel(cmd, &npe->regs->exec_status_cmd); 187 /* Iintroduce extra read cycles after issuing read command to NPE 188 so that we read the register after the NPE has updated it. 189 This is to overcome race condition between XScale and NPE */ 190 __raw_readl(&npe->regs->exec_data); 191 __raw_readl(&npe->regs->exec_data); 192 return __raw_readl(&npe->regs->exec_data); 193 } 194 195 static void npe_clear_active(struct npe *npe, u32 reg) 196 { 197 u32 val = npe_cmd_read(npe, reg, CMD_RD_ECS_REG); 198 npe_cmd_write(npe, reg, CMD_WR_ECS_REG, val & ~ECS_REG_0_ACTIVE); 199 } 200 201 static void npe_start(struct npe *npe) 202 { 203 /* ensure only Background Context Stack Level is active */ 204 npe_clear_active(npe, ECS_PRI_1_CTXT_REG_0); 205 npe_clear_active(npe, ECS_PRI_2_CTXT_REG_0); 206 npe_clear_active(npe, ECS_DBG_CTXT_REG_0); 207 208 __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); 209 __raw_writel(CMD_NPE_START, &npe->regs->exec_status_cmd); 210 } 211 212 static void npe_stop(struct npe *npe) 213 { 214 __raw_writel(CMD_NPE_STOP, &npe->regs->exec_status_cmd); 215 __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); /*FIXME?*/ 216 } 217 218 static int __must_check npe_debug_instr(struct npe *npe, u32 instr, u32 ctx, 219 u32 ldur) 220 { 221 u32 wc; 222 int i; 223 224 /* set the Active bit, and the LDUR, in the debug level */ 225 npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG, 226 ECS_REG_0_ACTIVE | (ldur << ECS_REG_0_LDUR_BITS)); 227 228 /* set CCTXT at ECS DEBUG L3 to specify in which context to execute 229 the instruction, and set SELCTXT at ECS DEBUG Level to specify 230 which context store to access. 231 Debug ECS Level Reg 1 has form 0x000n000n, where n = context number 232 */ 233 npe_cmd_write(npe, ECS_DBG_CTXT_REG_1, CMD_WR_ECS_REG, 234 (ctx << ECS_REG_1_CCTXT_BITS) | 235 (ctx << ECS_REG_1_SELCTXT_BITS)); 236 237 /* clear the pipeline */ 238 __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); 239 240 /* load NPE instruction into the instruction register */ 241 npe_cmd_write(npe, ECS_INSTRUCT_REG, CMD_WR_ECS_REG, instr); 242 243 /* we need this value later to wait for completion of NPE execution 244 step */ 245 wc = __raw_readl(&npe->regs->watch_count); 246 247 /* issue a Step One command via the Execution Control register */ 248 __raw_writel(CMD_NPE_STEP, &npe->regs->exec_status_cmd); 249 250 /* Watch Count register increments when NPE completes an instruction */ 251 for (i = 0; i < MAX_RETRIES; i++) { 252 if (wc != __raw_readl(&npe->regs->watch_count)) 253 return 0; 254 udelay(1); 255 } 256 257 print_npe(KERN_ERR, npe, "reset: npe_debug_instr(): timeout\n"); 258 return -ETIMEDOUT; 259 } 260 261 static int __must_check npe_logical_reg_write8(struct npe *npe, u32 addr, 262 u8 val, u32 ctx) 263 { 264 /* here we build the NPE assembler instruction: mov8 d0, #0 */ 265 u32 instr = INSTR_WR_REG_BYTE | /* OpCode */ 266 addr << 9 | /* base Operand */ 267 (val & 0x1F) << 4 | /* lower 5 bits to immediate data */ 268 (val & ~0x1F) << (18 - 5);/* higher 3 bits to CoProc instr. */ 269 return npe_debug_instr(npe, instr, ctx, 1); /* execute it */ 270 } 271 272 static int __must_check npe_logical_reg_write16(struct npe *npe, u32 addr, 273 u16 val, u32 ctx) 274 { 275 /* here we build the NPE assembler instruction: mov16 d0, #0 */ 276 u32 instr = INSTR_WR_REG_SHORT | /* OpCode */ 277 addr << 9 | /* base Operand */ 278 (val & 0x1F) << 4 | /* lower 5 bits to immediate data */ 279 (val & ~0x1F) << (18 - 5);/* higher 11 bits to CoProc instr. */ 280 return npe_debug_instr(npe, instr, ctx, 1); /* execute it */ 281 } 282 283 static int __must_check npe_logical_reg_write32(struct npe *npe, u32 addr, 284 u32 val, u32 ctx) 285 { 286 /* write in 16 bit steps first the high and then the low value */ 287 if (npe_logical_reg_write16(npe, addr, val >> 16, ctx)) 288 return -ETIMEDOUT; 289 return npe_logical_reg_write16(npe, addr + 2, val & 0xFFFF, ctx); 290 } 291 292 static int npe_reset(struct npe *npe) 293 { 294 u32 val, ctl, exec_count, ctx_reg2; 295 int i; 296 297 ctl = (__raw_readl(&npe->regs->messaging_control) | 0x3F000000) & 298 0x3F3FFFFF; 299 300 /* disable parity interrupt */ 301 __raw_writel(ctl & 0x3F00FFFF, &npe->regs->messaging_control); 302 303 /* pre exec - debug instruction */ 304 /* turn off the halt bit by clearing Execution Count register. */ 305 exec_count = __raw_readl(&npe->regs->exec_count); 306 __raw_writel(0, &npe->regs->exec_count); 307 /* ensure that IF and IE are on (temporarily), so that we don't end up 308 stepping forever */ 309 ctx_reg2 = npe_cmd_read(npe, ECS_DBG_CTXT_REG_2, CMD_RD_ECS_REG); 310 npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2 | 311 ECS_DBG_REG_2_IF | ECS_DBG_REG_2_IE); 312 313 /* clear the FIFOs */ 314 while (__raw_readl(&npe->regs->watchpoint_fifo) & WFIFO_VALID) 315 ; 316 while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE) 317 /* read from the outFIFO until empty */ 318 print_npe(KERN_DEBUG, npe, "npe_reset: read FIFO = 0x%X\n", 319 __raw_readl(&npe->regs->in_out_fifo)); 320 321 while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE) 322 /* step execution of the NPE intruction to read inFIFO using 323 the Debug Executing Context stack */ 324 if (npe_debug_instr(npe, INSTR_RD_FIFO, 0, 0)) 325 return -ETIMEDOUT; 326 327 /* reset the mailbox reg from the XScale side */ 328 __raw_writel(RESET_MBOX_STAT, &npe->regs->mailbox_status); 329 /* from NPE side */ 330 if (npe_debug_instr(npe, INSTR_RESET_MBOX, 0, 0)) 331 return -ETIMEDOUT; 332 333 /* Reset the physical registers in the NPE register file */ 334 for (val = 0; val < NPE_PHYS_REG; val++) { 335 if (npe_logical_reg_write16(npe, NPE_REGMAP, val >> 1, 0)) 336 return -ETIMEDOUT; 337 /* address is either 0 or 4 */ 338 if (npe_logical_reg_write32(npe, (val & 1) * 4, 0, 0)) 339 return -ETIMEDOUT; 340 } 341 342 /* Reset the context store = each context's Context Store registers */ 343 344 /* Context 0 has no STARTPC. Instead, this value is used to set NextPC 345 for Background ECS, to set where NPE starts executing code */ 346 val = npe_cmd_read(npe, ECS_BG_CTXT_REG_0, CMD_RD_ECS_REG); 347 val &= ~ECS_REG_0_NEXTPC_MASK; 348 val |= (0 /* NextPC */ << 16) & ECS_REG_0_NEXTPC_MASK; 349 npe_cmd_write(npe, ECS_BG_CTXT_REG_0, CMD_WR_ECS_REG, val); 350 351 for (i = 0; i < 16; i++) { 352 if (i) { /* Context 0 has no STEVT nor STARTPC */ 353 /* STEVT = off, 0x80 */ 354 if (npe_logical_reg_write8(npe, NPE_STEVT, 0x80, i)) 355 return -ETIMEDOUT; 356 if (npe_logical_reg_write16(npe, NPE_STARTPC, 0, i)) 357 return -ETIMEDOUT; 358 } 359 /* REGMAP = d0->p0, d8->p2, d16->p4 */ 360 if (npe_logical_reg_write16(npe, NPE_REGMAP, 0x820, i)) 361 return -ETIMEDOUT; 362 if (npe_logical_reg_write8(npe, NPE_CINDEX, 0, i)) 363 return -ETIMEDOUT; 364 } 365 366 /* post exec */ 367 /* clear active bit in debug level */ 368 npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG, 0); 369 /* clear the pipeline */ 370 __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); 371 /* restore previous values */ 372 __raw_writel(exec_count, &npe->regs->exec_count); 373 npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2); 374 375 /* write reset values to Execution Context Stack registers */ 376 for (val = 0; val < ARRAY_SIZE(ecs_reset); val++) 377 npe_cmd_write(npe, ecs_reset[val].reg, CMD_WR_ECS_REG, 378 ecs_reset[val].val); 379 380 /* clear the profile counter */ 381 __raw_writel(CMD_CLR_PROFILE_CNT, &npe->regs->exec_status_cmd); 382 383 __raw_writel(0, &npe->regs->exec_count); 384 __raw_writel(0, &npe->regs->action_points[0]); 385 __raw_writel(0, &npe->regs->action_points[1]); 386 __raw_writel(0, &npe->regs->action_points[2]); 387 __raw_writel(0, &npe->regs->action_points[3]); 388 __raw_writel(0, &npe->regs->watch_count); 389 390 val = ixp4xx_read_feature_bits(); 391 /* reset the NPE */ 392 ixp4xx_write_feature_bits(val & 393 ~(IXP4XX_FEATURE_RESET_NPEA << npe->id)); 394 /* deassert reset */ 395 ixp4xx_write_feature_bits(val | 396 (IXP4XX_FEATURE_RESET_NPEA << npe->id)); 397 for (i = 0; i < MAX_RETRIES; i++) { 398 if (ixp4xx_read_feature_bits() & 399 (IXP4XX_FEATURE_RESET_NPEA << npe->id)) 400 break; /* NPE is back alive */ 401 udelay(1); 402 } 403 if (i == MAX_RETRIES) 404 return -ETIMEDOUT; 405 406 npe_stop(npe); 407 408 /* restore NPE configuration bus Control Register - parity settings */ 409 __raw_writel(ctl, &npe->regs->messaging_control); 410 return 0; 411 } 412 413 414 int npe_send_message(struct npe *npe, const void *msg, const char *what) 415 { 416 const u32 *send = msg; 417 int cycles = 0; 418 419 debug_msg(npe, "Trying to send message %s [%08X:%08X]\n", 420 what, send[0], send[1]); 421 422 if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE) { 423 debug_msg(npe, "NPE input FIFO not empty\n"); 424 return -EIO; 425 } 426 427 __raw_writel(send[0], &npe->regs->in_out_fifo); 428 429 if (!(__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNF)) { 430 debug_msg(npe, "NPE input FIFO full\n"); 431 return -EIO; 432 } 433 434 __raw_writel(send[1], &npe->regs->in_out_fifo); 435 436 while ((cycles < MAX_RETRIES) && 437 (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)) { 438 udelay(1); 439 cycles++; 440 } 441 442 if (cycles == MAX_RETRIES) { 443 debug_msg(npe, "Timeout sending message\n"); 444 return -ETIMEDOUT; 445 } 446 447 #if DEBUG_MSG > 1 448 debug_msg(npe, "Sending a message took %i cycles\n", cycles); 449 #endif 450 return 0; 451 } 452 453 int npe_recv_message(struct npe *npe, void *msg, const char *what) 454 { 455 u32 *recv = msg; 456 int cycles = 0, cnt = 0; 457 458 debug_msg(npe, "Trying to receive message %s\n", what); 459 460 while (cycles < MAX_RETRIES) { 461 if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE) { 462 recv[cnt++] = __raw_readl(&npe->regs->in_out_fifo); 463 if (cnt == 2) 464 break; 465 } else { 466 udelay(1); 467 cycles++; 468 } 469 } 470 471 switch(cnt) { 472 case 1: 473 debug_msg(npe, "Received [%08X]\n", recv[0]); 474 break; 475 case 2: 476 debug_msg(npe, "Received [%08X:%08X]\n", recv[0], recv[1]); 477 break; 478 } 479 480 if (cycles == MAX_RETRIES) { 481 debug_msg(npe, "Timeout waiting for message\n"); 482 return -ETIMEDOUT; 483 } 484 485 #if DEBUG_MSG > 1 486 debug_msg(npe, "Receiving a message took %i cycles\n", cycles); 487 #endif 488 return 0; 489 } 490 491 int npe_send_recv_message(struct npe *npe, void *msg, const char *what) 492 { 493 int result; 494 u32 *send = msg, recv[2]; 495 496 if ((result = npe_send_message(npe, msg, what)) != 0) 497 return result; 498 if ((result = npe_recv_message(npe, recv, what)) != 0) 499 return result; 500 501 if ((recv[0] != send[0]) || (recv[1] != send[1])) { 502 debug_msg(npe, "Message %s: unexpected message received\n", 503 what); 504 return -EIO; 505 } 506 return 0; 507 } 508 509 510 int npe_load_firmware(struct npe *npe, const char *name, struct device *dev) 511 { 512 const struct firmware *fw_entry; 513 514 struct dl_block { 515 u32 type; 516 u32 offset; 517 } *blk; 518 519 struct dl_image { 520 u32 magic; 521 u32 id; 522 u32 size; 523 union { 524 u32 data[0]; 525 struct dl_block blocks[0]; 526 }; 527 } *image; 528 529 struct dl_codeblock { 530 u32 npe_addr; 531 u32 size; 532 u32 data[0]; 533 } *cb; 534 535 int i, j, err, data_size, instr_size, blocks, table_end; 536 u32 cmd; 537 538 if ((err = request_firmware(&fw_entry, name, dev)) != 0) 539 return err; 540 541 err = -EINVAL; 542 if (fw_entry->size < sizeof(struct dl_image)) { 543 print_npe(KERN_ERR, npe, "incomplete firmware file\n"); 544 goto err; 545 } 546 image = (struct dl_image*)fw_entry->data; 547 548 #if DEBUG_FW 549 print_npe(KERN_DEBUG, npe, "firmware: %08X %08X %08X (0x%X bytes)\n", 550 image->magic, image->id, image->size, image->size * 4); 551 #endif 552 553 if (image->magic == swab32(FW_MAGIC)) { /* swapped file */ 554 image->id = swab32(image->id); 555 image->size = swab32(image->size); 556 } else if (image->magic != FW_MAGIC) { 557 print_npe(KERN_ERR, npe, "bad firmware file magic: 0x%X\n", 558 image->magic); 559 goto err; 560 } 561 if ((image->size * 4 + sizeof(struct dl_image)) != fw_entry->size) { 562 print_npe(KERN_ERR, npe, 563 "inconsistent size of firmware file\n"); 564 goto err; 565 } 566 if (((image->id >> 24) & 0xF /* NPE ID */) != npe->id) { 567 print_npe(KERN_ERR, npe, "firmware file NPE ID mismatch\n"); 568 goto err; 569 } 570 if (image->magic == swab32(FW_MAGIC)) 571 for (i = 0; i < image->size; i++) 572 image->data[i] = swab32(image->data[i]); 573 574 if (cpu_is_ixp42x() && ((image->id >> 28) & 0xF /* device ID */)) { 575 print_npe(KERN_INFO, npe, "IXP43x/IXP46x firmware ignored on " 576 "IXP42x\n"); 577 goto err; 578 } 579 580 if (npe_running(npe)) { 581 print_npe(KERN_INFO, npe, "unable to load firmware, NPE is " 582 "already running\n"); 583 err = -EBUSY; 584 goto err; 585 } 586 #if 0 587 npe_stop(npe); 588 npe_reset(npe); 589 #endif 590 591 print_npe(KERN_INFO, npe, "firmware functionality 0x%X, " 592 "revision 0x%X:%X\n", (image->id >> 16) & 0xFF, 593 (image->id >> 8) & 0xFF, image->id & 0xFF); 594 595 if (cpu_is_ixp42x()) { 596 if (!npe->id) 597 instr_size = NPE_A_42X_INSTR_SIZE; 598 else 599 instr_size = NPE_B_AND_C_42X_INSTR_SIZE; 600 data_size = NPE_42X_DATA_SIZE; 601 } else { 602 instr_size = NPE_46X_INSTR_SIZE; 603 data_size = NPE_46X_DATA_SIZE; 604 } 605 606 for (blocks = 0; blocks * sizeof(struct dl_block) / 4 < image->size; 607 blocks++) 608 if (image->blocks[blocks].type == FW_BLOCK_TYPE_EOF) 609 break; 610 if (blocks * sizeof(struct dl_block) / 4 >= image->size) { 611 print_npe(KERN_INFO, npe, "firmware EOF block marker not " 612 "found\n"); 613 goto err; 614 } 615 616 #if DEBUG_FW 617 print_npe(KERN_DEBUG, npe, "%i firmware blocks found\n", blocks); 618 #endif 619 620 table_end = blocks * sizeof(struct dl_block) / 4 + 1 /* EOF marker */; 621 for (i = 0, blk = image->blocks; i < blocks; i++, blk++) { 622 if (blk->offset > image->size - sizeof(struct dl_codeblock) / 4 623 || blk->offset < table_end) { 624 print_npe(KERN_INFO, npe, "invalid offset 0x%X of " 625 "firmware block #%i\n", blk->offset, i); 626 goto err; 627 } 628 629 cb = (struct dl_codeblock*)&image->data[blk->offset]; 630 if (blk->type == FW_BLOCK_TYPE_INSTR) { 631 if (cb->npe_addr + cb->size > instr_size) 632 goto too_big; 633 cmd = CMD_WR_INS_MEM; 634 } else if (blk->type == FW_BLOCK_TYPE_DATA) { 635 if (cb->npe_addr + cb->size > data_size) 636 goto too_big; 637 cmd = CMD_WR_DATA_MEM; 638 } else { 639 print_npe(KERN_INFO, npe, "invalid firmware block #%i " 640 "type 0x%X\n", i, blk->type); 641 goto err; 642 } 643 if (blk->offset + sizeof(*cb) / 4 + cb->size > image->size) { 644 print_npe(KERN_INFO, npe, "firmware block #%i doesn't " 645 "fit in firmware image: type %c, start 0x%X," 646 " length 0x%X\n", i, 647 blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D', 648 cb->npe_addr, cb->size); 649 goto err; 650 } 651 652 for (j = 0; j < cb->size; j++) 653 npe_cmd_write(npe, cb->npe_addr + j, cmd, cb->data[j]); 654 } 655 656 npe_start(npe); 657 if (!npe_running(npe)) 658 print_npe(KERN_ERR, npe, "unable to start\n"); 659 release_firmware(fw_entry); 660 return 0; 661 662 too_big: 663 print_npe(KERN_INFO, npe, "firmware block #%i doesn't fit in NPE " 664 "memory: type %c, start 0x%X, length 0x%X\n", i, 665 blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D', 666 cb->npe_addr, cb->size); 667 err: 668 release_firmware(fw_entry); 669 return err; 670 } 671 672 673 struct npe *npe_request(unsigned id) 674 { 675 if (id < NPE_COUNT) 676 if (npe_tab[id].valid) 677 if (try_module_get(THIS_MODULE)) 678 return &npe_tab[id]; 679 return NULL; 680 } 681 682 void npe_release(struct npe *npe) 683 { 684 module_put(THIS_MODULE); 685 } 686 687 static int ixp4xx_npe_probe(struct platform_device *pdev) 688 { 689 int i, found = 0; 690 691 for (i = 0; i < NPE_COUNT; i++) { 692 struct npe *npe = &npe_tab[i]; 693 if (!(ixp4xx_read_feature_bits() & 694 (IXP4XX_FEATURE_RESET_NPEA << i))) 695 continue; /* NPE already disabled or not present */ 696 if (!(npe->mem_res = request_mem_region(npe->regs_phys, 697 REGS_SIZE, 698 npe_name(npe)))) { 699 print_npe(KERN_ERR, npe, 700 "failed to request memory region\n"); 701 continue; 702 } 703 704 if (npe_reset(npe)) 705 continue; 706 npe->valid = 1; 707 found++; 708 } 709 710 if (!found) 711 return -ENODEV; 712 return 0; 713 } 714 715 static int ixp4xx_npe_remove(struct platform_device *pdev) 716 { 717 int i; 718 719 for (i = 0; i < NPE_COUNT; i++) 720 if (npe_tab[i].mem_res) { 721 npe_reset(&npe_tab[i]); 722 release_resource(npe_tab[i].mem_res); 723 } 724 725 return 0; 726 } 727 728 static struct platform_driver ixp4xx_npe_driver = { 729 .driver = { 730 .name = "ixp4xx-npe", 731 }, 732 .probe = ixp4xx_npe_probe, 733 .remove = ixp4xx_npe_remove, 734 }; 735 module_platform_driver(ixp4xx_npe_driver); 736 737 MODULE_AUTHOR("Krzysztof Halasa"); 738 MODULE_LICENSE("GPL v2"); 739 MODULE_FIRMWARE(NPE_A_FIRMWARE); 740 MODULE_FIRMWARE(NPE_B_FIRMWARE); 741 MODULE_FIRMWARE(NPE_C_FIRMWARE); 742 743 EXPORT_SYMBOL(npe_names); 744 EXPORT_SYMBOL(npe_running); 745 EXPORT_SYMBOL(npe_request); 746 EXPORT_SYMBOL(npe_release); 747 EXPORT_SYMBOL(npe_load_firmware); 748 EXPORT_SYMBOL(npe_send_message); 749 EXPORT_SYMBOL(npe_recv_message); 750 EXPORT_SYMBOL(npe_send_recv_message); 751