1eace21faSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2fcf2d897SLinus Walleij /* 3fcf2d897SLinus Walleij * Intel IXP4xx Network Processor Engine driver for Linux 4fcf2d897SLinus Walleij * 5fcf2d897SLinus Walleij * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl> 6fcf2d897SLinus Walleij * 7fcf2d897SLinus Walleij * The code is based on publicly available information: 8fcf2d897SLinus Walleij * - Intel IXP4xx Developer's Manual and other e-papers 9fcf2d897SLinus Walleij * - Intel IXP400 Access Library Software (BSD license) 10fcf2d897SLinus Walleij * - previous works by Christian Hohnstaedt <chohnstaedt@innominate.com> 11fcf2d897SLinus Walleij * Thanks, Christian. 12fcf2d897SLinus Walleij */ 13fcf2d897SLinus Walleij 14fcf2d897SLinus Walleij #include <linux/delay.h> 15fcf2d897SLinus Walleij #include <linux/dma-mapping.h> 16fcf2d897SLinus Walleij #include <linux/firmware.h> 17fcf2d897SLinus Walleij #include <linux/io.h> 18fcf2d897SLinus Walleij #include <linux/kernel.h> 19fcf2d897SLinus Walleij #include <linux/module.h> 20fcf2d897SLinus Walleij #include <linux/of.h> 21bc4d7eafSLinus Walleij #include <linux/platform_device.h> 224af20dc5SLinus Walleij #include <linux/soc/ixp4xx/npe.h> 23fcf2d897SLinus Walleij 24fcf2d897SLinus Walleij #define DEBUG_MSG 0 25fcf2d897SLinus Walleij #define DEBUG_FW 0 26fcf2d897SLinus Walleij 27fcf2d897SLinus Walleij #define NPE_COUNT 3 28fcf2d897SLinus Walleij #define MAX_RETRIES 1000 /* microseconds */ 29fcf2d897SLinus Walleij #define NPE_42X_DATA_SIZE 0x800 /* in dwords */ 30fcf2d897SLinus Walleij #define NPE_46X_DATA_SIZE 0x1000 31fcf2d897SLinus Walleij #define NPE_A_42X_INSTR_SIZE 0x1000 32fcf2d897SLinus Walleij #define NPE_B_AND_C_42X_INSTR_SIZE 0x800 33fcf2d897SLinus Walleij #define NPE_46X_INSTR_SIZE 0x1000 34fcf2d897SLinus Walleij #define REGS_SIZE 0x1000 35fcf2d897SLinus Walleij 36fcf2d897SLinus Walleij #define NPE_PHYS_REG 32 37fcf2d897SLinus Walleij 38fcf2d897SLinus Walleij #define FW_MAGIC 0xFEEDF00D 39fcf2d897SLinus Walleij #define FW_BLOCK_TYPE_INSTR 0x0 40fcf2d897SLinus Walleij #define FW_BLOCK_TYPE_DATA 0x1 41fcf2d897SLinus Walleij #define FW_BLOCK_TYPE_EOF 0xF 42fcf2d897SLinus Walleij 43fcf2d897SLinus Walleij /* NPE exec status (read) and command (write) */ 44fcf2d897SLinus Walleij #define CMD_NPE_STEP 0x01 45fcf2d897SLinus Walleij #define CMD_NPE_START 0x02 46fcf2d897SLinus Walleij #define CMD_NPE_STOP 0x03 47fcf2d897SLinus Walleij #define CMD_NPE_CLR_PIPE 0x04 48fcf2d897SLinus Walleij #define CMD_CLR_PROFILE_CNT 0x0C 49fcf2d897SLinus Walleij #define CMD_RD_INS_MEM 0x10 /* instruction memory */ 50fcf2d897SLinus Walleij #define CMD_WR_INS_MEM 0x11 51fcf2d897SLinus Walleij #define CMD_RD_DATA_MEM 0x12 /* data memory */ 52fcf2d897SLinus Walleij #define CMD_WR_DATA_MEM 0x13 53fcf2d897SLinus Walleij #define CMD_RD_ECS_REG 0x14 /* exec access register */ 54fcf2d897SLinus Walleij #define CMD_WR_ECS_REG 0x15 55fcf2d897SLinus Walleij 56fcf2d897SLinus Walleij #define STAT_RUN 0x80000000 57fcf2d897SLinus Walleij #define STAT_STOP 0x40000000 58fcf2d897SLinus Walleij #define STAT_CLEAR 0x20000000 59fcf2d897SLinus Walleij #define STAT_ECS_K 0x00800000 /* pipeline clean */ 60fcf2d897SLinus Walleij 61fcf2d897SLinus Walleij #define NPE_STEVT 0x1B 62fcf2d897SLinus Walleij #define NPE_STARTPC 0x1C 63fcf2d897SLinus Walleij #define NPE_REGMAP 0x1E 64fcf2d897SLinus Walleij #define NPE_CINDEX 0x1F 65fcf2d897SLinus Walleij 66fcf2d897SLinus Walleij #define INSTR_WR_REG_SHORT 0x0000C000 67fcf2d897SLinus Walleij #define INSTR_WR_REG_BYTE 0x00004000 68fcf2d897SLinus Walleij #define INSTR_RD_FIFO 0x0F888220 69fcf2d897SLinus Walleij #define INSTR_RESET_MBOX 0x0FAC8210 70fcf2d897SLinus Walleij 71fcf2d897SLinus Walleij #define ECS_BG_CTXT_REG_0 0x00 /* Background Executing Context */ 72fcf2d897SLinus Walleij #define ECS_BG_CTXT_REG_1 0x01 /* Stack level */ 73fcf2d897SLinus Walleij #define ECS_BG_CTXT_REG_2 0x02 74fcf2d897SLinus Walleij #define ECS_PRI_1_CTXT_REG_0 0x04 /* Priority 1 Executing Context */ 75fcf2d897SLinus Walleij #define ECS_PRI_1_CTXT_REG_1 0x05 /* Stack level */ 76fcf2d897SLinus Walleij #define ECS_PRI_1_CTXT_REG_2 0x06 77fcf2d897SLinus Walleij #define ECS_PRI_2_CTXT_REG_0 0x08 /* Priority 2 Executing Context */ 78fcf2d897SLinus Walleij #define ECS_PRI_2_CTXT_REG_1 0x09 /* Stack level */ 79fcf2d897SLinus Walleij #define ECS_PRI_2_CTXT_REG_2 0x0A 80fcf2d897SLinus Walleij #define ECS_DBG_CTXT_REG_0 0x0C /* Debug Executing Context */ 81fcf2d897SLinus Walleij #define ECS_DBG_CTXT_REG_1 0x0D /* Stack level */ 82fcf2d897SLinus Walleij #define ECS_DBG_CTXT_REG_2 0x0E 83fcf2d897SLinus Walleij #define ECS_INSTRUCT_REG 0x11 /* NPE Instruction Register */ 84fcf2d897SLinus Walleij 85fcf2d897SLinus Walleij #define ECS_REG_0_ACTIVE 0x80000000 /* all levels */ 86fcf2d897SLinus Walleij #define ECS_REG_0_NEXTPC_MASK 0x1FFF0000 /* BG/PRI1/PRI2 levels */ 87fcf2d897SLinus Walleij #define ECS_REG_0_LDUR_BITS 8 88fcf2d897SLinus Walleij #define ECS_REG_0_LDUR_MASK 0x00000700 /* all levels */ 89fcf2d897SLinus Walleij #define ECS_REG_1_CCTXT_BITS 16 90fcf2d897SLinus Walleij #define ECS_REG_1_CCTXT_MASK 0x000F0000 /* all levels */ 91fcf2d897SLinus Walleij #define ECS_REG_1_SELCTXT_BITS 0 92fcf2d897SLinus Walleij #define ECS_REG_1_SELCTXT_MASK 0x0000000F /* all levels */ 93fcf2d897SLinus Walleij #define ECS_DBG_REG_2_IF 0x00100000 /* debug level */ 94fcf2d897SLinus Walleij #define ECS_DBG_REG_2_IE 0x00080000 /* debug level */ 95fcf2d897SLinus Walleij 96fcf2d897SLinus Walleij /* NPE watchpoint_fifo register bit */ 97fcf2d897SLinus Walleij #define WFIFO_VALID 0x80000000 98fcf2d897SLinus Walleij 99fcf2d897SLinus Walleij /* NPE messaging_status register bit definitions */ 100fcf2d897SLinus Walleij #define MSGSTAT_OFNE 0x00010000 /* OutFifoNotEmpty */ 101fcf2d897SLinus Walleij #define MSGSTAT_IFNF 0x00020000 /* InFifoNotFull */ 102fcf2d897SLinus Walleij #define MSGSTAT_OFNF 0x00040000 /* OutFifoNotFull */ 103fcf2d897SLinus Walleij #define MSGSTAT_IFNE 0x00080000 /* InFifoNotEmpty */ 104fcf2d897SLinus Walleij #define MSGSTAT_MBINT 0x00100000 /* Mailbox interrupt */ 105fcf2d897SLinus Walleij #define MSGSTAT_IFINT 0x00200000 /* InFifo interrupt */ 106fcf2d897SLinus Walleij #define MSGSTAT_OFINT 0x00400000 /* OutFifo interrupt */ 107fcf2d897SLinus Walleij #define MSGSTAT_WFINT 0x00800000 /* WatchFifo interrupt */ 108fcf2d897SLinus Walleij 109fcf2d897SLinus Walleij /* NPE messaging_control register bit definitions */ 110fcf2d897SLinus Walleij #define MSGCTL_OUT_FIFO 0x00010000 /* enable output FIFO */ 111fcf2d897SLinus Walleij #define MSGCTL_IN_FIFO 0x00020000 /* enable input FIFO */ 112fcf2d897SLinus Walleij #define MSGCTL_OUT_FIFO_WRITE 0x01000000 /* enable FIFO + WRITE */ 113fcf2d897SLinus Walleij #define MSGCTL_IN_FIFO_WRITE 0x02000000 114fcf2d897SLinus Walleij 115fcf2d897SLinus Walleij /* NPE mailbox_status value for reset */ 116fcf2d897SLinus Walleij #define RESET_MBOX_STAT 0x0000F0F0 117fcf2d897SLinus Walleij 118fcf2d897SLinus Walleij #define NPE_A_FIRMWARE "NPE-A" 119fcf2d897SLinus Walleij #define NPE_B_FIRMWARE "NPE-B" 120fcf2d897SLinus Walleij #define NPE_C_FIRMWARE "NPE-C" 121fcf2d897SLinus Walleij 122fcf2d897SLinus Walleij const char *npe_names[] = { NPE_A_FIRMWARE, NPE_B_FIRMWARE, NPE_C_FIRMWARE }; 123fcf2d897SLinus Walleij 124fcf2d897SLinus Walleij #define print_npe(pri, npe, fmt, ...) \ 125fcf2d897SLinus Walleij printk(pri "%s: " fmt, npe_name(npe), ## __VA_ARGS__) 126fcf2d897SLinus Walleij 127fcf2d897SLinus Walleij #if DEBUG_MSG 128fcf2d897SLinus Walleij #define debug_msg(npe, fmt, ...) \ 129fcf2d897SLinus Walleij print_npe(KERN_DEBUG, npe, fmt, ## __VA_ARGS__) 130fcf2d897SLinus Walleij #else 131fcf2d897SLinus Walleij #define debug_msg(npe, fmt, ...) 132fcf2d897SLinus Walleij #endif 133fcf2d897SLinus Walleij 134fcf2d897SLinus Walleij static struct { 135fcf2d897SLinus Walleij u32 reg, val; 136fcf2d897SLinus Walleij } ecs_reset[] = { 137fcf2d897SLinus Walleij { ECS_BG_CTXT_REG_0, 0xA0000000 }, 138fcf2d897SLinus Walleij { ECS_BG_CTXT_REG_1, 0x01000000 }, 139fcf2d897SLinus Walleij { ECS_BG_CTXT_REG_2, 0x00008000 }, 140fcf2d897SLinus Walleij { ECS_PRI_1_CTXT_REG_0, 0x20000080 }, 141fcf2d897SLinus Walleij { ECS_PRI_1_CTXT_REG_1, 0x01000000 }, 142fcf2d897SLinus Walleij { ECS_PRI_1_CTXT_REG_2, 0x00008000 }, 143fcf2d897SLinus Walleij { ECS_PRI_2_CTXT_REG_0, 0x20000080 }, 144fcf2d897SLinus Walleij { ECS_PRI_2_CTXT_REG_1, 0x01000000 }, 145fcf2d897SLinus Walleij { ECS_PRI_2_CTXT_REG_2, 0x00008000 }, 146fcf2d897SLinus Walleij { ECS_DBG_CTXT_REG_0, 0x20000000 }, 147fcf2d897SLinus Walleij { ECS_DBG_CTXT_REG_1, 0x00000000 }, 148fcf2d897SLinus Walleij { ECS_DBG_CTXT_REG_2, 0x001E0000 }, 149fcf2d897SLinus Walleij { ECS_INSTRUCT_REG, 0x1003C00F }, 150fcf2d897SLinus Walleij }; 151fcf2d897SLinus Walleij 152fcf2d897SLinus Walleij static struct npe npe_tab[NPE_COUNT] = { 153fcf2d897SLinus Walleij { 154fcf2d897SLinus Walleij .id = 0, 155fcf2d897SLinus Walleij }, { 156fcf2d897SLinus Walleij .id = 1, 157fcf2d897SLinus Walleij }, { 158fcf2d897SLinus Walleij .id = 2, 159fcf2d897SLinus Walleij } 160fcf2d897SLinus Walleij }; 161fcf2d897SLinus Walleij 162fcf2d897SLinus Walleij int npe_running(struct npe *npe) 163fcf2d897SLinus Walleij { 164fcf2d897SLinus Walleij return (__raw_readl(&npe->regs->exec_status_cmd) & STAT_RUN) != 0; 165fcf2d897SLinus Walleij } 166fcf2d897SLinus Walleij 167fcf2d897SLinus Walleij static void npe_cmd_write(struct npe *npe, u32 addr, int cmd, u32 data) 168fcf2d897SLinus Walleij { 169fcf2d897SLinus Walleij __raw_writel(data, &npe->regs->exec_data); 170fcf2d897SLinus Walleij __raw_writel(addr, &npe->regs->exec_addr); 171fcf2d897SLinus Walleij __raw_writel(cmd, &npe->regs->exec_status_cmd); 172fcf2d897SLinus Walleij } 173fcf2d897SLinus Walleij 174fcf2d897SLinus Walleij static u32 npe_cmd_read(struct npe *npe, u32 addr, int cmd) 175fcf2d897SLinus Walleij { 176fcf2d897SLinus Walleij __raw_writel(addr, &npe->regs->exec_addr); 177fcf2d897SLinus Walleij __raw_writel(cmd, &npe->regs->exec_status_cmd); 178fcf2d897SLinus Walleij /* Iintroduce extra read cycles after issuing read command to NPE 179fcf2d897SLinus Walleij so that we read the register after the NPE has updated it. 180fcf2d897SLinus Walleij This is to overcome race condition between XScale and NPE */ 181fcf2d897SLinus Walleij __raw_readl(&npe->regs->exec_data); 182fcf2d897SLinus Walleij __raw_readl(&npe->regs->exec_data); 183fcf2d897SLinus Walleij return __raw_readl(&npe->regs->exec_data); 184fcf2d897SLinus Walleij } 185fcf2d897SLinus Walleij 186fcf2d897SLinus Walleij static void npe_clear_active(struct npe *npe, u32 reg) 187fcf2d897SLinus Walleij { 188fcf2d897SLinus Walleij u32 val = npe_cmd_read(npe, reg, CMD_RD_ECS_REG); 189fcf2d897SLinus Walleij npe_cmd_write(npe, reg, CMD_WR_ECS_REG, val & ~ECS_REG_0_ACTIVE); 190fcf2d897SLinus Walleij } 191fcf2d897SLinus Walleij 192fcf2d897SLinus Walleij static void npe_start(struct npe *npe) 193fcf2d897SLinus Walleij { 194fcf2d897SLinus Walleij /* ensure only Background Context Stack Level is active */ 195fcf2d897SLinus Walleij npe_clear_active(npe, ECS_PRI_1_CTXT_REG_0); 196fcf2d897SLinus Walleij npe_clear_active(npe, ECS_PRI_2_CTXT_REG_0); 197fcf2d897SLinus Walleij npe_clear_active(npe, ECS_DBG_CTXT_REG_0); 198fcf2d897SLinus Walleij 199fcf2d897SLinus Walleij __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); 200fcf2d897SLinus Walleij __raw_writel(CMD_NPE_START, &npe->regs->exec_status_cmd); 201fcf2d897SLinus Walleij } 202fcf2d897SLinus Walleij 203fcf2d897SLinus Walleij static void npe_stop(struct npe *npe) 204fcf2d897SLinus Walleij { 205fcf2d897SLinus Walleij __raw_writel(CMD_NPE_STOP, &npe->regs->exec_status_cmd); 206fcf2d897SLinus Walleij __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); /*FIXME?*/ 207fcf2d897SLinus Walleij } 208fcf2d897SLinus Walleij 209fcf2d897SLinus Walleij static int __must_check npe_debug_instr(struct npe *npe, u32 instr, u32 ctx, 210fcf2d897SLinus Walleij u32 ldur) 211fcf2d897SLinus Walleij { 212fcf2d897SLinus Walleij u32 wc; 213fcf2d897SLinus Walleij int i; 214fcf2d897SLinus Walleij 215fcf2d897SLinus Walleij /* set the Active bit, and the LDUR, in the debug level */ 216fcf2d897SLinus Walleij npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG, 217fcf2d897SLinus Walleij ECS_REG_0_ACTIVE | (ldur << ECS_REG_0_LDUR_BITS)); 218fcf2d897SLinus Walleij 219fcf2d897SLinus Walleij /* set CCTXT at ECS DEBUG L3 to specify in which context to execute 220fcf2d897SLinus Walleij the instruction, and set SELCTXT at ECS DEBUG Level to specify 221fcf2d897SLinus Walleij which context store to access. 222fcf2d897SLinus Walleij Debug ECS Level Reg 1 has form 0x000n000n, where n = context number 223fcf2d897SLinus Walleij */ 224fcf2d897SLinus Walleij npe_cmd_write(npe, ECS_DBG_CTXT_REG_1, CMD_WR_ECS_REG, 225fcf2d897SLinus Walleij (ctx << ECS_REG_1_CCTXT_BITS) | 226fcf2d897SLinus Walleij (ctx << ECS_REG_1_SELCTXT_BITS)); 227fcf2d897SLinus Walleij 228fcf2d897SLinus Walleij /* clear the pipeline */ 229fcf2d897SLinus Walleij __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); 230fcf2d897SLinus Walleij 231fcf2d897SLinus Walleij /* load NPE instruction into the instruction register */ 232fcf2d897SLinus Walleij npe_cmd_write(npe, ECS_INSTRUCT_REG, CMD_WR_ECS_REG, instr); 233fcf2d897SLinus Walleij 234fcf2d897SLinus Walleij /* we need this value later to wait for completion of NPE execution 235fcf2d897SLinus Walleij step */ 236fcf2d897SLinus Walleij wc = __raw_readl(&npe->regs->watch_count); 237fcf2d897SLinus Walleij 238fcf2d897SLinus Walleij /* issue a Step One command via the Execution Control register */ 239fcf2d897SLinus Walleij __raw_writel(CMD_NPE_STEP, &npe->regs->exec_status_cmd); 240fcf2d897SLinus Walleij 241fcf2d897SLinus Walleij /* Watch Count register increments when NPE completes an instruction */ 242fcf2d897SLinus Walleij for (i = 0; i < MAX_RETRIES; i++) { 243fcf2d897SLinus Walleij if (wc != __raw_readl(&npe->regs->watch_count)) 244fcf2d897SLinus Walleij return 0; 245fcf2d897SLinus Walleij udelay(1); 246fcf2d897SLinus Walleij } 247fcf2d897SLinus Walleij 248fcf2d897SLinus Walleij print_npe(KERN_ERR, npe, "reset: npe_debug_instr(): timeout\n"); 249fcf2d897SLinus Walleij return -ETIMEDOUT; 250fcf2d897SLinus Walleij } 251fcf2d897SLinus Walleij 252fcf2d897SLinus Walleij static int __must_check npe_logical_reg_write8(struct npe *npe, u32 addr, 253fcf2d897SLinus Walleij u8 val, u32 ctx) 254fcf2d897SLinus Walleij { 255fcf2d897SLinus Walleij /* here we build the NPE assembler instruction: mov8 d0, #0 */ 256fcf2d897SLinus Walleij u32 instr = INSTR_WR_REG_BYTE | /* OpCode */ 257fcf2d897SLinus Walleij addr << 9 | /* base Operand */ 258fcf2d897SLinus Walleij (val & 0x1F) << 4 | /* lower 5 bits to immediate data */ 259fcf2d897SLinus Walleij (val & ~0x1F) << (18 - 5);/* higher 3 bits to CoProc instr. */ 260fcf2d897SLinus Walleij return npe_debug_instr(npe, instr, ctx, 1); /* execute it */ 261fcf2d897SLinus Walleij } 262fcf2d897SLinus Walleij 263fcf2d897SLinus Walleij static int __must_check npe_logical_reg_write16(struct npe *npe, u32 addr, 264fcf2d897SLinus Walleij u16 val, u32 ctx) 265fcf2d897SLinus Walleij { 266fcf2d897SLinus Walleij /* here we build the NPE assembler instruction: mov16 d0, #0 */ 267fcf2d897SLinus Walleij u32 instr = INSTR_WR_REG_SHORT | /* OpCode */ 268fcf2d897SLinus Walleij addr << 9 | /* base Operand */ 269fcf2d897SLinus Walleij (val & 0x1F) << 4 | /* lower 5 bits to immediate data */ 270fcf2d897SLinus Walleij (val & ~0x1F) << (18 - 5);/* higher 11 bits to CoProc instr. */ 271fcf2d897SLinus Walleij return npe_debug_instr(npe, instr, ctx, 1); /* execute it */ 272fcf2d897SLinus Walleij } 273fcf2d897SLinus Walleij 274fcf2d897SLinus Walleij static int __must_check npe_logical_reg_write32(struct npe *npe, u32 addr, 275fcf2d897SLinus Walleij u32 val, u32 ctx) 276fcf2d897SLinus Walleij { 277fcf2d897SLinus Walleij /* write in 16 bit steps first the high and then the low value */ 278fcf2d897SLinus Walleij if (npe_logical_reg_write16(npe, addr, val >> 16, ctx)) 279fcf2d897SLinus Walleij return -ETIMEDOUT; 280fcf2d897SLinus Walleij return npe_logical_reg_write16(npe, addr + 2, val & 0xFFFF, ctx); 281fcf2d897SLinus Walleij } 282fcf2d897SLinus Walleij 283fcf2d897SLinus Walleij static int npe_reset(struct npe *npe) 284fcf2d897SLinus Walleij { 285fcf2d897SLinus Walleij u32 val, ctl, exec_count, ctx_reg2; 286fcf2d897SLinus Walleij int i; 287fcf2d897SLinus Walleij 288fcf2d897SLinus Walleij ctl = (__raw_readl(&npe->regs->messaging_control) | 0x3F000000) & 289fcf2d897SLinus Walleij 0x3F3FFFFF; 290fcf2d897SLinus Walleij 291fcf2d897SLinus Walleij /* disable parity interrupt */ 292fcf2d897SLinus Walleij __raw_writel(ctl & 0x3F00FFFF, &npe->regs->messaging_control); 293fcf2d897SLinus Walleij 294fcf2d897SLinus Walleij /* pre exec - debug instruction */ 295fcf2d897SLinus Walleij /* turn off the halt bit by clearing Execution Count register. */ 296fcf2d897SLinus Walleij exec_count = __raw_readl(&npe->regs->exec_count); 297fcf2d897SLinus Walleij __raw_writel(0, &npe->regs->exec_count); 298fcf2d897SLinus Walleij /* ensure that IF and IE are on (temporarily), so that we don't end up 299fcf2d897SLinus Walleij stepping forever */ 300fcf2d897SLinus Walleij ctx_reg2 = npe_cmd_read(npe, ECS_DBG_CTXT_REG_2, CMD_RD_ECS_REG); 301fcf2d897SLinus Walleij npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2 | 302fcf2d897SLinus Walleij ECS_DBG_REG_2_IF | ECS_DBG_REG_2_IE); 303fcf2d897SLinus Walleij 304fcf2d897SLinus Walleij /* clear the FIFOs */ 305fcf2d897SLinus Walleij while (__raw_readl(&npe->regs->watchpoint_fifo) & WFIFO_VALID) 306fcf2d897SLinus Walleij ; 307fcf2d897SLinus Walleij while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE) 308fcf2d897SLinus Walleij /* read from the outFIFO until empty */ 309fcf2d897SLinus Walleij print_npe(KERN_DEBUG, npe, "npe_reset: read FIFO = 0x%X\n", 310fcf2d897SLinus Walleij __raw_readl(&npe->regs->in_out_fifo)); 311fcf2d897SLinus Walleij 312fcf2d897SLinus Walleij while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE) 313fcf2d897SLinus Walleij /* step execution of the NPE intruction to read inFIFO using 314fcf2d897SLinus Walleij the Debug Executing Context stack */ 315fcf2d897SLinus Walleij if (npe_debug_instr(npe, INSTR_RD_FIFO, 0, 0)) 316fcf2d897SLinus Walleij return -ETIMEDOUT; 317fcf2d897SLinus Walleij 318fcf2d897SLinus Walleij /* reset the mailbox reg from the XScale side */ 319fcf2d897SLinus Walleij __raw_writel(RESET_MBOX_STAT, &npe->regs->mailbox_status); 320fcf2d897SLinus Walleij /* from NPE side */ 321fcf2d897SLinus Walleij if (npe_debug_instr(npe, INSTR_RESET_MBOX, 0, 0)) 322fcf2d897SLinus Walleij return -ETIMEDOUT; 323fcf2d897SLinus Walleij 324fcf2d897SLinus Walleij /* Reset the physical registers in the NPE register file */ 325fcf2d897SLinus Walleij for (val = 0; val < NPE_PHYS_REG; val++) { 326fcf2d897SLinus Walleij if (npe_logical_reg_write16(npe, NPE_REGMAP, val >> 1, 0)) 327fcf2d897SLinus Walleij return -ETIMEDOUT; 328fcf2d897SLinus Walleij /* address is either 0 or 4 */ 329fcf2d897SLinus Walleij if (npe_logical_reg_write32(npe, (val & 1) * 4, 0, 0)) 330fcf2d897SLinus Walleij return -ETIMEDOUT; 331fcf2d897SLinus Walleij } 332fcf2d897SLinus Walleij 333fcf2d897SLinus Walleij /* Reset the context store = each context's Context Store registers */ 334fcf2d897SLinus Walleij 335fcf2d897SLinus Walleij /* Context 0 has no STARTPC. Instead, this value is used to set NextPC 336fcf2d897SLinus Walleij for Background ECS, to set where NPE starts executing code */ 337fcf2d897SLinus Walleij val = npe_cmd_read(npe, ECS_BG_CTXT_REG_0, CMD_RD_ECS_REG); 338fcf2d897SLinus Walleij val &= ~ECS_REG_0_NEXTPC_MASK; 339fcf2d897SLinus Walleij val |= (0 /* NextPC */ << 16) & ECS_REG_0_NEXTPC_MASK; 340fcf2d897SLinus Walleij npe_cmd_write(npe, ECS_BG_CTXT_REG_0, CMD_WR_ECS_REG, val); 341fcf2d897SLinus Walleij 342fcf2d897SLinus Walleij for (i = 0; i < 16; i++) { 343fcf2d897SLinus Walleij if (i) { /* Context 0 has no STEVT nor STARTPC */ 344fcf2d897SLinus Walleij /* STEVT = off, 0x80 */ 345fcf2d897SLinus Walleij if (npe_logical_reg_write8(npe, NPE_STEVT, 0x80, i)) 346fcf2d897SLinus Walleij return -ETIMEDOUT; 347fcf2d897SLinus Walleij if (npe_logical_reg_write16(npe, NPE_STARTPC, 0, i)) 348fcf2d897SLinus Walleij return -ETIMEDOUT; 349fcf2d897SLinus Walleij } 350fcf2d897SLinus Walleij /* REGMAP = d0->p0, d8->p2, d16->p4 */ 351fcf2d897SLinus Walleij if (npe_logical_reg_write16(npe, NPE_REGMAP, 0x820, i)) 352fcf2d897SLinus Walleij return -ETIMEDOUT; 353fcf2d897SLinus Walleij if (npe_logical_reg_write8(npe, NPE_CINDEX, 0, i)) 354fcf2d897SLinus Walleij return -ETIMEDOUT; 355fcf2d897SLinus Walleij } 356fcf2d897SLinus Walleij 357fcf2d897SLinus Walleij /* post exec */ 358fcf2d897SLinus Walleij /* clear active bit in debug level */ 359fcf2d897SLinus Walleij npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG, 0); 360fcf2d897SLinus Walleij /* clear the pipeline */ 361fcf2d897SLinus Walleij __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); 362fcf2d897SLinus Walleij /* restore previous values */ 363fcf2d897SLinus Walleij __raw_writel(exec_count, &npe->regs->exec_count); 364fcf2d897SLinus Walleij npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2); 365fcf2d897SLinus Walleij 366fcf2d897SLinus Walleij /* write reset values to Execution Context Stack registers */ 367fcf2d897SLinus Walleij for (val = 0; val < ARRAY_SIZE(ecs_reset); val++) 368fcf2d897SLinus Walleij npe_cmd_write(npe, ecs_reset[val].reg, CMD_WR_ECS_REG, 369fcf2d897SLinus Walleij ecs_reset[val].val); 370fcf2d897SLinus Walleij 371fcf2d897SLinus Walleij /* clear the profile counter */ 372fcf2d897SLinus Walleij __raw_writel(CMD_CLR_PROFILE_CNT, &npe->regs->exec_status_cmd); 373fcf2d897SLinus Walleij 374fcf2d897SLinus Walleij __raw_writel(0, &npe->regs->exec_count); 375fcf2d897SLinus Walleij __raw_writel(0, &npe->regs->action_points[0]); 376fcf2d897SLinus Walleij __raw_writel(0, &npe->regs->action_points[1]); 377fcf2d897SLinus Walleij __raw_writel(0, &npe->regs->action_points[2]); 378fcf2d897SLinus Walleij __raw_writel(0, &npe->regs->action_points[3]); 379fcf2d897SLinus Walleij __raw_writel(0, &npe->regs->watch_count); 380fcf2d897SLinus Walleij 381fcf2d897SLinus Walleij val = ixp4xx_read_feature_bits(); 382fcf2d897SLinus Walleij /* reset the NPE */ 383fcf2d897SLinus Walleij ixp4xx_write_feature_bits(val & 384fcf2d897SLinus Walleij ~(IXP4XX_FEATURE_RESET_NPEA << npe->id)); 385fcf2d897SLinus Walleij /* deassert reset */ 386fcf2d897SLinus Walleij ixp4xx_write_feature_bits(val | 387fcf2d897SLinus Walleij (IXP4XX_FEATURE_RESET_NPEA << npe->id)); 388fcf2d897SLinus Walleij for (i = 0; i < MAX_RETRIES; i++) { 389fcf2d897SLinus Walleij if (ixp4xx_read_feature_bits() & 390fcf2d897SLinus Walleij (IXP4XX_FEATURE_RESET_NPEA << npe->id)) 391fcf2d897SLinus Walleij break; /* NPE is back alive */ 392fcf2d897SLinus Walleij udelay(1); 393fcf2d897SLinus Walleij } 394fcf2d897SLinus Walleij if (i == MAX_RETRIES) 395fcf2d897SLinus Walleij return -ETIMEDOUT; 396fcf2d897SLinus Walleij 397fcf2d897SLinus Walleij npe_stop(npe); 398fcf2d897SLinus Walleij 399fcf2d897SLinus Walleij /* restore NPE configuration bus Control Register - parity settings */ 400fcf2d897SLinus Walleij __raw_writel(ctl, &npe->regs->messaging_control); 401fcf2d897SLinus Walleij return 0; 402fcf2d897SLinus Walleij } 403fcf2d897SLinus Walleij 404fcf2d897SLinus Walleij 405fcf2d897SLinus Walleij int npe_send_message(struct npe *npe, const void *msg, const char *what) 406fcf2d897SLinus Walleij { 407fcf2d897SLinus Walleij const u32 *send = msg; 408fcf2d897SLinus Walleij int cycles = 0; 409fcf2d897SLinus Walleij 410fcf2d897SLinus Walleij debug_msg(npe, "Trying to send message %s [%08X:%08X]\n", 411fcf2d897SLinus Walleij what, send[0], send[1]); 412fcf2d897SLinus Walleij 413fcf2d897SLinus Walleij if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE) { 414fcf2d897SLinus Walleij debug_msg(npe, "NPE input FIFO not empty\n"); 415fcf2d897SLinus Walleij return -EIO; 416fcf2d897SLinus Walleij } 417fcf2d897SLinus Walleij 418fcf2d897SLinus Walleij __raw_writel(send[0], &npe->regs->in_out_fifo); 419fcf2d897SLinus Walleij 420fcf2d897SLinus Walleij if (!(__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNF)) { 421fcf2d897SLinus Walleij debug_msg(npe, "NPE input FIFO full\n"); 422fcf2d897SLinus Walleij return -EIO; 423fcf2d897SLinus Walleij } 424fcf2d897SLinus Walleij 425fcf2d897SLinus Walleij __raw_writel(send[1], &npe->regs->in_out_fifo); 426fcf2d897SLinus Walleij 427fcf2d897SLinus Walleij while ((cycles < MAX_RETRIES) && 428fcf2d897SLinus Walleij (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)) { 429fcf2d897SLinus Walleij udelay(1); 430fcf2d897SLinus Walleij cycles++; 431fcf2d897SLinus Walleij } 432fcf2d897SLinus Walleij 433fcf2d897SLinus Walleij if (cycles == MAX_RETRIES) { 434fcf2d897SLinus Walleij debug_msg(npe, "Timeout sending message\n"); 435fcf2d897SLinus Walleij return -ETIMEDOUT; 436fcf2d897SLinus Walleij } 437fcf2d897SLinus Walleij 438fcf2d897SLinus Walleij #if DEBUG_MSG > 1 439fcf2d897SLinus Walleij debug_msg(npe, "Sending a message took %i cycles\n", cycles); 440fcf2d897SLinus Walleij #endif 441fcf2d897SLinus Walleij return 0; 442fcf2d897SLinus Walleij } 443fcf2d897SLinus Walleij 444fcf2d897SLinus Walleij int npe_recv_message(struct npe *npe, void *msg, const char *what) 445fcf2d897SLinus Walleij { 446fcf2d897SLinus Walleij u32 *recv = msg; 447fcf2d897SLinus Walleij int cycles = 0, cnt = 0; 448fcf2d897SLinus Walleij 449fcf2d897SLinus Walleij debug_msg(npe, "Trying to receive message %s\n", what); 450fcf2d897SLinus Walleij 451fcf2d897SLinus Walleij while (cycles < MAX_RETRIES) { 452fcf2d897SLinus Walleij if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE) { 453fcf2d897SLinus Walleij recv[cnt++] = __raw_readl(&npe->regs->in_out_fifo); 454fcf2d897SLinus Walleij if (cnt == 2) 455fcf2d897SLinus Walleij break; 456fcf2d897SLinus Walleij } else { 457fcf2d897SLinus Walleij udelay(1); 458fcf2d897SLinus Walleij cycles++; 459fcf2d897SLinus Walleij } 460fcf2d897SLinus Walleij } 461fcf2d897SLinus Walleij 462fcf2d897SLinus Walleij switch(cnt) { 463fcf2d897SLinus Walleij case 1: 464fcf2d897SLinus Walleij debug_msg(npe, "Received [%08X]\n", recv[0]); 465fcf2d897SLinus Walleij break; 466fcf2d897SLinus Walleij case 2: 467fcf2d897SLinus Walleij debug_msg(npe, "Received [%08X:%08X]\n", recv[0], recv[1]); 468fcf2d897SLinus Walleij break; 469fcf2d897SLinus Walleij } 470fcf2d897SLinus Walleij 471fcf2d897SLinus Walleij if (cycles == MAX_RETRIES) { 472fcf2d897SLinus Walleij debug_msg(npe, "Timeout waiting for message\n"); 473fcf2d897SLinus Walleij return -ETIMEDOUT; 474fcf2d897SLinus Walleij } 475fcf2d897SLinus Walleij 476fcf2d897SLinus Walleij #if DEBUG_MSG > 1 477fcf2d897SLinus Walleij debug_msg(npe, "Receiving a message took %i cycles\n", cycles); 478fcf2d897SLinus Walleij #endif 479fcf2d897SLinus Walleij return 0; 480fcf2d897SLinus Walleij } 481fcf2d897SLinus Walleij 482fcf2d897SLinus Walleij int npe_send_recv_message(struct npe *npe, void *msg, const char *what) 483fcf2d897SLinus Walleij { 484fcf2d897SLinus Walleij int result; 485fcf2d897SLinus Walleij u32 *send = msg, recv[2]; 486fcf2d897SLinus Walleij 487fcf2d897SLinus Walleij if ((result = npe_send_message(npe, msg, what)) != 0) 488fcf2d897SLinus Walleij return result; 489fcf2d897SLinus Walleij if ((result = npe_recv_message(npe, recv, what)) != 0) 490fcf2d897SLinus Walleij return result; 491fcf2d897SLinus Walleij 492fcf2d897SLinus Walleij if ((recv[0] != send[0]) || (recv[1] != send[1])) { 493fcf2d897SLinus Walleij debug_msg(npe, "Message %s: unexpected message received\n", 494fcf2d897SLinus Walleij what); 495fcf2d897SLinus Walleij return -EIO; 496fcf2d897SLinus Walleij } 497fcf2d897SLinus Walleij return 0; 498fcf2d897SLinus Walleij } 499fcf2d897SLinus Walleij 500fcf2d897SLinus Walleij 501fcf2d897SLinus Walleij int npe_load_firmware(struct npe *npe, const char *name, struct device *dev) 502fcf2d897SLinus Walleij { 503fcf2d897SLinus Walleij const struct firmware *fw_entry; 504fcf2d897SLinus Walleij 505fcf2d897SLinus Walleij struct dl_block { 506fcf2d897SLinus Walleij u32 type; 507fcf2d897SLinus Walleij u32 offset; 508fcf2d897SLinus Walleij } *blk; 509fcf2d897SLinus Walleij 510fcf2d897SLinus Walleij struct dl_image { 511fcf2d897SLinus Walleij u32 magic; 512fcf2d897SLinus Walleij u32 id; 513fcf2d897SLinus Walleij u32 size; 514fcf2d897SLinus Walleij union { 515fcf2d897SLinus Walleij u32 data[0]; 516fcf2d897SLinus Walleij struct dl_block blocks[0]; 517fcf2d897SLinus Walleij }; 518fcf2d897SLinus Walleij } *image; 519fcf2d897SLinus Walleij 520fcf2d897SLinus Walleij struct dl_codeblock { 521fcf2d897SLinus Walleij u32 npe_addr; 522fcf2d897SLinus Walleij u32 size; 523fcf2d897SLinus Walleij u32 data[0]; 524fcf2d897SLinus Walleij } *cb; 525fcf2d897SLinus Walleij 526fcf2d897SLinus Walleij int i, j, err, data_size, instr_size, blocks, table_end; 527fcf2d897SLinus Walleij u32 cmd; 528fcf2d897SLinus Walleij 529fcf2d897SLinus Walleij if ((err = request_firmware(&fw_entry, name, dev)) != 0) 530fcf2d897SLinus Walleij return err; 531fcf2d897SLinus Walleij 532fcf2d897SLinus Walleij err = -EINVAL; 533fcf2d897SLinus Walleij if (fw_entry->size < sizeof(struct dl_image)) { 534fcf2d897SLinus Walleij print_npe(KERN_ERR, npe, "incomplete firmware file\n"); 535fcf2d897SLinus Walleij goto err; 536fcf2d897SLinus Walleij } 537fcf2d897SLinus Walleij image = (struct dl_image*)fw_entry->data; 538fcf2d897SLinus Walleij 539fcf2d897SLinus Walleij #if DEBUG_FW 540fcf2d897SLinus Walleij print_npe(KERN_DEBUG, npe, "firmware: %08X %08X %08X (0x%X bytes)\n", 541fcf2d897SLinus Walleij image->magic, image->id, image->size, image->size * 4); 542fcf2d897SLinus Walleij #endif 543fcf2d897SLinus Walleij 544fcf2d897SLinus Walleij if (image->magic == swab32(FW_MAGIC)) { /* swapped file */ 545fcf2d897SLinus Walleij image->id = swab32(image->id); 546fcf2d897SLinus Walleij image->size = swab32(image->size); 547fcf2d897SLinus Walleij } else if (image->magic != FW_MAGIC) { 548fcf2d897SLinus Walleij print_npe(KERN_ERR, npe, "bad firmware file magic: 0x%X\n", 549fcf2d897SLinus Walleij image->magic); 550fcf2d897SLinus Walleij goto err; 551fcf2d897SLinus Walleij } 552fcf2d897SLinus Walleij if ((image->size * 4 + sizeof(struct dl_image)) != fw_entry->size) { 553fcf2d897SLinus Walleij print_npe(KERN_ERR, npe, 554fcf2d897SLinus Walleij "inconsistent size of firmware file\n"); 555fcf2d897SLinus Walleij goto err; 556fcf2d897SLinus Walleij } 557fcf2d897SLinus Walleij if (((image->id >> 24) & 0xF /* NPE ID */) != npe->id) { 558fcf2d897SLinus Walleij print_npe(KERN_ERR, npe, "firmware file NPE ID mismatch\n"); 559fcf2d897SLinus Walleij goto err; 560fcf2d897SLinus Walleij } 561fcf2d897SLinus Walleij if (image->magic == swab32(FW_MAGIC)) 562fcf2d897SLinus Walleij for (i = 0; i < image->size; i++) 563fcf2d897SLinus Walleij image->data[i] = swab32(image->data[i]); 564fcf2d897SLinus Walleij 565fcf2d897SLinus Walleij if (cpu_is_ixp42x() && ((image->id >> 28) & 0xF /* device ID */)) { 566fcf2d897SLinus Walleij print_npe(KERN_INFO, npe, "IXP43x/IXP46x firmware ignored on " 567fcf2d897SLinus Walleij "IXP42x\n"); 568fcf2d897SLinus Walleij goto err; 569fcf2d897SLinus Walleij } 570fcf2d897SLinus Walleij 571fcf2d897SLinus Walleij if (npe_running(npe)) { 572fcf2d897SLinus Walleij print_npe(KERN_INFO, npe, "unable to load firmware, NPE is " 573fcf2d897SLinus Walleij "already running\n"); 574fcf2d897SLinus Walleij err = -EBUSY; 575fcf2d897SLinus Walleij goto err; 576fcf2d897SLinus Walleij } 577fcf2d897SLinus Walleij #if 0 578fcf2d897SLinus Walleij npe_stop(npe); 579fcf2d897SLinus Walleij npe_reset(npe); 580fcf2d897SLinus Walleij #endif 581fcf2d897SLinus Walleij 582fcf2d897SLinus Walleij print_npe(KERN_INFO, npe, "firmware functionality 0x%X, " 583fcf2d897SLinus Walleij "revision 0x%X:%X\n", (image->id >> 16) & 0xFF, 584fcf2d897SLinus Walleij (image->id >> 8) & 0xFF, image->id & 0xFF); 585fcf2d897SLinus Walleij 586fcf2d897SLinus Walleij if (cpu_is_ixp42x()) { 587fcf2d897SLinus Walleij if (!npe->id) 588fcf2d897SLinus Walleij instr_size = NPE_A_42X_INSTR_SIZE; 589fcf2d897SLinus Walleij else 590fcf2d897SLinus Walleij instr_size = NPE_B_AND_C_42X_INSTR_SIZE; 591fcf2d897SLinus Walleij data_size = NPE_42X_DATA_SIZE; 592fcf2d897SLinus Walleij } else { 593fcf2d897SLinus Walleij instr_size = NPE_46X_INSTR_SIZE; 594fcf2d897SLinus Walleij data_size = NPE_46X_DATA_SIZE; 595fcf2d897SLinus Walleij } 596fcf2d897SLinus Walleij 597fcf2d897SLinus Walleij for (blocks = 0; blocks * sizeof(struct dl_block) / 4 < image->size; 598fcf2d897SLinus Walleij blocks++) 599fcf2d897SLinus Walleij if (image->blocks[blocks].type == FW_BLOCK_TYPE_EOF) 600fcf2d897SLinus Walleij break; 601fcf2d897SLinus Walleij if (blocks * sizeof(struct dl_block) / 4 >= image->size) { 602fcf2d897SLinus Walleij print_npe(KERN_INFO, npe, "firmware EOF block marker not " 603fcf2d897SLinus Walleij "found\n"); 604fcf2d897SLinus Walleij goto err; 605fcf2d897SLinus Walleij } 606fcf2d897SLinus Walleij 607fcf2d897SLinus Walleij #if DEBUG_FW 608fcf2d897SLinus Walleij print_npe(KERN_DEBUG, npe, "%i firmware blocks found\n", blocks); 609fcf2d897SLinus Walleij #endif 610fcf2d897SLinus Walleij 611fcf2d897SLinus Walleij table_end = blocks * sizeof(struct dl_block) / 4 + 1 /* EOF marker */; 612fcf2d897SLinus Walleij for (i = 0, blk = image->blocks; i < blocks; i++, blk++) { 613fcf2d897SLinus Walleij if (blk->offset > image->size - sizeof(struct dl_codeblock) / 4 614fcf2d897SLinus Walleij || blk->offset < table_end) { 615fcf2d897SLinus Walleij print_npe(KERN_INFO, npe, "invalid offset 0x%X of " 616fcf2d897SLinus Walleij "firmware block #%i\n", blk->offset, i); 617fcf2d897SLinus Walleij goto err; 618fcf2d897SLinus Walleij } 619fcf2d897SLinus Walleij 620fcf2d897SLinus Walleij cb = (struct dl_codeblock*)&image->data[blk->offset]; 621fcf2d897SLinus Walleij if (blk->type == FW_BLOCK_TYPE_INSTR) { 622fcf2d897SLinus Walleij if (cb->npe_addr + cb->size > instr_size) 623fcf2d897SLinus Walleij goto too_big; 624fcf2d897SLinus Walleij cmd = CMD_WR_INS_MEM; 625fcf2d897SLinus Walleij } else if (blk->type == FW_BLOCK_TYPE_DATA) { 626fcf2d897SLinus Walleij if (cb->npe_addr + cb->size > data_size) 627fcf2d897SLinus Walleij goto too_big; 628fcf2d897SLinus Walleij cmd = CMD_WR_DATA_MEM; 629fcf2d897SLinus Walleij } else { 630fcf2d897SLinus Walleij print_npe(KERN_INFO, npe, "invalid firmware block #%i " 631fcf2d897SLinus Walleij "type 0x%X\n", i, blk->type); 632fcf2d897SLinus Walleij goto err; 633fcf2d897SLinus Walleij } 634fcf2d897SLinus Walleij if (blk->offset + sizeof(*cb) / 4 + cb->size > image->size) { 635fcf2d897SLinus Walleij print_npe(KERN_INFO, npe, "firmware block #%i doesn't " 636fcf2d897SLinus Walleij "fit in firmware image: type %c, start 0x%X," 637fcf2d897SLinus Walleij " length 0x%X\n", i, 638fcf2d897SLinus Walleij blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D', 639fcf2d897SLinus Walleij cb->npe_addr, cb->size); 640fcf2d897SLinus Walleij goto err; 641fcf2d897SLinus Walleij } 642fcf2d897SLinus Walleij 643fcf2d897SLinus Walleij for (j = 0; j < cb->size; j++) 644fcf2d897SLinus Walleij npe_cmd_write(npe, cb->npe_addr + j, cmd, cb->data[j]); 645fcf2d897SLinus Walleij } 646fcf2d897SLinus Walleij 647fcf2d897SLinus Walleij npe_start(npe); 648fcf2d897SLinus Walleij if (!npe_running(npe)) 649fcf2d897SLinus Walleij print_npe(KERN_ERR, npe, "unable to start\n"); 650fcf2d897SLinus Walleij release_firmware(fw_entry); 651fcf2d897SLinus Walleij return 0; 652fcf2d897SLinus Walleij 653fcf2d897SLinus Walleij too_big: 654fcf2d897SLinus Walleij print_npe(KERN_INFO, npe, "firmware block #%i doesn't fit in NPE " 655fcf2d897SLinus Walleij "memory: type %c, start 0x%X, length 0x%X\n", i, 656fcf2d897SLinus Walleij blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D', 657fcf2d897SLinus Walleij cb->npe_addr, cb->size); 658fcf2d897SLinus Walleij err: 659fcf2d897SLinus Walleij release_firmware(fw_entry); 660fcf2d897SLinus Walleij return err; 661fcf2d897SLinus Walleij } 662fcf2d897SLinus Walleij 663fcf2d897SLinus Walleij 664fcf2d897SLinus Walleij struct npe *npe_request(unsigned id) 665fcf2d897SLinus Walleij { 666fcf2d897SLinus Walleij if (id < NPE_COUNT) 667fcf2d897SLinus Walleij if (npe_tab[id].valid) 668fcf2d897SLinus Walleij if (try_module_get(THIS_MODULE)) 669fcf2d897SLinus Walleij return &npe_tab[id]; 670fcf2d897SLinus Walleij return NULL; 671fcf2d897SLinus Walleij } 672fcf2d897SLinus Walleij 673fcf2d897SLinus Walleij void npe_release(struct npe *npe) 674fcf2d897SLinus Walleij { 675fcf2d897SLinus Walleij module_put(THIS_MODULE); 676fcf2d897SLinus Walleij } 677fcf2d897SLinus Walleij 678bc4d7eafSLinus Walleij static int ixp4xx_npe_probe(struct platform_device *pdev) 679fcf2d897SLinus Walleij { 680fcf2d897SLinus Walleij int i, found = 0; 6810b458d7bSLinus Walleij struct device *dev = &pdev->dev; 6820b458d7bSLinus Walleij struct resource *res; 683fcf2d897SLinus Walleij 684fcf2d897SLinus Walleij for (i = 0; i < NPE_COUNT; i++) { 685fcf2d897SLinus Walleij struct npe *npe = &npe_tab[i]; 6860b458d7bSLinus Walleij 6870b458d7bSLinus Walleij res = platform_get_resource(pdev, IORESOURCE_MEM, i); 6880b458d7bSLinus Walleij if (!res) 6890b458d7bSLinus Walleij return -ENODEV; 6900b458d7bSLinus Walleij 691fcf2d897SLinus Walleij if (!(ixp4xx_read_feature_bits() & 6920b458d7bSLinus Walleij (IXP4XX_FEATURE_RESET_NPEA << i))) { 6930b458d7bSLinus Walleij dev_info(dev, "NPE%d at 0x%08x-0x%08x not available\n", 6940b458d7bSLinus Walleij i, res->start, res->end); 695fcf2d897SLinus Walleij continue; /* NPE already disabled or not present */ 6960b458d7bSLinus Walleij } 6970b458d7bSLinus Walleij npe->regs = devm_ioremap_resource(dev, res); 698*cd3967beSDan Carpenter if (IS_ERR(npe->regs)) 699*cd3967beSDan Carpenter return PTR_ERR(npe->regs); 7000b458d7bSLinus Walleij 7010b458d7bSLinus Walleij if (npe_reset(npe)) { 7020b458d7bSLinus Walleij dev_info(dev, "NPE%d at 0x%08x-0x%08x does not reset\n", 7030b458d7bSLinus Walleij i, res->start, res->end); 704fcf2d897SLinus Walleij continue; 705fcf2d897SLinus Walleij } 706fcf2d897SLinus Walleij npe->valid = 1; 7070b458d7bSLinus Walleij dev_info(dev, "NPE%d at 0x%08x-0x%08x registered\n", 7080b458d7bSLinus Walleij i, res->start, res->end); 709fcf2d897SLinus Walleij found++; 710fcf2d897SLinus Walleij } 711fcf2d897SLinus Walleij 712fcf2d897SLinus Walleij if (!found) 713fcf2d897SLinus Walleij return -ENODEV; 714fcf2d897SLinus Walleij return 0; 715fcf2d897SLinus Walleij } 716fcf2d897SLinus Walleij 717bc4d7eafSLinus Walleij static int ixp4xx_npe_remove(struct platform_device *pdev) 718fcf2d897SLinus Walleij { 719fcf2d897SLinus Walleij int i; 720fcf2d897SLinus Walleij 721fcf2d897SLinus Walleij for (i = 0; i < NPE_COUNT; i++) 7220b458d7bSLinus Walleij if (npe_tab[i].regs) { 723fcf2d897SLinus Walleij npe_reset(&npe_tab[i]); 724fcf2d897SLinus Walleij } 725bc4d7eafSLinus Walleij 726bc4d7eafSLinus Walleij return 0; 727fcf2d897SLinus Walleij } 728fcf2d897SLinus Walleij 729e00797f2SLinus Walleij static const struct of_device_id ixp4xx_npe_of_match[] = { 730e00797f2SLinus Walleij { 731e00797f2SLinus Walleij .compatible = "intel,ixp4xx-network-processing-engine", 732e00797f2SLinus Walleij }, 733e00797f2SLinus Walleij {}, 734e00797f2SLinus Walleij }; 735e00797f2SLinus Walleij 736bc4d7eafSLinus Walleij static struct platform_driver ixp4xx_npe_driver = { 737bc4d7eafSLinus Walleij .driver = { 738bc4d7eafSLinus Walleij .name = "ixp4xx-npe", 739e00797f2SLinus Walleij .of_match_table = of_match_ptr(ixp4xx_npe_of_match), 740bc4d7eafSLinus Walleij }, 741bc4d7eafSLinus Walleij .probe = ixp4xx_npe_probe, 742bc4d7eafSLinus Walleij .remove = ixp4xx_npe_remove, 743bc4d7eafSLinus Walleij }; 744bc4d7eafSLinus Walleij module_platform_driver(ixp4xx_npe_driver); 745fcf2d897SLinus Walleij 746fcf2d897SLinus Walleij MODULE_AUTHOR("Krzysztof Halasa"); 747fcf2d897SLinus Walleij MODULE_LICENSE("GPL v2"); 748fcf2d897SLinus Walleij MODULE_FIRMWARE(NPE_A_FIRMWARE); 749fcf2d897SLinus Walleij MODULE_FIRMWARE(NPE_B_FIRMWARE); 750fcf2d897SLinus Walleij MODULE_FIRMWARE(NPE_C_FIRMWARE); 751fcf2d897SLinus Walleij 752fcf2d897SLinus Walleij EXPORT_SYMBOL(npe_names); 753fcf2d897SLinus Walleij EXPORT_SYMBOL(npe_running); 754fcf2d897SLinus Walleij EXPORT_SYMBOL(npe_request); 755fcf2d897SLinus Walleij EXPORT_SYMBOL(npe_release); 756fcf2d897SLinus Walleij EXPORT_SYMBOL(npe_load_firmware); 757fcf2d897SLinus Walleij EXPORT_SYMBOL(npe_send_message); 758fcf2d897SLinus Walleij EXPORT_SYMBOL(npe_recv_message); 759fcf2d897SLinus Walleij EXPORT_SYMBOL(npe_send_recv_message); 760